JP2014182861A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory having many on-die termination circuits capable of preventing decrease of supply voltage level, increase of peak current, and the like.SOLUTION: The semiconductor memory includes: plural on-die termination circuits connected to each of plural input/output pads; and a control circuit that controls the on-die termination circuits. The on-die termination circuit includes: a pull-up element which is connected to a first terminal and an output terminal thereacross; and a pull-down element which is connected to an output terminal and a second terminal thereacross. The pull-up element is driven by a first pull-up element driver; and the pull-down element is driven by a first pull-down element driver. The control circuit activates the plural on-die termination circuits at timing different from each other.

Description

  Embodiments described in this specification relate to a semiconductor memory device.

  In recent years, a semiconductor chip such as a NAND flash memory has been required to increase the speed of an interface for exchanging data with a controller chip. For the purpose of speeding up, an on-die termination circuit may be used in the input / output buffer. This on-die termination circuit functions to optimize the waveform of the input signal, thereby contributing to the speeding up of the interface.

  However, since the on-die termination circuit allows a through current to flow, if a large number of on-die termination circuits are simultaneously activated, there is a risk of promoting a decrease in power supply voltage level, an increase in peak current, and the like.

JP 2006-129423 A

  Embodiments described below provide a semiconductor memory device that can prevent a decrease in power supply voltage level, an increase in peak current, and the like in a semiconductor memory device having a large number of on-die termination circuits. It is.

  A semiconductor memory device according to an embodiment described below includes a memory device in which memory cells are arranged, a data output buffer that outputs data read from the memory device, and a data input that receives data to be written to the memory device A buffer, a plurality of input / output pads to which the data input buffer for inputting / outputting data and the data output buffer are respectively connected, and a plurality of input / output pads connected to each of the data input / output buffers. A plurality of on-die termination circuits and a control circuit for controlling the on-die termination circuit.

  The on-die termination circuit includes a pull-up element connected between the first terminal and the output terminal, and a pull-down element connected between the output terminal and the second terminal. The pull-up element is driven by a first pull-up element driver, and the pull-down element is driven by a first pull-down element driver. The control circuit activates the plurality of on-die termination circuits at different timings.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment. FIG. FIG. 2 is a circuit diagram showing a configuration of a memory cell array 1 shown in FIG. 1. A specific configuration example of the termination circuit 5 will be described. The structure of the inverter chain circuit in the control circuit 7 is shown. It is a block diagram which shows the structure of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. A specific configuration example of the termination circuit 5 will be described. The structure of the inverter chain circuit in the control circuit 7 is shown. A specific configuration example of the termination circuit 5 will be described. A specific configuration example of the termination circuit 5 will be described. A specific configuration example of the termination circuit 5 will be described. A specific configuration example of the termination circuit 5 will be described. A specific configuration example of the termination circuit 5 will be described. FIG. 10 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a sixth embodiment. FIG. 13B is a correspondence table showing the relationship between combinations of circuits selected simultaneously in FIG. 13A and the values of termination resistors obtained. It is a block diagram which shows the structure of the non-volatile semiconductor memory device which concerns on 7th Embodiment. 14B is a correspondence table showing the relationship between combinations of circuits simultaneously selected in FIG. 14A and the value of the termination resistance obtained.

  Next, the nonvolatile semiconductor memory device according to the embodiment will be described with reference to the drawings.

[First Embodiment]
[Constitution]
FIG. 1 is a block diagram showing the configuration of the nonvolatile semiconductor memory device according to the first embodiment. In the first embodiment, a description will be given assuming that the nonvolatile semiconductor memory device is a NAND flash memory as an example. However, the embodiments described below can be applied to various types of storage devices other than the NAND flash memory.

  The nonvolatile semiconductor memory device according to the first embodiment includes a memory chip 100 including memory cells and a memory controller 200 that controls the memory chip 100. The memory chip 100 includes a memory cell array 1 in which the nonvolatile semiconductor memory device has memory cells MC that store data arranged in a matrix. The memory cell array 1 includes a plurality of bit lines BL, a plurality of word lines WL, a source line SRC, and a plurality of memory cells MC. The memory cells MC are configured to be electrically rewritable and are arranged in a matrix at the intersections of the bit lines BL and the word lines WL.

  A bit line control circuit 2 for controlling the voltage of the bit line BL and a word line control circuit 6 for controlling the voltage of the word line WL are connected to the memory cell array 1. The bit line control circuit 2 reads data in the memory cell MC in the memory cell array 1 through the bit line BL. In addition, writing is performed to the memory cell MC in the memory cell array 1 via the bit line BL.

A column decoder 3, a data input buffer / output buffer 4, and a data input / output pad 5 are connected to the bit line control circuit 2. The data input buffer / output buffer 4 has a function of outputting data read from the memory cell array 1 via the bit line control circuit 2 and receiving data to be written to the memory cell array 1. The data input / output pad 5 is connected to a data input buffer and a data output buffer via a termination circuit 9 described later.
For example, the data input / output pad 5 includes eight pads PAD0-7 for inputting / outputting 8-bit data DQ0-DQ7, pads PAD8, 9 for inputting / outputting strobe signals DQS and BDQS, and a clock Pads PAD 10 and 11 for inputting and outputting signals RE and BRE are provided.

  Data of the memory cell MC read from the memory cell array 1 is output from the data input / output pad 5 to the outside. The write data input from the outside to the data input / output pad 5 is input to the bit line control circuit 2 by the column decoder 3 and is written to the designated memory cell MC.

  The bit line control circuit 2, the column decoder 3, the data input buffer / output buffer 4, and the word line control circuit 6 are connected to the control circuit 7. The control circuit 7 controls the bit line control circuit 2, the column decoder 3, the data input buffer / data output buffer 4, and the word line control circuit 6 according to the control signal input to the control signal input terminal 8. Is generated. Note that the control circuit 7 may include a counter that counts the number of times of execution of the write operation and the number of times of execution of the erase operation, and a timer that times the accumulated time of the operation.

  A termination circuit 9 is connected between the data input / output pad 5 and the data input buffer / output buffer 4. This termination circuit 9 is provided in order to achieve impedance matching between the output resistance of the memory controller 200 and the input resistance of the memory chip 100 and to suppress signal reflection.

  FIG. 2 is a circuit diagram showing a configuration of memory cell array 1 shown in FIG. The memory cell array 1 is composed of a plurality of blocks B as shown in FIG. In the memory cell array 1, data is erased in block B units (block erase processing).

  As shown in FIG. 2, the block B includes a plurality of memory units MU. One memory unit MU includes a memory string MS including, for example, 16 memory cells MC connected in series, and first and second selection transistors S1 and S2 connected to both ends thereof. One end of the first selection transistor S1 is connected to the bit line BL, and one end of the second selection transistor S2 is connected to the source line SRC. The control gate electrodes of the memory cells MC arranged in a line in the Y direction are commonly connected to any one of the word lines WL1 to WL16. The control gate electrodes of the first selection transistors S1 arranged in a line in the Y direction are commonly connected to the select line SG1, and the control gate electrodes of the second selection transistors S2 arranged in a line in the Y direction are connected to the select line. Commonly connected to SG2. A set P of a plurality of memory cells MC connected to one word line WL constitutes one page or a plurality of pages. Data is written and read for each set P.

  Next, a specific configuration example of the termination circuit 5 will be described with reference to FIG. The termination circuit 5 of this embodiment is configured by connecting an on-die termination circuit ODT as shown in FIG. 3 to one input / output pad PADi.

  The on-die termination circuit ODT includes a pull-up p-type MOS transistor MP1 as a pull-up element and a resistor R1, and a resistor R2 as a pull-down element between a power supply terminal (VDD) and a ground terminal (Vss). The pull-down n-type MOS transistor MN1 is connected in series. The on-die termination circuit ODT is a circuit for matching input resistance and output resistance when data is input from the memory controller 200 to the memory chip 100, for example. A pad PADi is connected to a connection node N1 between the resistors R1 and R2, and an inverter IN1 as a driver is connected.

The output terminal of the driver DODT1 is connected to the gate of the p-type MOS transistor MP1, and the output terminal of the driver DODT2 is connected to the gate of the n-type MOS transistor MN1. The driver DODT1 is a CMOS inverter composed of a p-type MOS transistor MP2 and an n-type MOS transistor MN2, and an activation signal ODTENi is supplied to its input terminal. On the other hand, the driver DODT2 is a CMOS inverter composed of a p-type MOS transistor MP3 and an n-type MOS transistor MN3, and an activation signal ODTENib is supplied to its input terminal. The signals ODTENi and ODTENib (i = 0 to 7) have different rising timings as will be described later, thereby activating a plurality of on-die termination circuits ODT at different timings.
In the on-die termination circuit ODT, the on-resistances R1 and R2 may be omitted. That is, the pull-up element of the on-die termination circuit ODT may include only the p-type MOS transistor MP1, and the pull-down element of the on-die termination circuit ODT includes only the n-type MOS transistor MN1. May be.

  An off-chip driver circuit OCD is also connected to the pad PAD. The off-chip driver circuit OCD is provided for matching input resistance and output resistance when data is output from the memory chip 100 to the memory controller 200. The off-chip driver circuit OCD includes a p-type MOS transistor MP4 and an n-type MOS transistor MN4 connected in series between a power supply terminal and a ground terminal. The gates of the p-type MOS transistor MP4 and the n-type MOS transistor MN4 are controlled by drivers (not shown).

  These on-die termination circuits ODT are put into a dormant state in a standby state where no data is input from the memory controller 200, thereby reducing power consumption. On the other hand, in the active state where data is input from the memory controller 200, the on-die termination circuit ODT is activated. However, if the plurality of on-die termination circuits ODT are activated at the same time in the active state, the power supply voltage becomes unstable or the peak current increases to increase the burden on the power supply circuit. Problems arise.

Therefore, the present embodiment has a configuration in which a plurality of on-die termination circuits ODT are sequentially activated. Specifically, the control circuit 7 in FIG. 1 generates the activation signals ODTENi and ODTENib (i = 0 to 7) described above via an inverter chain circuit as shown in FIG. The inverter chain circuit of FIG. 4 includes a large number of inverter circuits INV connected in series in two rows. Activation signals ODTEN and ODTENb are input to the input terminals of the first two inverter circuits INV, respectively. Since the activation signals ODTENi and ODTENib described above are output through different numbers of inverter circuits INV, their rise timings are different. Such activation signals ODTENi and ODTENib are input to the driver circuits DODT1 and DODT2 connected to the ODT of the on-die termination circuit, respectively. Therefore, the plurality of on-die termination circuits ODT are sequentially activated at different timings. As a result, it is possible to prevent a plurality of on-die termination circuits ODT from being activated all at once.
Note that the on-die termination circuit ODT illustrated in FIG. 3 is configured by connecting a resistor and a transistor in series, but may be configured by only a transistor. Further, the off-chip driver circuit OCD is composed of only transistors in FIG. 3, but it can also be composed of a resistor and a transistor connected in series like the on-die termination circuit ODT of FIG. .

  The activation signals ODTENi and ODTENib input to one on-die termination circuit ODT may change at the same timing or may change at different timings. When the activation signals ODTENi and ODTENib change at different timings, the driver circuits DODT1 and DODT2 are also activated at different timings.

[Second Embodiment]
Next, a nonvolatile semiconductor memory device according to a second embodiment will be described with reference to FIG. The nonvolatile semiconductor memory device of this embodiment includes a memory chip 100 and a memory controller 200, as in the first embodiment. The internal structure of the memory chip 100 is the same as that of the first embodiment (however, in FIG. 5, some components are omitted for simplification of illustration).

  However, the second embodiment is different from the first embodiment in that one memory controller 200 controls a plurality (four in FIG. 5) of memory chips 100A to 100D. . The memory controller 200 is selectively connected to the memory chips 100A to 100D under the control of the multiplexer 300.

  Each of the memory chips 100A to 100D includes pads PAD0A to 7A, PAD0B to 7B, PAD0C to 7C, and PAD0D to 7D for inputting 8-bit data, respectively. Each pad PAD0A-7A is connected to an on-die termination circuit ODT similar to that of the first embodiment, as shown in FIG. Such an on-die termination circuit ODT is sequentially activated in the same manner as in the first embodiment by an inverter chain circuit as shown in FIG. Thereby, the effect similar to 1st Embodiment can be acquired.

[Third Embodiment]
Next, a nonvolatile semiconductor memory device according to a third embodiment will be described with reference to FIG. The entire configuration of the nonvolatile semiconductor memory device according to the third embodiment is substantially the same as that of the first embodiment (FIG. 1). However, in the third embodiment, the configurations of the drivers DODT1 and DODT2 are different from those of the first embodiment. In FIG. 8, the same components as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted below.

  In the third embodiment, in addition to controlling the rising timing of the plurality of on-die termination circuits ODT, it is possible to control the slew rate of the output signal of the on-die termination circuit ODT. Yes. That is, the driver DODT1 of the third embodiment is configured by connecting p-type MOS transistors MP2 and MP4 and n-type MOS transistors MN4 and MN2 in series. The driver DODT2 is configured by connecting p-type MOS transistors MP3 and MP5 and n-type MOS transistors MN5 and MN3 in series.

  Signals IREFPi and IREFNi (i = 0 to 7) are input to the gates of the transistors MP4 and MN4. Signals IREFPi and IREFNi are also input to the gates of the transistors MP5 and MN5. This signal IREFPi is a signal that falls from “H” to “L” with a controlled slope (slew rate) when the on-die termination circuit ODT is activated. Conversely, the signal IREFNi is a signal that rises from “L” to “H” with a controlled slope (slew rate) when the on-die termination circuit ODT is activated. In other words, the signals IREFPi and IREFNi can be changed in slew rate.

  Thus, by controlling the slopes of the signals IREFPi and IREFNi, the on-die termination circuit ODT of the pads PAD0 to 7 can change the slew rate of the output signal. The slopes of the signals IREFPi and IREFNi can be controlled independently using an RC circuit (not shown). Conversely, the signals IREFPi and IREFNi (i = 0 to 7) can all be controlled to have the same slope.

On the contrary, in the circuit of FIG. 8, the rising timings of the signals ODTENi and ODTENib (i = 0 to 7) are all made the same, while the slopes of the signals IREFPi and IREFNi can be controlled independently. This also makes it possible to control the rising timing of the on-die termination circuit ODT.
The rising timings of the signals ODTENi and ODTENib and the rising timings of the signals IREFPi and IREFNi may be the same or different.

[Fourth Embodiment]
Next, a nonvolatile semiconductor memory device according to a fourth embodiment will be described with reference to FIG. The overall configuration of the nonvolatile semiconductor memory device according to the fourth embodiment is substantially the same as that of the first embodiment (FIG. 1). However, the fourth embodiment also includes drivers DODT3 and DODT4 in addition to the drivers DODT1 and DODT2 as drivers for controlling the on-die termination circuit ODT. 9, the same components as those in FIG. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted below.
The

  The driver DODT3 is configured by connecting p-type MOS transistors MP6 and MP7 and n-type MOS transistors MN6 and MN7 in series, and drives the transistor MP1 by its output signal. The activation signal ODTENi is input to the transistors MP6 and MN7 in the same manner as the driver DODT1. On the other hand, enable signals ENb and EN are input to the transistors MP7 and MN6, respectively. The enable signal EN is a signal that rises from “L” to “H” with a high slew rate at the timing of activating the corresponding on-die termination circuit ODT, while the enable signal ENb is the enable signal EN Is an inverted signal.

  The driver DODT4 is configured by connecting p-type MOS transistors MP8 and MP9 and n-type MOS transistors MN8 and MN9 in series, and drives the transistor MP2 by its output signal. Similarly to the driver DODT2, the activation signal ODTENib is input to the transistors MP8 and MN9. On the other hand, enable signals ENb and EN are input to the transistors MP9 and MN8, respectively.

  As described above, in this embodiment, the on-die termination circuit ODT includes the drivers DODT1 and DODT2 for driving the signals IREFPi and IREFNi whose slew rate is controlled, and an enable signal having a fixed high slew rate. Drivers DODT3 and DODT4 driven in accordance with EN and ENb are also present. When drivers DODT1 and DODT2 are used, in addition to activating a plurality of on-die termination circuits ODT at different timings, the slew rate of the output signal of each on-die termination circuit ODT is also controlled. Can do. On the other hand, when the drivers DODT3 and DODT4 are used, a plurality of on-die termination circuits ODT are activated at different timings, and the individual on-die termination circuits ODT are driven by high fixed enable signals EN and ENb. It can be activated quickly. Thus, in the present embodiment, the operation of the on-die termination circuit ODT can be made different between the case where the drivers DODT1 and DODT2 are used and the case where the drivers DODT3 and DODT4 are used.

[Fifth Embodiment]
Next, a nonvolatile semiconductor memory device according to a fifth embodiment is described with reference to FIG. The overall configuration of the nonvolatile semiconductor memory device according to the fifth embodiment is substantially the same as that of the first embodiment (FIG. 1). However, in the fifth embodiment, the on-die termination circuit ODT also functions as an off-chip driver circuit OCD, which is different from the above-described embodiment. Hereinafter, a circuit that combines the function of the on-die termination circuit and the function of the off-chip driver circuit is referred to as “shared circuit OCD / ODT”.

In this embodiment, the drivers DODT1 and DODT2 are provided as drivers for causing the shared circuit OCD / ODT to function as the on-die termination circuit ODT. The configurations of the drivers DODT1 and DODT2 are substantially the same as those in the above-described embodiment.
In this embodiment, the drivers DOCD1 and DOCD2 are provided as drivers for causing the shared circuit OCD / ODT to function as the off-chip driver circuit OCD.

  The driver DOCD1 is configured by connecting transistors MP6 and MP7 and transistors MN6 and MN7 in series. The signal OCDENi is input to the transistors MP6 and MN7. Signals IREFP2i and IREFN2i are input to the gates of the transistors MP7 and MN6. The signals IREFP2i and IREFN2i are signals having a controlled slew rate like the signals IREFP1i and IREFN1i input to the driver DODT1, and are signals different from the signals IREFP1i and IREFN1i. The signals IREFP2i and IREFN2i (i = 0 to 7) can be independently changed in slew rate, or all may be given the same slew rate.

  The driver DOCD2 is configured by connecting transistors MP8 and MP9 and transistors MN8 and MN9 in series. The signal OCDENib is input to the transistors MP8 and MN9. Signals IREFP2i and IREFN2i are input to the gates of the transistors MP9 and MN8.

  The signals OCDENi, OCDENib, IREFP2, and IREFN2 are set to voltage values suitable for operating the shared circuit OCD / ODT as the off-chip driver circuit OCD.

  FIG. 11 shows a first modification of the fifth embodiment. In FIG. 11, the transistor MP7 is omitted from the driver DOCD1, and the transistor MN8 is omitted from the driver DOCD2. This circuit can achieve the same operation as that of the fifth embodiment. FIG. 12 shows a second modification of the fifth embodiment. In FIG. 12, in the driver DOCD1, the transistor MP4 is replaced with two small transistors MP41 and MP42. Further, the transistor MN4 is replaced with two small transistors MN41 and MN42. In the driver DOCD2, the transistor MP5 is replaced with two small transistors MP51 and MP52. Further, the transistor MN5 is replaced with two small transistors MN51 and MN52.

[Sixth Embodiment]
Next, a nonvolatile semiconductor memory device according to a sixth embodiment is described with reference to FIG. 13A. The entire configuration of the nonvolatile semiconductor memory device according to the sixth embodiment is substantially the same as that of the first embodiment (FIG. 1).

  However, in the sixth embodiment, as shown in FIG. 13A, a plurality of off-chip driver circuits OCD and shared circuits OCD / ODT are connected to one pad PADi. This is different from the embodiment. In FIG. 13, numerals (300, 150, 200, 116.7, 87.5, 64.3) written together in the blocks of the circuit OCD and the dual-purpose circuit OCD indicate termination resistors provided by the respective circuits. That is, in the example of FIG. 13, four shared circuits OCT / ODT are connected to one pad PADi, and three off-chip driver circuits OCD are connected. The four circuits OCT / ODT have termination resistors 300Ω, 150Ω, 200Ω, and 200Ω, respectively. The three off-chip driver circuits OCD have termination resistors 116.7Ω, 87.5Ω, and 64.3Ω, respectively. These resistance values are based on, for example, ONFi / Toggle standards. Although the off-chip driver circuit OCD and the dual-purpose circuit OCT / ODT are shown as a block diagram in FIG. 13, the circuit configuration thereof may be the same as that of the above-described embodiment.

  As described above, drivers DOCD1, DOCD2, DODT1, and DODT2 are provided as circuits for selectively activating a plurality of off-chip driver circuits OCD and dual-purpose circuits OCT / ODT connected to one pad PADi. ing. The drivers DOCD1, 2 and DODT1, 2 are also shown in a block diagram in FIG. 13, but their detailed circuit configurations may be the same as those in the above-described embodiment. A selection circuit Sel is provided as a selection circuit for selectively driving these drivers DOCD and DODT.

  In this example, the selection circuit Sel is selected by the selection circuits Sel (300), Sel (150), Sel (200), Sel (200) ′, Sel (116.7), Sel (87.5), Sel (64. 3). The selection circuits Sel (300), Sel (150), Sel (200), Sel (200) ′, Sel (116.7), Sel (87.5), and Sel (64.3) are respectively used as the shared circuit OCD. / ODT (300), OCD / ODT (150), OCD / ODT (200), OCD / ODT (200) ′, circuit OCD (116.7), OCD (87.5), OCD (64.3) Correspondingly provided. With such a selection circuit Sel, any combination of the off-chip driver circuit OCD and the dual-purpose circuit OCT / ODT can be activated to set the termination resistance of the pad PADi to various different values. The selection circuit Sel is activated when the signals S_300, S_150, S_200, S_200 ′, S_116.7, S_87.5, and S_64.3 input from the outside become “H”, and the corresponding circuit OCD or shared circuit Operate OCD / ODT. The selection circuit Sel receives the signal ODT_en or OCD_en. When the signal ODT_en becomes “H”, the selection circuit Sel drives the corresponding drivers DODT1 and 2 to operate the shared circuit OCD / ODT as an on-die termination circuit. When the signal OCD_en becomes “H”, the selection circuit Sel drives the corresponding drivers DCDT1 and 2 to operate the shared circuit OCD / ODT as an off-chip driver circuit and operates the circuit OCD. Let

  In order to give various values of termination resistance to the pad PADi, the dual-purpose circuit OCD / ODT and the circuit OCD move to the operating state independently or simultaneously. FIG. 13B is a correspondence table showing the relationship between the combination of circuits selected at the same time and the value of the termination resistance obtained. The cross mark indicates that it is an operation target. As shown in FIG. 13B, for example, when the circuits OCD / ODT (300) and OCD / ODT (150) are simultaneously in operation, the combined termination resistance provided is 100Ω. In addition, similarly, a plurality of shared circuits OCD / ODT and / or the circuit OCD can be operated simultaneously to provide an OCD or ODT having various termination resistances.

  As described above, according to the present embodiment, the same effect as the above-described embodiment can be obtained, and in addition, the termination resistance of each pad PAD can be switched to various values. Yes. Also in this embodiment, the operation timing of the shared circuit OCD / ODT and / or the circuit OCD and the slew rate of the output signal can be controlled in the same manner as in the above-described embodiment.

[Seventh Embodiment]
Next, a nonvolatile semiconductor memory device according to a seventh embodiment will be described with reference to FIG. 14A. The entire configuration of the nonvolatile semiconductor memory device according to the seventh embodiment is substantially the same as that of the first embodiment (FIG. 1).

  However, in the seventh embodiment, as shown in FIG. 14A, a plurality of off-chip driver circuits OCD and a plurality of on-die termination circuits OCD are connected to one pad PADi. This is different from the previous embodiment. In the sixth embodiment, the dual-purpose circuit OCD / ODT is connected. In the seventh embodiment, the circuit dedicated to the off-chip driver circuit (OCD) and the dedicated on-die termination circuit are used. Only the circuit (ODT) is connected. In other words, the circuit OCD functions only as an off-chip driver circuit, and the circuit ODT functions only as an on-die termination circuit. Therefore, only the signal ODT_en is input to each of the selection circuits Sel (300), Sel (150), Sel (200), and Sel (200) '. Further, only the signal OCD_en is input to the selection circuits Sel (50), Sel (116.7), Sel (87.5), and Sel (64.3). FIG. 14B is a correspondence table showing the relationship between the combination of circuits selected at the same time and the value of the termination resistance obtained. The cross mark indicates that it is an operation target.

  As described above, according to the present embodiment, the same effect as the above-described embodiment can be obtained, and in addition, the termination resistance of each pad PAD can be switched to various values. Yes. Also in this embodiment, the operation timing of the shared circuit OCD / ODT and / or the circuit OCD and the slew rate of the output signal can be controlled in the same manner as in the above-described embodiment.

  As mentioned above, although several embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 100 ... Memory chip, 200 ... Memory controller, 1 ... Memory re-cell array, 2 ... Bit line control circuit, 3 ... Column decoder, 4 ... Data input buffer / output buffer, 5・ ・ ・ Data input / output pad, 6 ・ ・ ・ Word line control circuit, 7 ・ ・ ・ Control circuit, 8 ・ ・ ・ Control signal input terminal, 9 ・ ・ ・ Termination circuit, DODT ・ ・ ・ Driver, ODT ・ ・ ・On-die termination circuit, OCD: Off-chip driver circuit.

Claims (12)

A memory device formed by arranging memory cells;
A data output buffer for outputting data read from the memory device and a data input buffer for receiving data to be written to the memory device;
A plurality of input / output pads to which the data input buffer and the data output buffer for inputting / outputting the data are respectively connected;
A plurality of on-die termination circuits connected to each of the plurality of input / output pads; and a control circuit for controlling the on-die termination circuit;
Each of the plurality of on-die termination circuits is
A pull-up element connected between the first terminal and the output terminal;
A pull-down element connected between the output terminal and the second terminal,
The pull-up element is driven by a first pull-up element driver;
The pull-down element is driven by a first pull-down element driver,
The control circuit activates the plurality of on-die termination circuits at different timings.   The control circuit is configured to transmit a first activation signal for activating the plurality of on-die termination circuits at different timings to the first pull-up element driver and the first pull-down element driver. The semiconductor memory device according to claim 1.   3. The semiconductor memory according to claim 1, wherein the control circuit is configured to transmit a second activation signal whose slew rate can be changed to the first pull-up element driver and the first pull-down element driver. apparatus. A plurality of the on-die termination circuits are connected to one input / output pad,
2. The control circuit according to claim 1, wherein the control circuit is configured to selectively drive at least one or more of the plurality of on-die termination circuits to provide different termination resistors to the input / output pads. Semiconductor memory device. At least some of the plurality of on-die termination circuits also function as off-chip driver circuits when outputting data from the memory cell array to the outside,
A second pull-up element driver that drives the pull-up element when the on-die termination circuit functions as the off-chip driver circuit;
The semiconductor memory device according to claim 1, further comprising: a second pull-down element driver that drives the pull-down element when the on-die termination circuit functions as the off-chip driver circuit. A plurality of the on-die termination circuits are connected to one input / output pad,
6. The control circuit according to claim 5, wherein the control circuit is configured to selectively drive at least one or more of the plurality of on-die termination circuits to provide different termination resistors to the input / output pads. Semiconductor memory device.   The semiconductor memory device according to claim 1, wherein the first pull-up element driver and the first pull-down element driver are activated at different timings. A memory device formed by arranging memory cells;
A data output buffer for outputting data read from the memory device and a data input buffer for receiving data to be written to the memory device;
A plurality of input / output pads to which the data input buffer and the data output buffer for inputting / outputting the data are respectively connected;
A plurality of on-die termination circuits and a plurality of off-chip driver circuits connected to each of the plurality of input / output pads;
A control circuit for controlling the on-die termination circuit and the off-chip driver circuit,
The control circuit is configured to selectively drive at least one or more of the on-die termination circuit or the off-chip driver circuit to provide different termination resistors to the input / output pads. A semiconductor memory device.   9. The semiconductor memory device according to claim 8, wherein the plurality of on-die termination circuits connected to one of the plurality of input / output pads have different resistance values.   9. The semiconductor memory device according to claim 8, wherein the plurality of off-chip driver circuits connected to one of the plurality of input / output pads have different resistance values. The plurality of on-die termination circuits connected to one of the plurality of input / output pads have different resistance values;
9. The semiconductor memory device according to claim 8, wherein the plurality of off-chip driver circuits connected to one of the plurality of input / output pads have different resistance values. The pull-up element includes a first transistor and a first resistor connected in series,
The semiconductor memory device according to claim 1, wherein the pull-down element includes a second transistor and a second resistor connected in series.

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