JP2014178172A - Infrared sensor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid such a problem that circuit characteristics in a peripheral circuit region may be changed due to heat generated when forming a thermo-pile of a sensor region in a manufacturing method of an infrared sensor.SOLUTION: The manufacturing method of the infrared sensor includes: a step for forming a thermo-pile support layer in a first region; a step for forming a thermo-pile 24 on an upper surface of the thermo-pile support layer; a step for forming a circuit element on a second region after the formation of the thermo-pile; a step for forming an upper layer 41 so as to cover the first and second regions; a step for digging down the upper layer 41 up to a halfway; a step for forming an etching hole 38 by further digging down the upper layer 41; and a step for forming a sensor part 2 by etching a part of a semiconductor substrate 1 through the etching hole 38 and floating the thermo-pile support layer and the thermo-pole 24 from the semiconductor substrate 1. An upper surface 2u of the sensor part 2 is lower than an upper surface 41u of the upper layer 41 in the second region.

Description

  The present invention relates to an infrared sensor and a method for manufacturing the same.

  In recent electronic devices, the surrounding environment is detected, and the detection result is used for operation control. For example, in an air conditioner, operation control is performed in which the presence of a person is detected and temperature control is performed targeting a place where the person is present. Further, in the lighting device, control is performed such that the presence of a person in a certain area is detected and lighting in the area is turned on. In such control, a sensor device for detecting the surrounding environment is used, and an infrared sensor that detects an object temperature in a non-contact manner by radiant heat from the object is used as a kind of sensor device.

  An example of an infrared sensor based on the prior art is described in Japanese Patent No. 4661207 (Patent Document 1). The infrared sensor described in Patent Document 1 includes a square infrared absorption film disposed so as to float above a recess provided in a substrate. The infrared absorption film is supported by two support beams. A silicon oxide film is laminated on the upper side of the substrate, and the support beam connects the infrared absorption film to the silicon oxide film. Each support beam has a shape bent at a right angle of 2 degrees, and a P-type polysilicon layer and an N-type polysilicon layer are linearly formed inside each support beam, and these constitute a thermopile. Yes. When the infrared absorbing film receives infrared rays and becomes high temperature, a temperature difference is generated between the infrared absorbing film and the surrounding silicon oxide film, and the temperature difference is converted into an electric signal by a thermopile, thereby reducing the amount of infrared rays. Can be detected.

  In patent document 1, in order to obtain an infrared sensor, the following manufacturing methods are described. First, element isolation is performed on a sensor region and a wiring region by LOCOS on a silicon substrate. An etching sacrificial layer made of polysilicon is formed in the sensor region, and a gate wiring made of polysilicon is formed in the wiring region. The height of the sensor region is raised by further stacking an etching sacrificial layer made of polysilicon in the sensor region. A silicon oxide film is formed so as to cover the entire surface. In the sensor region, a P-type polysilicon layer and an N-type polysilicon layer are formed in a predetermined shape to form a thermopile.

  A predetermined aluminum wiring is formed in the sensor region and the wiring region, and a silicon oxide film is formed on the entire surface so as to cover these aluminum wirings. The surface of the silicon oxide film is flattened by CMP or the like so that the aluminum wiring is not exposed. In the sensor region, the silicon oxide film is selectively etched to form a slit. By performing anisotropic etching using a strong alkali solution through the slit, the etching sacrificial layer and the silicon substrate in the sensor region are removed. As a result, in the sensor region, a cavity that is dug from the upper surface of the silicon substrate is formed. Thereby, the structure where the member containing a thermopile floated from the silicon substrate is obtained.

Japanese Patent No. 4661207

  In the manufacturing method of the infrared sensor described in Patent Document 1, the thermopile in the sensor region is formed after the wiring in the wiring region is formed. The process of forming the thermopile in the sensor region includes an ion diffusion process, which involves heating. This heating changes the diffusion concentration in the wiring region where the wiring is already formed, resulting in a change in circuit characteristics. In the wiring area, various circuit elements such as switching circuits and amplifier circuits are formed. In this way, if the manufacturing method is such that the characteristics change due to heat applied in the process after the circuit element formation, Each change may require adjustment at the design stage, or may require special changes to the circuit design compared to other products.

  Further, when the number of stacked layers for wiring formation in the wiring region increases or when the sensor is to be thinned, the height of the sensor region to be raised increases, so the thickness of the etching sacrificial layer formed in the sensor region Need to be increased. When the etching sacrificial layer is formed of a silicon oxide film, the thickness that can be obtained by one growth process is limited. Therefore, in order to obtain an etching sacrificial layer having a large thickness, the film growth process must be repeated a plurality of times. However, the number of processes increases. In this case, a gap is generated between the mask and the substrate during circuit wiring lithography, resulting in variations in pattern size. Due to this influence, there is a possibility that a conduction failure of the circuit element occurs.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an infrared sensor and a method for manufacturing the infrared sensor that avoids the inconvenience associated with a phenomenon in which circuit characteristics change in a peripheral circuit region due to heat when forming a thermopile in the sensor region.

  In order to achieve the above object, an infrared sensor manufacturing method according to the present invention provides a thermopile support on the first region of a semiconductor substrate having a first region to be a sensor region and a second region to be a peripheral circuit region on the upper surface. A step of forming a layer; a step of forming a thermopile on an upper surface of the thermopile support layer; a step of forming a circuit element in the second region after the step of forming the thermopile; A step of forming an upper layer covering the second region; a step of digging the upper layer partway in the first region; and a part of the region in which the upper layer is dug partway. Forming an etching hole in which the semiconductor substrate is exposed by digging, and being in the first region through the etching hole Forming a sensor part by etching a part of the semiconductor substrate to float the thermopile support layer and the thermopile from the semiconductor substrate, and the upper surface of the sensor part is the upper part in the second region. The position is lower than the upper surface of the layer.

  According to the present invention, after the thermopile is formed in the first region to be the sensor region at an early stage, the circuit element is formed in the second region, the upper layer is once formed thereon, and then the recess is formed in the sensor region. The sensor part including the thermopile is formed by exposing the layer close to the thermopile by digging in, so after the circuit elements in the peripheral circuit region are formed, avoid the heat associated with the thermopile forming process. be able to. Therefore, it is possible to manufacture an infrared sensor while avoiding the disadvantage associated with the phenomenon that the circuit characteristics change in the peripheral circuit region due to heat when forming the thermopile in the sensor region.

It is a flowchart of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 1st process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 2nd process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 3rd process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 4th process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 5th process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 6th process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 7th process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 8th process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is explanatory drawing of the 9th process of the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is sectional drawing of the infrared sensor chip obtained using the infrared sensor manufactured by the manufacturing method of the infrared sensor in Embodiment 1 based on this invention. It is sectional drawing of the model of simulation. It is a graph which shows the simulation result in case the thickness of a sensor part is 2.5 micrometers. It is a graph which shows the simulation result in case the thickness of a sensor part is 4.0 micrometers.

(Embodiment 1)
(Production method)
With reference to FIGS. 1-10, the manufacturing method of the infrared sensor in Embodiment 1 based on this invention is demonstrated. FIG. 1 shows a flowchart of the manufacturing method of the infrared sensor in the present embodiment.

  In the manufacturing method of the infrared sensor in the present embodiment, the thermopile support layer is formed in the first region of the semiconductor substrate having the first region to be the sensor region and the second region to be the peripheral circuit region on the upper surface. A step S2 of forming a thermopile on the upper surface of the thermopile support layer, a step S3 of forming a circuit element in the second region after the step S2 of forming the thermopile, the first region and the second region A step S4 for forming an upper layer covering the region; a step S5 for digging the upper layer partway in the first region; and a part of the region obtained by digging the upper layer partway. Step S6 of forming an etching hole exposing the semiconductor substrate by digging down, and the first through the etching hole. Forming a sensor part by etching a part of the semiconductor substrate in the region to float the thermopile support layer and the thermopile from the semiconductor substrate, and the upper surface of the sensor part includes the second surface The position is lower than the upper surface of the upper layer in the region.

  The semiconductor substrate is, for example, a silicon substrate. The circuit element is, for example, a transistor, a capacitor, a resistor, or the like.

Each step will be described in detail below.
First, as shown in FIG. 2, a semiconductor substrate 1 is prepared. Here, for convenience of explanation, the elements belonging to the sensor area 401 and the peripheral circuit area 402 are representatively extracted and displayed side by side. The area displayed as the sensor area 401 corresponds to the first area, and the area displayed as the peripheral circuit area 402 corresponds to the second area.

  As shown in FIG. 3, a silicon oxide film 21 is formed on a part of the upper surface of the semiconductor substrate 1 by a LOCOS (Local Oxidation of Silicon) method. The silicon oxide film 21 in the sensor region 401 corresponds to a thermopile support layer. Therefore, the step of forming the silicon oxide film 21 corresponds to step S1.

As shown in FIG. 4, an SiN film 22 is formed on the silicon oxide film 21, and an SiO ₂ film 23 is formed so as to cover the SiN film 22. A polysilicon film is formed so as to entirely cover the upper side of the SiO ₂ film 23, and this polysilicon film is etched, so that only a portion corresponding to a thermocouple constituting a thermopile is left behind. P-type polysilicon film 25 and N-type polysilicon film 26 are formed as shown in FIG. 4 by locally injecting P-type and N-type impurities into the polysilicon film and performing an annealing process. The P type polysilicon film 25 and the N type polysilicon film 26 constitute a thermopile 24. Thus, the process of forming the P-type polysilicon film 25 and the N-type polysilicon film 26 is a process of forming a thermopile, and therefore corresponds to the process S2.

  Actually, the thermopile is usually configured as an assembly in which a plurality of thermocouples are connected, and a plurality of pairs of P-type polysilicon film 25 and N-type polysilicon film 26 included in the thermopile are arranged and formed. Is done. In FIG. 4, only the P-type polysilicon film 25 and the N-type polysilicon film 26 corresponding to a pair of thermocouples are representatively shown for convenience of explanation.

  After step S2, transistors 28a and 28b and a resistor 39 are formed as circuit elements in the peripheral circuit region 402, as shown in FIG. The step of forming these circuit elements corresponds to step S3. However, the circuit elements formed in the peripheral circuit region 402 are merely examples, and the type, number, and arrangement of circuit elements are not limited to those shown here. Since step S3 is performed after the thermopile 24 is formed in step S2, the circuit element formed in step S3 is not affected by heat during the formation of the thermopile.

  As shown in FIG. 6, the insulating layer 27 is formed, the surface is flattened, and the wiring layer 29 a is formed on the upper surface of the insulating layer 27. The insulating layer 27 may be, for example, a BPSG (Boron Phosphorus Silicon Glass) layer. The planarization of the surface may be performed by, for example, a CMP (Chemical Mechanical Polishing) method. The wiring layer 29a can be formed of aluminum, for example. In the sensor region 401, a part of the wiring layer 29 a is connected to the P-type polysilicon film 25 or the N-type polysilicon film 26 through a through hole formed in the insulating layer 27. In the peripheral circuit region 402, a part of the wiring layer 29 a is connected to the transistors 28 a and 28 b or the resistor 39 through a through hole formed in the insulating layer 27. An insulating layer 30 is further formed so as to cover the insulating layer 27 and the wiring layer 29 a, and a wiring layer 29 b is formed on the upper surface of the insulating layer 30. A part of the wiring layer 29b is connected to one of the wiring layers 29a through a through hole formed in a predetermined position of the insulating layer 30. Wiring layer 29b can be formed of aluminum, for example. The wiring layers 29a and 29b may be formed by a laminated body of an aluminum layer and a copper layer, for example. In the peripheral circuit region 402, necessary wiring related to circuit elements is provided by the wiring layers 29a and 29b.

As shown in FIG. 6, an SiO ₂ film 31 is formed so as to cover the entire insulating layer 30 and wiring layer 29b. A SiN film 32 is further formed so as to cover the upper surface of the SiO ₂ film 31. The combined portion of the SiO ₂ film 31 and the SiN film 32 becomes a wiring protective film 40.

  In the example shown here, the layers from the insulating layer 27 to the SiN film 32 correspond to the “upper layer” 41. Accordingly, the process from the step of forming the insulating layer 27 to the step of forming the SiN film 32 corresponds to step S4.

  As shown in FIG. 7, the recess 33 is formed in the sensor region 401 by performing etching. The concave portion 33 is formed so that the bottom surface is positioned slightly higher than the wiring layer 29a. This etching step corresponds to step S5 because it is a step of digging the upper layer partway in the sensor region, which is the first region.

  After forming the thermopile in step S2, circuit elements are formed in step S3, and the upper layer 41 including various wirings is formed in step S4, so that the thermopile 24 is temporarily buried in the upper layer 41. However, when the upper layer 41 is dug halfway in the sensor region 401 in step S5, the thermopile 24 is again only buried shallowly below the bottom surface of the recess 33. After making such a state, a process for manufacturing the sensor portion is performed as follows.

  As shown in FIG. 8, an absorption layer 34 is formed in a region to be the sensor portion in the bottom surface of the recess 33. The absorption layer 34 can be formed of Ti or TiN. Further, a TEOS film 35 is formed so as to cover the entire surface. As a result, the bottom surface of the recess 33 is covered with the TEOS film 35. The absorption layer 34 is also covered with the TEOS film 35.

  Further, as shown in FIG. 8, at an appropriate time, a recess 36 is formed so that the wiring layer 29b is exposed above the resistor 39. Thereafter, a metal film 37 is formed so as to cover the inner surface of the recess 36. The metal film 37 may include an Au film.

  As shown in FIG. 9, an etching hole 38 is formed so that the semiconductor substrate 1 is directly exposed at a part of the bottom surface of the recess 33. The etching hole 38 occupies a partial area in the sensor opening. The step of forming the etching hole 38 corresponds to step S6.

  As shown in FIG. 10, the semiconductor substrate 1 is etched through the etching hole 38. An alkaline solution can be used for this etching. For this etching, for example, a TMAH (tetramethylammonium hydroxide) solution can be used. By this etching, the recess 5 is formed so as to dig up the upper surface of the semiconductor substrate 1. As a result, the sensor unit 2 having a structure that is supported by being floated from the semiconductor substrate 1 is formed. When a plurality of sensor units 2 are arranged in the sensor region 401, the recesses 5 are respectively formed corresponding to the individual sensor units 2. Thus, the process of forming the sensor unit 2 by etching the semiconductor substrate 1 corresponds to the process S7.

  The sensor unit 2 is supported by one or more beams from any part of the upper layer 31. As the planar shape of the sensor unit 2, the planar shape of a known thermopile infrared sensor may be employed. The planar shape of the sensor unit 2 may be one described in Patent Document 1, for example.

  As shown in FIG. 10, the upper surface 2u of the sensor unit 2 is positioned lower than the upper surface 41u of the upper layer 41 in the peripheral circuit region 402 as the second region. Thus, the infrared sensor 101 is obtained.

  As shown in FIG. 11, the cap member 502 is attached using a sealing material 503. A metal can be used as the sealing material 503. The internal space 505 covered with the cap member 502 and the substrate 1 may be sealed in a vacuum by a known technique. The sensor unit 2 is supported in the internal space 505. In FIG. 10, since the sensor units 2 are schematically displayed, it looks as if the plurality of sensor units 2 are integrally continuous plates, but in reality, each sensor unit 2 is a semiconductor. Each is held by some beam so as to float above the recess 5 of the substrate 1. In FIG. 10, for convenience of explanation, only four sensor units 2 are displayed, but actually a larger number of sensor units 2 may be arranged. The space in each recess 5 communicates with the internal space 505.

  In this way, the infrared sensor chip 601 is obtained. The infrared sensor chip 601 has an image receiving area in which a plurality of sensor units 2 are arranged in a matrix. The infrared sensor chip 601 includes a plurality of infrared sensors 101.

(Action / Effect)
According to the manufacturing method of the infrared sensor in the present embodiment, after forming the thermopile in the sensor region at an early stage, the circuit elements are formed in the peripheral circuit region and once formed including the upper layer disposed thereon. Then, by digging the recess in the sensor area, the layer close to the thermopile is exposed and the sensor part including the thermopile is formed in that state, so after forming the circuit element in the peripheral circuit area, the thermopile formation Heat applied during the process can be avoided. Therefore, it is possible to manufacture an infrared sensor while avoiding the disadvantage associated with the phenomenon that the circuit characteristics change in the peripheral circuit region due to heat when forming the thermopile in the sensor region.

  As shown in the present embodiment, the step S1 of forming the thermopile support layer preferably includes a step of forming an oxide film by the LOCOS method. By adopting this method, an appropriate thermopile support layer can be easily formed.

  As shown in the present embodiment, the upper layer preferably includes wiring layers 29a and 29b inside. By adopting this method, wiring necessary for connection between circuit elements can be easily secured.

(Embodiment 2)
(Constitution)
Referring to FIG. 11, infrared sensor 101 according to the second embodiment based on the present invention will be described. The infrared sensor 101 includes a semiconductor substrate 1 having a recess 5 on the upper surface, an upper layer 41 formed on the upper side of the semiconductor substrate 1 and having a sensor opening that is an opening corresponding to the recess 5, and an inner portion of the sensor opening. And a sensor part 2 supported in the sensor opening in a state of being separated from the inner surface of the recess 5 so as to be connected to at least one of the circumferences. The sensor unit 2 includes a thermopile. A peripheral circuit region 402 in which circuit elements are formed in the upper layer 41 is provided at a location different from the sensor opening as viewed in a plan view. The upper surface 2 u of the sensor unit 2 is located at a position lower than the upper surface 41 u of the upper layer 41 in the peripheral circuit region 402.

(Action / Effect)
In the infrared sensor according to the present embodiment, since the upper surface 2u of the sensor unit 2 is located lower than the upper surface 41u of the upper layer 41, the thermopile of the sensor unit 2 is formed before the circuit elements in the peripheral circuit region 402 are formed. Therefore, it is possible to avoid the heat accompanying the process of forming the thermopile from being applied to the circuit elements and various wirings inside the upper layer. Therefore, it is possible to provide an infrared sensor that can avoid inconvenience associated with the phenomenon that the circuit characteristics change in the peripheral circuit region due to heat when forming the thermopile in the sensor region.

  As shown in the first and second embodiments, making the upper surface 2 u of the sensor unit 2 lower than the upper surface 41 u of the upper layer 41 leads to a reduction in the thickness of the sensor unit 2. The thinning of the sensor unit 2 leads to high sensitivity and high speed as a sensor.

  As shown in the first and second embodiments, if the upper surface 2u of the sensor unit 2 is positioned lower than the upper surface 41u of the upper layer 41, the sensor unit 2 can be obtained even when the upper layer in the peripheral circuit region is thick. Easy to thin.

  If the thermopile of the sensor unit 2 is formed before the circuit elements in the peripheral circuit region 402 are formed, the characteristics of the circuit elements in the peripheral circuit region are not changed, so that a highly versatile circuit design is possible. It becomes.

(Experimental result)
In order to confirm how much speed can be achieved when the sensor unit 2 is thinned by making the upper surface 2u of the sensor unit 2 lower than the upper surface 41u of the upper layer 41, the following is performed. A simulation as described was performed.

In the simulation, a model as shown in FIG. 12 was assumed. A recess 5 is provided in the semiconductor substrate 1, and a silicon oxide film 21, a SiN film 22, a TEOS film 23, and an insulating layer 27 are stacked on the upper side of the semiconductor substrate 1 in this order from the side closer to the semiconductor substrate 1. The TEOS film 35 is formed as the outermost layer. The insulating layer 27 is formed of a BPSG layer. A P-type polysilicon film 25 and an N-type polysilicon film 26 are disposed inside the insulating layer 27 as an equivalent to a thermopile. A portion including the thermopile is disposed above the recess 5 so as to correspond to the sensor unit. By adjusting the thickness of the TEOS film 35, two models were prepared: a model in which the total thickness of the sensor portion was 2.5 μm and a model in which the thickness was 4.0 μm. With respect to these two models, a simulation was performed on the transition of temperature when a heat flux of 125.94 W / m ² was applied from the upper surface.

  The simulation results are shown in FIG. 13 and FIG. The results when the thickness of the sensor part is 2.5 μm are shown in FIG. The inventors paid attention to the time until the temperature reaches 63% of the maximum value. When the thickness of the sensor portion was 2.5 μm, as can be seen from FIG. 13, the time until the temperature reached 63% of the maximum value was 10 milliseconds.

  FIG. 14 shows the result when the thickness of the sensor part is 4.0 μm. When the thickness of the sensor part was 4.0 μm, as can be seen from FIG. 14, the time until the temperature reached 63% of the maximum value was 13 milliseconds. When the thickness of the sensor part is 2.5 μm compared to 4.0 μm, the time until the temperature reaches 63% of the maximum value is shortened by about 0.76 times, and the response speed is increased. It can be said that. Although there is a difference in the numerical value itself between the simulation result and the actual measurement value, it is thought that the general tendency is the same. From this simulation result, it is clear that thinning the sensor part contributes to speeding up the sensor. It was.

  In addition, the said embodiment disclosed this time is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

1 semiconductor substrate, 2 a sensor unit, 2u (sensor section) top, 5 recess 21 silicon oxide film, 22 and 32 SiN film, 23 and 31 SiO ₂ film, 24 thermopile, 25 P-type polysilicon film, 26 N-type Polysilicon film, 27, 30 insulating layer, 28a, 28b transistor, 29a, 29b wiring layer, 33 recess, 34 absorption layer, 35 TEOS film, 36 recess, 37 metal film, 38 etching hole, 39 resistor, 40 wiring protection Membrane, 41 upper layer, 41u (upper layer) upper surface, 101 infrared sensor, 401 sensor region, 402 peripheral circuit region, 502 cap member, 503 sealing material, 505 internal space, 601 infrared sensor chip.

Claims (4)

Forming a thermopile support layer in the first region of the semiconductor substrate having a first region to be a sensor region and a second region to be a peripheral circuit region on the upper surface;
Forming a thermopile on the top surface of the thermopile support layer;
A step of forming a circuit element in the second region after the step of forming the thermopile;
Forming an upper layer covering the first region and the second region;
Digging the upper layer partway in the first region;
Forming an etching hole in which the semiconductor substrate is exposed by further digging down the upper layer in a part of the region where the upper layer is dug down partway;
Forming a sensor part by etching a part of the semiconductor substrate in the first region through the etching hole to float the thermopile support layer and the thermopile from the semiconductor substrate,
The method for manufacturing an infrared sensor, wherein an upper surface of the sensor unit is positioned lower than an upper surface of the upper layer in the second region.   The method for manufacturing an infrared sensor according to claim 1, wherein the step of forming the thermopile support layer includes a step of forming an oxide film by a LOCOS method.   The method for manufacturing an infrared sensor according to claim 1, wherein the upper layer includes a wiring layer therein. A semiconductor substrate having a recess on the upper surface;
An upper layer formed above the semiconductor substrate and having a sensor opening which is an opening corresponding to the recess;
A sensor portion supported in the sensor opening in a state separated from the inner surface of the recess so as to be connected to at least one location on the inner periphery of the sensor opening;
The sensor unit includes a thermopile,
In a place different from the sensor opening in plan view, a peripheral circuit region in which circuit elements are formed inside the upper layer is provided,
An infrared sensor, wherein an upper surface of the sensor unit is positioned lower than an upper surface of the upper layer in the peripheral circuit region.

Images