JP2014170826A - Wiring structure, method for forming wiring, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the value of resistance of a wiring comprising a polycrystalline conductor.SOLUTION: A graphene film 6 comprising a single layer or multiple laminated layers of graphene 61 having a plurality of graphene domains is formed on a polycrystalline conductor 5. Specifically, the graphene domains are preferably configured so as to be located above the grain boundary of the polycrystalline conductor 5 and to be located to extend over between crystals of the polycrystalline conductors 5 adjacent each other with the grain boundary sandwiched therebetween.

Description

  The present invention relates to a wiring structure using graphene, a wiring forming method, and an electronic device having the wiring structure.

  As wiring in electronic devices such as semiconductor devices and liquid crystal display devices, for example, aluminum, aluminum alloys, copper, copper alloys, and the like are frequently used. In recent years, it has been necessary to miniaturize wiring along with miniaturization and high integration of electronic devices, and it has become very important to reduce the resistance value of wiring. Therefore, a technique has been proposed in which the density of crystal grain boundaries existing inside the wiring body is reduced to lower the resistance value of the wiring (for example, see Patent Document 1).

JP 2010-147311 A (paragraph 0012, etc.)

  As described above, in Patent Document 1, the wiring is made of a polycrystalline conductor, and attention is paid to the fact that the resistance value of the wiring is influenced by the density of the crystal grain boundary. Technology has been proposed. However, the effect of reducing the resistance value by reducing the density of crystal grain boundaries is limited, and a technique for further reducing the resistance value is desired.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing the resistance value of a wiring composed of a polycrystalline conductor, and an electronic device using the technique. .

  The wiring structure according to the present invention is characterized in that a graphene film formed by stacking a single layer or a plurality of layers of graphene having a plurality of graphene domains is formed on a polycrystalline conductor. The wiring forming method according to the present invention includes a conductor forming step of forming a polycrystalline conductor on a substrate, and a single layer or a plurality of layers of graphene having a plurality of graphene domains on the polycrystalline conductor. And a graphene film forming step of forming a graphene film. In the invention configured as described above, as described in detail later, the resistance value of the polycrystalline conductor is significantly reduced by adopting a wiring structure in which a graphene film is formed on the polycrystalline conductor.

  Here, the principle that the above-described phenomenon of reduction in electrical resistance occurs is currently being intensively verified and is not clear. However, the specific experimental results indicate that the graphene domain is located above the crystal grain boundary of the polycrystalline conductor across the crystal grain boundary and between adjacent polycrystalline conductor crystals to reduce electrical resistance. It was found that it contributed greatly to.

  In addition, in order to reduce the resistance value of the polycrystalline conductor, it is desirable to reduce not only the combined effect with the graphene film as described above but also the resistance value of the polycrystalline conductor itself. Therefore, it is preferable to anneal the polycrystalline conductor before executing the graphene film forming step.

  Note that when a structure having the above wiring structure is used as an electrical wiring in an electronic device, power saving and high speed of the electronic device can be achieved.

It is a figure for demonstrating one Embodiment of the wiring formation method concerning this invention. It is the photograph which imaged the surface of the copper wiring after annealing treatment with the scanning electron microscope. It is the photograph which imaged the surface of the graphene film formed on copper wiring with the scanning electron microscope.

  FIG. 1 is a view for explaining an embodiment of a wiring forming method according to the present invention. FIG. 1A shows an example of a wiring manufacturing system for carrying out the wiring forming method. FIG. 4B is a schematic diagram for explaining the wiring forming method. FIG. 4C is not directly related to the wiring formation method, but is a reference diagram for explaining the operation effect of the wiring manufactured by the wiring formation method. In FIG. It is a figure which shows typically manufacture of the graphene film to the glass substrate by the graphene film-forming apparatus of this.

  The wiring manufacturing system 1 includes a plasma sputtering apparatus 2 and a graphene film forming apparatus 3, and forms copper (Cu) as an example of a polycrystalline conductor on a base material 4 such as a glass substrate. The resistance value of the copper wiring is greatly reduced by forming a graphene film on the copper wiring.

  Among these apparatuses, in the plasma sputtering apparatus 2, after the base material 4 such as a glass substrate is carried into the processing chamber from the outside of the apparatus (arrow R1 in the figure), the inside of the processing chamber reaches a predetermined degree of vacuum. In this state, a copper target is sputtered, whereby a thin-film copper wiring 5 is deposited on the surface of the substrate 4. In the present embodiment, a sputtering process is performed for 30 minutes while maintaining the temperature in the processing chamber at 200 [° C.] to form a copper wiring 5 having a thickness of about 200 [nm] on the substrate 4 (b-1). : Conductor formation step). And when the base material 4 was taken out from the processing chamber and the resistance value of the copper wiring 5 deposited on the base material 4 was measured, it was 25 to 30 [Ω].

When the formation of the copper wiring 5 is completed in this way, the base material 4 on which the copper wiring 5 is formed is taken out from the plasma sputtering apparatus 2 and transferred to the graphene film forming apparatus 3 (arrow R2 in the figure). The graphene film forming apparatus 3 employed in the present embodiment has the same configuration as the apparatus described in Japanese Patent Application Laid-Open No. 2012-20915. That is, the graphene film forming apparatus 3 has a CVD (Chemical Vapor Deposition) reaction vessel made of a quartz tube. Argon (Ar) or hydrogen (H ₂ ) is introduced as a carrier gas from one side of the quartz tube and exhausted from the other side, and an argon flow is formed inside the quartz tube. Further, inside the quartz tube, a container for storing camphor, which is a raw material for graphene, is disposed, and a tray for supporting the base material 4 is disposed on the downstream side of the container in the direction of the argon flow. .

  Two types of heating units are provided around the outside of the quartz tube. More specifically, one heating part is provided corresponding to the arrangement position of the container, and controls the ambient temperature of the container to a predetermined temperature range. The other heating unit is provided corresponding to the position of the tray, and controls the ambient temperature of the substrate 4 supported by the tray within a predetermined temperature range. As described above, since the two heating units can be controlled independently, the graphene film forming apparatus 3 configured as described above has not only the film forming function of the graphene film but also the base material 4. It is operable so as to exhibit an annealing process function of annealing the deposited copper wiring 5. That is, when the base material 4 on which the copper wiring 5 is formed is transported to the tray, at this stage, only the heating part on the tray side is operated while a certain amount of hydrogen is allowed to flow without putting the container containing the camphor into the quartz tube. The copper wiring 5 is annealed (b-2: annealing process). In this embodiment, by annealing at 550 [° C.] for 3 hours, as shown in the scanning electron micrograph of FIG. 2, the copper wiring 5 is adjusted to an average particle size of about 20 to 30 [μm], The resistance value also decreases from the value before annealing (25-30 [Ω]) to 6-8 [Ω]. However, this resistance value does not sufficiently satisfy the market demand, and further reduction is required.

  Therefore, in the present embodiment, when the annealing process by the graphene film forming apparatus 3 is completed, the supply of argon is continued, and the container containing the camphor is kept while keeping the temperature of the heating unit on the tray side at 550 [° C.]. It is put into a quartz tube, and the ambient temperature of the container is raised to a temperature suitable for the vaporization of camphor by the heating part on the container side. Thereby, the vaporized camphor is transported on the surface of the copper wiring 5 by the argon flow, and is thermally decomposed on the surface of the copper wiring 5. Then, a graphene film 6 made of carbon atoms is formed on the copper wiring 5. This graphene film 6 is formed by laminating a single layer or a plurality of layers of graphene (or sometimes referred to as “graphene sheet”) 61. In this embodiment, the graphene film 6 having a thickness of about 1 [nm] is formed on the copper wiring 5 by stacking three layers. When film formation of the graphene film 6 is completed in this way, the base material 4 is unloaded from the processing chamber from the graphene film formation apparatus 3 (arrow R3 in the figure).

  And when the resistance value of the copper wiring 5 by which the graphene film 6 was formed on the surface was measured, it has fallen to 1-2 [ohm]. Here, in order to consider the reason for reducing the resistance value, the resistance value of the graphene film 6 alone was measured, and the wiring structure manufactured by the wiring manufacturing system 1 was examined in detail. First, since there is a possibility that the resistance value of the copper wiring 5 is lowered due to the low resistance value of the graphene film 6, the graphene film 6 is formed on the substrate 4 as shown in FIG. A simple substance was deposited and its resistance value was measured. As a result, the resistance value of the graphene film 6 alone was 2 to 4 [kΩ]. This is considered to be caused by the fact that the graphene 61 constituting the graphene film 6 is a so-called polycrystalline layer having a plurality of graphene domains as described below. In other words, each graphene domain has a carbon six-membered ring network structure, and in the graphene domain, the electron mobility is extremely high, and the resistance value at room temperature is lower than that of the smallest silver. Yes. However, since there are a plurality of graphene domains in the graphene 61, it is considered that the resistance value is significantly increased.

  Therefore, the graphene film 6 formed on the copper wiring 5 by the wiring manufacturing system 1 was imaged with a scanning electron microscope. As a result, as shown in the electron micrograph of FIG. 3, the graphene 61 is not a single crystal but is composed of a plurality of graphene domains 62 having an average particle size of about 10 to 50 [μm] (in FIG. 3). The white dotted line shows part of the graphene domain). Furthermore, when the relationship between the graphene domain 62 and the crystal grain boundary of the copper wiring 5 was observed, it was found that a part of the graphene domain 62 existed across the crystal grain boundary of the copper wiring 5. . From these facts, it is presumed that the existence of the graphene domain 62 at the crystal grain boundary of the copper wiring 5 causes electron movement in a movement path that has not been clarified so far and the resistance value of the copper wiring 5 is greatly reduced. The In order to elucidate the mechanism by which the phenomenon that the resistance value of the copper wiring 5 decreases as described above, various experiments and verifications are still ongoing.

  As described above, in the present embodiment, by forming the graphene film 6 on the polycrystalline copper wiring 5, the resistance value of the copper wiring 5 can be significantly reduced. Further, by forming the graphene film 6 on the copper wiring 5, the graphene film 6 functions as a protective film on the surface of the copper wiring 5, and exhibits a function of preventing the surface oxidation of the copper wiring 5. In addition, since the graphene film 6 has excellent thermal conductivity, it also has a function of promoting heat dissipation from the copper wiring 5. Furthermore, since copper functions as a catalyst for accelerating the growth of graphene, the combination of the copper wiring 5 and the graphene film 6 is preferable also in this respect.

  The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above embodiment, the copper wiring 5 is formed by plasma sputtering, but the manufacturing method is not limited to this, and the copper wiring 5 may be formed on the substrate 4 by any method. .

  In the above embodiment, copper (face-centered cubic structure: lattice constant = 0.61496 [nm]) is used as the wiring material. However, other wiring materials such as aluminum (face-centered cubic structure: lattice constant = 0.404934 [nm] are used. ], Nickel (face-centered cubic structure: lattice constant = 0.524 [nm]), gold (face-centered cubic structure: lattice constant = 0.407864 [nm]), alloys thereof, and the like can be used. The above lattice constants are values around room temperature. Further, ITO (Indium Tin Oxide), which is frequently used as a transparent electrode, may be used as a wiring material, and a graphene film may be formed on the ITO to reduce the resistance value of the ITO. Thus, by adopting the electrode structure according to the present invention for electronic devices such as semiconductor devices, liquid crystal display devices and solar cells, it is possible to achieve power saving, high speed and high efficiency of the electronic devices. It is suitable as an application object of the electrode structure according to the invention.

  Furthermore, in the above embodiment, the graphene film 6 is formed by stacking three layers of graphene 61, but the graphene 61 constituting the graphene film 6 is not limited to this, and is a single layer, two layers, or four layers. You may comprise in a layer or more.

  The present invention can be suitably applied to a wiring technique for reducing the resistance value of a polycrystalline conductor and to all electronic devices having the wiring.

4 ... Substrate 5 ... Copper wiring 6 ... Graphene film 61 ... Graphene

Claims (6)

  A wiring structure, wherein a graphene film formed by stacking a single layer or a plurality of layers of graphene having a plurality of graphene domains is formed over a polycrystalline conductor. The wiring structure according to claim 1,
A wiring structure in which a part of the plurality of graphene domains is located between crystal grains adjacent to each other across the crystal grain boundary above the crystal grain boundary of the polycrystal conductor. A conductor forming step of forming a polycrystalline conductor on the substrate;
And a graphene film forming step of forming a graphene film by stacking a single layer or a plurality of layers of graphene having a plurality of graphene domains on the polycrystalline conductor. The wiring forming method according to claim 3,
In the graphene film forming step, the graphene film is formed so that the plurality of graphene domains straddle between the crystals of the polycrystalline conductor adjacent to each other across the crystal grain boundary above the crystal grain boundary of the polycrystalline conductor. A wiring forming method to be formed. It is the wiring formation method of Claim 3 or 4,
A wiring forming method comprising an annealing step of annealing the polycrystalline conductor to reduce a resistance value of the polycrystalline conductor before performing the graphene film forming step.   An electronic device using the structure having the wiring structure according to claim 1 as electric wiring.