JP2014166060A - Power storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power storage device capable of protecting a cell in which heightening of resistance occurred from overvoltage breakdown, and also capable of generally maintaining the capacity of a power storage unit as a whole even when heightening of resistance occurs in some cells.SOLUTION: An uninterruptible power supply device is provided with a module in which DC power is stored. The module includes a plurality of cells 1 and a plurality of short circuits 10. The plurality of cells 1 each have a positive electrode T1 and a negative electrode T2, and are connected in series. The plurality of short circuits 10 are connected to the plurality of cells 1 in parallel, respectively. The plurality of short circuits 10 each have a transistor Q1 and a voltage detection unit VD1. The transistor Q1 is electrically connected between the positive electrode T1 and the negative electrode T2 of a corresponding cell, and, in response to a conductivity signal S1, transitions from a non-conductive state to a conductive state. The voltage detection unit VD1 detects an inter-electrode voltage V1 between the positive electrode T1 and the negative electrode T2, and outputs the conductivity signal S1 when the inter-electrode voltage V1 exceeds a prescribed reference voltage E1.

Description

  The present invention relates to a power storage device.

  The uninterruptible power supply device includes a storage battery or an electric double layer capacitor as a power storage unit. The rated voltage per cell of the storage battery or the electric double layer capacitor is, for example, 2 to 4V. The charge / discharge voltage of the power storage unit is adjusted by connecting a large number of cells in series. A plurality of cells connected in series is also called a module. In order to secure the necessary capacity, a plurality of modules are connected in parallel to constitute a power storage unit.

  Due to factors such as manufacturing variations, the capacitance of each cell may be non-uniform. The relationship among the charging current I, voltage V, and capacitance C in an ideal capacitor is expressed as I = CdV / dt. An equal charging current I flows in all the cells connected in series. For this reason, the voltage of a cell having a small capacitance increases faster than the voltage of a cell having a large capacitance.

  It is necessary to charge so that all the cells do not exceed the withstand voltage. However, when the voltage of a cell having a large capacitance is charged to a fully charged state, the voltage of the cell having a small capacitance may exceed the withstand voltage. On the other hand, if charging is performed so that the voltage of a cell having a small capacitance is less than the withstand voltage, the cell having a large capacitance cannot be charged to a fully charged state.

  In order to solve the above problems, a configuration for adjusting the cell voltage using a voltage dividing resistor has been proposed. For example, a capacitor power storage device disclosed in Japanese Patent Laid-Open No. 2001-178209 (Patent Document 1) is configured by connecting a plurality of capacitors in series in a plurality of stages. This capacitor power storage device includes a voltage dividing resistor connected in parallel with each stage capacitor. The setting criterion for the lower limit value of the resistance value of the voltage dividing resistor is that the current dividing ratio to the voltage dividing resistor at the time of initial charging of the capacitor power storage device is 10% or less. In addition, the setting criterion for the upper limit value of the resistance value of the voltage dividing resistor is that the combined resistance value of the leakage resistance and the voltage dividing resistance of each capacitor is 10% or less.

JP 2001-178209 A

  By applying voltage, the electrode or the electrolytic solution may be deteriorated. Alternatively, the electrolyte can evaporate over time. Due to these factors, the internal resistance of the cell increases. This phenomenon is called increasing the resistance of the cell. As the resistance of a cell increases, the cell may reach an open failure. An open failure is a failure in which the cell electrodes are open. An open failure may occur due to, for example, disconnection or poor electrode contact.

  For example, when the charged state is continued for a long time, the resistance can be increased in some cells. In the steady state, the voltage applied to the module is divided in proportion to the resistance value of each cell. For this reason, as the resistance of the cell increases, the voltage applied to the cell gradually increases. Therefore, the voltage applied to the cell may exceed the breakdown voltage of the cell.

  Generally, a power storage unit includes a large number of cells. As an example, the power storage unit includes five modules connected in parallel. Each module includes, for example, 250 cells connected in series. When the resistance of one of the 250 cells is increased, a voltage exceeding the withstand voltage may be applied to the cell. Therefore, the cell may be destroyed by overvoltage. Alternatively, when a cell open failure occurs due to disconnection or the like, the cell may be destroyed by overvoltage. This makes the module containing the cell useless. If one module becomes useless, the capacity of the power storage unit is greatly reduced. There is a possibility that the required performance for the power storage unit cannot be satisfied with only the remaining four modules. Therefore, even when some cells become useless, it is required to maintain the capacity of the entire power storage unit.

  In the capacitor power storage device disclosed in Patent Document 1, an overvoltage protection circuit is connected in parallel to each cell. The overvoltage protection circuit prevents the voltage applied to the cell with the increased resistance from exceeding a predetermined reference voltage in a steady state. Thereby, it is possible to prevent the cell in which the resistance is increased from being destroyed by overvoltage.

  However, in the capacitor power storage device disclosed in Patent Document 1, there is a possibility that a voltage exceeding the withstand voltage may be applied to the cell in which the resistance is increased in a transient state (for example, during discharge). Therefore, it is impossible to prevent overvoltage breakdown of the cell in which the resistance is increased.

  An object of the present invention is to provide a power storage device that protects cells with increased resistance from overvoltage breakdown and that can generally maintain the capacity of the entire power storage unit even when higher resistance occurs in some cells. That is.

  According to one aspect of the present invention, a power storage device includes a power storage module. The power storage module includes a plurality of cells and a plurality of first overvoltage protection circuits. Each of the plurality of cells has a positive electrode and a negative electrode and is connected in series. The plurality of first overvoltage protection circuits are respectively connected in parallel to the plurality of cells. Each of the plurality of first overvoltage protection circuits includes a first switch and a first voltage detection unit. The first switch is electrically connected between the positive electrode and the negative electrode of the corresponding cell of the plurality of cells, and shifts from the non-conductive state to the conductive state in response to the first conductive signal. The first voltage detection unit detects a voltage between the positive electrode and the negative electrode, and outputs a first conduction signal when the voltage between the electrodes exceeds a predetermined first reference voltage.

  Preferably, the first reference voltage is set higher than the inter-electrode voltage in the fully charged state of each of the plurality of cells.

  Preferably, the power storage module further includes a plurality of second overvoltage protection circuits. The plurality of second overvoltage protection circuits are respectively connected in parallel to the plurality of cells. Each of the plurality of second overvoltage protection circuits includes a second voltage detection unit, a shunt resistor, and a second switch. The second switch is electrically connected between the positive electrode and the negative electrode of the corresponding cell of the plurality of cells, and shifts from the non-conductive state to the conductive state in response to the second conductive signal. The second voltage detection unit detects a voltage between the positive electrode and the negative electrode, and outputs a second conduction signal when the voltage between the electrodes exceeds a predetermined second reference voltage. The shunt resistor is connected in series with the second switch. The second reference voltage is set higher than the inter-electrode voltage in the fully charged state and lower than the first reference voltage.

  Preferably, the power storage module further includes a spare cell connected in series to the plurality of cells in preparation for an open failure of any of the plurality of cells.

  Preferably, the power storage module further includes a plurality of voltage dividing resistors. The plurality of voltage dividing resistors are respectively connected in parallel to the plurality of cells.

  Preferably, the DC power supply is a converter that converts AC power supplied from the AC power supply into DC power. The power storage device further includes a converter and an inverter. The inverter is configured to convert DC power from the converter and DC power stored in the power storage module into AC power and supply the AC power to the load.

  Preferably, the power storage device further includes a warning unit that issues a warning and a control circuit that controls the warning unit. The control circuit receives a signal indicating whether or not the first conduction signal is output from each of the plurality of first overvoltage protection circuits. The control circuit controls the warning unit to issue a warning when the signal indicates the output of the first conduction signal in at least one of the plurality of first overvoltage protection circuits.

  According to the present invention, it is possible to provide a power storage device that protects cells with increased resistance from overvoltage breakdown and can maintain the capacity of the power storage unit as a whole even when some of the cells have increased resistance. be able to.

1 is a circuit block diagram schematically showing a power storage device according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram schematically showing a configuration of a power storage unit shown in FIG. 1. It is a circuit diagram which shows roughly the structure of the 2nd overvoltage protection circuit with which the conventional electrical storage apparatus is provided. FIG. 2 is a circuit diagram schematically showing a configuration of a first overvoltage protection circuit included in the power storage device shown in FIG. 1. FIG. 5 is a diagram for comparing changes in the voltage between electrodes accompanying the increase in resistance of a cell in the first and second overvoltage protection circuits shown in FIGS. 3 and 4, respectively. FIG. 3 is a diagram for explaining discharge of the power storage unit shown in FIG. 2. FIG. 5 is a diagram for comparing changes in the interelectrode voltage when the power storage unit is discharged in the first and second overvoltage protection circuits shown in FIGS. 3 and 4, respectively. It is a figure for demonstrating the voltage drop in each cell to which the voltage dividing circuit was connected in parallel after discharge of an electrical storage part. FIG. 3 is a diagram for describing a configuration in which redundancy is provided for the number of cells in the power storage unit illustrated in FIG. 2. FIG. 5 is a diagram for explaining transmission of a first conduction signal from the first overvoltage protection circuit shown in FIG. 4 to the control circuit. It is a circuit block diagram which shows roughly the structure of the 1st and 2nd overvoltage protection circuit with which the electrical storage apparatus which concerns on Embodiment 2 of this invention is provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or an equivalent part in a figure, and the description is not repeated.

[Embodiment 1]
FIG. 1 is a circuit block diagram schematically showing the configuration of the uninterruptible power supply according to Embodiment 1 of the present invention. Referring to FIG. 1, uninterruptible power supply (power storage device) 100 is an uninterruptible power supply of a constant inverter power supply system, for example. The uninterruptible power supply 100 includes a power storage unit 3, a converter 4, an inverter 5, an insulation transformer 6, a control circuit 8, a switch 91, an uninterruptible switching switch (Static Transfer Switch) 92, and a warning unit 9. With. The “power storage device” according to the present invention is not particularly limited to an uninterruptible power supply device as long as it includes a power storage unit.

  Each of AC power supplies 71 and 72 supplies AC power, for example, a three-phase AC power supply. Each of AC power supplies 71 and 72 may be a single-phase AC power supply. The uninterruptible power supply 100 receives AC power from the AC power source 72 and supplies the AC power to the load 11. Further, uninterruptible power supply 100 is configured to receive AC power from AC power supply 71 of another system in order to continue power supply even when converter 4 or inverter 5 fails.

  One terminal of the switch 91 receives an AC voltage from the AC power supply 71. The other terminal of the switch 91 is electrically connected to the load 11. The uninterruptible changeover switch 92 is connected to the switch 91 in parallel.

  The control circuit 8 controls the uninterruptible power supply 100. The control circuit 8 is a microcomputer, for example. Converter 4 converts AC power from AC power supply 72 into DC power based on control signal CTRL 1 from control circuit 8, and supplies the DC power to inverter 5 and power storage unit 3. Power storage unit 3 stores the DC power generated by converter 4. Power storage unit 3 is, for example, a storage battery such as a lithium ion battery, a nickel metal hydride battery, or a lead storage battery, or a capacitor such as an electric double layer capacitor or a lithium ion capacitor. Inverter 5 converts DC power from converter 4 or power storage unit 3 into AC power based on control signal CTRL 2 from control circuit 8, and outputs the AC power to insulating transformer 6. The insulation transformer 6 transmits the AC voltage from the inverter 5 to the load 11.

  The load 11 is not particularly limited as long as it is an electrical device that consumes AC power. The load 11 is, for example, a personal computer or a server.

  The warning unit 9 issues a warning to the user or administrator of the uninterruptible power supply 100 based on the control by the control circuit 8 when an abnormality occurs in the power storage unit 3. As a method of issuing a warning, it is possible to employ a technique such as lighting an abnormality notification lamp (not shown), generating a warning sound, or displaying a message on a display screen (not shown) of the control circuit 8. it can.

  Uninterruptible power supply 100 has an inverter power supply mode and a bypass power supply mode. In the inverter power supply mode, converter 4 converts AC power from AC power supply 72 into DC power, and supplies the DC power to converter 4 and power storage unit 3. Inverter 5 converts the DC power from converter 4 or power storage unit 3 into AC power and outputs the AC power to insulating transformer 6. Each of the switches 91 and 92 is non-conductive.

  When the failure of the inverter 5 or the converter 4 occurs, the uninterruptible power supply 100 switches from the inverter power supply mode to the bypass power supply mode. In the bypass power supply mode, the uninterruptible changeover switch 92 shifts from the non-conductive state to the conductive state based on the control by the control circuit 8. Thereby, AC power can be supplied to the load 11 so as not to be interrupted. Further, the switch 91 shifts from a non-conductive state to a conductive state based on control by the control circuit 8. The uninterruptible change-over switch 92 is switched again to the non-conductive state after the switch 91 shifts to the conductive state. Thus, in the bypass power supply mode, AC power from the AC power supply 71 is directly supplied to the load 11. On the other hand, the operation of converter 4 and inverter 5 is stopped based on the control by control circuit 8.

  FIG. 2 is a circuit diagram schematically showing the configuration of power storage unit 3 shown in FIG. Referring to FIG. 2, power storage unit 3 includes n (n is a natural number) modules (power storage modules) 21 to 2n connected in parallel. Each of the modules 21 to 2n includes m (m is a natural number) cells 1 connected in series. As an example, m = 250 and n = 5. When the rated voltage of each cell 1 is about 2.5V, the rated voltage of each module is about 625V. In addition, although the inverter 5 (refer FIG. 1) is also connected to the electrical storage part 3, in FIG. 2, since it becomes complicated, only the converter 4 is shown.

  The above configuration is not limited to uninterruptible power supply 100 according to Embodiment 1, but is common to conventional uninterruptible power supplies. Also in the conventional uninterruptible power supply, each cell is provided with an overvoltage protection circuit. First, an overvoltage protection circuit provided in a conventional power storage device will be described.

  FIG. 3 is a circuit diagram schematically showing a configuration of a voltage dividing circuit provided in a conventional uninterruptible power supply. Referring to FIG. 3, cell 1 includes a positive electrode T1 and a negative electrode T2. A voltage dividing resistor R and a voltage dividing circuit 20 are connected in parallel between the positive electrode T1 and the negative electrode T2 of the cell 1 (between the electrodes).

  The cell 1 is represented by an equivalent circuit including a capacitor C, an internal resistance Ra, and a leakage resistance Rb. An internal resistor Ra and a capacitor C are connected in series between the electrodes of the cell 1. The leakage resistance Rb is a resistance component corresponding to the magnitude of the leakage current of the capacitor C. Leakage resistance Rb is connected in parallel to a series circuit of internal resistance Ra and capacitor C.

  At the time of initial charging in which no charge is accumulated in the capacitor C, each cell 1 is charged according to the inverse ratio (reciprocal ratio) of the capacitance of the capacitor C with respect to the other cells 1. In other words, the ratio of the voltage of the cell having the capacitance C1 and the voltage of the cell having the capacitance C2 is expressed as 1 / C1: 1 / C2. Even in the steady state after the charging is completed, the charging voltage is continuously applied to the module.

  The resistance value of leakage resistance Rb (for example, 1,000Ω) is significantly higher than the resistance value of internal resistance Ra (for example, 2 mΩ). When the charging state of the module is continued for a long period of time, the voltage between the positive electrode T1 and the negative electrode T2 of each cell 1 (hereinafter also referred to as an interelectrode voltage V2) is a leakage resistance Rb between the other cells 1. It converges to the direct ratio of the resistance value. In other words, the voltage between the electrodes of the cell having the leakage resistance Rb1 (not shown) and the voltage between the electrodes of the other cells having the leakage resistance Rb2 (not shown) converge to a ratio represented by Rb1: Rb2. To do.

  Due to factors such as manufacturing variations, the resistance value of the leakage resistance Rb may be non-uniform. For this reason, the voltage dividing resistor R is connected in parallel between the electrodes of the cell 1 in order to reduce the influence of the variation in the resistance value of the leakage resistance Rb on the interelectrode voltage V2. Thereby, the interelectrode voltage V2 of each cell 1 after a long period of time becomes a voltage proportional to the combined resistance value (Rb × R / (Rb + R)) of the leakage resistance Rb and the voltage dividing resistance R in each cell 1. . In other words, although not shown, the ratio between the interelectrode voltage of the cell having the leakage resistance Rb10 and the voltage dividing resistance R10 and the interelectrode voltage of other cells having the leakage resistance Rb20 and the voltage dividing resistance R20 is (Rb10 × R10 / (Rb10 + R10)): converges to (Rb20 × R20 / (Rb20 + R20)). The resistance value (for example, 100Ω) of the voltage dividing resistor R is set to an order of magnitude smaller than the resistance value (for example, 1,000Ω) of the leakage resistance Rb. For this reason, the combined resistance value of the leakage resistance Rb and the voltage dividing resistance R is substantially determined by the resistance value of the voltage dividing resistance R. The variation in resistance value of the voltage dividing resistor R is smaller than the variation in resistance value of the leakage resistance Rb. Therefore, it is possible to reduce the influence of variation in the resistance value of the leakage resistance Rb in the interelectrode voltage V2.

  The voltage dividing circuit 20 includes a voltage detection unit VD2, a shunt resistor R2, and a transistor (second switch) Q2. The voltage detection unit VD2 detects the interelectrode voltage V2 of the cell 1. The voltage detection unit VD2 compares the interelectrode voltage V2 with a predetermined reference voltage E2, and outputs a signal indicating the comparison result from the output node. The reference voltage E2 is given by a known reference voltage generation circuit (not shown). The interelectrode voltage V2 of the cell 1 is the highest when the cell 1 is fully charged. As the discharge of the cell 1 proceeds, the interelectrode voltage V2 decreases. The reference voltage E2 is set higher than the interelectrode voltage V2 when the cell 1 is fully charged. As an example, when the voltage V2 between the electrodes in the fully charged state of the cell 1 is 2.5V, the reference voltage E2 is set to 2.6V.

  The transistor Q2 is, for example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The drain and source of the transistor Q2 are electrically connected between the electrodes of the cell 1. The gate of transistor Q2 is electrically connected to the output node of voltage detector VD2. The shunt resistor R2 is provided to shunt the charge / discharge current of the cell 1. The shunt resistor R2 is electrically connected between the drain of the transistor Q2 and the positive electrode T1.

  When the interelectrode voltage V2 exceeds the reference voltage E2, the voltage detection unit VD2 outputs a conduction signal (second conduction signal: logic high) S2 to the gate of the transistor Q2. Transistor Q2 transitions from the non-conducting state to the conducting state in response to conduction signal S2.

  Next, an overvoltage protection circuit included in the power storage device according to Embodiment 1 will be described. FIG. 4 is a circuit diagram schematically showing a configuration of a short circuit included in uninterruptible power supply 100 shown in FIG. Referring to FIG. 4, short circuit (first overvoltage protection circuit) 10 is different from voltage dividing circuit 20 shown in FIG. 3 in that it does not include shunt resistor R2. The conduction signal S1 from the voltage detection unit (first voltage detection unit) VD1 is also output to the control circuit 8. Since the other configuration of the short circuit 10 is the same as the configuration of the voltage dividing circuit 20, detailed description will not be repeated. The short circuit 10 corresponds to a “first overvoltage protection circuit” according to the present invention. The voltage dividing circuit 20 corresponds to a “second overvoltage protection circuit” according to the present invention.

  The voltage detector VD1 detects the interelectrode voltage V1 of the cell 1 and compares the interelectrode voltage V1 with a predetermined reference voltage E1. The reference voltage E1 is set larger than the reference voltage E2. As an example, when the voltage V2 between the electrodes in the fully charged state of the cell 1 is 2.5V and the reference voltage E2 is 2.6V, the reference voltage E1 is set to 2.8V. Therefore, the reference voltage E1 is higher than the maximum value of the voltage applied between the electrodes of the plurality of cells 1 when the modules 21 to 2n are fully charged. The reference voltage E2 is higher than the maximum value of the voltage applied between the electrodes of the plurality of cells 1 when the modules 21 to 2n are fully charged, and is lower than the reference voltage E1.

  When the interelectrode voltage V1 exceeds the reference voltage E1, the voltage detection unit VD1 outputs a conduction signal (first conduction signal: logic high) S1 to the gate of the transistor (first switch) Q1. Transistor Q1 shifts from the non-conductive state to the conductive state in response to conductive signal S1.

  FIG. 5 is a diagram for comparing changes in the interelectrode voltages V1, V2 due to the increase in resistance of the cell 1 in the voltage dividing circuit 20 and the short circuit 10 shown in FIGS. 3 and 4, respectively. FIG. 5A shows the interelectrode voltage V2 in the cell 1 to which the voltage dividing circuit 20 is connected in parallel. FIG. 5B shows the interelectrode voltage V1 in the cell 1 to which the short circuit 10 is connected in parallel.

  First, the interelectrode voltage V2 in the cell 1 to which the voltage dividing circuit 20 is connected in parallel will be described with reference to FIG. Time t0 is an arbitrary time in a state where no charge is stored in the cell 1. At time tch, constant voltage charging by applying charging voltage Ech is started.

  During the period from time tch to time t1, cell 1 is fully charged. During this time, a constant charging voltage Ech is continuously applied to the cell 1.

  At time t1, the increase in the internal resistance Ra of the cell 1 starts. On the other hand, the internal resistance Ra of other normal cells does not change. The charging voltage Ech is divided into each cell according to the resistance value of each cell (the combined resistance value of the internal resistance Ra, the leakage resistance Rb, and the voltage dividing resistance R). Therefore, the interelectrode voltage V2 of the cell 1 increases.

  At time t2, the interelectrode voltage V2 of the cell 1 exceeds the reference voltage E2. The voltage detector VD2 detects this and outputs a conduction signal S2 to the gate of the transistor Q2. Transistor Q2 transitions from the non-conducting state to the conducting state in response to conduction signal S2. The combined resistance value of the shunt resistor R2 and the on-resistance of the transistor Q2 is smaller than the resistance value of the cell 1 in which the resistance is increased. Therefore, the charging current that has been flowing through the cell 1 flows mainly between the shunt resistor R2 and the drain-source of the transistor Q2. Since the charging current hardly flows through the cell 1, the energy stored in the cell 1 does not increase. Therefore, the interelectrode voltage V2 of the cell 1 is maintained at the reference voltage E2.

  Next, the interelectrode voltage V1 of the cell 1 to which the short circuit 10 is connected in parallel will be described with reference to FIG. The change in the interelectrode voltage V1 up to the time t1 is the same as the change in the interelectrode voltage V2 up to the same time, so the detailed description will not be repeated. The reference voltage E1 is set higher than the reference voltage E2. Therefore, the increase in the interelectrode voltage V1 accompanying the increase in the internal resistance Ra of the cell 1 continues from time t2 to time t3 when more time has passed.

  At time t3, the interelectrode voltage V1 exceeds the reference voltage E1. The voltage detector VD1 detects this and outputs a conduction signal S1 to the gate of the transistor Q1. Transistor Q1 shifts from the non-conductive state to the conductive state in response to conductive signal S1. That is, the electrodes of the cell 1 are short-circuited. The on-resistance of the transistor Q1 is significantly smaller than the combined resistance value of the leakage resistance Rb and the voltage dividing resistance R. For this reason, the electric charge stored in the cell 1 is discharged through the drain-source of the transistor Q1. Therefore, the interelectrode voltage V1 of the cell 1 is 0V.

  Thus, the short circuit 10 and the voltage dividing circuit 20 can prevent the increase of the interelectrode voltages V1 and V2 due to the high resistance of the cell 1, respectively. However, in the voltage dividing circuit 20, there is a possibility that an overvoltage is applied to the cell by charging and discharging. The change due to the discharge of the interelectrode voltages V1, V2 of the cell in which the resistance is increased will be described.

  FIG. 6 is a diagram for explaining the discharge of power storage unit 3 shown in FIG. Referring to FIG. 6, each of modules 21, 2a, 2n includes m cells. The module 2a includes a cell 1a in which the resistance is increased. Cells 1 other than the cell 1a of the module 2a are normal. The cells 1 included in the modules 21 and 2n are all normal. Discharge currents I1 and I2 represent discharge currents flowing through modules 21 and 2n and module 2a, respectively. Each of the cells 1 and 1a is connected to the voltage dividing resistor R and the short circuit 10 or the voltage dividing circuit 20 in parallel, but is not shown in FIG.

  FIG. 7 is a diagram for comparing changes in the interelectrode voltages V1 and V2 when the power storage unit 3 is discharged in the voltage dividing circuit 20 and the short circuit 10 shown in FIGS. 3 and 4, respectively. Referring to FIG. 7, FIG. 7 is contrasted with FIG.

  FIG. 8 is a diagram for explaining a voltage drop in each cell to which the voltage dividing circuit 20 is connected in parallel after the power storage unit 3 is discharged. Referring to FIG. 8, the horizontal axis represents cells in each module. The vertical axis represents the potential of each cell based on the potential of the mth cell. The potential after discharge of each cell in the modules 21 and 2n is indicated by a broken line. The electric potential after the discharge of each cell in the module 2a is indicated by a solid line.

  First, with reference to FIG. 3, FIG. 7 (A), and FIG. 8, the voltage change in the cell 1a to which the voltage dividing resistor R and the voltage dividing circuit 20 are connected in parallel will be described. The change in the interelectrode voltage V2 of the cell 1a up to time t2 is the same as the change in the interelectrode voltage V2 up to the same time in FIG. 5, and thus detailed description will not be repeated.

  At time t4, discharging of the power storage unit 3 is started. As an example, when the rated voltage of each cell is about 2.5V and the number of cells connected in series is 250, the voltage of each of the modules 21, 2a, 2n before the start of discharge is about 625V. is there. The voltage of each of the normal modules 21 and 2n decreases by, for example, 125V due to the discharge. In modules 21 and 2n, each cell 1 is discharged evenly. Therefore, the potential of each cell changes linearly between the cell 1 and the cell m (see the broken line in FIG. 8). That is, the voltage drop in each cell is 125V / 250 = 0.5V.

  In the module 2a including the cell 1a in which the resistance is increased, the normal cell 1 has a resistance value (for example, 2 mΩ) that is significantly smaller than the resistance value of the voltage dividing resistor R (for example, 100Ω). Therefore, the discharge current I2 flows through the cell 1.

  On the other hand, the resistance value (for example, 10,000Ω) of the cell 1a in which the resistance is increased is large. The resistance values of the voltage dividing resistor R and the shunt resistor R2 are, for example, 100Ω. The resistance value (for example, 10 mΩ) of the on-resistance of the transistor Q2 is also small. Therefore, in the cell 1a in which the resistance is increased, the discharge current I2 mainly flows through the voltage dividing resistor R and between the shunt resistor R2 and the drain and source of the transistor Q2.

  Discharge current I2 (for example, 1A) is smaller than discharge current I1 (for example, 10A) flowing through normal modules 21 and 2n. However, the resistance values of the voltage dividing resistor R and the shunt resistor R2 are both relatively large. As a result, the voltage drop ΔV (1A × 100Ω = 100V) at the voltage dividing resistor R and the shunt resistor R2 of the cell 1a is very large (see the solid line in FIG. 8). Thus, when the module 2a is discharged, most of the voltage drop between the cell 1 and the cell m is realized by the voltage drop ΔV at the voltage dividing resistor R or the shunt resistor R2 of the cell 1a. Accordingly, the voltage V2 between the electrodes of the cell 1a greatly increases during discharge. Thereby, there exists a possibility that the cell 1a may lead to overvoltage destruction.

  Next, with reference to FIG. 4 and FIG. 7B, the voltage change in the cell 1a to which the short circuit 10 is connected in parallel will be described. The change in the interelectrode voltage V1 of the cell 1 up to time t3 is the same as the change in the interelectrode voltage V1 up to the same time in FIG.

  At time t4, discharging of the power storage unit 3 is started. The electrodes of the cell 1a are short-circuited by a short circuit 10. As described above, the resistance value (for example, 10 mΩ) of the on-resistance of the transistor Q1 is compared with the resistance value (for example, 10,000Ω) of the cell 1a in which the resistance is increased and the resistance value (for example, 100Ω) of the voltage dividing resistor R. Remarkably small. Therefore, the discharge current I2 mainly flows between the drain and source of the transistor Q1. Even if discharge current I2 (for example, 10 A) is large, the voltage drop at transistor Q1 is very small (for example, 10 A × 10 mΩ = 0.1 V). Accordingly, the interelectrode voltage V1 of the cell 1a hardly changes even during discharge. Therefore, it is possible to prevent the cell 1a from being overvoltage destroyed.

  The change of the interelectrode voltages V1, V2 due to the discharge of the power storage unit 3 has been described. However, before the initial charging of the power storage unit 3 (charging from a state in which no charge is accumulated), an open failure may occur in the cell 1a due to, for example, disconnection or poor contact. At the time of initial charging, a charging current from the converter 4 (see FIG. 1) flows into the module 2a including the cell 1a having the open failure. Although the direction of current differs between charging and discharging, a voltage drop across the resistor occurs regardless of the direction of the current. Therefore, changes in the interelectrode voltages V1, V2 of the cell 1a are the same as described above, and thus the detailed description will not be repeated.

  When the electrodes of one cell 1a are short-circuited, the voltage to be applied to the cell 1a is divided into each of the other normal cells 1. However, many (for example, 250) cells are connected in series to the module. For this reason, the influence on each inter-electrode voltage V1 of the normal cell 1 is slight. As an example, when one cell 1a is short-circuited, the increase amount of the interelectrode voltage V1 of each of the 249 normal cells 1 is only about 0.4%. Therefore, the normal 249 cells 1 continue to function. Therefore, according to Embodiment 1, the capacity of power storage unit 3 can be generally maintained even when the resistance of cell 1a is increased. Thereby, the required performance about the uninterruptible power supply apparatus 100 can be satisfied stably.

  Even when the power loss at each shunt resistor R2 is 1 W, for example, a power loss of 1,250 W occurs as the power storage unit. According to the first embodiment, it is not necessary to provide the shunt resistor R2 in each cell. For this reason, power consumption corresponding to this power loss is reduced. Furthermore, there is no need to provide a cooling fan for removing heat corresponding to this power loss. In general, the cooling fan generates noise and easily breaks down. According to the first embodiment, noise reduction and reliability improvement can be achieved.

  In the conventional uninterruptible power supply, the voltage dividing resistor R or the shunt resistor R2 may be overvoltage destroyed. In general, the voltage dividing resistors R and the voltage dividing circuits 20 of all the cells included in each module are provided on the same substrate. Therefore, even if some of the voltage dividing resistors R or the shunt resistors R2 are damaged, the repair requires replacement of the entire board, resulting in high member costs. According to the first embodiment, the voltage dividing resistor R is prevented from being damaged, so that this cost can be reduced.

  The voltage dividing resistor R may not be provided. In this case, in the voltage dividing circuit 20, the charge / discharge current in the cell 1a mainly flows through the shunt resistor R2. As a result, a voltage drop ΔV occurs at the shunt resistor R2. On the other hand, in the short circuit 10, the charge / discharge current flows between the drain and source of the transistor Q1 as in the above description. The voltage drop at transistor Q1 is very small. That is, changes in the interelectrode voltages V1 and V2 of the cell 1a are the same as described above, and thus detailed description will not be repeated.

  By providing redundancy for the number of cells included in each module, the reliability of the module can be improved. FIG. 9 is a diagram for describing a configuration in which redundancy is provided for the number of cells 1 in power storage unit 3 shown in FIG. 2. With reference to FIG. 9, description will be made using an example of the above-described 250 series × 5 parallel configuration. FIG. 9A is a diagram illustrating a configuration of a power storage unit in a conventional uninterruptible power supply. FIG. 9B is a diagram showing a configuration of power storage unit 3 in uninterruptible power supply 100 according to Embodiment 1.

  Referring to FIG. 9A, a voltage dividing resistor R and a voltage dividing circuit 20 are connected in parallel to each of cells 1 and 1a included in a conventional uninterruptible power supply (see FIG. 3). However, since it becomes complicated, it is not shown in FIG. In the conventional uninterruptible power supply, when the cell 1a has an open failure, the module including the cell 1a (modules 21 and 22 in FIG. 9A) becomes useless. Therefore, a spare module 26 is added to prepare for an open failure of one cell 1. That is, it is necessary to add 250 cells 1.

  On the other hand, referring to FIG. 9B, voltage dividing resistor R and short circuit 10 are connected in parallel to each of cells 1 and 1a included in uninterruptible power supply apparatus 100 according to the first embodiment ( (See FIG. 4). However, since it becomes complicated, it is not shown in FIG. In the uninterruptible power supply 100 according to the first embodiment, each module includes 252 cells 1. That is, two spare cells 1b are added to each of the modules 21 to 25. Even if two cells open fail in the same module, the module contains 250 normal cells. For this reason, the module functions normally. Even if several cells fail further and the number of normal cells falls below 250, the module can function normally.

  Thus, according to the first embodiment, it is possible to ensure the reliability of power storage unit 3 for a longer period of time as compared with the method of providing redundancy in the conventional uninterruptible power supply. Further, according to the first embodiment, it is only necessary to add two cells 1 to each of the five modules 21 to 25. That is, in the conventional uninterruptible power supply apparatus, 250 cells 1 need to be added, whereas according to the uninterruptible power supply apparatus according to Embodiment 1, the number of spare cells 1 may be ten.

  Further, in the conventional uninterruptible power supply, even if one spare module 26 is added, if an abnormality occurs in the cell 1a included in each of the two modules 21 and 22, one unit is consequently obtained. Lack of modules. For this reason, a required capacity cannot be secured. According to the uninterruptible power supply according to Embodiment 1, backup is possible even when an abnormality occurs in a cell included in each of two or more modules. As described above, the uninterruptible power supply 100 according to Embodiment 1 is advantageous from the viewpoint of reducing the member cost and improving the reliability.

  FIG. 10 is a diagram for explaining the transmission of the conduction signal S1 from the short circuit 10 shown in FIG. 4 to the control circuit 8. In FIG. Referring to FIG. 10, each of the plurality of cells 1 generates a conduction signal S1 indicating a conduction command to transistor Q1. Therefore, the same number (for example, 1,250) of conduction signals S1 as the number of cells 1 are generated. However, the number of input terminals (not shown) of the control circuit 8 is limited. Therefore, the OR circuits 81 to 8n and the OR circuit 80 are electrically connected between the plurality of short-circuit circuits 10 and the control circuit 8.

  Each of the modules 21 to 2n includes m cells. OR circuits 81-8n receive m input signals from modules 21-2n, respectively. Each of the OR circuits 81 to 8n outputs a logic high signal to the OR circuit 80 when at least one of the m input signals is the conduction signal S1 (logic high). The OR circuit 80 receives n signals from the OR circuits 81 to 8n. The OR circuit 80 outputs a logic high signal to the control circuit 8 when at least one of the n input signals is logic high. Thereby, when at least one of the total (m × n) voltage detection units VD1 outputs the conduction signal S1, the control circuit 8 can detect it.

  Moreover, the control circuit 8 controls the warning part 9 so that the warning which shows that when the abnormality of the electrical storage part 3 is detected is issued. By receiving this warning, the user or administrator of the uninterruptible power supply 100 can request the manufacturer or maintenance manager of the uninterruptible power supply 100 for inspection. Note that the above-described configuration of the OR circuit is an example, and the number of OR circuits and the number of stages are set as appropriate.

[Embodiment 2]
The short circuit 10 and the voltage dividing circuit 20 can be used in combination. FIG. 11 is a circuit block diagram schematically showing the configuration of the overvoltage protection circuit included in the uninterruptible power supply according to Embodiment 2 of the present invention. Referring to FIG. 11, voltage dividing circuit 20 and short circuit 10 are connected in parallel between the electrodes of cell 1. The reference voltage E1 is set higher than the reference voltage E2.

  According to the second embodiment, when the interelectrode voltage of the cell 1 gradually increases and exceeds the reference voltage E2 due to the increase in resistance, the interelectrode voltage of the cell 1 is maintained at the reference voltage E2 by the voltage dividing circuit 20. The That is, since the interelectrode voltage does not become larger than the reference voltage E2, it is possible to suppress an increase in the variation in the interelectrode voltage of each cell 1. The variation in the voltage between the electrodes tends to increase when the variation in the capacitance of the cell 1 is large or when the variation in the deterioration of the cell 1 is large. Therefore, the uninterruptible power supply according to Embodiment 2 is effective in these cases.

  Further, when the interelectrode voltage of the cell 1a exceeds the reference voltage E1 due to the progress of increasing resistance or the occurrence of an abnormality such as disconnection, the short circuit 10 shorts the electrodes of the cell 1a. Thereby, the cell 1a can be protected from overvoltage breakdown.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 1a, 1b cell, 2a, 21, 22, 2n module, 3 power storage unit, 4 converter, 5 inverter, 6 insulation transformer, 71, 72 AC power supply, 8 control circuit, 80, 81-8n OR circuit, 9 warning Part, 10 short circuit, 11 load, 20 voltage divider circuit, 100 uninterruptible power supply, C, C1, C2 capacitor, E1, E2 reference voltage, Q1, Q2 transistor, R voltage dividing resistor, R2 current dividing resistor, Ra internal resistance , Rb leakage resistance, T1 positive electrode, T2 negative electrode, VD1, VD2 voltage detector.

Claims (7)

A power storage module that stores DC power from a DC power supply
The power storage module is:
A plurality of cells, each having a positive electrode and a negative electrode, connected in series;
A plurality of first overvoltage protection circuits respectively connected in parallel to the plurality of cells;
Each of the plurality of first overvoltage protection circuits includes:
A first switch that is electrically connected between the positive electrode and the negative electrode of a corresponding cell of the plurality of cells and that transitions from a non-conductive state to a conductive state in response to a first conductive signal. When,
A first voltage detector that detects a voltage between the positive electrode and the negative electrode and outputs the first conduction signal when the voltage between the electrodes exceeds a predetermined first reference voltage; A power storage device.   2. The power storage device according to claim 1, wherein the first reference voltage is set higher than the inter-electrode voltage in a fully charged state of each of the plurality of cells. The power storage module further includes a plurality of second overvoltage protection circuits respectively connected in parallel to the plurality of cells,
Each of the plurality of second overvoltage protection circuits includes:
A second switch that is electrically connected between the positive electrode and the negative electrode of the corresponding cell of the plurality of cells and that transitions from a non-conductive state to a conductive state in response to a second conductive signal; When,
A second voltage detector that detects the voltage between the positive electrode and the negative electrode and outputs the second conduction signal when the voltage between the electrodes exceeds a predetermined second reference voltage. When,
A shunt resistor connected in series with the second switch;
The power storage device according to claim 2, wherein the second reference voltage is set higher than the inter-electrode voltage in the fully charged state and lower than the first reference voltage.   The power storage device according to claim 1, wherein the power storage module further includes a spare cell connected in series to the plurality of cells in preparation for an open failure of any of the plurality of cells.   The power storage device according to claim 1, wherein the power storage module further includes a plurality of voltage dividing resistors respectively connected in parallel to the plurality of cells. The DC power source is a converter that converts AC power supplied from an AC power source into DC power,
The converter;
The DC power from the converter and the DC power stored in the power storage module are converted into AC power, and further includes an inverter configured to be able to supply the AC power to a load. The power storage device according to one item. A warning section that issues a warning;
A control unit for controlling the warning unit,
The control unit receives a signal indicating whether or not the first conduction signal is output from each of the plurality of first overvoltage protection circuits, and the signal is included in the plurality of first overvoltage protection circuits. The power storage device according to claim 6, wherein the warning unit is controlled to issue the warning when the output of the first conduction signal in at least one of the first and second signals is indicated.

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