JP2014165467A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that when a metal film is formed in contact with a diffusion region, there is the potential for an increase in contact resistance between the metal film and the diffusion region.SOLUTION: A semiconductor device comprises: a first connection member CM of a first transistor TR1 composing a memory cell MC together with a capacitative element CP, which includes a silicide-containing film (silicide film SC1); and a first contact hole CH1 in which the first connection member CM is formed and which pierces an insulation film (e.g., insulation film DF2 composing a side wall SW1) and reaches a first diffusion region DR1. At least a part of the silicide-containing film (silicide film SC1) is silicided. The silicide-containing film (silicide film SC1) is formed by silicidation of silicon formed in the first contact hole CH1.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is a technique applicable to, for example, a logic mixed memory.

  Currently, various techniques relating to the formation of silicide films have been proposed. Patent Document 1 describes a gate electrode made of fully silicided metal silicide. Patent Document 2 describes a method of forming cobalt silicide on a diffusion layer. The method described in Patent Document 2 includes a step of forming a cobalt film in a contact hole by sputtering, and a step of forming a cobalt silicide by reacting the deposited cobalt film with silicon in a diffusion layer.

  The silicide film may be formed on the surface of the diffusion region (source / drain region). Such a silicide layer can contribute to an improvement in data processing speed in the memory cell transistor. On the other hand, the silicide layer formed on the surface of the diffusion region can cause an increase in leakage current from the source and drain electrodes to the substrate. In response, Patent Document 3 describes a transistor in which no silicide layer is formed on the surface of the diffusion region in the memory circuit formation region.

JP 2008-130798 A JP 2010-165839 A JP 2001-308293 A

  In order to reduce junction leakage from the source and drain electrodes to the substrate in the memory cell transistor, a silicide film may not be formed in the diffusion region as in the transistor described in Patent Document 3. In this case, the metal film of the electrode is formed in contact with the diffusion region. On the other hand, when the metal film is formed in contact with the diffusion region, the contact resistance between the metal film and the diffusion region may increase.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the connection member of the transistor that forms the memory cell together with the capacitor includes a silicide-containing film. The connecting member is formed in the contact hole. The contact hole passes through the insulating film and reaches the diffusion region. At least a part of the silicide-containing film is silicided. The silicide-containing film is formed by siliciding silicon formed in the contact hole. As another example, the silicide-containing film is formed of silicide and is formed along the bottom and side walls of the contact hole. In another example, the connection member includes a metal film formed in a region surrounded by the silicide-containing film in a plan view and overlapping with the silicide-containing film in the height direction.

  According to the one embodiment, the contact resistance between the connection member and the diffusion region can be reduced.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing the semiconductor device shown in FIG. 1. FIG. 2 is an enlarged plan view showing a DRAM region of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. FIG. 18 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 17. FIG. 18 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 17. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment. FIG. 21 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 20.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing the semiconductor device SD according to the first embodiment. FIG. 1 is a schematic diagram showing the semiconductor device SD, and the configuration of the semiconductor device SD is not limited to that shown in FIG.

  As shown in FIG. 1, the semiconductor device SD includes a transistor TR1, a transistor TR2, an insulating film (for example, an insulating film DF2 and an etching stopper film ES constituting the sidewall SW1), a first connection member CM1, The second connection member CM2, the capacitive element CP, and the wiring IC are included. The first transistor TR1 includes a first gate electrode GE1 and a first diffusion region DR1. The first gate electrode GE1 is formed on the substrate SUB. The first diffusion region DR1 is formed in the substrate SUB on the side of the first gate electrode GE1. The second transistor TR2 includes a second gate electrode GE2 and a second diffusion region DR2. The second gate electrode GE2 is formed on the substrate SUB. The second diffusion region DR2 is formed in the substrate SUB on the side of the second gate electrode GE2. The insulating film (for example, the insulating film DF2 and the etching stopper film ES) is formed on the substrate SUB. The first connection member CM1 is formed in the first contact hole CH1. The first contact hole CH1 passes through the insulating film (for example, the insulating film DF2) and reaches the first diffusion region DR1. The second connection member CM2 is formed in the second contact hole CH2. The second contact hole CH2 passes through the insulating film (for example, the etching stopper film ES) and reaches the second diffusion region DR2. The capacitive element CP constitutes a memory cell MC together with the transistor TR1. The capacitive element CP is electrically connected to the first diffusion region DR1. The wiring IC forms a logic circuit together with the transistor TR2. The wiring IC is electrically connected to the second diffusion region DR2. The first connection member CM1 includes a silicide-containing film (first silicide film SC1). At least a part of the silicide-containing film (first silicide film SC1) is silicided. The silicide-containing film (first silicide film SC1) is formed by siliciding silicon formed in the first contact hole CH1.

  Hereinafter, the semiconductor device SD according to the present embodiment will be described in detail.

  FIG. 2 is a plan view showing the semiconductor device SD shown in FIG. FIG. 2 is a schematic diagram showing the semiconductor device SD, and the configuration of the semiconductor device SD is not limited to that shown in FIG.

  As shown in FIG. 2, the semiconductor device SD is a mixed DRAM (Dynamic Random Access Memory) including a DRAM region DR, a logic region LR, an I / O region IO, and a DRAM peripheral circuit region DP. When the semiconductor device SD is an embedded DRAM, the semiconductor device SD may further include an SRAM area in addition to these circuits. The positional relationship between these circuits is not limited to that shown in FIG. 2 and can be changed as appropriate. The semiconductor device SD may be a general-purpose DRAM, for example. In this case, the semiconductor device SD includes the DRAM region DR and the DRAM peripheral circuit region DP, and does not include the logic region LR, the I / O region IO, and the SRAM region. The DRAM region DR has a plurality of memory cells MC. The DRAM peripheral circuit region DP includes a circuit that controls reading or writing of these memory cells MC. The DRAM peripheral circuit region DP may include a decoder or a sense amplifier.

  FIG. 3 is an enlarged plan view showing the DRAM region DR of the semiconductor device SD shown in FIG. FIG. 3 is a schematic diagram showing the DRAM region DR, and the size relationship, positional relationship, and the like of each component are not limited to those shown in FIG. In the DRAM region DR, as shown in FIG. 3, a plurality of first diffusion regions DR1, a plurality of gate lines GL, and a plurality of bit lines BL are provided. The gate line GL and the bit line BL are provided so as to be orthogonal to each other. The DRAM region DR includes a plurality of capacitor contacts CC and a plurality of bit contacts BC. The capacitive contact CC connects the capacitive element CP and the first diffusion region DR1. The bit contact BC connects the bit line BL and the first diffusion region DR1. In the present embodiment, a plurality of transistors TR1 are configured by the plurality of first diffusion regions DR1 and the plurality of gate lines GL. That is, the gate line GL is the first gate electrode GE1. In the DRAM region DR, the plurality of transistors TR1 may be arranged in an array.

  The transistor TR1 will be described in detail. The transistor TR1 may form a memory cell MC in the DRAM region DR. When the semiconductor device SD is an embedded DRAM including an SRAM area, the transistor TR1 may constitute an SRAM area. Note that the transistor TR1 shown in FIG. 1 forms a DRAM region DR.

As shown in FIG. 1, the transistor TR1 includes a first gate insulating film GI1, a first gate electrode GE1, a first diffusion region DR1, a first extension region EX1, an offset spacer OS1, and a sidewall SW1. And sidewall SW3. The transistor TR1 is provided on the well WL1. When the transistor TR1 is an n-type transistor, the well WL1 is p-type. The first gate insulating film GI1 is provided on the substrate SUB. The substrate SUB may be a semiconductor substrate (for example, a silicon substrate). The first gate insulating film GI1 is formed of an insulating film. The first gate insulating film GI1 is formed of a silicon oxide film (SiO ₂ ), a silicon oxynitride film (SiON film), or a high dielectric constant film (for example, a hafnium silicate film (HfSiO) or a nitrogen-added hafnium silicate film). Also good. The first gate electrode GE1 is provided on the first gate insulating film GI1. The first gate electrode GE1 may be formed of polycrystalline silicon. The first gate electrode GE1 may be a metal gate using a metal such as titanium nitride (TiN) depending on the characteristics of the transistor TR1. An impurity having a concentration according to the characteristics of the transistor TR1 may be introduced into the first gate electrode GE1. The offset spacer OS1 is provided on the side surfaces of the first gate electrode GE1 and the first gate insulating film GI1. The offset spacer OS1 is formed of an insulating film. The sidewall SW3 is provided on the side surfaces of the first gate electrode GE1 and the first gate insulating film GI1 via the offset spacer OS1 and the sidewall SW1. The sidewall SW1 is provided between the offset spacer OS1 and the sidewall SW3 and between the substrate SUB and the sidewall SW3. For this reason, the sidewall SW1 has an L-shape when viewed in the direction in which the first gate electrode GE1 extends. The sidewall SW3 is provided on the sidewall SW1. Further, the sidewall SW3 functions as an etching stopper film when etching a film made of an insulating material different from that of the sidewall SW1. The sidewall SW1 and the sidewall SW3 are formed of an insulating film. The sidewall SW1 and the sidewall SW3 may be formed of a silicon oxide film or a silicon nitride film. When the sidewall SW1 is formed of a silicon nitride film, the sidewall SW3 is preferably formed of a silicon oxide film. When the sidewall SW1 is formed of a silicon oxide film, the sidewall SW3 is preferably formed of a silicon nitride film. Thus, it is preferable that the sidewall SW3 is formed of a material that can have an etching selectivity with respect to the sidewall SW1. The first diffusion region DR1 is formed in the substrate SUB on both sides of the gate electrode GE1. The first extension region EX1 is formed in the substrate SUB between the first diffusion region DR1 and the first gate electrode GE1 in plan view. The first extension region EX1 may be formed by impurity implantation using the offset spacer OS1 as a mask. A first gate silicide layer GS1 is provided on the first gate electrode GE1. The first gate silicide layer GS1 is formed of silicide. The first gate silicide layer GS1 may be formed of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. In the present embodiment, the first gate silicide layer GS1 is preferably formed of Pt-containing Ni silicide (Ni _1-x Pt _x Si (0.01 <x <0.2)) containing Ni as a main component. . Thereby, the contact resistance in the first gate electrode GE1 can be reduced while reducing the gate electrode resistance. The layer thickness of the first gate silicide layer GS1 may be 10 nm or more and 40 nm or less.

As shown in FIG. 1, the semiconductor device SD further includes a first connection member CM1. A part of the first connection member CM1 is connected to the bit line BL. The first connection member CM1 connected to the bit line BL constitutes a bit contact BC. The other part of the first connection member CM1 is connected to the capacitive element CP. The first connection member CM1 connected to the capacitive element CP constitutes a capacitive contact CC. The first connection member CM1 is formed in the first contact hole CH1. The first contact hole CH1 penetrates through the sidewall SW1, the etching stopper film ES, and the interlayer insulating film ID1, and reaches the first diffusion region DR1. The etching stopper film ES is provided on the substrate SUB, the transistor TR1, and the transistor TR2. The etching stopper film ES may be provided on the entire surface of the substrate SUB so as to cover the transistors TR1 and TR2. The etching stopper film ES is formed of an insulating film. The etching stopper film ES may be formed of a silicon nitride film. The etching stopper film ES functions as an etching stopper when etching the interlayer insulating film ID1. The interlayer insulating film ID1 is provided on the etching stopper film ES. The interlayer insulating film ID1 is formed of an insulating film. The interlayer insulating film ID1 may be formed of a silicon oxide film or a low dielectric constant film. The first connection member CM1 includes a first silicide film SC1. The first silicide film SC1 is formed of silicide. The first silicide film SC1 may be made of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. The first silicide film SC1 is formed by siliciding silicon formed in the first contact hole CH1. The first silicide film SC1 is in contact with the first diffusion region DR1, the insulating film DF2 constituting the sidewall SW1, the etching stopper film ES, and the interlayer insulating film ID1 from the bottom to the side wall of the first contact hole CH1. When the distance between the first transistor TR1 and the first contact hole CH1 is short, the first silicide film SC1 may be in contact with the sidewall SW3. The first silicide film SC1 may be formed up to a position higher than the upper surface of the first gate electrode GE1. “Position higher than the upper surface of the first gate electrode GE1” means that the first gate silicide layer GS1 is formed on the surface of the first gate electrode GE1 as shown in FIG. The position is higher than the surface of the silicide layer GS1. Alternatively, the film thickness of the first silicide film SC1 may be greater than or equal to the sum of the film thickness of the first gate insulating film GI1 (for example, 10 nm to 50 nm) and the film thickness of the first gate electrode GE1 (for example, 100 nm). . As shown in FIG. 1, the first connection member CM1 may further include a first metal film MF1. Alternatively, the first connection member CM1 may not include the first metal film MF1. When the first connection member CM1 does not include the first metal film MF1, the first silicide film SC1 fills the entire contact hole CH1. On the other hand, when the first connection member CM1 includes the first metal film MF1, the first metal film MF1 is formed on the silicide film SC1. The first metal film MF1 may be formed of a barrier metal film and a conductor member formed on the barrier metal film. In this case, the barrier metal film is formed from the upper surface of the first silicide film SC1 to the side wall of the first contact hole CH. The conductor member is formed in a region surrounded by the barrier metal film in plan view. The barrier metal film may be formed of a laminated film in which titanium (Ti) and titanium nitride (TiN) are sequentially laminated, or a single layer film of titanium nitride (TiN). The conductor member may be formed of tungsten (W).

  Next, the transistor TR2 will be described in detail. The transistor TR2 may constitute a logic area LR, an I / O area OP, a DRAM peripheral circuit area DP, or an SRAM area. Note that the transistor TR2 shown in FIG. 1 forms a logic region LR.

As shown in FIG. 1, the transistor TR2 includes a second gate insulating film GI2, a second gate electrode GE2, a second diffusion region DR2, a second extension region EX2, an offset spacer OS2, and a sidewall SW2. And sidewall SW4. The semiconductor device SD may include an n-type transistor TR1 and a p-type transistor TR1. In this case, the n-type transistor TR1 is provided on the p-type well WL1. The p-type transistor TR1 is provided on the n-type well WL2. The second gate insulating film GI2 is provided on the substrate SUB. The second gate insulating film GI2 is formed of an insulating film. The second gate insulating film GI2 is formed of a silicon oxide film (SiO ₂ ), a silicon oxynitride film (SiON film) or a high dielectric constant film (for example, a hafnium silicate film (HfSiON) or a nitrogen-added hafnium silicate film). Also good. The film thickness of the second gate insulating film GI2 may be different from the film thickness of the first gate insulating film GI1 depending on the characteristics of the transistor TR2. The second gate electrode GE2 is provided on the gate insulating film GI2. The second gate electrode GE2 may be formed of polycrystalline silicon. The second gate electrode GE2 may be a metal gate using a metal such as titanium nitride (TiN) depending on the characteristics of the transistor TR2. An impurity having a concentration according to the characteristics of the transistor TR2 may be introduced into the second gate electrode GE2. The offset spacer OS2 is provided on the side surfaces of the second gate electrode GE2 and the second gate insulating film GI2. The offset spacer OS2 is formed of an insulating film. The sidewall SW4 is provided on the side surfaces of the second gate electrode GE2 and the second gate insulating film GI2 via the offset spacer OS2 and the sidewall SW2. The sidewall SW2 is provided between the offset spacer OS2 and the sidewall SW4, and between the substrate SUB and the sidewall SW4. Therefore, the sidewall SW2 has an L-shape when viewed in the direction in which the second gate electrode GE2 extends. The side wall SW4 is provided on the side wall SW2. Further, the sidewall SW4 functions as an etching stopper film when etching a film made of an insulating material different from that of the sidewall SW2. The sidewall SW2 and the sidewall SW4 are formed of an insulating film. The sidewall SW2 and the sidewall SW4 may be formed of a silicon oxide film or a silicon nitride film. When the sidewall SW2 is formed of a silicon nitride film, the sidewall SW4 is preferably formed of a silicon oxide film. Further, when the sidewall SW2 is formed of a silicon oxide film, the sidewall SW4 is preferably formed of a silicon nitride film. Thus, it is preferable that the sidewall SW4 is formed of a material that can have an etching selectivity with respect to the sidewall SW2. The second diffusion region DR2 is formed on the substrate SUB on both sides of the second gate electrode GE2. The second extension region EX2 is formed in the substrate SUB between the second diffusion region DR2 and the second gate electrode GE2 in plan view. The second extension region EX2 may be formed by impurity implantation using the offset spacer OS2 as a mask. A second gate silicide layer GS2 is provided on the gate electrode GE2. The second gate silicide layer GS2 is formed of silicide. The second gate silicide layer GS2 may be formed of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. In the present embodiment, the second gate silicide layer GS2 is preferably Ni is formed by Pt-containing Ni silicide of the main component _{(Ni 1-x Pt x Si} (0.01 <x <0.2)) . Thereby, the contact resistance in the second gate electrode GE2 can be reduced while reducing the gate electrode resistance. The layer thickness of the second gate silicide layer GS2 may be 10 nm or more and 40 nm or less.

As shown in FIG. 1, the semiconductor device SD further includes a second connection member CM2. The second connection member CM2 is formed in the second contact hole CH2. The second contact hole CH2 penetrates through the etching stopper film ES and the interlayer insulating film ID1 and reaches the second diffusion region DR2. The second connection member CM2 includes a second silicide film SC2. The second silicide film SC2 is formed of silicide. The second silicide film SC2 may be formed of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. The second silicide film SC2 is formed by siliciding silicon formed in the second contact hole CH2. The second silicide film SC2 is in contact with the second diffusion region DR2, the etching stopper film ES, and the interlayer insulating film ID1 from the bottom to the side wall of the second contact hole CH2. When the distance between the second transistor TR2 and the second contact hole CH2 is short, the second silicide film SC2 may be in contact with the sidewall SW4. The second silicide film SC2 may be formed up to a position higher than the upper surface of the second gate electrode GE2. “A position higher than the upper surface of the second gate electrode GE2” means that the second gate silicide layer GS2 is formed on the surface of the second gate electrode GE2 as shown in FIG. The position is higher than the surface of the silicide layer GS2. Alternatively, the thickness of the second silicide film SC2 may be greater than or equal to the sum of the thickness of the second gate insulating film GI2 (for example, 10 nm to 50 nm) and the thickness of the second gate electrode GE2 (for example, 100 nm). . The film thickness of the second silicide film SC2 may be 10 nm or more. The film thickness of the second silicide film SC2 may be substantially the same as the film thickness of the first silicide film SC1. The “substantially the same” is realized by forming the first silicide film SC1 and the second silicide film SC2 in the same process as will be described later. As shown in FIG. 1, the second connection member CM2 may further include a second metal film MF2. Alternatively, the second connection member CM2 may not include the second metal film MF2. When the second connection member CM2 does not include the second metal film MF2, the second silicide film SC2 fills the entire contact hole CH2. On the other hand, when the second connection member CM2 includes the second metal film MF2, the metal film MF2 is formed on the second silicide film SC2. The second metal film MF2 may be formed of a barrier metal film and a conductor member formed on the barrier metal film. In this case, the barrier metal film is formed from the upper surface of the second silicide film SC2 to the side wall of the second contact hole CH2. The conductor member is formed in a region surrounded by the barrier metal film in plan view. The barrier metal film may be formed of a laminated film in which titanium (Ti) and titanium nitride (TiN) are sequentially laminated, or a single layer film of titanium nitride (TiN). The conductor member may be formed of tungsten (W).

Next, details of the first diffusion region DR1 and the second diffusion region DR2 will be described. A diffusion region silicide layer DS is formed on the surface of the second diffusion region DR2. The diffusion region silicide layer DS is formed of silicide. The diffusion region silicide layer DS may be made of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. In the present embodiment, the diffusion region silicide layer DS is formed before the second connection member CM2 is formed in the second contact hole CH2, as will be described later. On the other hand, in the present embodiment, as described later, such a silicide layer is formed on the surface of the first diffusion region CH1 before the first connection member CM1 is formed in the first contact hole CH1. There is no. Therefore, the first diffusion region DR1 at the interface between the first contact hole CH1 and the first diffusion region DR1 is not silicided. Alternatively, even if a part of the first diffusion region DR1 is silicided during the formation of the first silicide film SC1 of the first connection member CM1 (for the method of forming the first silicide film SC1 of the first connection member CM1, The metal concentration constituting the silicide in the first diffusion region DR1 is lower than the metal concentration constituting the silicide in the second diffusion region DR2. Therefore, the metal concentration for forming silicide in the first diffusion region DR1 at the interface between the first contact hole CH1 and the first diffusion region DR1 is the second diffusion at the interface between the second contact hole CH2 and the second diffusion region DR2. The concentration is lower than the metal concentration for forming silicide in the region DR2.

  As described above, in the present embodiment, silicide is not formed in the first diffusion region DR1, or hardly formed in the first diffusion region DR1. For this reason, the leakage current from the first connection member CM1 to the substrate SUB via the silicide in the first diffusion region DR1 is reduced. In the present embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is formed of silicide (first connection member CM1) and a semiconductor (first diffusion region DR1). The contact resistance at the interface between the silicide and the semiconductor is smaller than the contact resistance at the interface between the metal and the semiconductor. Therefore, in the present embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is compared with a case where the interface is formed of a metal (first connection member CM1) and a semiconductor (first diffusion region DR1). Thus, the contact resistance between the first connection member CM1 and the first diffusion region DR1 can be reduced. In addition, when an interface between a metal and a semiconductor is formed, the semiconductor crystal may be distorted by the stress of the metal. Such crystal distortion can cause a leak path. On the other hand, in the present embodiment, such a metal-semiconductor interface is not formed at the interface between the first connecting member CM1 and the first diffusion region DR1. For this reason, a leak path due to crystal distortion in the first diffusion region DR1 can be reduced.

  Another configuration of the semiconductor device SD will be described. Element isolation films STI1 and STI2 are formed on the substrate SUB. The element isolation film STI1 is formed in the DRAM region DR. The element isolation film STI2 is formed in the logic region LR. The element isolation film STI1 has a function of electrically isolating the transistor TR1 constituting one memory cell MC from the transistors constituting another memory cell MC. The element isolation film STI2 has a function of electrically isolating the transistor TR2 from other transistors TR2. The element isolation films STI1 and STI2 are formed of insulating films. The element isolation films STI1 and STI2 may be formed of a silicon oxide film. A bit line BL is provided on the interlayer insulating film ID1. The bit line BL is connected to the first diffusion region DR1 through the first connection member CM1. The bit line BL may be formed of tungsten (W). The bit line BL1 may have a barrier metal film. The barrier metal film may be formed of a laminated film in which titanium (Ti) and titanium nitride (TiN) are sequentially laminated, or a single layer film of titanium nitride (TiN). An interlayer insulating film ID2 is provided on the interlayer insulating film ID1 so as to cover the bit line BL. The interlayer insulating film ID2 is formed of an insulating film. The interlayer insulating film ID2 may be formed of a silicon oxide film or a low dielectric constant film. In the interlayer insulating film ID2, the third connection member CM3 is embedded in the DRAM region DR, and the fourth connection member CM4 is embedded in the logic region LR. The third connection member CM3 is formed in the contact hole CH3. The contact hole CH3 passes through the interlayer insulating film ID2 and reaches the first connection member CM1. The fourth connection member CM4 is formed in the contact hole CH4. The contact hole CH4 penetrates the interlayer insulating film ID2 and reaches the second connection member CM2. The third connection member CM3 connects the capacitive element CP and the connection member CM1. The connection member CM4 connects the wiring IC and the connection member CM2. The connection members CM3 and CM4 may be formed of a barrier metal film and a conductor member formed on the barrier metal film. In this case, the barrier metal film is formed from the upper surfaces of the first connection member CM1 and the second connection member CM2 to the side walls of the third contact hole CH3 and the fourth contact hole CH4, respectively. The conductor member is formed in a region surrounded by the barrier metal film in plan view. The barrier metal film may be formed of a laminated film in which titanium (Ti) and titanium nitride (TiN) are sequentially laminated, or a single layer film of titanium nitride (TiN). The conductor member may be formed of tungsten (W). A capacitive element CP is provided in the interlayer insulating film ID2. The capacitive element CP includes a lower electrode LE, a capacitive insulating film CI, and an upper electrode UE. The lower electrode LE is connected to the third connection member CM3. Thereby, the capacitive element CP is connected to the third connection member CM3. The capacitive insulating film CI is provided on the lower electrode LE. The upper electrode UE is provided on the capacitive insulating film CI. On the interlayer insulating film ID2, an interlayer insulating film ID3 is provided. The interlayer insulating film ID3 is formed of an insulating film. The interlayer insulating film ID3 may be formed of a silicon oxide film or a low dielectric constant film. A wiring IC is embedded in the interlayer insulating film ID3. The wiring IC constitutes a logic circuit. The wiring IC may be formed by a barrier metal film and a conductor member formed on the barrier metal film. In this case, the barrier metal film is formed from the bottom of the wiring trench in which the wiring IC is embedded to the side wall. The conductor member is formed in a region surrounded by the barrier metal film in plan view. The barrier metal film may be formed of tantalum (Ta) or tantalum nitride (TaN). The conductor member may be made of copper (Cu).

Next, a method for manufacturing the semiconductor device SD will be described. The manufacturing method of the semiconductor device SD in this embodiment includes the following steps (A) to (F).
Step (A): The first gate electrode GE1 and the second gate electrode GE2 are formed on the substrate SUB, and the first diffusion region DR1 is formed on the substrate SUB on each side of the first gate electrode GE1 and the second gate electrode GE2. Step of forming second diffusion region DR2 Step (B): Step of forming insulating film (for example, insulating film DF2, etching stopper film ES) on substrate SUB Step (C): Insulating film (for example, insulating film DF2) ) To reach the first diffusion region DR1 and the second contact hole CH2 to penetrate the insulating film (for example, the etching stopper film ES) and reach the second diffusion region DR2. Step Step (D): forming the first connection member CM1 in the first contact hole CH1 and in the second contact hole CH2 Step of forming second connecting member CM2 Step (E): Step of forming capacitive element CP electrically connected to first diffusion region DR1 Step (F): Electrically connected to second diffusion region DR2. Step of Forming Wiring IC In the method of manufacturing the semiconductor device SD in the present embodiment, the step of forming the first connection member CM1 in the step (D) includes the step of forming a silicide-containing film (first layer) from the bottom to the side wall of the first contact hole CH1. 1 silicide film SC1) is formed. The silicon-containing film (first silicide film SC1) is at least partially silicided.

  Details of the method of manufacturing the semiconductor device SD in the present embodiment will be described with reference to FIGS. 4 to 17 are sectional views showing a method for manufacturing the semiconductor device SD shown in FIG. 4 to 17 are schematic views showing a method for manufacturing the semiconductor device SD, and the method for manufacturing the semiconductor device SD is not limited to that shown in FIGS.

  First, the element isolation film STI1 and the element isolation film STI2 are formed in the DRAM region DR and the logic region LR of the substrate SUB, respectively. The element isolation films STI1 and STI2 are STI (Shallow Trench Isolation) formed by burying an oxide film in a groove provided in the substrate SUB. Next, ion implantation is performed on a region where each transistor is to be formed, thereby forming a well WL1, a well WL2, and a well WL3. Next, an insulating film constituting the first gate insulating film GI1 and the second gate insulating film GI2, and a polycrystalline silicon film constituting the first gate electrode GE1 and the second gate electrode GE2 are sequentially stacked on the substrate SUB. The film thickness of the first gate electrode GE1 and the second gate electrode GE2 may be 100 nm. Next, these insulating film and polycrystalline silicon film are patterned. Thus, the first gate insulating film GI1 and the first gate electrode GE1 are formed in the DRAM region DR. The first gate electrode GE1 is formed on the first gate insulating film GI1. Simultaneously with the formation of the first gate insulating film GI1 and the first gate electrode GE1, the second gate insulating film GI2 and the second gate electrode GE2 are formed in the logic region LR. The second gate electrode GE2 is formed on the second gate insulating film GI2. The distance between two adjacent first gate electrodes GE1 may be 150 nm. Further, by forming the first gate insulating film GI1 and the second gate insulating film GI2 as follows, the thickness of the first gate insulating film GI1 is made larger than the thickness of the second gate insulating film GI2. Good. First, an insulating film constituting the first gate insulating film GI1 and the second gate insulating film GI2 is formed on the substrate SUB. Next, a portion of the insulating film that constitutes the second gate insulating film GI2 is removed by wet etching using dilute hydrofluoric acid. Next, insulating films constituting the first gate insulating film GI1 and the second gate insulating film GI2 are formed again on the substrate SUB. Thereby, the film thickness of the first gate insulating film GI1 obtained after patterning can be made larger than the film thickness of the second gate insulating film GI2. After the first gate insulating film GI1, the second gate insulating film GI2, the first gate electrode GE1, and the second gate electrode GE are formed as described above, the insulating film DF1 is formed on the substrate SUB (FIG. 4). (A)). The insulating film DF1 is formed of an insulating film. The film thickness of the insulating film DF1 may be 10 nm. The insulating film ID1 is provided on the substrate SUB so as to cover the gate electrode GE1 and the gate electrode GE2.

  Next, the insulating film ID1 is etched back. As a result, the offset spacer OS1 is formed on the side surfaces of the gate electrode GE1 and the gate insulating film GI1, and the offset spacer OS2 is formed on the side surfaces of the gate electrode GE2 and the gate insulating film GI2. The insulating film DF1 may be etched back after the first extension region EX1 and the second extension region EX2 are formed. After the formation of the offset spacers OS1 and OS2, a photoresist PR1 is formed on the region where the p-type transistor TR1 is to be formed. Next, impurities are implanted into the substrate SUB using the photoresist PR1, the first gate electrode GE1, the second gate electrode GE2, the offset spacer OS1, the offset spacer OS2, the element isolation film STI1, and the element isolation film STI2 as a mask. The impurity implanted at this time may be phosphorus (P) or arsenic (As). As a result, the first extension region EX1 constituting the n-type transistor TR1 is formed in the DRAM region DR. At the same time, the second extension region EX2 constituting the n-type transistor TR2 is formed in the logic region LR (FIG. 4B). Next, the photoresist PR1 is removed by an ashing process or a wet process using a sulfuric acid hydrogen peroxide mixture (sulfuric acid / hydrogen peroxide mixture). Note that the first extension region EX1 constituting the n-type transistor TR1 and the second extension region EX2 constituting the transistor TR2 may be formed in separate steps.

Next, a photoresist PR2 is formed over the n-type transistor TR1 and the transistor TR2. Next, impurities are implanted into the substrate SUB using the photoresist PR2, the second gate electrode GE2, the offset spacer OS1, the element isolation film STI1, and the element isolation film STI2 as a mask. Thereby, the second extension region EX2 constituting the p-type transistor TR2 is formed (FIG. 5A). The impurity implanted at this time may be boron (B) or boron trifluoride (BF ₃ ). Next, the photoresist PR2 is removed by an ashing process or a wet process using a sulfuric acid / hydrogen peroxide mixture (sulfuric acid / hydrogen peroxide). Thereby, the structure shown in FIG. 5B is obtained.

  Next, the insulating film DF2 and the insulating film DF3 are sequentially formed on the substrate SUB (FIG. 6A). The insulating film DF2 and the insulating film DF3 are formed on the substrate SUB so as to cover the first gate electrode GE1, the second gate electrode GE2, the offset spacer OS1, and the offset spacer OS2. The film thickness of the insulating film DF2 may be 10 nm. The film thickness of the insulating film DF3 may be 20 nm or more and 25 nm or less. The insulating film DF2 and the insulating film DF3 are formed of an insulating film. The insulating film DF2 and the insulating film DF3 may be made of different materials. When the insulating film DF2 is formed of a silicon nitride film, the insulating film DF3 is preferably formed of a silicon oxide film. In this case, the insulating film DF2 functions as an etching stopper when the insulating film DF3 is etched.

  Next, the insulating film DF3 is etched back (FIG. 6B). Thereby, portions of the insulating film DF3 other than those located on the side surface of the first gate electrode GE1 and the side surface of the second gate electrode GE2 are removed. At this time, the insulating film DF2 functions as an etching stopper.

  Next, a photoresist PR3 is formed so as to cover the second gate electrode GE2 and the second extension region EX2 (FIG. 7A). The photoresist PR3 may be formed by exposing and developing a resist film provided on the substrate SUB. Photoresist PR3 may be provided so as to cover a region other than DRAM region DR. Next, impurities are implanted into the substrate SUB using the first gate electrode GE1, the insulating film DF3 provided on the side surface of the first gate electrode GE1, the photoresist PR3, and the element isolation film STI1 as a mask. The impurity implanted at this time may be phosphorus (P) or arsenic (As). Thus, the first diffusion region DR1 is formed on both sides of the first gate electrode GE1. The position of the PN junction formed under the sidewall SW1 can be changed by changing the film thickness of the insulating film DF2 in accordance with the characteristics of the transistor TR1. Since the insulating film DF2 is removed in a subsequent process, the film thickness of the insulating film DF2 can be set independently of other process conditions.

  Next, the photoresist PR3 is removed. The photoresist PR3 may be removed by ashing or wet treatment with sulfuric acid / hydrogen peroxide. Next, the insulating film DF3 is removed (FIG. 7B). The insulating film DF3 may be removed by isotropic etching using dilute hydrofluoric acid. At this time, the insulating film DF2 functions as an etching stopper.

  Next, an insulating film DF4 is formed on the insulating film DF2 (FIG. 8A). The insulating film DF4 is provided so as to cover the first gate electrode GE1 and the second gate electrode GE2. The insulating film DF4 is made of a material different from that of the insulating film DF2. Specifically, the insulating film DF4 may be a silicon oxide film. Thereby, the etching selectivity with respect to the insulating film DF2 is obtained. In the present embodiment, the space between each of the plurality of first gate electrodes GE1 provided in the DRAM region DR may be filled with the insulating film DF4. At this time, the film thickness a of the insulating film DF4 located on the first diffusion region DR1 may be larger than the film thickness b of the insulating film DF4 located on the first gate electrode GE1. Here, the growth of the insulating film DF4 in the space between the first gate electrodes GE1 includes growth from the surface of the first diffusion region DR1 and growth from the side surface of the first gate electrode GE1. By adjusting the film formation conditions and the film thickness of the insulating film DF4, the insulating films DF4 grown from the side surfaces of the two first gate electrodes GE1 located across the first diffusion region DR1 can be brought into contact with each other. Thereby, the film thickness of the insulating film DF4 located on the first diffusion region DR1 can be made larger than the film thickness of the insulating film DF4 located on the first gate electrode GE1. The insulating film DF4 is preferably formed by a film forming method having excellent coverage. For forming the insulating film DF4, LPCVD (Low Pressure Chemical Vapor Deposition), SACVD (Sub-Atmospheric Pressure Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) may be used. The film thickness of the insulating film DF4 is preferably set to a thickness of ½ or more of the distance between two adjacent first gate electrodes GE1. The thickness of the insulating film DF4 may be 55 nm or more and 100 nm or less. By setting the film thickness of the insulating film DF4 to be equal to or less than the above upper limit value, it is possible to prevent the productivity and controllability in the film formation of the insulating film DF4 and the dry etching in the next process from being deteriorated. Further, by setting the thickness of the insulating film DF4 to be equal to or greater than the above lower limit value, the thickness of the insulating film DF4 positioned on the first diffusion region DR1 is changed to the thickness of the insulating film DF4 positioned on the first gate electrode GE1. It is possible to make it sufficiently thicker.

  Next, the insulating film DF4 is etched back by dry etching (FIG. 8B). In the present embodiment, the insulating film DF4 is formed so that the film thickness of the insulating film DF4 on the first diffusion region DR is larger than the film thickness of the insulating film DF4 on the first gate electrode GE1. For this reason, the insulating film DF4 remains so as to cover the entire surface of the first diffusion region DR1. Therefore, in the DRAM region DR, a portion of the insulating film DF4 that is located on the side surface of the first gate electrode GE1 and a portion that is located between the first gate electrodes GE1 so as to cover the entire surface of the first diffusion region DR1 remain. Will be. On the other hand, in the region other than the DRAM region DR, portions of the insulating film DF4 other than those located on the side surfaces of the second gate electrode GE2 are removed. At this time, the insulating film DF2 functions as an etching stopper. In addition to dry etching, CMP (Chemical Mechanical Polishing) may be used for processing the insulating film DF4. However, the pattern density of the gate electrode differs between the DRAM region DR and the logic region LR or inside the logic region LR. For this reason, a difference occurs in the polishing rate in CMP between the DRAM region DR and the logic region LR or in the logic region LR. In this case, there is a possibility that a problem may occur from the viewpoint of processing accuracy. Therefore, the processing of the insulating film DF4 is preferably performed by dry etching.

  Next, a photoresist PR4 is formed so as to cover the DRAM region DR. Next, using the photoresist PR4 as a mask, the insulating film DF4 located in a region other than the DRAM region DR is removed (FIG. 9A). The insulating film DF4 may be removed by isotropic etching using diluted hydrofluoric acid.

  Next, the photoresist PR4 is removed. The photoresist PR4 may be removed by ashing or wet treatment with sulfuric acid / hydrogen peroxide. Next, an insulating film DF5 is formed. The insulating film DF5 is provided on the insulating film DF2 and the insulating film DF4 so as to cover the first gate electrode GE1 and the second gate electrode GE2. The thickness of the insulating film DF5 may be 20 nm or more and 25 nm or less. The insulating film DF5 may be made of a material different from that of the insulating film DF2. Specifically, the insulating film DF5 may be a silicon oxide film. Thereby, the etching selectivity with respect to the insulating film DF2 is obtained.

  Next, the insulating film DF5, the insulating film DF1 on the first gate electrode GE1, and the insulating film DF2 on the second gate electrode GE2 are etched back. As a result, in the DRAM region DR, at least a portion of the insulating film DF5 located on the first gate electrode GE1 is removed. In regions other than the DRAM region DR, portions other than the portion of the insulating film DF5 located on the side surface of the second gate electrode GE2 are removed. As a result, the portion of the insulating film DF5 located on the side surface of the second gate electrode GE2 constitutes the sidewall SW4 provided on the side surface of the second gate electrode GE2 (FIG. 10A). At this time, the insulating film DF2 on the first gate electrode GE1, the insulating film DF2 on the second gate electrode GE2, and the insulating film DF2 on the portions of the substrate SUB located on both sides of the second gate electrode GE2 are also removed. . Thus, the insulating film DF2 is selectively removed, and the upper surface of the first gate electrode GE1, the upper surface of the second gate electrode GE2, and portions of the substrate SUB located on both sides of the first gate electrode GE1 (hereinafter, referred to as “the first gate electrode GE1”). It is also referred to as an exposed portion). The removal of the insulating film DF2 may be performed by a separate process after the process of removing the insulating film DF5, or may be performed simultaneously with the removal of the insulating film DF5. As a result, the sidewall SW1 is provided on the side surface of the first gate electrode GE1, and the sidewall SW2 is provided on the side surface of the second gate electrode GE2.

  Next, a photoresist PR5 is formed so as to cover the region where the p-type transistor TR1 is formed in the logic region LR and the DRAM region DR. Next, impurities are implanted into the semiconductor substrate SUB using the photoresist PR5 as a mask. The impurity implanted at this time may be phosphorus (P) or arsenic (As). Thereby, the second diffusion region DR2 constituting the n-type transistor TR2 is formed (FIG. 10B). At this time, the second diffusion region DR2 is formed on both sides of the second gate electrode GE2 and in the exposed portion. Next, the photoresist PR5 is removed by an ashing process or a wet process using sulfuric acid / hydrogen peroxide.

Next, a photoresist PR6 is formed so as to cover the region where the n-type transistor TR2 is formed in the logic region LR and the DRAM region. Next, impurities are implanted into the substrate SUB using the photoresist PR6 as a mask. The impurity implanted at this time may be boron (B) or boron trifluoride (BF ₃ ). Thereby, the second diffusion region DR2 constituting the p-type transistor TR2 is formed (FIG. 11A). At this time, the second diffusion region DR2 is formed on both sides of the second gate electrode GE2 and in the exposed portion. Next, the photoresist PR6 is removed by ashing or wet treatment with sulfuric acid / hydrogen peroxide.

  Next, the logic region LR is covered with a photoresist PR7, and the insulating film DF4 and the insulating film DF5 in the DRAM region are removed (FIG. 11B). The removal of the insulating film DF4 and the insulating film DF5 may be performed by isotropic etching using diluted hydrofluoric acid. When removing the insulating film DF4 and the insulating film DF5, the sidewall SW1 provided on the side surface of the first gate electrode GE1 and on the first diffusion region DR1 functions as an etching stopper. However, depending on wet etching conditions, a portion of the offset spacer OS1 that is not covered with the sidewall SW1 is etched. When the offset spacer OS1 is etched in this way, there is a possibility that problems such as film peeling and an abnormally thick gate silicide are formed during silicide formation. For this reason, it is preferable to select a film having a lower etching rate in wet etching than the insulating film DF4 as the offset spacer OS1. Such an etching rate can be realized by using LPCVD for the offset spacer OS1 and SACVD for the insulating film DF4. Here, by removing the insulating film DF4 and the insulating film DF5, the opening can be facilitated when the contact hole CH1 is formed.

  Next, the photoresist PR7 is removed. An ashing process may be used to remove the photoresist PR7. Next, an insulating film DF6 is formed (FIG. 12A). The insulating film DF6 is provided to cover the first gate electrode GE1, the second gate electrode GE2, the first diffusion region DR1, and the second diffusion region DR2. The insulating film DF6 may be provided on the entire surface of the substrate SUB. The insulating film DF6 may be a silicon oxide film. The thickness of the insulating film DF6 may be 10 nm or more and 20 nm or less. Next, impurity activation annealing is performed on the substrate SUB. The activation annealing may be performed by heat-treating the substrate SUB using a lamp annealing method at 900 ° C. or higher and 1100 ° C. or lower. As a heat treatment method, other techniques such as flash lamp annealing, laser annealing, or annealing using microwaves may be used. Here, the activation annealing is performed in a state where the entire surface is covered with the insulating film DF6. However, the activation annealing may be performed after the next insulating film DF6 is etched.

  Next, the insulating film DF6 is selectively removed by dry etching. In this embodiment, for example, after the photoresist is formed so that the regions for forming the transistors TR1 and TR2 are exposed, the dry etching is performed. As a result, in the DRAM region DR, at least a portion of the insulating film DF6 located on the first gate electrode GE1 is removed. In regions other than the DRAM region DR, portions other than the portion of the insulating film DF6 located on the side surface of the second gate electrode GE2 are removed. Here, in the DRAM region DR, portions other than the portion located on the side surface of the first gate electrode GE1 are removed. Thereby, the sidewall SW3 is formed (FIG. 12B).

  Next, a diffusion region silicide layer DS is formed in the second diffusion region DR2, a first gate silicide layer GS1 is formed on the first gate electrode GE1, and a second gate silicide layer GS2 is formed on the second gate electrode GE2 (FIG. 13 (a)). The diffusion region silicide layer DS, the first gate silicide layer GS1, and the second gate silicide layer GS2 are formed of silicide. The diffusion region silicide layer DS, the first gate silicide layer GS1, and the second gate silicide layer GS2 may be formed of the same material. In contrast to the second diffusion region DR2, the first gate electrode GE1, and the second gate electrode GE2, such a silicide layer is not formed in the first diffusion region DR1. The above silicide layer forming step is performed as follows using a salicide (self-aligned silicide) method. First, a silicide metal film is formed on the second diffusion region DR2, the first gate electrode GE1, and the second gate electrode GE2. The silicide metal film may be provided so as to be in contact with the second diffusion region DR2, the first gate electrode GE1, and the second gate electrode GE2 and cover the entire surface of the substrate SUB. The silicide metal film can be appropriately selected according to the material of the silicide layer to be formed, but may be an alloy film of Ni and Pt. In this case, the Pt content in the alloy film is, for example, 1 atomic% or more and 20 atomic% or less. The silicide metal film may be formed using PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). Next, first annealing is performed. The first annealing may be performed by heat-treating the substrate SUB and the metal film using a lamp annealing method at a temperature of 200 ° C. to 350 ° C. for 20 seconds to 120 seconds. For the first annealing, furnace annealing or a heater heating method may be used in addition to lamp annealing. Next, unreacted metal in the silicide metal film is removed. The removal of the unreacted metal is performed using a wet stripping method using a chemical solution such as sulfuric acid / hydrogen peroxide or aqua regia. Next, second annealing is performed. The second annealing may be performed by heat-treating the substrate SUB using a lamp annealing method at a temperature of 350 ° C. to 550 ° C. for 20 seconds to 120 seconds. In addition to lamp annealing, furnace annealing or a heater heating method may be used for the second annealing. As a result, nickel monosilicide having a low resistance and Pt added is formed. Thus, the diffusion region silicide layer DS is provided on the second diffusion region DR2, the first gate silicide layer GS1 is provided on the first gate electrode GE1, and the second gate silicide layer GS2 is provided on the second gate electrode GE2. Will be. On the second diffusion region DR2, the diffusion region silicide layer DS is formed in a portion of the second diffusion region DR2 that is not covered with the insulating film DF6. Further, since the first diffusion region DR1 is covered with the sidewall SW2 formed of the insulating film DF2, no silicide layer is formed on the first diffusion region DR1.

  In this embodiment, in this way, the transistor TR1 including the first gate electrode GE1, the first gate insulating film GI1, the first diffusion region DR1, the first extension region EX1, the offset spacer OS1, the sidewall SW1, and the sidewall SW3. Is obtained. Also, the transistor TR2 including the second gate electrode GE2, the second gate insulating film GI2, the second diffusion region DR2, the second extension region EX2, the offset spacer OS2, the sidewall SW2, and the sidewall SW4 is obtained.

  Next, an etching stopper film ES is provided (FIG. 13B). The etching stopper film ES is provided on the entire surface of the substrate SUB so as to cover the transistors TR1 and TR2. The etching stopper film ES may be formed of a silicon nitride film.

  Next, an interlayer insulating film ID1 is formed on the etching stopper film ES. Next, the surface of the interlayer insulating film ID1 is planarized (FIG. 14A). The planarization of the surface of the interlayer insulating film ID1 may be performed by CMP.

  Next, a contact hole CH1 and a contact hole CH2 are formed in the interlayer insulating film ID1 (FIG. 14B). In the present embodiment, the contact hole CH1 is formed so as to penetrate the interlayer insulating film ID1, the etching stopper film ES, and the insulating film DF2 and reach the first diffusion region DR1. For this reason, the first diffusion region DR1 is exposed at the bottom of the contact hole CH1. The contact hole CH2 is formed so as to penetrate the interlayer insulating film ID1 and the etching stopper film ES and reach the diffusion region silicide layer DS. Therefore, the diffusion region silicide layer DS is exposed at the bottom of the contact hole CH2.

  Next, a first semiconductor film SM1 and a second semiconductor film SM2 are formed in the contact hole CH1 and the contact hole CH2, respectively (FIG. 15A). The first semiconductor film SM1 is formed from the bottom to the side wall of the contact hole CH1. Similarly, the second semiconductor film SM2 is formed from the bottom to the side wall of the contact hole CH2. The first semiconductor film SM1 and the second semiconductor film SM2 contain silicon and are not silicided. The first semiconductor film SM1 and the second semiconductor film SM2 may be formed of amorphous silicon, polycrystalline silicon, or doped silicon. The first semiconductor film SM1 and the second semiconductor film SM2 do not need to be embedded in the contact holes CH1 and CH2, respectively, and it is only necessary that part of the contact holes CH1 and CH2 is embedded in the height direction. . Specifically, the first semiconductor film SM1 and the second semiconductor film SM2 may be formed to a position higher than the upper surface of the first gate electrode GE1 and a position higher than the upper surface of the second gate electrode, respectively. “Position higher than the upper surface of the first gate electrode GE1” means that the first gate silicide layer GS1 is formed on the surface of the first gate electrode GE1 as shown in FIG. The position is higher than the surface of the first gate silicide layer GS1. Similarly, “a position higher than the upper surface of the second gate electrode GE2” means that the second gate silicide layer GS2 is formed on the surface of the second gate electrode GE2 as shown in FIG. Is higher than the surface of the second gate silicide layer GS2. Alternatively, the film thickness of the first semiconductor film SM1 may be greater than or equal to the sum of the film thickness (for example, 10 nm to 50 nm) of the first gate insulating film GI1 and the film thickness (for example, 100 nm) of the first gate electrode GE1. . The film thickness of the second semiconductor film SM2 may be greater than or equal to the sum of the film thickness of the second gate insulating film GI2 (for example, 10 nm to 50 nm) and the film thickness of the second gate electrode GE2 (for example, 100 nm).

  A method for forming the first semiconductor film SM1 and the second semiconductor film SM2 will be described. The first semiconductor film SM1 and the second semiconductor film SM2 may be formed by selective growth. Alternatively, the first semiconductor film SM1 and the second semiconductor film SM2 may be formed non-selectively. In this case, the first semiconductor film SM1 and the second semiconductor film SM2 are formed by forming a semiconductor film containing silicon over the entire surface of the interlayer insulating film ID1, and then etching back the semiconductor film. Since the film thicknesses of the first semiconductor film SM1 and the second semiconductor film SM2 are parameters that affect the subsequent processes, it is preferable that these film thicknesses be constant in any contact hole. With the above-described method for forming the first semiconductor film SM1 and the second semiconductor film SM2 by non-selective formation of the semiconductor film and etchback of the semiconductor film, a constant film without greatly depending on the pattern and the impurity concentration The thick first semiconductor film SM1 and second semiconductor film SM2 can be formed favorably. The first semiconductor film SM1 and the second semiconductor film SM2 may be formed at the same time. In this case, the film thicknesses of the first semiconductor film SM1 and the second semiconductor film SM2 are substantially the same. The deposition temperatures of the first semiconductor film SM1 and the second semiconductor film SM2 are preferably lower than the formation temperatures of the first gate silicide layer GS1, the second gate silicide layer GS2, and the diffusion region silicide layer DS. This is because, when the deposition temperature of the first semiconductor film SM1 and the second semiconductor film SM2 is higher than the formation temperature of these silicide layers, the already formed first gate silicide layer GS1, second gate silicide layer GS2 and This is because in the diffusion region silicide layer DS, alteration such as aggregation and phase transition occurs. From the viewpoint of such a formation temperature, the first semiconductor film SM1 and the second semiconductor film SM2 are preferably amorphous silicon or doped silicon. Amorphous silicon or doped silicon can be deposited at a lower temperature than polycrystalline silicon.

  Next, metal is introduced into the first semiconductor film SM1 and the second semiconductor film SM2, and the first semiconductor film SM1 and the second semiconductor film SM2 are silicided. Thereby, the first silicide film SC1 and the second silicide film SC2 formed of silicide are formed (FIG. 15B). The first silicide film SC1 and the second silicide film SC2 do not need to be embedded in the entire contact holes CH1 and CH2, respectively, and it is sufficient that part of the contact holes CH1 and CH2 is embedded in the height direction. . Specifically, the first silicide film SC1 and the second silicide film SC2 may be formed up to a position higher than the upper surface of the first gate electrode GE1 and a position higher than the upper surface of the second gate electrode. “Position higher than the upper surface of the first gate electrode GE1” means that the first gate silicide layer GS1 is formed on the surface of the first gate electrode GE1 as shown in FIG. The position is higher than the surface of the first gate silicide layer GS1. Similarly, “a position higher than the upper surface of the second gate electrode GE2” means that the second gate silicide layer GS2 is formed on the surface of the second gate electrode GE2 as shown in FIG. 15B. Is higher than the surface of the second gate silicide layer GS2. Alternatively, the thickness of the first silicide film SC1 may be greater than or equal to the sum of the thickness of the first gate insulating film GI1 (for example, 10 nm to 50 nm) and the thickness of the first gate electrode (for example, 100 nm). The film thickness of the second silicide film SC2 may be greater than or equal to the sum of the film thickness of the second gate insulating film GI2 (for example, 10 nm to 50 nm) and the film thickness of the second gate electrode GE2 (for example, 100 nm).

  A method for forming the first silicide film SC1 and the second silicide film SC2 will be described. First, a metal film is formed over the first semiconductor film SM1 and the second semiconductor film SM2. CVD, PVD, or sputtering may be used for forming the metal film. The metal film may be formed not only on the semiconductors SM1 and SM2, but also on the entire interlayer insulating film ID1. Nickel (Ni) may be used as the metal film. Thereafter, the substrate SUB and the metal film are heat-treated. The temperature of this heat treatment is preferably lower than the formation temperature of the first gate silicide layer GS1, the second gate silicide layer GS2, and the diffusion region silicide layer DS. This is because, when the temperature of the heat treatment is higher than the formation temperature of these silicide layers, the first gate silicide layer GS1, the second gate silicide layer GS2 and the diffusion region silicide layer DS which have already been formed are aggregated and phase-transitioned. This is because alteration occurs. From the viewpoint of such a heat treatment temperature, the metal film is preferably nickel (Ni). If nickel (Ni) is used, silicidation is possible at a temperature lower than the temperature of formation of the silicide layer in the first gate silicide layer GS1, the second gate silicide layer GS2, and the diffusion region silicide layer DS. Alternatively, microwave annealing may be used for the heat treatment. With microwave annealing, silicidation is possible at a low temperature. The silicidation of the first semiconductor film SM1 and the second anti-relative film SM2 may be performed simultaneously. When the first semiconductor film SM1 and the second semiconductor film SM2 are formed at the same time and the silicidation of the first semiconductor film SM1 and the second semiconductor film SM2 is performed at the same time, the first silicide film SC1 and the second silicide film The film thickness of SC2 is substantially the same. In the first silicide film SC1 formed as described above, the silicide concentration in the vicinity of the upper surface of the first silicide film SC1 is higher than the silicide concentration in the vicinity of the interface between the first silicide film SC1 and the first diffusion region DR1. can do. The same applies to the silicide concentration in the second silicide film SC2. The silicide concentration can be determined by the intensity of a signal derived from silicide in X-ray photoelectron spectroscopy (XPS).

  In forming the first silicide film SC1, most of the first semiconductor film SM1 is preferably silicided in order to reduce the contact resistance between the first connection member CM1 and the first diffusion region DR1. On the other hand, if the entire first semiconductor film SM1 is to be silicided, the first diffusion region DR1 at the interface between the first contact hole CH1 and the first diffusion region DR1 may also be silicided. However, even if such silicidation is performed in the first diffusion region DR1, the first diffusion region DR1 is not silicided in the process shown in FIG. Therefore, the metal concentration for forming silicide in the first diffusion region DR1 at the interface between the first contact hole CH1 and the first diffusion region DR1 is the second diffusion at the interface between the second contact hole CH2 and the second diffusion region DR2. The concentration is lower than the metal concentration for forming silicide in the region DR2. Further, compared to the case where the first diffusion region DR1 is silicided in the step shown in FIG. 13A, the metal concentration for forming silicide in the first diffusion region in this embodiment is lower. Therefore, in the present embodiment, the first connection member CM1 and the first diffusion region are reduced while reducing the leakage current from the first connection member CM1 to the substrate SUB via the silicide in the first diffusion region DR1. Contact resistance with DR1 can be reduced.

  Next, a first metal film MF1 and a second metal film MF2 are formed on the first silicide film SC1 and the second silicide film SC2, respectively. Accordingly, the first connection member CM1 and the second connection member CM2 are formed in the first contact hole CH1 and the second contact hole CH2, respectively (FIG. 16). A method of forming the first metal film MF1 and the second metal film MF2 is as follows. The first method includes a step of forming a barrier metal film from the upper surface of the first silicide film SC1 and the second silicide film SC2 to the side surfaces of the first contact hole CH1 and the second contact hole CH2, and on the barrier metal film. The step of filling the first contact hole CH1 and the second contact hole CH2 with the conductive member by forming the conductive member, and the CMP of the barrier metal film and the conductive member formed outside the first contact hole CH1 and the second contact hole CH2 are performed. And removing it. The barrier metal film in this method may be composed of a laminated film in which titanium (Ti) and titanium nitride (TiN) are sequentially laminated, or a single layer film of titanium nitride (TiN). The conductor member may be made of tungsten (W). The second method is to form a barrier metal film from the upper surface of the first silicide film SC1 and the second silicide film SC2 to the side surfaces of the first contact hole CH1 and the second contact hole CH2, and on the barrier metal film. A step of forming a copper seed layer, a step of filling the first contact hole CH1 and the second contact hole CH2 with copper by copper plating using the copper seed layer, and formation outside the first contact hole CH1 and the second contact hole CH2. Removing the barrier metal film, the copper seed layer, and the copper by CMP.

  After the formation of the first connection member CM1 and the second connection member CM2, the interlayer insulation film ID2, the capacitor element CP, the third connection member CM3, and the first metal film MF2 are formed on the interlayer insulation film ID1, the first metal film MF1, and the second metal film MF2. Four connection members CM4 are formed. Thereafter, the interlayer insulating film ID3 and the wiring IC are formed on the interlayer insulating film ID2. Thereby, the semiconductor device SD shown in FIG. 1 is obtained.

  In the present embodiment, silicide is not formed or hardly formed in the first diffusion region DR1. For this reason, the leakage current from the first connection member CM1 to the substrate SUB via the silicide in the first diffusion region DR1 is reduced. In the present embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is formed of silicide (first connection member CM1) and a semiconductor (first diffusion region DR1). The contact resistance at the interface between the silicide and the semiconductor is smaller than the contact resistance at the interface between the metal and the semiconductor. Therefore, in the present embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is compared with a case where the interface is formed of a metal (first connection member CM1) and a semiconductor (first diffusion region DR1). Thus, the contact resistance between the first connection member CM1 and the first diffusion region DR1 can be reduced. In addition, when an interface between a metal and a semiconductor is formed, the semiconductor crystal may be distorted by the stress of the metal. Such crystal distortion can cause a leak path. On the other hand, in the present embodiment, such a metal-semiconductor interface is not formed at the interface between the first connecting member CM1 and the first diffusion region DR1. For this reason, a leak path due to crystal distortion in the first diffusion region DR1 can be reduced.

(Second Embodiment)
FIG. 17 is a cross-sectional view showing a semiconductor device SD according to the second embodiment. FIG. 17 is a schematic diagram showing the semiconductor device SD, and the configuration of the semiconductor device SD is not limited to that shown in FIG. The semiconductor device SD according to the present embodiment is the same as the semiconductor device SD according to the first embodiment, except that the first connection member CM1 and the second connection member CM2 further include the first semiconductor film SM1 and the second semiconductor film SM2, respectively. It has the same configuration as.

The first connection member CM1 in the present embodiment will be described in detail. The first connection member CM1 includes a first semiconductor film SM1 and a first silicide film SC1. The first semiconductor film SM1 is in contact with the interlayer insulating film ID1, the insulating film DF2 constituting the sidewall SW1, the etching stopper film ES, and the interlayer insulating film ID1 from the bottom to the side wall of the first contact hole CH1. When the distance between the first transistor TR1 and the first contact hole CH1 is short, the first semiconductor film SM1 may be in contact with the sidewall SW3. The first semiconductor film SM1 contains silicon but is not silicided. The first silicide film SC1 is formed on the first semiconductor film SM1. The first silicide film SC1 is formed of silicide. The first semiconductor film SM1 may be doped with impurities. In this case, the conductivity type of the first semiconductor film SM1 may be the same as the conductivity type of the first diffusion region DR1 with which the first semiconductor film SM1 is in contact. The first silicide film SC1 may be made of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. The first silicide film SC1 may be formed up to a position higher than the upper surface of the first gate electrode GE1. “Position higher than the upper surface of the first gate electrode GE1” means that the first gate silicide layer GS1 is formed on the surface of the first gate electrode GE1 as shown in FIG. The position is higher than the surface of the silicide layer GS1. Alternatively, the sum of the film thickness of the first semiconductor film SM1 and the film thickness of the first silicide film SC1 is the film thickness of the first gate insulating film GI1 (for example, 10 nm or more and 50 nm or less) and the film thickness of the first gate electrode GE1 ( For example, it may be greater than or equal to the total of 100 nm). The first connection member CM1 may further include a first metal film MF1. Alternatively, the first connection member CM1 may not include the first metal film MF1. When the first connection member CM1 does not include the first metal film MF1, the first semiconductor film SM1 and the first silicide film SC1 fill the entire first contact hole CH1. On the other hand, when the first connection member CM1 includes the first metal film MF1, the first metal film MF1 is formed on the first silicide film SC1. The configuration of the first metal film MF1 is the same as that of the first metal film MF1 of the first embodiment.

The second connection member CM2 will be described in detail. The second connection member CM2 includes a second semiconductor film SM2 and a second silicide film SC2. The second semiconductor film SM2 is in contact with the second diffusion region DR2, the etching stopper film ES, and the interlayer insulating film ID1 from the bottom to the side wall of the second contact hole CH2. When the distance between the second transistor TR2 and the first contact hole CH2 is short, the second semiconductor film SM2 may be in contact with the sidewall SW4. The second semiconductor film SM2 includes silicon but is not silicided. The second silicide film SC2 is formed on the semiconductor film SM2. The second silicide film SC2 is formed of silicide. The second semiconductor film SM2 may be doped with impurities. In this case, the conductivity type of the second semiconductor film SM2 may be the same as the conductivity type of the second diffusion region DR2 with which the second semiconductor film SM2 is in contact. The second silicide film SC2 may be formed of Ni silicide (Ni _1-x Pt _x Si (0 <x <1)) containing Ni silicide, Pt silicide, Co silicide, Ti silicide, or Pt. The second silicide film SC2 may be formed up to a position higher than the upper surface of the second gate electrode GE2. “Position higher than the upper surface of the second gate electrode GE2” means that the second gate silicide layer GS2 is formed on the surface of the second gate electrode GE2 as shown in FIG. The position is higher than the surface of the silicide layer GS2. Alternatively, the sum of the thickness of the second semiconductor film SM2 and the thickness of the second silicide film SC2 is the thickness of the second gate insulating film GI2 (for example, 10 nm or more and 50 nm or less) and the thickness of the second gate electrode GE2 ( For example, it may be greater than or equal to the total of 100 nm). The total thickness of the second semiconductor film SM2 and the second silicide film SC2 may be substantially the same as the total thickness of the first semiconductor film SM1 and the first silicide film SC1. “Substantially the same” is realized by forming the first semiconductor film SM1 and the first silicide film SC1, and the second semiconductor SM2 and the second silicide film SC2 in the same process, as will be described later. . The second connection member CM2 may further include a second metal film MF2. Alternatively, the second connection member CM2 may not include the second metal film MF2. When the second connection member CM2 does not include the second metal film MF2, the second semiconductor film SM2 and the second silicide film SC2 fill the entire second contact hole CH2. On the other hand, when the second connection member CM2 includes the second metal film MF2, the second metal film MF2 is formed on the second silicide film SC2. The configuration of the second metal film MF2 is the same as that of the second metal film MF2 of the first embodiment.

  In the present embodiment, the first semiconductor film SM1 is interposed between the first silicide film SC1 and the first diffusion region DR1. For this reason, a certain distance can be taken between the first silicide film SC1 and the first diffusion region DR1. Thereby, the leakage current from the first connection member CM1 to the substrate SUB via the first diffusion region DR1 can be suppressed. Further, in the vicinity of the interface of the first connection member CM1, an interface of silicide (first silicide film SC1) -semiconductor (semiconductor film SM1) and an interface of semiconductor (semiconductor film SM1) -semiconductor (first diffusion region DR1) are formed. ing. The contact resistance at such an interface is smaller than the contact resistance at the metal-semiconductor interface. Therefore, in the present embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is compared with a case where the interface is formed of a metal (first connection member CM1) and a semiconductor (first diffusion region DR1). Thus, the contact resistance between the first connection member CM1 and the first diffusion region DR1 can be reduced.

  Next, details of the method of manufacturing the semiconductor device SD in the present embodiment will be described with reference to FIGS. 18 and 19 are cross-sectional views showing a method for manufacturing the semiconductor device SD shown in FIG. 18 and 19 are schematic views showing a method for manufacturing the semiconductor device SD, and the method for manufacturing the semiconductor device SD is not limited to that shown in FIGS. The manufacturing method of the semiconductor device SD in the present embodiment is the same as that in the first embodiment in FIGS. 4 to 14, and the steps shown in FIGS. 18 and 19 are executed after the step shown in FIG. The

  After the steps shown in FIGS. 4 to 14, a first semiconductor film SM1 and a second semiconductor film SM2 are formed in the contact hole CH1 and the contact hole CH2, respectively (FIG. 18A). The method for forming the first semiconductor film SM1 and the second semiconductor film SM2 is the same as the method for forming the first semiconductor film SM1 and the second semiconductor film SM2 in the step shown in FIG. The process in the present embodiment may further include a process of doping the first semiconductor film SM1 and the second semiconductor film SM2 with impurities. For impurity doping, ion implantation, in-situ doping, or vapor phase doping may be used.

  Next, metal is introduced into the first semiconductor film SM1 and the second semiconductor film SM2, and the first semiconductor film SM1 and the second semiconductor film SM2 are silicided. This silicidation step is the same as the step shown in FIG. 15B except that the first semiconductor film SM1 at the interface between the first semiconductor film SM1 and the first diffusion region DR1 is not silicided. As a result, the first semiconductor film SM1 remains between the first silicide film SC1 and the first diffusion region DR1 (FIG. 18B). In the present embodiment, the ratio of silicidation in the first semiconductor film SM1 is appropriately adjusted. Conditions for appropriately adjusting the ratio of silicidation include heat treatment conditions and the concentration of metal constituting the silicide. In the present embodiment, the semiconductor film SM2 at the interface between the semiconductor film SM2 and the second diffusion region DR2 is similarly not silicided. When such a silicidation process is performed, it is preferable that the first semiconductor film SM1 and the second semiconductor film SM2 are doped with impurities. Thus, the dopant implanted into the first semiconductor film SM1 and the second semiconductor film SM2 is not easily taken into the silicide formed in the silicidation process. For this reason, the dopant concentration of the first semiconductor film SM1 and the second semiconductor film SM2 that have not been silicided increases. As a result, the contact resistance between the first semiconductor film SM1 and the first silicide film SC1 is reduced, and the contact resistance between the second semiconductor film SM2 and the second silicide film SC2 is reduced. In the first silicide film SC1 formed as described above, the silicide concentration in the vicinity of the upper surface of the first silicide film SC1 is set higher than the silicide concentration in the vicinity of the interface between the first silicide film SC1 and the first semiconductor film SM1. Can be high. The same applies to the silicide concentration in the second silicide film SC2. The silicide concentration can be determined by the strength of a signal derived from silicide in XPS. Further, when the formation of the first semiconductor film SM1 and the second semiconductor film SM2 is performed at the same time, and the silicidation of the first semiconductor film SM1 and the second semiconductor film SM2 is performed at the same time, the film thickness of the second semiconductor film SM2 and The total thickness of the second silicide film SC2 is substantially the same as the total thickness of the first semiconductor film SM1 and the first silicide film SC1.

  Next, a first metal film MF1 and a second metal film MF2 are formed on the first silicide film SC1 and the second silicide film SC2, respectively (FIG. 19). The method of forming the first metal film MF1 and the second metal film MF2 is the same as the process shown in FIG.

  Thereafter, the interlayer insulating film ID2, the capacitive element CP, the third connecting member CM3, and the fourth connecting member CM4 are formed on the interlayer insulating film ID1, the first metal film MF1, and the second metal film MF2. Thereafter, the interlayer insulating film ID3 and the wiring IC are formed on the interlayer insulating film ID2. Thereby, the semiconductor device SD shown in FIG. 17 is obtained.

  In the present embodiment, the first semiconductor film SM1 is interposed between the first silicide film SC1 and the first diffusion region DR1. For this reason, a certain distance can be taken between the first silicide film SC1 and the first diffusion region DR1. Thereby, the leakage current from the first connection member CM1 to the substrate SUB via the first diffusion region DR1 can be suppressed. Further, in the vicinity of the interface of the first connection member CM1, an interface of silicide (first silicide film SC1) -semiconductor (semiconductor film SM1) and an interface of semiconductor (semiconductor film SM1) -semiconductor (first diffusion region DR1) are formed. ing. The contact resistance at such an interface is smaller than the contact resistance at the metal-semiconductor interface. Therefore, in the present embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is compared with a case where the interface is formed of a metal (first connection member CM1) and a semiconductor (first diffusion region DR1). Thus, the contact resistance between the first connection member CM1 and the first diffusion region DR1 can be reduced.

(Third embodiment)
FIG. 20 is a cross-sectional view showing a semiconductor device SD according to the third embodiment. FIG. 20 is a schematic diagram showing the semiconductor device SD, and the configuration of the semiconductor device SD is not limited to that shown in FIG. The semiconductor device SD in the present embodiment is the same as the semiconductor device SD in the first embodiment, except for the configuration of the first silicide film SC1, the first metal film MF1, the second silicide film SC2, and the second metal film MF2. It has a configuration.

  The first connection member CM1 in the present embodiment will be described in detail. The first connection member CM1 includes a first silicide film SC1 and a first metal film MF1. The first silicide film SC1 is formed of silicide. The first silicide film SC1 is formed along the bottom and side walls of the first contact hole CH1. Such a structure of the first silicide film SC1 is realized by depositing the first silicide film SC1 directly from the bottom of the first contact hole CH1 to the side wall, as will be described later. In the present embodiment, the first silicide film SC1 may be formed on the entire side wall of the first contact hole CH1. The first metal film MF1 is formed in a region surrounded by the first silicide film SC1 in a plan view and overlapping the first silicide film SC1 in the height direction.

  The second connection member CM2 will be described in detail. The second connection member CM2 includes a second silicide film SC2 and a second metal film MF2. The second silicide film SC2 is formed of silicide. The second silicide film SC2 is formed along the bottom and side walls of the second contact hole CH2. Such a structure of the second silicide film SC2 is realized by depositing the second silicide film SC2 directly from the bottom of the second contact hole CH2 to the side wall, as will be described later. The film thickness of the second silicide film SC2 may be substantially the same as the film thickness of the first silicide film SC1. The “substantially the same” is realized by forming the first silicide film SC1 and the second silicide film SC2 in the same process as will be described later. In the present embodiment, the second silicide film SC2 may be formed on the entire side wall of the second contact hole CH2. The second metal film MF2 is formed in a region surrounded by the second silicide film SC2 in plan view and overlapping the second silicide film SC2 in the height direction.

  Also in the present embodiment, a silicide (first silicide film SC1) -semiconductor (first diffusion region DR1) interface is formed at the interface between the first connection member CM1 and the first diffusion region DR1. For this reason, as in the first embodiment, in this embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is made of a metal (first connection member CM1) and a semiconductor (first diffusion region DR1). Compared with the case where it is formed, the contact resistance between the first connecting member CM1 and the first diffusion region DR1 can be reduced.

  Next, details of the method of manufacturing the semiconductor device SD in the present embodiment will be described with reference to FIG. FIG. 21 is a cross-sectional view showing a method for manufacturing the semiconductor device SD shown in FIG. FIG. 21 is a schematic view showing a method for manufacturing the semiconductor device SD, and the method for manufacturing the semiconductor device SD is not limited to that shown in FIG. The manufacturing method of the semiconductor device SD in the present embodiment is the same as that in the first embodiment in FIGS. 4 to 14, and the process shown in FIG. 21 is executed after the process shown in FIG.

  After the steps shown in FIGS. 4 to 14, the first silicide film SC1 is deposited from the bottom of the first contact hole CH1 to the side wall. Similarly, a silicon-containing film SC2 is deposited from the bottom to the side wall of the second contact hole CH2. Thus, the first silicide film SC1 is formed from the bottom to the side wall of the first contact hole CH1, and the second silicide film SC2 is formed from the bottom to the side wall of the second contact hole CH2 (FIG. 21 (FIG. 21)). a)). CVD or sputtering may be used for the deposition of the first silicide film SC1 and the second silicide film SC2. By directly depositing the first silicide film SC1 and the second silicide film SC2 in this way, the first silicide film SC1 is formed along the bottom and side walls of the first contact hole CH1, and the second silicide film SC2 is formed along the bottom and side wall of second contact hole CH2. The deposition of the first silicide film SC1 and the second silicide film SC2 may be performed simultaneously. In this case, the film thicknesses of the first silicide film SC1 and the second silicide film SC2 are substantially the same. When the first silicide film SC1 and the second silicide film SC2 are directly deposited as described above, the step of forming a semiconductor film in the first contact hole CH1 and the second contact hole CH2 can be omitted. Thereby, simplification of a process is realized.

  Next, a first metal film MF1 and a second metal film MF2 are formed on the first silicide film SC1 and the second silicide film SC2, respectively (FIG. 21B). The first metal film MF1 and the second metal film MF2 are formed in a region surrounded by the first silicide film SC1 in a plan view and a region surrounded by the second silicide film SC2 in a plan view. The method of forming the first metal film MF1 and the second metal film MF2 is the same as the process shown in FIG.

  Thereafter, the interlayer insulating film ID2, the capacitive element CP, the third connecting member CM3, and the fourth connecting member CM4 are formed on the interlayer insulating film ID1, the first connecting member CM1, and the second connecting member CM2. Thereafter, the interlayer insulating film ID3 and the wiring IC are formed on the interlayer insulating film ID2. Thereby, the semiconductor device SD shown in FIG. 20 is obtained.

  In the present embodiment, it is not necessary to form a semiconductor film in the first contact hole CH1 and the second contact hole CH2 in manufacturing the semiconductor device SD. On the other hand, a silicide (first silicide film SC1) -semiconductor (first diffusion region DR1) interface is formed at the interface between the first connection member CM1 and the first diffusion region DR1. For this reason, as in the first embodiment, in this embodiment, the interface between the first connection member CM1 and the first diffusion region DR1 is made of a metal (first connection member CM1) and a semiconductor (first diffusion region DR1). Compared with the case where it is formed, the contact resistance between the first connecting member CM1 and the first diffusion region DR1 can be reduced. For this reason, in this embodiment, simplification of a manufacturing process is realizable, obtaining the effect in 1st Embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SD semiconductor device SUB substrate DR DRAM region LR logic region LR
TR1 transistor TR2 transistor WL1 well WL2 well WL3 well STI1 element isolation film STI2 element isolation film GI1 first gate insulating film GI2 second gate insulating film GE1 first gate electrode GE2 second gate electrode SW1 sidewall SW2 sidewall SW3 sidewall SW4 Side wall OS1 Offset spacer OS2 Offset spacer ES Etching stopper film DR1 First diffusion region DR2 Second diffusion region EX1 First extension region EX2 Second extension region GS1 First gate silicide layer GS2 Second gate silicide layer DS Diffusion region silicide layer CH1 First contact hole CH2 Second contact hole CH3 Third contact hole CH4 Fourth contact hole CM1 First connection member CM Second connecting member CM3 Third connecting member CM4 Fourth connecting member SC1 First silicide film SC2 Second silicide film MF1 First metal film MF2 Second metal film SM1 First semiconductor film SM2 Second semiconductor film ID1 Interlayer insulating film ID2 Interlayer Insulating film ID3 Interlayer insulating film MC Memory cell CP Capacitance element UE Upper electrode CI Capacitor insulating film LE Lower electrode IC Wiring BL Bit line IO I / O area DP DRAM peripheral circuit area BC Bit contact CC Capacitance contact GL Gate wiring DF1 Insulating film DF2 Insulating film DF3 insulating film DF4 insulating film DF5 insulating film DF6 insulating film PR1 photoresist PR2 photoresist PR3 photoresist PR4 photoresist PR5 photoresist PR6 photoresist PR7 photoresist PR7 photoresist

Claims (11)

A first gate electrode formed on the substrate;
A first diffusion region formed in the substrate at a side of the first gate electrode;
A first transistor comprising:
A second gate electrode formed on the substrate;
A second diffusion region formed in the substrate at a side of the second gate electrode;
A second transistor comprising:
An insulating film formed on the substrate;
A first connection member formed in a first contact hole penetrating the insulating film and reaching the first diffusion region;
A second connection member formed in a second contact hole that penetrates the insulating film and reaches the second diffusion region;
A capacitive element that forms a memory cell together with the first transistor and is electrically connected to the first diffusion region;
A wiring that constitutes a logic circuit together with the second transistor and is electrically connected to the second diffusion region;
Including
The first connection member includes a silicide-containing film that is at least partially silicided, and the silicide-containing film is formed by siliciding silicon formed in the first contact hole. . A first gate electrode formed on the substrate;
A first diffusion region formed in the substrate at a side of the first gate electrode;
A first transistor comprising:
A second gate electrode formed on the substrate;
A second diffusion region formed in the substrate at a side of the second gate electrode;
A second transistor comprising:
An insulating film formed on the substrate;
A first connection member formed in a first contact hole penetrating the insulating film and reaching the first diffusion region;
A second connection member formed in a second contact hole that penetrates the insulating film and reaches the second diffusion region;
A capacitive element that forms a memory cell together with the first transistor and is electrically connected to the first diffusion region;
A wiring that constitutes a logic circuit together with the second transistor and is electrically connected to the second diffusion region;
Including
The first connection member includes a first silicide film formed along the bottom and side walls of the first contact hole and formed of silicide.
The first connecting member includes a first metal film formed in a region surrounded by the first silicide film in a plan view and overlapping the first silicide film in a height direction. The semiconductor device according to claim 1,
The silicide-containing film is a semiconductor device including a first silicide film formed of silicide. The semiconductor device according to claim 3,
The semiconductor device, wherein the first silicide film is formed up to a position higher than an upper surface of the first gate electrode. The semiconductor device according to claim 1,
The silicide-containing film is
A first semiconductor film that is in contact with the first diffusion region and the insulating film from the bottom to the side wall of the first contact hole and that includes silicon and is not silicided;
A semiconductor device including a first silicide film formed of silicide and formed on the semiconductor layer. The semiconductor device according to claim 3,
The second connecting member is
A second silicide film formed by silicide and formed by siliciding silicon formed in the second contact hole;
The metal concentration for forming silicide in the first diffusion region at the interface between the first contact hole and the first diffusion region is set in the second diffusion region at the interface between the second contact hole and the second diffusion region. A semiconductor device having a lower concentration of metal that forms silicide. Forming a first gate electrode and a second gate electrode on the substrate, and forming a first diffusion region and a second diffusion region in the substrate on a side of each of the first gate electrode and the second gate electrode; When,
Forming an insulating film on the substrate;
Forming a first contact hole that penetrates the insulating film and reaches the first diffusion region, and a second contact hole that penetrates the insulating film and reaches the second diffusion region;
Forming a first connecting member in the first contact hole and forming a second connecting member in the second contact hole;
Forming a capacitive element electrically connected to the first diffusion region;
Forming a wiring electrically connected to the second diffusion region;
Including
The step of forming the first connection member includes a step of forming a silicide-containing film that is at least partially silicided from the bottom to the side wall of the first contact hole. A method of manufacturing a semiconductor device according to claim 7,
The step of forming the silicide-containing film includes:
Forming a first semiconductor film that includes silicon and is not silicided from the bottom of the first contact hole to the side wall;
Introducing a metal into the first semiconductor film to silicide the first semiconductor film;
A method of manufacturing a semiconductor device including: A method for manufacturing a semiconductor device according to claim 8, comprising:
Before the step of forming the second connection member, further comprising the step of forming a silicide layer in the second diffusion region,
The step of forming the second connection member includes:
Forming a second semiconductor film containing silicon and not silicided from the bottom to the side wall of the second contact hole;
Introducing a metal into the second semiconductor film to silicide the second semiconductor film;
Including
A method of manufacturing a semiconductor device in which a silicide layer is not formed in the first diffusion region before the step of forming the first connection member. A method for manufacturing a semiconductor device according to claim 8, comprising:
A method of manufacturing a semiconductor device, wherein, in the step of siliciding the semiconductor film, the semiconductor film at the interface between the semiconductor film and the first diffusion region is not silicided. A method of manufacturing a semiconductor device according to claim 7,
The step of forming the silicon-containing film includes a step of depositing a silicide film from the bottom surface of the first contact hole to the side wall,
A method of manufacturing a semiconductor device, further comprising a step of forming a metal film on the silicide film.

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