JP2014164664A - Task parallel processing method and device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an access time to data shared between processors.SOLUTION: In a task parallel processing method, when the preceding task (second task) of a first task assigned to a first processor is assigned to any processor other than the first processor, the first processor is allowed to stand by for executing the first task until the output data of the second task can be referenced by the first processor, and after the output data of the second task is able to be referenced by the first processor, the output data are acquired from the storage source of the output data, and stored in a first local memory owned by the first processor, and the first processor is allowed to execute the first task by referencing the output data stored in the first local memory, and the output data of the first task are stored in the first local memory, and when a following task (third task) of the first task is assigned to any processor other than the first processor, the output data of the first task can be referenced by any processor other than the first processor.

Description

  The present invention relates to a task parallel processing method, apparatus, and program, and more particularly, to a task parallel processing method, apparatus, and program for processing signals received using a wired line and a wireless line.

  In order for a plurality of processors to perform parallel processing in cooperation, the plurality of processors need to share data by some means. For example, in a multi-core processor in which a plurality of processors are mounted on one LSI (Large Scale Integration), a common data sharing means is to use a shared memory accessible from the plurality of processors.

  The shared memory accessible from a plurality of processors usually takes time to access due to access arbitration. Therefore, it is common to arrange a high-speed memory in each processor. As a means for realizing a high-speed memory of each processor, either a local memory or a cache (memory) can be cited.

  The cache is temporary storage means for storing a partial copy of the shared memory (hereinafter referred to as “partial copy”), and the operation of the cache is automatically controlled by the cache itself. On the other hand, the local memory is merely temporary storage means.

  In a multi-core processor, when each processor has a cache, it is necessary to maintain data consistency (coherent) of the plurality of caches. There are two methods for maintaining coherence: a hardware method for adding such a function to the cache itself, and a software method. In general, hardware methods are often used. The hardware method has the demerit of increasing the cache circuit scale and increasing the power consumption of the cache.

  On the other hand, the software method can avoid the disadvantages, but each processor needs to follow a predetermined software procedure when accessing the shared data. This predetermined software procedure also affects the configuration of the entire software operating on the multi-core processor. One example of a software method is reported in Patent Document 5.

  Since the cache automatically manages a partial copy of the shared memory, it is a very convenient temporary storage means. However, the time taken from when the processor requests the cache to read data until the cache delivers the data to the processor varies greatly depending on whether or not the data exists in the cache. That is, the time required for reading data from the cache varies.

  Therefore, there is a field in which local memory is actively used in order to avoid variations in cache data read time. In particular, a multi-core processor having a local memory is used in a field where real-time characteristics are important.

  Unlike a cache, the local memory takes a short time to read data from the local memory. However, since the capacity of the local memory is limited, it is necessary for a developer who designs software operating on a multi-core processor to strictly design what data is to be arranged in the local memory.

  What kind of data is arranged in the local memory is closely related to the problem of how to perform parallel processing in a multi-core processor. For this reason, software developers have studied both parallel processing and data placement.

  Conventionally, a method of arranging data that can be accessed by a plurality of processors in a shared memory and arranging data accessed by only one processor in a local memory has been generally used (for example, FIG. 11). This method determines the data arrangement in a fixed manner. This method is very simple and easy to think, but has its disadvantages. This is a disadvantage that it takes time to access data arranged in the shared memory.

  In order to avoid this disadvantage, a method of placing a partial copy of the shared memory in the local memory can be considered. However, in this case, another problem that management of partial copying becomes very complicated occurs. In order to execute this method, it is necessary to consider parallel processing in multi-core processors, management of partial copies in the local memory of each processor, and maintaining consistency of partial copies among multiprocessors. . Maintaining the consistency of partial copies is to place the same partial copies in the local memory of a plurality of processors so that they are not rewritten with different values.

  In other words, in order to place a partial copy on the local memory in parallel processing, it is necessary to handle the partial copy management, consistency maintenance, and parallel processing on the local memory in an integrated manner. However, it is not practical to handle these in an integrated manner because it is a heavy burden on the programmer and takes a lot of man-hours.

  In addition, there exist the following patent documents 1-4 as a related technique. Patent Document 1 discloses a multi-purpose power source that reduces power consumption without degrading processing performance, and reduces power while observing time constraints when executing a program that requires real-time processing. Techniques relating to processor systems and compilers are disclosed.

  Patent Document 2 discloses a technique related to a memory management method for efficiently arranging data in a memory. In particular, the processor according to Patent Document 1 divides a storage area of a memory into a plurality of blocks having different sizes, selects a block having a size suitable for data used when the task is executed, and assigns a task to the selected block. Stores data used during execution of.

  Patent Document 3 discloses a technique related to a processing system having a shared memory and a plurality of processors, each processor having a local memory. The processor according to Patent Document 3 copies data from a shared memory to a local memory related to program execution or the like.

  Patent Document 4 discloses a technique related to a multiprocessor system including a plurality of processors having no interprocessor exclusive control function and a shared memory. In the multiprocessor system according to Patent Document 4, when a certain processor receives a processing request from another processor, it performs processing based on the data in the transmission buffer, and then notifies the processing requesting processor of the end of processing.

JP 2006-293768 A JP 2008-217134 A JP 2006-221638 A JP 2000-235553 A International Publication No. 2009/057762

  As described above, in parallel processing on a multi-core processor including a shared memory and a local memory, it has been generally known that “shared data that can be accessed from multiple processors is arranged in the shared memory”. However, the shared data arrangement method used in the field has a problem that “access to data arranged in the shared memory takes time”. This problem leads to a problem that the processing time of the entire parallel processing increases when the number of shared data is large. This is because shared data such as variables stored in the shared memory can be accessed multiple times during the execution of a task. Patent Documents 1 to 5 do not disclose means for solving these problems.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a task parallel processing method, apparatus, and program for shortening access time to data shared between processors.

The task parallel processing method according to the first aspect of the present invention includes:
When the second task that is the preceding task in the first task assigned to the first processor is assigned to other than the first processor, the output data from the second task can be referred to by the first processor , Wait for the execution of the first task,
After the output data from the second task can be referred to by the first processor, the output data is acquired from the output data storage source and stored in the first local memory of the first processor;
With reference to the output data stored in the first local memory, the first processor executes the first task, stores the output data from the first task in the first local memory,
When a third task, which is a subsequent task in the first task, is assigned to a processor other than the first processor, the output data from the first task can be referred to from a processor other than the first processor. .

The task parallel processing device according to the second aspect of the present invention is:
Comprising a plurality of processors having local memory;
A first processor of the plurality of processors is
Having a first local memory;
When the second task, which is the preceding task in the first task assigned to the first processor, is assigned to other than the first processor, the first task is used until the output data from the second task can be referred to. Wait for task execution,
After the output data by the second task can be referred to, the output data is obtained from the storage source of the output data and stored in the first local memory,
Referring to output data stored in the first local memory, executing the first task, storing output data by the first task in the first local memory,
When a third task, which is a subsequent task in the first task, is assigned to a processor other than the first processor, the output data from the first task can be referred to from a processor other than the first processor. .

The task parallel processing program according to the third aspect of the present invention is:
When the second task that is the preceding task in the first task assigned to the first processor is assigned to other than the first processor, the output data from the second task can be referred to by the first processor A process of waiting for the execution of the first task;
After the output data from the second task can be referred to by the first processor, the output data is acquired from the storage source of the output data and stored in the first local memory of the first processor;
A process in which the first processor executes the first task with reference to the output data stored in the first local memory, and stores the output data from the first task in the first local memory;
When a third task, which is a subsequent task in the first task, is assigned to a processor other than the first processor, the output data from the first task can be referred to from a processor other than the first processor. Processing,
Is executed on the computer.

  According to the present invention, it is possible to provide a task parallel processing method, apparatus, and program for shortening access time to data shared between processors.

It is a block diagram which shows the example of a structure and data arrangement | positioning of the multi-core processor concerning embodiment of this invention. It is a figure which shows the example of the taskflow graph made into object by embodiment of this invention. It is a flowchart which shows the flow of a process of the task parallel processing method concerning embodiment of this invention. It is a flowchart which shows the flow of a process of the processor concerning embodiment of this invention. It is a figure which shows the example of the task allocation and data arrangement | positioning concerning the specific example 1 of embodiment of this invention. It is a flowchart which shows the flow of the task process concerning the specific example 1 of embodiment of this invention. It is a flowchart which shows the flow of the task process concerning the specific example 1 of embodiment of this invention. It is a figure which shows the example of the task allocation and data arrangement | positioning concerning the specific example 2 of embodiment of this invention. It is a flowchart which shows the flow of the task process concerning the specific example 2 of embodiment of this invention. It is a flowchart which shows the flow of the task process concerning the specific example 2 of embodiment of this invention. It is a block diagram which shows the example of the data arrangement | positioning in the multi-core processor concerning related technology.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

  First, in describing the embodiment of the present invention, a parallel processing model and a topological sort to be processed by the present embodiment will be described.

<Parallel processing model targeted by the present invention>
The parallel processing handled by the exemplary embodiment of the present invention will be described. An exemplary embodiment of the present invention deals with parallel processing that can be represented by a task flow graph belonging to a directed acyclic graph (DAG). Hereinafter, unless otherwise specified, it is assumed that the “task flow graph” belongs to the acyclic directed graph.

  The task flow graph has a graph structure representing data dependency of calculation processes (tasks) constituting parallel processing. A calculation process constituting parallel processing is called a task. In the task flow graph, a node represents a task, and an edge between nodes represents a data dependency between tasks. An example of a task flow graph is shown in FIG. In FIG. 2, there are six tasks T1 to T6. By using the task flow graph, it is possible to easily express the data dependency relationship of the tasks constituting the target parallel processing. “Data dependency” here means between a data supply task that plays the role of supplying data related to the data used by the task to be executed and a data use task that plays the role of using the data The dependency relations such as the execution order (preceding and succeeding) existing in FIG.

  For example, it is assumed that the task T2 uses the calculation result (data A) of the task T1. In this case, for data A, task T1 is a data supply task and task T2 is a data use task. In such a case, it can be said that there is a data dependency relationship from the task T1 that is the data supply task to the task T2 that is the data use task. If there is a data dependency from task T1 to task T2, task T2 must be executed after task T1. In this case, the task T2 is a preceding task in the task T1, and the task T1 is a succeeding task in the task T2.

  Furthermore, in the parallel processing handled by the exemplary embodiment of the present invention, it is assumed that each node in the task flow graph is assigned a sequence number based on topological sort. The topological sort will be described later.

  In addition, in the parallel processing handled by the exemplary embodiment of the present invention, calculation processing that can be expressed by a task flow graph is performed by a plurality of processors or a plurality of cores (hereinafter referred to as “processors” including the processor and the core). It is assumed that calculation is performed in parallel, and which processor executes each task of the task flow graph is determined in advance. Information about which processor executes which task is information attached to the task flow graph. Generally, since the number of tasks is larger than the number of processors, one processor executes a plurality of tasks. As described above, since tasks are given sequence numbers based on topological orders, the exemplary embodiment of the present invention regards this sequence number as the execution order of tasks, and each processor has a sequence number. The tasks are executed in order from the smallest task. The present embodiment handles parallel processing of computation processing that can be represented by such a task flow graph.

<About topological sort>
Next, the topological sort will be described. The topological sort is to order each node of the acyclic directed graph so that every node comes before the node ahead of its output edge. Typical usage examples of topological sort are task scheduling and instruction scheduling in a compiler. In other words, the order in which tasks should be executed can be understood by representing a task set having data dependency relationships with a directed acyclic graph and topologically sorting the acyclic directed graph. The order obtained by the topological sort is not limited to one, and a plurality of correct orders may exist.

<Problems of general data placement methods>
Subsequently, prior to the description of the embodiment of the present invention, problems of a general data arrangement method according to related technology are summarized. 11 shows an example of a general data arrangement method in the multi-core processor 900 including the CPUs 21 to 24 having the local memories 11 to 14 and the shared memory 30. The method according to the related art shown in FIG. 11 classifies data as non-shared or shared, places the shared data 901 in the shared memory 30, and sets the non-shared data 911, 921, 931 and 941 to the local memories 11, 12, 13 and 14, respectively. Here, there is no overlap between the data arranged in the shared memory 30 and the local memories 11-14. That is, the shared data 901 is data used by a plurality of processors, the non-shared data 911 is data used only by the CPU 21, the non-shared data 921 is data used only by the CPU 22, and the non-shared data 931 is the CPU 23. The non-shared data 941 is data that only the CPU 24 uses.

  The shared memory generally takes time to read and write data compared to the local memory. Therefore, arranging a large amount of shared data in the shared memory increases the calculation time of the entire parallel processing using the shared data. Furthermore, in the method according to the related art, all shared data used by two or more processors is placed in the shared memory. If the number of processors is increased to increase the number of processes to be operated in parallel, the shared memory is stored in the shared memory. Since the number of accessing processors increases, the number of accesses to the shared memory increases. That is, the method according to the related art has a problem that the processor accesses the shared memory having a long access time many times.

<An exemplary embodiment of the present invention>
Exemplary embodiments of the invention are described. The present embodiment is a parallel information processing method and apparatus that provides parallel processing on a multi-core processor including a plurality of processors including a local memory. FIG. 1 is a block diagram showing an example of the configuration and data arrangement of a multi-core processor 100 according to an embodiment of the present invention. The multi-core processor 100 includes local memories 11 to 14, CPUs 21 to 24, and a shared memory 30. In the local memories 11 to 14 of the processors 21 to 24, data (assigned task reference data 111, 121, 131, and 141) referred to by the task to which each processor is allocated is arranged and accessible from all processors. Data (multitask reference data 301) to be shared by a plurality of processors is placed in the shared memory 30.

  In the present embodiment, regarding the execution of an arbitrary first task of a program that can be expressed as a task flow graph, before executing the first task, the task flow graph has an edge to the first task, and the first task is Wait until the output data of the second task group to be executed by other than the first processor to execute is ready to be referred to (first step), and after the first step, the output data of the second task group is sent to the first processor. Copy to the local memory (second step), execute the first task, store the calculation result in the local memory of the first processor (third step), and have an edge from the first task in the task flow graph. A state in which the third task group can refer to the output data of the first task when there is a third task group to be executed by other than the first processor To (Fourth step), characterized in that, in parallel information processing apparatus, and methods. In addition to the first task, the second task and the third task are implemented as programs that can be expressed as a task flow graph.

  In other words, in the present embodiment, when the second task that is the preceding task in the first task assigned to the first processor is assigned to other than the first processor, the output data from the second task is the first task. Wait for execution of the first task until it can be referred to by one processor, and after the output data from the second task becomes referenceable by the first processor, obtain the output data from the storage source of the output data To the first local memory of the first processor, referring to the output data stored in the first local memory, the first processor executes the first task, and the output data from the first task is The third task, which is stored in the first local memory and is a subsequent task in the first task, is sent to a processor other than the first processor. If you are devoted Ri, the output data of the first task to see ready the processor other than the first processor, a task parallel processing method, method and program.

  The multi-core processor 100 performs the first step (S1) to the fourth step (S4) as shown in FIG. 3 with an arbitrary task of a program that can be expressed as a task flow graph as the first task.

  The first step is a process of waiting until the first task is ready to be executed. Here, the second task group is a task group that is executed by other than the first processor and supplies input data to the first task. When it is confirmed that the first task can refer to the output data of the second task group, the first task can be executed. If the second task group does not exist, there is no second task group to which the output data should be referenced, so no waiting is required, and the first task is in an executable state. For example, if all tasks having an edge to the first task are executed by the first processor (processor that executes the first task) in the task flow graph, the second task group does not exist. Further, the second task group may be one or more tasks.

  The above can be paraphrased as follows. That is, it is assumed that the first processor is assigned in advance as a processor that executes the first task. Assume that a processor other than the first processor is assigned in advance as a processor that executes the second task. Further, it is assumed that the second task is a preceding task in the first task. In this case, the first processor waits for execution of the first task until the output data from the second task can be referred to by the first processor (S1).

  The second step is a process of copying the output data of the second task group serving as input data to the first task to the local memory of the first processor. Although the output data of the second task group is stored in a location that can be referred to from the first processor, the access time of the local memory is earlier than that location for the first processor. Therefore, by copying the output data of the second task group to the local memory of the first processor, the first processor executing the first task can access the input data of the first task at high speed. In the second step, the location where the output data of the second task group is stored may be a shared memory or a local memory of each processor accessible from other processors. If the second task group does not exist, there is no output data to be copied, so the copy process is unnecessary.

  The above can be paraphrased as follows. That is, after the output data from the second task can be referred to by the first processor, the first processor acquires the output data from the storage source of the output data and stores it in the first local memory of the first processor (S2). .

  Also, when it is clear that the output data to be copied exists in the local memory of the processor that executes the first task, the copy process is unnecessary. For example, if a plurality of first tasks assigned to a certain processor have the same task as the second task group, the output data to be copied in the second step is the same. In this case, in the other second step, it is clear that the output data to be copied exists in the local memory, so that the copy process is not necessary after the first second step.

  The above can be paraphrased as follows. That is, the fourth task executed after the first task is also assigned to the first processor. It is assumed that the preceding task in the fourth task is the second task. In this case, the first processor refers to the output data of the second task stored in the first local memory before the execution of the first task without acquiring the output data from the storage source of the output data of the second task. Then, the fourth task is executed.

  The third step is a process for executing the first task. Since it is confirmed that the state is executable in the first step and the input data is prepared in the second step, the first task is ready for execution. In the third step, the first processor executes the first task using the input data existing in the local memory of the first processor, and the output data of the first task is stored in the local memory of the first processor.

  The above can be paraphrased as follows. That is, the first processor refers to the output data stored in the first local memory, executes the first task (S3), and stores the output data from the first task in the first local memory.

  The fourth step is a process of making the output data of the first task stored in the local memory of the first processor accessible for the third task group that uses the output data of the first task as input data. It is. In this process, when the output data of the first task is not referable from other than the first processor, the process of copying the output data of the first task to a place (for example, shared memory) that can be referred to by other than the first processor; Recording the fact that the execution of the first task is completed and the output data can be referred to. This copy process is a process that is paired with the copy process in the second step. If the copy source in the second step is a shared memory, the copy destination in the fourth step is also a shared memory. If the copy source of the second step is the local memory of a certain processor, each processor can access each other's local memory, so the copy process of the fourth step is unnecessary. Through this series of processing, the processor in charge of execution of the third task group can know that the output data of the first task can be referred to. If the third task group does not exist, since the output data of the first task is not used except for the first processor, the copy process in the fourth step is unnecessary, and whether the output data of the first task can be referred to. Since there is no task to know, there is no need to record the referenceable state of the output data of the first task.

  The above can be paraphrased as follows. That is, the first processor refers to output data from the first task from a processor other than the first processor when a third task that is a subsequent task in the first task is assigned to a processor other than the first processor. It sets so that it may be in a possible state (S4).

  Subsequently, the above-described first to fourth steps will be described from the viewpoint of each processor. FIG. 4 is a flowchart showing a processing flow of the processor according to the embodiment of the present invention. First, each processor selects tasks assigned to it in order from the smallest sequence number (S21). Each processor executes the selected task in the order from the first step to the fourth step described above (S22). Thereafter, it is determined whether or not the processing of all tasks assigned to itself has been completed (S23). Therefore, each processor repeats the first step to the fourth step as many times as the number of tasks to which execution is assigned.

  Furthermore, each processor executes tasks in order according to the sequence number based on the topological order. Since this execution order is an execution order determined in advance based on the data dependency relationship of the task flow graph, it is not necessary to confirm the completion of task execution among the tasks assigned to one processor. In addition, since the output data of the task assigned to one processor is stored in the same local memory, it is not necessary for the tasks assigned to one processor to pass output data through the shared memory. Therefore, as described above, when the second task group does not exist, the waiting for the first step becomes unnecessary and the copying process of the second step becomes unnecessary. Further, when the third task group does not exist, the copy process and the execution completion recording process in the fourth step are not necessary.

<Specific example 1 of embodiment of this invention>
A specific example 1 of the embodiment will be described. Specific example 1 is a parallel information processing apparatus and method for providing parallel processing on a multi-core processor including a plurality of processors including a local memory and a shared memory for sharing data between the processors.

  In the first specific example, an arbitrary task of a program that can be expressed as a task flow graph is set as the first task, and the first to fourth steps are performed. In Specific Example 1, data is shared between processors using a shared memory. Therefore, the copy source in the second step is a shared memory, and the copy destination in the fourth step is also a shared memory.

  In the first step, Example 1 waits until the first task can be executed (the output data of the second task group can be referred to). Subsequently, in the second step, the specific example 1 copies the output data of the second task group serving as input data to the first task from the shared memory to the local memory of the first processor. Subsequently, in the third step, the specific example 1 executes the first task and stores the output data in the local memory. Subsequently, in the fourth step, in the first specific example, if there is a third task group that uses the output data of the first task as input data, the first task is stored in the local memory of the first processor. The output data is copied to the shared memory, and the fact that the output data of the first task can be referenced is recorded in the shared memory.

  Subsequently, the above-described first to fourth steps will be described from the viewpoint of each processor. As described above, the exemplary embodiment of the present invention assumes that each processor executes in order from the task with the smallest sequence number. That is, each processor of the first specific example repeats the first step to the fourth step as many times as the number of tasks assigned to the processor.

  Furthermore, each processor executes tasks in order according to the sequence number based on the topological order. Since this execution order is an execution order determined in advance based on the data dependency relationship of the task flow graph, it is not necessary to confirm the completion of task execution among the tasks assigned to one processor. In addition, since the output data of the task assigned to one processor is stored in the same local memory, it is not necessary for the tasks assigned to one processor to pass output data through the shared memory. Therefore, as described above, when the second task group does not exist, the waiting for the first step becomes unnecessary and the copying process of the second step becomes unnecessary. Furthermore, when the third task group does not exist, the copy process and the output data referenceable state recording process in the fourth step are not necessary.

<Operation example of specific example 1>
Subsequently, an operation example of the first specific example will be described with reference to the drawings. First, FIG. 2 is a diagram illustrating an example of a task flow graph targeted by the first specific example. That is, it is assumed that the six tasks T1 to T6 have the data dependency as shown in FIG. Specifically, the task T1 has no preceding task, and the tasks T2 and T3 are the subsequent tasks. Therefore, the task T1 receives external data and outputs data A. The task T2 has the task T1 as a preceding task and the task T4 as a subsequent task. Therefore, the task T2 receives the data A output by the task T1 and outputs data B. The task T3 has the task T1 as a preceding task and the tasks T4 and T5 as subsequent tasks. Therefore, the task T3 receives the data A output by the task T1 and outputs data B. For the task T4, the tasks T2 and T3 are the preceding tasks, and the task T6 is the succeeding task. Therefore, task T4 receives data B output by task T2 and data C output by task T3, and outputs data D. The task T5 has the task T3 as a preceding task and the task T6 as a subsequent task. Therefore, the task T5 receives the data C output by the task T3 and outputs data E. It is assumed that task T6 has tasks T4 and T5 as preceding tasks and no subsequent tasks. Therefore, the task T6 receives the data D output by the task T4 and the data E output by the task T5, and outputs data F.

  FIG. 5 is a diagram illustrating an example of task assignment and data arrangement of the multi-core processor 100 according to the first specific example of the embodiment of the present invention. In FIG. 5, the number of processors included in the specific example 1 is described as four, but the number of processors is not limited to this. Assume that the six tasks T1 to T6 in FIG. 2 are assigned in advance to the four processors in the first specific example as shown in FIG. That is, the tasks T1 and T2 are assigned to the CPU 21, the tasks T3 and T4 are assigned to the CPU 22, the task T5 is assigned to the CPU 23, and the task T6 is assigned to the CPU 24. Since the assignment is determined in this way, the arrangement of the input / output data of each task is shown in FIG. It will be decided like 5. That is, the external data 511, data A512 and data B513 which are input / output data of the tasks T1 and T2 are stored in the local memory 11 of the CPU 21, and the data A521 which is input / output data of the tasks T3 and T4 are stored in the local memory 12 of the CPU 22. , Data B522, data C523 and data D524, data C531 and data E532 which are input / output data of task T5 in the local memory 13 of the CPU 23, and data D541 which is input / output data of task T6 in the local memory 14 of the CPU 24. , Data E542 and data F543 are respectively arranged.

  In Specific Example 1, since data is shared between processors using a shared memory, data to be passed between tasks executed between different processors is arranged in the shared memory 30 as shown in FIG. Will be. That is, the external memory 311, data A 312, data B 313, data C 314, data D 315, data E 316, and data F 317 are stored in the shared memory 30. The external data 511 and the external data 311 have the same contents, the data A 512, the data A 521, and the data A 312 have the same contents, the data B 513, the data B 522, and the data B 313 have the same contents, and the data C 523, the data C 531, and Data C314 has the same contents, data D524, data D541, and data D315 have the same contents, data E532, data E542, and data E316 have the same contents, and data F543 and data F317 have the same contents.

  Next, FIGS. 6 and 7 are flowcharts showing a flow of task processing (a state in which the task T1 to the task T6 are executed) according to the first specific example. 6 and 7, the four processors 21 to 24 of the first specific example sequentially execute the tasks according to the sequence numbers based on the topological order. Each task is executed based on the first to fourth steps described above. According to the task flow graph from task T1 to task T6 (FIG. 2), it is task T1 that performs calculation without using the output data of any task, so only task T1 does not need to wait for the first step. It can be seen that it is ready to execute. Accordingly, in FIG. 6 and FIG. 7, the operation starts from the processing of the task T1 by the CPU 21.

  The CPU 21 first performs the first step of the task T1, but as described above, since the waiting for the first step is not necessary for the task T1, the CPU 21 immediately moves to the second step of the task T1. Next, in the second step of the task T1, the CPU 21 copies the input data (external data 311) of the task T1 from the shared memory 30 to the local memory 11 (as external data 511) (S310). Next, in the third step of the task T1, the CPU 21 executes the task T1 (S311), and writes the output data (data A512) of the task T1 in the local memory 11. Next, since there is a task corresponding to the above-described third task group (task T3 executed by the CPU 22) in the fourth step of the task T1, the CPU 21 stores the output data (data A512) of the task T1 in the local memory 11 Is copied to the shared memory 30 (as data A312) (S312), and a flag (completion flag) that the output data of the task T1 can be referred is set (S313). The completion flag is placed on the shared memory 30. Thus far, the first to fourth steps of task T1 are completed.

  Subsequently, when the processing of the task T1 is completed, the CPU 21 performs the processing of the task T2 based on the execution order based on the sequence number. According to the task flow graph of FIG. 2, since the task T2 uses only the output data of the task T1, when the task T2 is regarded as the first task, there is no task corresponding to the second task group. Since the second task group does not exist and the task T1 has already been executed by the CPU 21, the first step of the task T2 is not necessary, and the CPU 21 immediately moves to the next step. Next, since there is no task corresponding to the second task group in the second step of task T2, the CPU 21 does not need to copy and moves to the next step. Next, in the third step of the task T2, the CPU 21 executes the task T2 (S314) and writes the output data (data B513) of the task T2 in the local memory 11. Next, since there is a task corresponding to the above-described third task group (task T4 executed by the CPU 22) in the fourth step of the task T2, the CPU 21 outputs the output data (data B513) of the task T2 to the local memory 11 To the shared memory 30 (as data B313) (S315), and a flag (completion flag) that the output data of the task T2 can be referred is set (S316). At this point, the first to fourth steps of task T2 are completed.

  Subsequently, processing of the task T3 by the CPU 22 will be described. When the CPU 21 executes the tasks T1 and T2, the output data of the tasks T1 and T2 can be referred to. According to the task flow graph of FIG. 2, the CPU 22 is in a state where the task T3 and the task T4 can be executed (after the execution of the task T3). According to the task flow graph of FIG. 2, when the task T3 is regarded as the first task, the task corresponding to the second task group is the task T1. The CPU 22 refers to a flag (completion flag) that the output data of the task T1 can be referred to in the first step of the task T3, and can execute the task T3 (refer to the output data of the task T1). Wait until it becomes possible (S320). Then, after the processing of task T1 by CPU 21 (from the first step to the fourth step) is completed, the output data reference flag (completion flag) of task T1 is set (S313), so that CPU 22 performs task T1. The completion flag is detected (S321), the waiting is finished, and the process proceeds to the next step. Next, since the task (task T1) corresponding to the second task group exists in the second step of the task T3, the CPU 22 transfers the output data (data A 312) of the task T1 from the shared memory 30 to the local memory 12 of the CPU 22. To (as data A521) is copied (S322). Next, in the third step of the task T3, the CPU 22 executes the task T3 (S323), and writes the output data (data C523) of the task T3 in the local memory 12. Next, in the fourth step of the task T3, the CPU 22 has a task corresponding to the above-described third task group (task T5 executed by the CPU 23), and therefore outputs the output data (data C523) of the task T3 to the local memory 12 To the shared memory 30 (as data C314) (S324), and a flag (completion flag) that the output data of the task T3 can be referred is set (S325). Thus far, the first to fourth steps of task T3 are completed.

  Next, the process of task T4 by the CPU 22 will be described. When the processing of the task T3 is completed, the CPU 22 performs the processing of the task T4 based on the execution order based on the sequence number. According to the task flow graph of FIG. 2, when the task T4 is regarded as the first task, the task corresponding to the second task group is the task T2. In the first step of task T4, the CPU 22 refers to a flag (completion flag) that the output data of task T2 can be referred to, and can execute task T4 (refer to the output data of task T2). Wait until it becomes possible. Here, after the processing of the task T2 by the CPU 21 (from the first step to the fourth step) is completed, the reference flag (completion flag) of the task T2 output data is set (S316). The completion flag is detected (S326), the waiting is finished, and the process proceeds to the next step. Next, since there is a task (task T2) corresponding to the second task group in the second step of task T4, the CPU 22 transfers the output data (data B313) of the task T2 from the shared memory 30 to the local memory 12 of the CPU 22. To (as data B522) (S327). Next, in the third step of the task T4, the CPU 22 executes the task T4 (S328), and writes the output data (data D524) of the task T4 to the local memory 12. Next, in the fourth step of task T4, the CPU 22 has a task corresponding to the above-described third task group (task T6 executed by the CPU 24), and therefore outputs the output data (data D524) of the task T4 to the local memory 12 To the shared memory 30 (as data D315) (S329), and a flag (completion flag) that the output data of the task T4 can be referred is set (S330). Thus far, the first step 4 of the task T4 is completed.

  Next, the process of task T5 by the CPU 23 will be described. When the CPU 22 executes the task T3, the output data of the task T3 can be referred to. According to the task flow graph of FIG. 2, the CPU 23 is ready to execute the task T5. According to the task flow graph of FIG. 2, when the task T5 is regarded as the first task, the task corresponding to the second task group is the task T3. In the first step of task T5, CPU 23 refers to a flag (completion flag) that the output data of task T3 can be referred to, and can execute task T5 (refer to the output data of task T3). Wait until it becomes possible (S340). After the processing of task T3 by CPU 22 (from the first step to the fourth step) is completed, the output data reference flag (completion flag) of task T3 is set (S325), so that CPU 23 performs task T3. The completion flag is detected (S341), the waiting is ended, and the process proceeds to the next step. Next, since there is a task (task T3) corresponding to the second task group in the second step of task T5, the CPU 23 transfers the output data (data C314) of the task T3 from the shared memory 30 to the local memory 13 of the CPU 23. To (as data C531) (S342). Next, in the third step of task T5, CPU 23 executes task T5 (S343), and writes the output data (data E532) of task T5 to local memory 13. Next, since there is a task corresponding to the above-described third task group (task T6 executed by the CPU 24) in the fourth step of the task T5, the CPU 23 outputs the output data (data E532) of the task T5 to the local memory 13 To the shared memory 30 (as data E316) (S344), and a flag (completion flag) that the output data of the task T5 can be referred is set (S345). Thus far, the first to fourth steps of task T5 are completed.

  Next, the process of task T6 by the CPU 24 will be described. When the CPU 22 executes the task T4 and the CPU 23 executes the task T5, the output data of the tasks T4 and T5 can be referred to. According to the task flow graph of FIG. 2, the CPU 24 is ready to execute the task T6. According to the task flow graph of FIG. 2, when the task T6 is regarded as the first task, the tasks corresponding to the second task group are the task T4 and the task T5. In the first step of task T6, the CPU 24 refers to a flag (completion flag) that the output data of task T3 can be referred to, and can execute task T6 (refer to the output data of task T3). Wait until it becomes possible (S350). Then, after the processing of task T4 by CPU 22 (from the first step to the fourth step) and the processing of task T5 by CPU 23 (from the first step to the fourth step) are completed, an output data reference flag (completed) of task T4 is completed. Flag) and the task T5 output data referable flag (completion flag) are set (S330 and S345), the CPU 24 detects the completion flags of the tasks T4 and T5 (S351 and S352), and ends the waiting. Move on to the next step. Next, since there is a task (task T4 and task T5) corresponding to the second task group in the second step of task T6, the CPU 24 outputs the output data (data D315 and data E316) of task T4 and task T5. Copy from the shared memory 30 to the local memory 14 of the CPU 24 (as data D541 and data E542) (S353 and S354). Next, the CPU 24 executes the task T6 in the third step of the task T6 (S355), and writes the output data (data F543) of the task T6 in the local memory 14. Next, in the fourth step of task T6, although there is no task corresponding to the aforementioned third task group, the output data of task T6 can be regarded as the output data of the entire task flow graph of FIG. The output data (data F543) of T6 is copied from the local memory 14 to the shared memory 30 (as data F317) (S356), and a flag (completion flag) that the output data of task T6 can be referred is set. (S357). Thus far, the first to fourth steps of task T6 are completed.

  The multi-core processor 100 according to the first specific example confirms that the output data of the task T6 that is the output data of the entire task flow graph of FIG. It is determined that the processing is completed.

<Specific Example 2 of Embodiment of the Present Invention>
Specific example 2 of the embodiment will be described. Specific example 2 is a parallel information processing apparatus and method for providing parallel processing on a multi-core processor configured such that each processor can mutually access local memory included in each of a plurality of processors.

  In the second specific example, an arbitrary task of a program that can be expressed as a task flow graph is set as the first task, and the first to fourth steps are performed. In the second specific example, the shared memory is not used, and the data is shared between the processors by referring to the local memory included in the processors. Therefore, the copy source of the second step is a local memory of a certain processor, and the copy process of the fourth step is not necessary.

  In the first step, the specific example 2 waits until the first task can be executed (the output data of the second task group can be referred to). Subsequently, in the second step, the specific example 2 shows that the output data of the second task group serving as input data to the first task is transferred from the local memory group of the processor that executed the second task group to the local memory of the first processor. Copy to. Subsequently, in the third step, the specific example 2 executes the first task and stores the output data in the local memory. Subsequently, in the fourth step, specific example 2 indicates that if there is a third task group that uses the output data of the first task as input data, the output data of the first task can be referred to. Record in the local memory of the first processor.

  Subsequently, the above-described first to fourth steps will be described from the viewpoint of each processor. As described above, the exemplary embodiment of the present invention assumes that each processor executes in order from the task with the smallest sequence number. That is, similarly to the specific example 1, each processor of the specific example 2 repeats the first step to the fourth step as many times as the number of tasks assigned to the processor. Further, each processor of the second specific example is similar to the second specific example in that the tasks are sequentially executed in accordance with the sequence number based on the topological order. Therefore, as in the second specific example, in the first specific example, it is not necessary to confirm the completion of the task execution among the tasks assigned to one processor, and the first step is performed when the second task group does not exist. Is not required, and the copy process in the second step is unnecessary, and when the third task group does not exist, the copy process in the fourth step and the output data referenceable state recording process are unnecessary.

<Operation example of specific example 2>
Subsequently, an operation example of the specific example 2 will be described with reference to the drawings. FIG. 8 is a diagram illustrating an example of task assignment and data arrangement of the multi-core processor 100a according to the second specific example of the embodiment of the present invention. In FIG. 8, the number of processors included in the specific example 2 is described as four, but the number of processors is not limited to this. The operation of specific example 2 will be described using the same task flow graph of FIG. 2 used in the description of specific example 1. It is assumed that the six tasks T1 to T6 in FIG. 2 are assigned in advance to the four processors 71 to 74 in the specific example 2 as shown in FIG. That is, task T1 and task T2 are assigned to CPU 71, task T3 and task T4 are assigned to CPU 72, task T5 is assigned to CPU 73, and task T6 is assigned to CPU 74. This assignment is also the same as in the first specific example. Since the assignment is determined in this way, the arrangement of the input / output data of each task is shown in FIG. It will be decided like 8. That is, the local memories 11 to 14 in FIG. 5 are replaced with the local memories 61 to 64. The data arrangement in the local memory is the same as in the first specific example. In the second specific example, data is shared between the processors using the local memory of each processor.

  Next, FIGS. 9 and 10 are flowcharts showing a flow of task processing (a state in which the task T1 to the task T6 are executed) according to the second specific example. There are two major differences between FIGS. 6 and 7 of the first specific example and FIGS. 9 and 10 of the second specific example. The first point is that the specific example 2 does not require the copy processing of the output data of the second task group in the second step of each task. Specifically, copy processing corresponding to S310, S322, S327, S342, S353, S354, and S356 of FIGS. 6 and 7 is not required in FIGS. The second point is that in specific example 2, the destination of the copy process for the third task group in the fourth step of each task is the local memory of the processor that executes the third task group. Specifically, the destination of the copy process corresponding to S312, S315, S324, S329, and S344 in FIGS. 6 and 7 is the local memory of the subsequent task.

  On the other hand, if the copy process for the third task group in the fourth step of each task is omitted, the output data of the second task group in the second step may be copied. realizable. That is, the second processor can reference the second local memory to the first processor after execution of the second task, and the first processor can reference the first local memory to the second processor after execution of the first task. Can also be realized.

<Other embodiments of the invention>
The parallel information processing method or apparatus according to another embodiment of the present invention can also be expressed as follows. That is, regarding the execution of an arbitrary first task of a program that can be expressed as a task flow graph, the first task that has an edge to the first task in the task flow graph and that executes the first task before executing the first task. Wait until the output data of the second task group executed by other than one processor becomes accessible (first step), and copy the output data of the second task group to the local memory of the first processor (second step). The first task is executed, the calculation result is stored in the local memory of the first processor (third step), and the third task that has an edge from the first task in the task flow graph and is executed by other than the first processor When there is a group, the output data of the first task is in a state that can be referred to by the third task group (fourth step), And wherein the door.

  In the second step, it is desirable to omit copying when it is clear that the output data of the second task group exists in the local memory of the first processor. Further, the copy source in the second step may be a shared memory, and the copy destination in the fourth step may be a shared memory. Alternatively, the copy source of the second step is the local memory of the processor that executes the second task group, and the copy process of the fourth step may be omitted by making the local memories of the processors mutually referable.

  In this way, according to the target parallel processing, the shared data is arranged in the local memory included in the multi-core processor, and the data is transferred between the processors, thereby reducing the number of accesses to the shared memory and further improving the overall parallel processing. It makes it possible to reduce processing time. That is, the embodiment according to the present invention is a parallel information processing apparatus in which the number of accesses to the shared memory is small and the overall processing time is small by a multi-core processor including the shared memory and the local memory, and software operating on the multi-core processor. A parallel information processing method is provided. Therefore, by utilizing the local memory provided in the processor, the number of accesses to the shared memory can be reduced, the memory access cost can be reduced, and the overall processing time can be shortened.

  The embodiment according to the present invention can be applied to parallel processing by various processors such as an embedded processor and a general-purpose computer processor.

  Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above. For example, in the above-described embodiment, the present invention has been described as a hardware configuration, but the present invention is not limited to this. The present invention can also realize arbitrary processing by causing a CPU (Central Processing Unit) to execute a computer program.

  In the above example, the program can be stored and supplied to a computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, DVD (Digital Versatile Disc), BD (Blu-ray (registered trademark) Disc), semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM ( Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

DESCRIPTION OF SYMBOLS 100 Multi-core processor 100a Multi-core processor 11 Local memory 12 Local memory 13 Local memory 14 Local memory 111 Allocation task reference data 121 Allocation task reference data 131 Allocation task reference data 141 Allocation task reference data 21 CPU
22 CPU
23 CPU
24 CPU
30 Shared memory 301 Multitask reference data 311 External data 312 Data A
313 Data B
314 Data C
315 Data D
316 Data E
317 Data F
511 External data 512 Data A
513 Data B
521 Data A
522 Data B
523 Data C
524 Data D
531 Data C
532 Data E
541 Data D
542 Data E
543 Data F
61 Local memory 62 Local memory 63 Local memory 64 Local memory 71 CPU
72 CPU
73 CPU
74 CPU
900 Multi-core processor 901 Shared data 911 Non-shared data 921 Non-shared data 931 Non-shared data 941 Non-shared data T1 task T2 task T3 task T4 task T5 task T6 task

Claims (10)

When the second task that is the preceding task in the first task assigned to the first processor is assigned to other than the first processor, the output data from the second task can be referred to by the first processor , Wait for the execution of the first task,
After the output data from the second task can be referred to by the first processor, the output data is acquired from the output data storage source and stored in the first local memory of the first processor;
With reference to the output data stored in the first local memory, the first processor executes the first task, stores the output data from the first task in the first local memory,
When a third task, which is a subsequent task in the first task, is assigned to a processor other than the first processor, the output data from the first task can be referred to from a processor other than the first processor. Task parallel processing method. If the preceding task in the fourth task executed after the first task in the first processor is the second task, the output data is not obtained from the storage source of the output data of the second task, 2. The task parallel processing method according to claim 1, wherein the first processor executes the fourth task with reference to output data of the second task stored in the first local memory before execution of the first task. . The storage source of the output data by the second task is a shared memory,
3. The task parallel processing method according to claim 1, wherein, after execution of the first task, the first processor reads output data from the first task from the first local memory and stores the data in the shared memory. The storage source of the output data by the second task is a second local memory included in a second processor that executes the second task,
The second processor can refer to the output data of the second task other than the second processor after the execution of the second task,
3. The task parallel processing method according to claim 1, wherein the first processor can refer to output data of the first task to a device other than the first processor after execution of the first task.   5. The task parallel processing according to claim 1, wherein the first task, the second task, and the third task are implemented as a program that can be expressed as a task flow graph. 6. Method. Comprising a plurality of processors having local memory;
A first processor of the plurality of processors is
Having a first local memory;
When the second task, which is the preceding task in the first task assigned to the first processor, is assigned to other than the first processor, the first task is used until the output data from the second task can be referred to. Wait for task execution,
After the output data by the second task can be referred to, the output data is obtained from the storage source of the output data and stored in the first local memory,
Referring to output data stored in the first local memory, executing the first task, storing output data by the first task in the first local memory,
When a third task, which is a subsequent task in the first task, is assigned to a processor other than the first processor, the output data from the first task can be referred to from a processor other than the first processor. Task parallel processing unit. The first processor is
When the preceding task in the fourth task executed after the first task in the first processor is the second task, the output data is not obtained from the storage source of the output data of the second task, The task parallel processing device according to claim 6, wherein the first processor executes the fourth task with reference to output data of the second task stored in the first local memory before execution of the first task. . The storage source of the output data by the second task is a shared memory,
The first processor is
8. The task parallel processing device according to claim 6, wherein, after execution of the first task, the first processor reads output data from the first task from the first local memory and stores the data in the shared memory. 9. The storage source of the output data by the second task is a second local memory included in a second processor that executes the second task,
The second processor can refer to the output data of the second task to other than the second processor after the execution of the second task,
8. The task parallel processing device according to claim 6, wherein the first processor can refer to output data of the first task to a device other than the first processor after the execution of the first task. When the second task that is the preceding task in the first task assigned to the first processor is assigned to other than the first processor, the output data from the second task can be referred to by the first processor A process of waiting for the execution of the first task;
After the output data from the second task can be referred to by the first processor, the output data is acquired from the storage source of the output data and stored in the first local memory of the first processor;
A process in which the first processor executes the first task with reference to the output data stored in the first local memory, and stores the output data from the first task in the first local memory;
When a third task, which is a subsequent task in the first task, is assigned to a processor other than the first processor, the output data from the first task can be referred to from a processor other than the first processor. Processing,
A task parallel processing program that causes a computer to execute.

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