JP2014164159A - Image data process circuit and method, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively reduce gradation unevenness and the like even when the gradation unevenness and/or flicker of a different amount occurs at positions of respective pixels in a display area.SOLUTION: An image data process circuit includes: a first storage section that stores image data for a plurality of pixels to be input; a correction data generation section that, as to each of the image data for the plurality of pixels, generates correction data for correcting an influence of a gradation voltage to be applied to the predetermined number of pixels in one line in a display panel on gradation unevenness and/or flicker on the basis of a position of the pixel in the display panel and the gradation voltage; a second storage section that stores correction data for the plurality of pixels to be generated by the correction data generation section; and a computation section that calculates image data for a plurality of corrected pixels on the basis of the image data for the plurality of pixels stored in the first storage section and the correction data for the plurality of pixels stored in the second storage section.

Description

  The present invention relates to an image data processing circuit and an image data processing method for processing image data supplied to a display unit including a display panel such as an LCD (Liquid Crystal Display) panel. Furthermore, the present invention relates to a display device using such an image data processing circuit, an electronic device such as a mobile phone, and the like.

  For example, in an active matrix liquid crystal display panel, a first transparent substrate on which a plurality of individual electrodes and a plurality of TFTs (Thin Film Transistors) connected thereto are formed, and one common electrode are formed. The arranged second transparent substrate is disposed opposite to each other, and liquid crystal is sealed between the first transparent substrate and the second transparent substrate.

  Here, if a DC voltage is continuously applied between the individual electrode and the common electrode, the characteristics of the liquid crystal deteriorate, so the polarity of the voltage applied between the individual electrode and the common electrode is inverted at a predetermined cycle. The In general, a frame inversion method in which the polarity of the applied voltage is inverted every frame, or a line inversion method in which the polarity of the applied voltage is inverted every line is used. In order to invert the polarity of the applied voltage, for example, the common potential applied to the common electrode is kept constant, and the polarity of the gradation voltage applied to the individual electrode is higher than the common potential. Is also reversed between low negative polarity.

  In such a liquid crystal display panel, since the common electrode has a parasitic resistance, gradation unevenness and flicker occur on the display screen. Even if the impedance at the connection point of the common potential line that supplies the common potential to the common electrode (also called the silver point because silver paste is used for connection) is low, the position of each pixel in the common electrode due to parasitic resistance And different common impedance lines have different impedances. When a current flows through this impedance, the potential of each pixel in the common electrode deviates from the common potential, resulting in gradation unevenness.

  In addition, a transistor (TFT) for driving the liquid crystal is an N-channel transistor, a drain connected to an individual electrode, a source connected to a source line to which a gradation voltage is supplied, and a gate line to which a scanning signal is supplied. And a gate connected to the gate. When the gradation voltage is positive, the source potential is high, so that the on-resistance of the transistor is increased. Accordingly, the amount of electric charge charged between the individual electrode and the common electrode varies depending on the parasitic resistance of the common electrode, the gradation voltage, and the on-resistance of the transistor. As a result, the voltage value applied between the individual electrode and the common electrode differs depending on whether the gradation voltage is positive or negative, and this is observed as flicker.

  Conventionally, the display frequency has been increased in order to make the flicker inconspicuous. However, when the display frequency is increased, power consumption increases, or high-frequency clock noise is mixed in the signal and the signal deteriorates. In addition, since an extra circuit and memory are required to increase the display frequency, the cost increases. Further, when the number of pixels in the liquid crystal display panel is increased, one horizontal synchronization period is shortened, so that there is a problem that flicker increases in measurement.

  As a related technique, Patent Document 1 discloses a liquid crystal display device for the purpose of displaying high-quality images with greatly reduced flicker. The liquid crystal display device includes a liquid crystal display panel having an effective display portion and an ineffective display portion formed outside the effective display portion, a driving circuit for driving the liquid crystal display panel, and effective display light in the ineffective display portion. A light blocking protection unit that blocks irradiation of the display unit, an intermediate luminance signal insertion circuit that inserts an intermediate luminance signal when the ineffective display unit is driven by the drive circuit, and a signal in which the intermediate luminance signal is inserted A photoelectric conversion element that converts the luminance of the display light of the driven non-effective display unit into an electrical signal, and a control circuit that controls the drive signal voltage of the drive circuit based on a detection signal from the photoelectric conversion element.

  According to this liquid crystal display device, the ineffective display portion of the liquid crystal display panel is driven by the signal with the intermediate luminance signal inserted, and the effective display portion is driven based on the detection voltage obtained by detecting the luminance at this time. By controlling the drive signal voltage to be generated, when a uniform flicker occurs in the entire display region, the flicker can be reduced.

Japanese Patent Laid-Open No. 2-156289 (2nd page, FIG. 1)

  However, if a different amount of flicker occurs at the position of each pixel in the display area, the flicker cannot be reduced effectively. Therefore, one of the objects of the present invention is to effectively reduce gradation unevenness and / or flicker even when different amounts of gradation unevenness and / or flicker occur at the position of each pixel in the display area. It is to be.

  In order to solve the above-described problems, an image data processing circuit according to one aspect of the present invention is an image data processing circuit that processes image data supplied to a display unit including a display panel, and includes a plurality of input pixels. A gradation voltage applied to a predetermined number of pixels in one line in the display panel for each of a plurality of image data for a first storage unit that stores image data for a plurality of pixels, and gradation unevenness and / or flicker Correction data generation unit for generating correction data for correcting the influence on the display panel based on the position of the pixel and the gradation voltage in the display panel, and correction data for a plurality of pixels generated by the correction data generation unit are stored Correction is performed based on the second storage unit, the image data for a plurality of pixels stored in the first storage unit, and the correction data for the plurality of pixels stored in the second storage unit. Comprising an arithmetic unit for calculating the image data of a plurality of pixels were.

  An image data processing method according to one aspect of the present invention is an image data processing method for processing image data supplied to a display unit including a display panel. The gradation voltage applied to a predetermined number of pixels in one line in the display panel causes gradation unevenness and / or flicker for each of the image data for a plurality of pixels stored in the storage unit 1 (a). Step (b) for generating correction data for correcting the influence exerted on the display panel based on the position of the pixel and the gradation voltage, and correction data for a plurality of pixels generated in Step (b) Based on step (c) storing in the storage unit, image data for a plurality of pixels stored in the first storage unit, and correction data for a plurality of pixels stored in the second storage unit Comprising a step (d) to calculate the corrected image data for a plurality of pixels were.

  According to one aspect of the present invention, even when a different amount of gradation unevenness and / or flicker occurs at each pixel position in the display area, the gradation unevenness and / or flicker is effectively reduced. be able to. At that time, since it is not necessary to increase the display frequency, an increase in power consumption and high-frequency clock noise can be suppressed. In addition, since a circuit and a memory for increasing the display frequency are not required, an increase in cost can be suppressed.

  In the image data processing circuit according to one aspect of the present invention, the correction data generation unit includes an impedance between one pixel and a common potential line in the common electrode of the display panel, and a gradation voltage applied to the pixel. The correction data may be generated by accumulating a value obtained by multiplying the product of and a coefficient for a predetermined number of pixels in one line. In that case, gradation unevenness and / or flicker caused by the parasitic resistance of the common electrode and the gradation voltage can be reduced.

  Furthermore, the correction data generation unit may change the coefficient according to the polarity of the gradation voltage for each frame or line. In that case, gradation unevenness and / or flicker caused by the influence of the parasitic resistance of the common electrode, the gradation voltage, and the on-resistance of the TFT can be reduced.

  An electronic apparatus according to one aspect of the present invention includes a display unit including a display panel and any one of the image data processing circuits. As a result, even when different amounts of gradation unevenness and / or flicker occur at the position of each pixel in the display area in the display panel, the gradation unevenness and / or flicker can be effectively reduced. .

1 is a block diagram of an electronic apparatus using an image data processing circuit according to an embodiment of the present invention. The front view which shows schematic shape of the display panel shown in FIG. 5 is a flowchart showing an image data processing method according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an electronic apparatus using an image data processing circuit according to an embodiment of the present invention. This electronic device is an electronic device such as a display device or a mobile phone. In FIG. 1, only the portion related to image display is shown.

  As shown in FIG. 1, the electronic device includes an image data processing circuit 10, a source line driving circuit 20, a gate line driving circuit 30, a common potential generation circuit 40, and a display panel 100. Here, the source line drive circuit 20 to the common potential generation circuit 40 may be built in a semiconductor integrated circuit device (display driver) and constitute a display unit together with the display panel 100. The image data processing circuit 10 may be incorporated in a semiconductor integrated circuit device (display controller) separate from the display driver, or may be incorporated in the display driver.

  The display panel 100 may be an active matrix liquid crystal display panel. In an active matrix liquid crystal display panel, a first transparent substrate on which a plurality of individual electrodes and a plurality of TFTs connected thereto are formed and a second transparent substrate on which one common electrode is formed are opposed to each other. The liquid crystal is sealed between the first transparent substrate and the second transparent substrate.

  In the display panel 100, for example, the same number of TFTs 111, 112, 113,..., 121, 122, 123,... Are arranged in a two-dimensional matrix corresponding to 720 × 132 pixels. . The drains of these TFTs are respectively connected to a plurality of individual electrodes of the display panel 100, and the sources of TFTs in a plurality of columns in the vertical direction in FIG. 1 are source lines S1, S2, S3,. , And the gates of the TFTs in a plurality of horizontal lines (rows) in FIG. 1 are connected to the gate lines G1, G2,.

  The TFT outputs a gradation voltage supplied to the source from the drain when a high level scanning signal is supplied to the gate and applies the gradation voltage to the corresponding individual electrode of the display panel 100. To do. In the display panel 100, capacitors formed between the plurality of individual electrodes and the common electrode are represented as capacitors C11, C12, C13,..., C21, C22, C23,.

  In the display panel 100, if a direct current voltage is continuously applied between the individual electrode and the common electrode, the characteristics of the liquid crystal deteriorate. Therefore, the polarity of the voltage applied between the individual electrode and the common electrode has a predetermined cycle. Inverted. In this embodiment, a frame inversion method in which the polarity of the applied voltage is inverted every frame or a line inversion method in which the polarity of the applied voltage is inverted every line is used.

  FIG. 2 is a front view showing a schematic shape of the display panel shown in FIG. The display panel 100 has a display area 101 where an image is displayed. Outside the display area 101, connection points (silver points) P1 to P4 of common potential lines for supplying a common potential to the common electrode formed on the second transparent substrate are provided.

  Since the common electrode has a parasitic resistance, even if the impedance at the connection point of the common potential line is low, due to the parasitic resistance, between the position of each pixel in the common electrode and the connection point of the common potential line, There will be different impedances. When a current flows through this impedance, the potential of each pixel in the common electrode deviates from the common potential, resulting in gradation unevenness.

  Further, the TFT for driving the liquid crystal is an N-channel transistor, and when the gradation voltage is positive, the source potential is increased, so that the on-resistance of the transistor is increased. Therefore, the amount of charge charged between the individual electrode and the common electrode varies depending on the parasitic resistance of the common electrode, the gradation voltage, and the on-resistance of the TFT. As a result, the voltage value applied between the individual electrode and the common electrode differs depending on whether the gradation voltage is positive or negative, and this is observed as flicker.

  In the present embodiment, the image data processing circuit 10 shown in FIG. 1 reduces such gradation unevenness and flicker. The image data processing circuit 10 includes an image data storage unit 11, a correction data generation unit 12, a correction data storage unit 13, a calculation unit 14, and a display timing generation unit 15, and includes a display panel 100. Process the supplied image data.

  The image data storage unit 11 is configured by a buffer memory or the like for a plurality of pixels (may be for one line), and stores input image data for a plurality of pixels. The correction data generation unit 12 affects the gradation unevenness and / or flickers of gradation voltages applied to a predetermined number of pixels in one line of the display panel 100 for each of the input image data for a plurality of pixels. Is generated based on the pixel position and the gradation voltage in the display panel 100.

  The correction data storage unit 13 is configured by a buffer memory or the like for a plurality of pixels (or even one line), and stores correction data for a plurality of pixels generated by the correction data generation unit 12. The calculation unit 14 corrects a plurality of pixels corrected based on the image data for a plurality of pixels stored in the image data storage unit 11 and the correction data for a plurality of pixels stored in the correction data storage unit 13. Image data is calculated. The corrected image data is supplied to the source line driving circuit 20.

  The display timing generation unit 15 receives a horizontal synchronization signal, a vertical synchronization signal, and the like, and generates various timing signals. The various timing signals include, for example, a scanning timing signal indicating the writing line switching timing in the display panel 100, a polarity inversion signal indicating inversion / non-inversion of the polarity of the gradation voltage, and the like.

Here, the correction method in the image data processing circuit 10 will be described in detail.
In the following, as shown in FIG. 2, in the XY plane including the common electrode, four connection points P1 (X1, Y1), P2 (X2, Y2), P3 (X3, Y3), P4 ( X4, Y4) are provided. An arbitrary pixel in the display area 101 is represented by P (X, Y). The origin for measuring the X and Y coordinates at each point may be located either inside or outside the display surface of the display panel 100 as long as it is a measurable position. In the present embodiment, the origin is set at the center of the display surface. Also, the coordinates of each connection point may be set at an arbitrary position within the connection point, or may be set at an arbitrary position outside the connection point as long as coordinate conversion is possible.

Assuming that the common electrode has a specific resistance ρ, an impedance Z1 between the pixel P and the connection point P1 of the common potential line is expressed by the following equation.
Z1 = ρL1 / (W1 · t1) = kL1
Here, L1 is a distance between the pixel P and the connection point P1, W1 is an effective width of a region where current flows between the pixel P and the connection point P1, and t1 is a common electrode. Is the thickness. Further, ρ / (W1 · t1) is represented by a constant k, assuming that the effective width W1 of the region where current flows and the thickness t1 of the common electrode are substantially constant.

Considering other connection points P2 to P4 of the common potential line, an impedance Z between the pixel P and the connection points P1 to P4 of the common potential line is expressed by the following equation.
Z = k / (L1 ⁻¹ + L2 ⁻¹ + L3 ⁻¹ + L4 ⁻¹ )

Further, when the impedance Z between the pixel P and the connection points P1 to P4 of the common potential line is expressed using XY coordinates, the following expression is established.
^{Z (X, Y) = k} / {[(X1-X) 2 + (Y1-Y) 2] -1/2 + [(X2-X) 2 + (Y2-Y) 2] -1/2 + ^{[(X3-X) 2 +} (Y3-Y) 2] -1/2 + [(X4-X) 2 + (Y4-Y) 2] -1/2} ··· (1)

  When the impedance Z (X, Y) in each pixel is obtained according to the equation (1) and replaced with luminance, and displayed as an image, a pattern close to the gradation unevenness pattern at the same gradation on the entire screen is displayed. Thus, it can be seen that the impedance Z (X, Y) in each pixel is a major factor in uneven gradation.

  However, in consideration of the supply of the gradation signal to the display panel 100 for each line and the fact that the luminance affects the gradation voltage until the TFT is turned off, a strict current is supplied to the entire display region. It is considered that the calculation of gradation unevenness by performing the calculation has little meaning. On the other hand, when half of the screen is set to a different gradation, gradation unevenness and flicker are affected in the other half of the screen. It can be seen that the gradation signal in the pixel has an effect.

  In view of the above, the gradation voltage V (X, Y) of the pixel P is corrected using the product of the impedance and the gradation voltage in a predetermined number of pixels located in the vicinity of the pixel P in one line. Is estimated to be effective. Therefore, the correction data generation unit 12 sets a value obtained by multiplying the product of the impedance between one pixel and the common potential line in the common electrode of the display panel 100 and the gradation voltage applied to the pixel by a coefficient of 1 Correction data may be generated by accumulating a predetermined number of pixels in the line. Thereby, gradation unevenness and / or flicker caused by the parasitic resistance of the common electrode and the gradation voltage can be reduced.

For this purpose, correction data C (X, Y) represented by the following equation (2) is generated.
C (X, Y) = A · Z (X, Y) · V (X, Y) + B · Z (X-1, Y) · V (X-1, Y) + B 2 · Z (X-2, Y) · V (X-2 , Y) + ··· + B · Z (X + 1, Y) · V (X + 1, Y) + B 2 · Z (X + 2, Y) · V (X + 2, Y) + ···
... (2)

  Here, the coefficient A represents the degree of influence of the product of the impedance and the gradation voltage in a certain pixel P on gradation unevenness and / or flicker in the pixel P, and the coefficient B represents the impedance in the certain pixel P. This represents the degree of influence that the product of the gradation voltage has on gradation unevenness and / or flicker in adjacent pixels.

  Since the optimum values of the coefficients A and B vary depending on the type and size of the display panel 100, they are obtained through experiments. In general, the ranges of 0.5% <A ≦ 1% and 0% <B ≦ 0.5% are preferable. For example, the coefficient A may be 0.7% to 0.8%, and the coefficient B may be 0.2% to 0.3%.

  Further, the number (predetermined number) of pixels used for correction is one or more and not more than the number of pixels for one line. For example, assuming that the predetermined number is “5”, the pixel P and the adjacent pixels on the left and right sides of the pixel P may be considered. However, when there is no adjacent pixel or adjacent pixel in the line, the term of the pixel is set to zero.

  Further, in order to correct that the on-resistance of the TFT is different between when the gradation voltage is positive and when it is negative, the values of the coefficients A and B are changed according to the polarity of the gradation voltage. Also good. When the gradation voltage is positive, the on-resistance of the TFT is increased as compared to when the gradation voltage is negative, so that the amount of charge charged between the individual electrode and the common electrode is reduced. Therefore, it is desirable that the values of the coefficients A and B when the gradation voltage is positive are larger than the values of the coefficients A and B when the gradation voltage is negative.

  In the case of the frame inversion method in which the polarity of the applied voltage is inverted every frame, the display timing generation unit 15 generates a polarity inversion signal that inverts the polarity of the gradation voltage for each frame. On the other hand, in the case of the line inversion method in which the polarity of the applied voltage is inverted for each line, the display timing generation unit 15 generates a polarity inversion signal for inverting the polarity of the gradation voltage for each line.

  The correction data generation unit 12 generates correction data by changing the values of the coefficients A and B according to the polarity of the gradation voltage for each frame or for each line according to the polarity inversion signal generated by the display timing generation unit 15. To do. As a result, gradation unevenness and / or flicker caused by the influence of the parasitic resistance of the common electrode, the gradation voltage, and the on-resistance of the TFT can be reduced.

  The calculation unit 14 corrects a plurality of pixels corrected based on the image data for a plurality of pixels stored in the image data storage unit 11 and the correction data for a plurality of pixels stored in the correction data storage unit 13. Image data is calculated. Further, the calculation unit 14 processes the image data so that the polarity of the gradation voltage is inverted for each frame or each line according to the polarity inversion signal generated by the display timing generation unit 15. For example, when the common potential applied to the common electrode is constant at 7V, the gradation voltage applied to the individual electrode is between 12V of positive polarity and 2V of negative polarity when the gradation is 100%. Inverted.

  The source line driving circuit 20 includes a RAM 201, a plurality of DACs 211, 212, 213,... And a plurality of voltage buffers 221, 222, 223,. The RAM 201 temporarily stores the image data input from the calculation unit 14. The DACs 211, 212, 213,... Respectively convert red (R), green (G), and blue (B) image data sequentially read from the RAM 201 into a plurality of gradation voltages in accordance with the scanning timing signal.

  The gradation voltages output from the DACs 211, 212, 213,... Are input to the voltage buffers 221, 222, 223,. The voltage buffers 221, 222, 223,... Buffer those gradation voltages and supply them to the source lines S1, S2, S3,.

  The gradation voltage supplied to the source line S1 is applied to the sources of the TFTs 111, 121,. The gradation voltage supplied to the source line S2 is applied to the sources of the TFTs 112, 122,. The gradation voltage supplied to the source line S3 is applied to the sources of the TFTs 113, 123,.

  The gate line driving circuit 30 sequentially activates a plurality of scanning signals respectively supplied to the gate lines G1, G2,... To a high level (for example, 15 V) according to the scanning timing signal. As a result, among the plurality of TFTs connected to each source line, the TFT whose gate line is at the high level is turned on, and the gradation voltage is applied to the individual electrode connected to the drain of the TFT. . The common potential generation circuit 40 generates a common potential COM and applies the common potential COM to the common electrode of the display panel 100. In this way, an image is displayed on the display panel 100.

  Next, an image data processing method performed using the image data processing circuit shown in FIG. 1 will be described with reference to FIG. FIG. 3 is a flowchart showing an image data processing method according to an embodiment of the present invention. This image data processing method is an image data processing method for processing image data supplied to a display unit including the display panel 100.

  In step S <b> 1 of FIG. 3, the image data processing circuit 10 stores input image data for a plurality of pixels in the image data storage unit 11. Next, in step S2, the correction data generation unit 12 determines that the gradation voltage applied to a predetermined number of pixels in one line in the display panel 100 for each of the input image data for a plurality of pixels is uneven gradation. Then, correction data for correcting the influence on the flicker based on the pixel position and the gradation voltage in the display panel 100 is generated.

  In step S <b> 3, the correction data generation unit 12 stores correction data for a plurality of pixels generated in step S <b> 2 in the correction data storage unit 13. In step S4, the calculation unit 14 performs correction based on the image data for a plurality of pixels stored in the image data storage unit 11 and the correction data for the plurality of pixels stored in the correction data storage unit 13. The image data for the plurality of pixels is calculated.

  According to the present embodiment, even when different amounts of gradation unevenness and / or flicker occur at each pixel position in the display area, the gradation unevenness and / or flicker can be effectively reduced. . At that time, since it is not necessary to increase the display frequency, an increase in power consumption and high-frequency clock noise can be suppressed. In addition, since a circuit and a memory for increasing the display frequency are not required, an increase in cost can be suppressed.

  The present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those having ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 10 ... Image data processing circuit, 11 ... Image data storage part, 12 ... Correction data generation part, 13 ... Correction data storage part, 14 ... Operation part, 15 ... Display timing generation part, 20 ... Source line drive circuit, 201 ... RAM , 211 ... DAC, 221 ... voltage buffer, 30 ... gate line drive circuit, 40 ... common potential generation circuit, 100 ... display panel, 101 ... display area, 111 to 123 ... TFT, S1, S2, S3 ... source line, G1 , G2: Gate lines, P1 to P4: Connection points of common potential lines

Claims (5)

An image data processing circuit for processing image data supplied to a display unit including a display panel,
A first storage for storing input image data for a plurality of pixels;
For each of the image data for the plurality of pixels, the influence of the gradation voltage applied to a predetermined number of pixels in one line on the display panel on gradation unevenness and / or flicker is determined by the position of the pixel on the display panel. And a correction data generation unit for generating correction data for correction based on the gradation voltage;
A second storage unit for storing correction data for a plurality of pixels generated by the correction data generation unit;
Based on image data for a plurality of pixels stored in the first storage unit and correction data for a plurality of pixels stored in the second storage unit, corrected image data for a plurality of pixels is obtained. A computing unit to calculate,
An image data processing circuit comprising:   A value obtained by multiplying the product of the impedance between one pixel and a common potential line in the common electrode of the display panel and the grayscale voltage applied to the pixel by the correction data generation unit in one line The image data processing circuit according to claim 1, wherein the correction data is generated by accumulating a predetermined number of pixels.   The image data processing circuit according to claim 2, wherein the correction data generation unit changes the coefficient according to the polarity of the gradation voltage for each frame or for each line. A display unit including a display panel;
The image data processing circuit according to any one of claims 1 to 3,
An electronic device comprising: An image data processing method for processing image data supplied to a display unit including a display panel,
Storing the input image data for a plurality of pixels in the first storage unit (a);
For each of the image data for the plurality of pixels, the influence of the gradation voltage applied to a predetermined number of pixels in one line on the display panel on gradation unevenness and / or flicker is determined by the position of the pixel on the display panel. And (b) generating correction data for correction based on the gradation voltage;
A step (c) of storing correction data for a plurality of pixels generated in step (b) in the second storage unit;
Based on image data for a plurality of pixels stored in the first storage unit and correction data for a plurality of pixels stored in the second storage unit, corrected image data for a plurality of pixels is obtained. Calculating step (d);
An image data processing method comprising:

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