JP2014161148A - Control system for multilevel power conversion circuit - Google Patents

Control system for multilevel power conversion circuit Download PDF

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JP2014161148A
JP2014161148A JP2013030100A JP2013030100A JP2014161148A JP 2014161148 A JP2014161148 A JP 2014161148A JP 2013030100 A JP2013030100 A JP 2013030100A JP 2013030100 A JP2013030100 A JP 2013030100A JP 2014161148 A JP2014161148 A JP 2014161148A
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semiconductor switch
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JP6111726B2 (en
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Akitake Takizawa
聡毅 滝沢
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Fuji Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To solve the problem that a conventional method of adding components externally in order to equalize voltage resistance when turning off serially connected elements each including a function for simultaneously maintaining ON and OFF operations in a multilevel conversion circuit may increase device cost.SOLUTION: For controlling a multilevel conversion circuit, a cut-off control method is used with which one element is first turned off in a serial connection circuit where three or more switch elements are connected in series, OFF signals are given to the remaining switch elements after the lapse of a predetermined time, next, the first turned-off element is turned on for a short time and after voltage states of a plurality of elements are regulated, the circuit is shifted to such a mode that a high voltage is applied to the switch circuit. As a result, e.g., in a five-level conversion circuit, voltages to be applied to elements in the case where a voltage is shifted like from a zero voltage through Ed (unit voltage) and 2Ed to 3Ed are collectively cut off, such that the voltage can be suppressed low in comparison with the case where a voltage to any element is first cut off.

Description

本発明は、交流電動機駆動などを目的とした直流電源から5レベル以上の電位を組合せて高調波成分の少ない交流電圧を生成する直流−交流変換又は交流電源から直流電源を生成する交流−直流変換を行うマルチレベル電力変換回路の制御方式に関する。   The present invention relates to a DC-AC conversion that generates an AC voltage with less harmonic components by combining a potential of five or more levels from a DC power source for the purpose of driving an AC motor, or an AC-DC conversion that generates a DC power source from an AC power source. The present invention relates to a control method of a multilevel power conversion circuit that performs the above.

図4に直流を交流に変換する電力変換回路である,半導体スイッチ素子としてIGBTを使用した5レベルインバータの回路例を示す。DP1,DP2が直列に接続された直流電源(電圧は2Ed×2)で,正側電位をP,負側電位をN,中点電位をMとしている。一般に本直流電源を交流電源システムより構成する場合は,図示していない整流器と大容量のコンデンサを直列接続などによって構成することが可能である。   FIG. 4 shows a circuit example of a five-level inverter that uses an IGBT as a semiconductor switch element, which is a power conversion circuit that converts direct current into alternating current. In a DC power source (voltage is 2Ed × 2) in which DP1 and DP2 are connected in series, the positive potential is P, the negative potential is N, and the midpoint potential is M. In general, when this DC power supply is constituted by an AC power supply system, a rectifier (not shown) and a large-capacity capacitor can be constituted by series connection or the like.

S1a〜S1c、S2、S3、S4a〜S4cが直流電源の正側電位Pと負側電位Nとの間に8個直列接続されているダイオードを逆並列接続したIGBTからなる第1の半導体スイッチ素子直列回路である。S5,S6は,IGBTS1cとS2との接続点と,IGBTS3とS4aとの接続点との間に2個直列接続されたダイオードを逆並列接続したIGBTからなる第2の半導体スイッチ素子直列回路である。S7,S8は直流電源の中点電位であるM電位と,IGBTS5とS6との接続点との間に接続された双方向性のスイッチ素子を構成するIGBTで,図4に示すように逆耐圧を有するIGBTを逆並列接続するか,もしくは図8(a),図8(b)に示すように逆耐圧を有しないIGBTとダイオードとを組み合わせで構成できる。またC1がフライングキャパシタと呼ばれるコンデンサで,第2の半導体スイッチ素子直列回路(IGBTS5とS6との直列回路)と並列に接続される。コンデンサC1の両端の平均的な電圧はEdに制御され,その充放電現象を利用して一方の直流電源の中間電位の出力を実現する。ここで、直流電源のP電位又はN電位と,フライングキャパシタの正側電位又は負側電位間に接続されているIGBTS1a〜S1c又はS4a〜S4cが3直列となっている理由は,この間に印加される電圧の最大値に応じて,全てのIGBTを同一電圧定格とするためである。   S1a to S1c, S2, S3, and S4a to S4c are first semiconductor switching elements comprising IGBTs in which eight diodes connected in series between the positive side potential P and the negative side potential N of the DC power supply are connected in reverse parallel It is a series circuit. S5 and S6 are second semiconductor switch element series circuits composed of IGBTs in which two diodes connected in series are connected in reverse parallel between the connection point of IGBTs 1c and S2 and the connection point of IGBTs 3 and S4a. . S7 and S8 are IGBTs constituting a bidirectional switch element connected between the M potential, which is the midpoint potential of the DC power supply, and the connection point between the IGBTTS5 and S6. As shown in FIG. 8 can be connected in reverse parallel or as shown in FIGS. 8 (a) and 8 (b), an IGBT having no reverse breakdown voltage and a diode can be combined. C1 is a capacitor called a flying capacitor and is connected in parallel with the second semiconductor switch element series circuit (series circuit of IGBTs 5 and S6). The average voltage at both ends of the capacitor C1 is controlled to Ed, and an intermediate potential output of one DC power supply is realized by utilizing the charge / discharge phenomenon. Here, the reason why the IGBTs 1a to S1c or S4a to S4c connected between the P potential or N potential of the DC power source and the positive side potential or negative side potential of the flying capacitor are in series is applied during this period. This is because all IGBTs have the same voltage rating according to the maximum voltage value.

これらの回路群AUを1相分として,3台(AU、AV、AW)を直流電源と並列接続することにより3相のインバータが構成できる。ここで、AVとAWについては直流電源の中点電位Mとの接続を省略している。
ACMが本システムの負荷例である交流電動機である。本回路構成とすることで,変換器の出力端子ACの電位は,P電位,N電位,M電位,及びIGBTのオンオフとコンデンサC1の電圧Edを利用してP−EdとN+Edの中間電位を出力することが可能となるため,5レベル出力のインバータとなる。図9に出力電圧(Vout)波形例を示す。
本方式は2レベルタイプのインバータに対して,低次の高調波成分が少ないことや,スイッチ素子(IGBT)のスイッチング損失が低減することから,高効率システムの構築が可能となる。
A three-phase inverter can be constructed by connecting these circuit groups AU for one phase and connecting three units (AU, AV, AW) in parallel with a DC power source. Here, for AV and AW, connection with the midpoint potential M of the DC power supply is omitted.
ACM is an AC motor that is an example of the load of this system. With this circuit configuration, the potential of the output terminal AC of the converter is set to the P potential, N potential, M potential, and the intermediate potential between P-Ed and N + Ed using the on / off of the IGBT and the voltage Ed of the capacitor C1. Since it becomes possible to output, it becomes a 5-level output inverter. FIG. 9 shows an example of the output voltage (Vout) waveform.
Since this method has fewer low-order harmonic components and reduces switching loss of the switch element (IGBT) compared to the two-level type inverter, a highly efficient system can be constructed.

また図5,図6に,図4に示す5レベルの変換回路などのマルチレベル変換回路の基本形となる回路を示す。図5は図4の回路におけるIGBTS2とS3を除き,IGBTS1a〜S1cを一つのスイッチ素子S1に、S4a〜S4cを一つのスイッチ素子S4とした構成である。また図6は,図4の回路におけるIGBTS5とIGBTS8の機能を双方向性のスイッチ素子ACS1とし,またIGBTS6とIGBTS7の機能を双方向性のスイッチ素子ACS2とした構成である。図5の端子部TA1,TA2,又は図6の端子部TA3,TA4に,IGBTなどのスイッチ素子などからなる変換回路を追加することで5レベル以上のマルチレベル化が可能となる(図4はIGBTS2とS3を接続した例である)。   5 and 6 show a basic circuit of a multilevel conversion circuit such as the five-level conversion circuit shown in FIG. FIG. 5 shows a configuration in which the IGBTs 1a to S1c are one switch element S1 and S4a to S4c are one switch element S4 except for the IGBTs 2 and S3 in the circuit of FIG. FIG. 6 shows a configuration in which the functions of the IGBTs 5 and 8 in the circuit of FIG. 4 are bidirectional switch elements ACS1, and the functions of the IGBTs 6 and IGBTTS7 are bidirectional switch elements ACS2. By adding a conversion circuit composed of a switching element such as an IGBT to the terminal portions TA1, TA2 in FIG. 5 or the terminal portions TA3, TA4 in FIG. This is an example in which IGBTTS2 and S3 are connected).

図7にはその応用回路として,スイッチ素子としてIGBTを使用し、全てのIGBTの電圧定格を全て等しくした場合の7レベルインバータの回路例を示す。図7の回路は,直流電源DP3とDP4を直列接続して構成した直流電源の電圧(3Ed×2)に対してIGBTS3のコレクタとIGBTS4のエミッタとの間に1単位の電圧(Ed)に充電されるコンデンサC2を,またIGBTS2のコレクタと,IGBTS5のエミッタとの間に2単位の電圧(2Ed)に充電されるコンデンサC3を,さらにIGBTS10のコレクタとIGBTS11のエミッタとの間に1単位の電圧(Ed)に充電されるコンデンサC4を接続することにより7レベルの電位の交流出力が可能となる。
図7に示すように全てのIGBTの電圧を同一電圧定格とした場合,IGBTS1はIGBTS1a〜S1dの4個の直列接続回路に、IGBTS6はIGBTS6a〜S6dの4個の直列接続回路にする必要がある。
FIG. 7 shows a circuit example of a 7-level inverter when an IGBT is used as a switching element as an application circuit and the voltage ratings of all the IGBTs are all equal. The circuit of FIG. 7 charges a unit voltage (Ed) between the collector of the IGBT 3 and the emitter of the IGBT TS4 with respect to the voltage (3Ed × 2) of the DC power source configured by connecting the DC power sources DP3 and DP4 in series. Capacitor C2 to be charged, a capacitor C3 charged to a voltage of 2 units (2Ed) between the collector of IGBTTS2 and the emitter of IGBTTS5, and a voltage of 1 unit between the collector of IGBTTS10 and the emitter of IGBTTS11. By connecting a capacitor C4 to be charged to (Ed), an AC output with a 7-level potential is possible.
As shown in FIG. 7, when all the IGBTs have the same voltage rating, the IGBTTS1 needs to be four series connection circuits of IGBTTS1a to S1d, and the IGBTTS6 needs to be four series connection circuits of IGBTTS6a to S6d. .

図10(a)〜(e)に図2に示す5レベルインバータ回路の1相分の動作遷移図例を示す。直流電源の中間点の電位を零とした場合の交流出力ACの電位の遷移を説明する。図10(a)はIGBTS1a〜S1c及びS2がオン状態で,交流出力ACに2Edの電位が出力される。図10(b)は,IGBTS1a〜S1cがターンオフし,IGBTS8,S6,S2がオンしている状態で,交流出力ACにはEdが出力される。この時、IGBTS1aのコレクタとS1cのエミッタとの間にはEdの電圧が印加される。図10(c)は,IGBTS2がターンオフし,IGBTS8,S6,S3がオンしている状態で,交流出力ACには零電位(M電位)が出力される。この時、IGBTS1aのコレクタとS1cのエミッタとの間にはEdの電圧が印加される。図10(d)は,IGBTS6がターンオフし,IGBTS8,S5,S3がオンしている状態で,交流出力ACには−Edが出力される。この時IGBTS1aのコレクタとS1cのエミッタとの間には2Edの電圧が印加される。図10(e)は,IGBTS8がターンオフし,IGBTS4a〜S4c,S3がオンしている状態で,交流出力ACには−2Edが出力される。この時IGBTS1aのコレクタとS1cのエミッタとの間には3Edの電圧が印加される。
以上のように,IGBTS1a〜S1cには図10(b)以降,静的にEdから3Edまで電圧がステップ的に印加されていく。
以上の5レベルインバータの回路例,マルチレベル回路の基本回路、動作などについては,特許文献1、特許文献2に示されている。
10A to 10E show examples of operation transition diagrams for one phase of the five-level inverter circuit shown in FIG. The transition of the potential of the AC output AC when the potential at the midpoint of the DC power supply is zero will be described. In FIG. 10A, the IGBTs 1a to S1c and S2 are in the ON state, and a potential of 2Ed is output to the AC output AC. In FIG. 10B, Ed is output to the AC output AC in a state where the IGBTs 1a to S1c are turned off and the IGBTs 8, S6, and S2 are turned on. At this time, the voltage of Ed is applied between the collector of the IGBT TS1a and the emitter of S1c. FIG. 10C shows a state where the IGBT TS2 is turned off and the IGBTs 8, S6, and S3 are turned on, and a zero potential (M potential) is output to the AC output AC. At this time, the voltage of Ed is applied between the collector of the IGBT TS1a and the emitter of S1c. In FIG. 10D, -Ed is output to the AC output AC in a state in which the IGBTTS 6 is turned off and the IGBTs 8, S5, and S3 are turned on. At this time, a voltage of 2 Ed is applied between the collector of the IGBTTS 1a and the emitter of the S1c. FIG. 10E shows that −2Ed is output to the AC output AC in a state where the IGBTTS 8 is turned off and the IGBTs 4a to S4c and S3 are turned on. At this time, a voltage of 3Ed is applied between the collector of the IGBT TS1a and the emitter of the S1c.
As described above, the voltages are applied to the IGBTTS 1a to S1c in a stepwise manner from Ed to 3Ed after FIG. 10B.
The circuit example of the above five-level inverter, the basic circuit of the multi-level circuit, the operation, and the like are shown in Patent Document 1 and Patent Document 2.

特表2009−525717号公報Special table 2009-525717 gazette 特開2010−182974号公報JP 2010-182974 A 特許第3767740号号公報Japanese Patent No. 3767740

図10に示すように,通常の運転状態において,S1a〜S1cがターンオフする場合,S1aのコレクタとS1cのエミッタ間に印加される電圧はEdとなる。実際にはスイッチング時の過渡時において,配線インダクタンスなどによって発生するサージ電圧が重畳されるが,本提案内容に対しては本質的でないのでここでは無視する。
その後,他のスイッチ素子(IGBT)のスイッチング状態が進み,IGBTS3,S4a〜S4cがオン状態で,IGBTS1a〜S1c,S2がオフの状態となった場合(交流出力にはN電位が出力されている状態)は,IGBTS1aのコレクタとS2のエミッタ間には4Edの電圧が印加される。すなわち,この状態になった場合はIGBTS1aのコレクタとS1cのエミッタ間には3Edの電圧が印加される。そのためIGBTを全て同一電圧定格とした場合,理想的にはS1として3個の直列数が必要となる。
As shown in FIG. 10, in the normal operation state, when S1a to S1c are turned off, the voltage applied between the collector of S1a and the emitter of S1c is Ed. In practice, surge voltage generated by wiring inductance, etc. is superimposed during switching transients, but it is not essential for this proposal and is ignored here.
Thereafter, the switching state of the other switch element (IGBT) advances, and the IGBTs 3, S4a to S4c are in the on state and the IGBTs 1a to S1c, S2 are in the off state (N potential is output to the AC output) In the state), a voltage of 4Ed is applied between the collector of the IGBT TS1a and the emitter of S2. That is, in this state, a voltage of 3Ed is applied between the collector of the IGBT TS1a and the emitter of S1c. Therefore, when all the IGBTs have the same voltage rating, ideally three serial numbers are required as S1.

一般にIGBTの高耐圧化には限界があり,また高耐圧のIGBTほどコストが高いという課題がある。また,IGBTを直列接続させた場合でターンオフさせる場合,各IGBTの特性ばらつきやゲート駆動回路の遅延時間ばらつきなどによって,全く同時にスイッチングさせることは不可能である。そのため従来,極力各IGBTに印加される電圧を均等化するために,素子特性の選別や,IGBTと並列に抵抗とコンデンサの直列回路を接続することや,ゲート駆動配線間にトランスを接続すること,などが行われている。しかしこれらはすべてコストアップ要因であり,課題となっていた。   In general, there is a limit to increasing the breakdown voltage of an IGBT, and there is a problem that the higher the breakdown voltage, the higher the cost. Further, when the IGBTs are connected in series and are turned off, it is impossible to perform switching at the same time due to variations in characteristics of the IGBTs and variations in delay time of the gate drive circuit. Therefore, conventionally, in order to equalize the voltage applied to each IGBT as much as possible, selection of element characteristics, connection of a series circuit of a resistor and a capacitor in parallel with the IGBT, and connection of a transformer between gate drive wirings , Etc. are done. However, these are all cost increasing factors and have been problems.

ところで、直列素子を同時にターンオフさせた際の最悪ケースは,ある特定IGBTのみ(仮にS1aとする)に電圧Edが印加され,その他のIGBT(S1b,S1c)には全く電圧が印加されない状態となる。本回路方式ではこの状態からその後,静的に3Edまで電圧が印加されるが,その際,2Ed(3Ed−Edで得られる)の電圧が3素子に均一に印加される(電流遮断を伴わない静的な電圧印加であるため,電圧分担は均一化する)ため,最終的に各IGBTに印加される電圧は,
S1a:Ed+2Ed/3=5Ed/3
S1b,S1c:2Ed/3
となる。
すなわち本ケースを想定すると,S1部に必要となるIGBTの電圧定格は,5Ed/3に対して余裕のあるものとする必要がある。
By the way, in the worst case when the series elements are turned off at the same time, the voltage Ed is applied only to a specific IGBT (assumed to be S1a), and no voltage is applied to the other IGBTs (S1b, S1c). . In this circuit system, a voltage is applied statically from this state up to 3Ed, and at that time, a voltage of 2Ed (obtained by 3Ed-Ed) is uniformly applied to the three elements (without current interruption). (Because it is a static voltage application, the voltage sharing is made uniform), so the voltage finally applied to each IGBT is
S1a: Ed + 2Ed / 3 = 5Ed / 3
S1b, S1c: 2Ed / 3
It becomes.
That is, assuming this case, it is necessary that the voltage rating of the IGBT required for the S1 part has a margin with respect to 5Ed / 3.

また、図7の7レベル方式では,同様に,
S1a: Ed+3Ed/4=7Ed/4
S1b〜S1d: 3Ed/4
となり,S1部に必要となるIGBTの電圧定格は,7Ed/4に対して余裕のあるものとする必要がある。
従来の直列接続IGBTの電圧均等化対策例は,特許文献3の図5,図9などに記載されている。
従って、本発明の課題は、マルチレベル電力変換回路において、同時にオン状態及びオフ状態を維持する機能を備えた少なくとも3個直列接続された半導体スイッチ素子群のオフ時に各半導体スイッチ素子に印加される電圧を主回路に部品を追加することなく極力均等化の方向に低減できる制御方式を提供することである。
Similarly, in the 7-level method of FIG.
S1a: Ed + 3Ed / 4 = 7Ed / 4
S1b to S1d: 3Ed / 4
Therefore, the voltage rating of the IGBT required for the S1 portion needs to have a margin with respect to 7Ed / 4.
Examples of voltage equalization countermeasures for conventional series-connected IGBTs are described in FIGS.
Accordingly, an object of the present invention is applied to each semiconductor switching element in the multilevel power conversion circuit when at least three series-connected semiconductor switching elements having the function of simultaneously maintaining the on state and the off state are turned off. To provide a control system capable of reducing the voltage in the direction of equalization as much as possible without adding parts to the main circuit.

上述の課題を解決するために、第1の発明においては、直流から交流,又は交流から直流に変換する電力変換回路であって,1相分の回路として,直流電源回路の正側端子と負側端子間に接続されたダイオードを逆並列接続した半導体スイッチ素子を少なくとも8個直列に接続した第1の半導体スイッチ素子直列回路と、前記直流電源回路の中間電位点に一方の端子が接続された双方向性にスイッチングが可能な双方向性スイッチ素子と、前記第1の半導体スイッチ素子直列回路の半導体スイッチ素子同士の接続点の中の特定の二つの接続点間に接続されるダイオードが逆並列接続された半導体スイッチ素子を直列接続した第2の半導体スイッチ素子直列回路と、前記第2の半導体スイッチ素子直列回路と並列接続されたコンデンサと、を備え、前記第2の半導体スイッチ素子直列回路の中間接続点に前記双方向性スイッチ素子の他方の端子を接続したマルチレベル電力変換回路であって、前記直流電源回路の正側端子又は負側端子に接続された同時にオン状態及びオフ状態を維持する機能を備えた少なくとも3個直列接続された半導体スイッチ素子群のターンオフ動作において,前記少なくとも3個直列接続された直列スイッチ素子群の内,最初にいずれか1個の半導体スイッチ素子のみをターンオフさせ,残りの半導体スイッチ素子は前記最初にターンオフした半導体スイッチ素子のターンオフ完了時点より時間を遅らせてターンオフさせる。   In order to solve the above-mentioned problem, in the first invention, a power conversion circuit for converting from direct current to alternating current or from alternating current to direct current, which is a circuit for one phase, the positive terminal of the direct current power supply circuit and the negative terminal A first semiconductor switch element series circuit in which at least eight semiconductor switch elements in which diodes connected between the side terminals are connected in reverse parallel are connected in series, and one terminal connected to an intermediate potential point of the DC power supply circuit; A bidirectional switching element capable of bidirectional switching and a diode connected between two specific connection points among the connection points of the semiconductor switch elements of the first semiconductor switch element series circuit are anti-parallel. A second semiconductor switch element series circuit in which connected semiconductor switch elements are connected in series; and a capacitor connected in parallel with the second semiconductor switch element series circuit. A multi-level power conversion circuit in which the other terminal of the bidirectional switch element is connected to an intermediate connection point of the second semiconductor switch element series circuit, and is connected to a positive terminal or a negative terminal of the DC power supply circuit. In the turn-off operation of at least three serially connected semiconductor switch elements having a function of maintaining the ON state and the OFF state at the same time, any one of the at least three serially connected series switch elements is first selected. Only one semiconductor switch element is turned off, and the remaining semiconductor switch elements are turned off with a time delay from the turn-off completion time of the first semiconductor switch element turned off.

第2の発明においては、第1の発明におけるマルチレベル電力変換回路の制御方式において,前記直流の正側電位又は負側電位に接続された少なくとも3個直列接続された半導体スイッチ素子群が全てターンオフした後に,最初にターンオフさせた半導体スイッチ素子を所定時間ターンオンさせる。   In the second invention, in the control method of the multilevel power conversion circuit in the first invention, at least three semiconductor switch elements connected in series connected to the positive or negative DC potential are all turned off. After that, the semiconductor switch element that is turned off first is turned on for a predetermined time.

第3の発明においては、第1の発明におけるマルチレベル電力変換回路の制御方式において,前記直流の正側電位又は負側電位に接続された少なくとも3個直列接続された半導体スイッチ素子群の中で,最初にターンオフさせる半導体スイッチ素子を,順次切り換える。   According to a third invention, in the control method of the multilevel power conversion circuit according to the first invention, among the at least three series-connected semiconductor switch element groups connected to the DC positive potential or negative potential. The semiconductor switch elements to be turned off first are sequentially switched.

第4の発明においては、第1〜第3の発明の何れかのマルチレベル電力変換回路の制御方式を、7レベル以上の電位で構成した交流電圧を出力するマルチレベル電力変換回路に適用する。   In the fourth invention, the control method of the multilevel power conversion circuit according to any one of the first to third inventions is applied to a multilevel power conversion circuit that outputs an alternating voltage composed of a potential of 7 levels or more.

本発明では、マルチレベル電力変換回路において、同時にオン状態及びオフ状態を維持する機能を備えた少なくとも3個直列接続された半導体スイッチ素子群をオフさせる制御方式として、直列接続された半導体スイッチ素子群の内,最初にいずれか1個の半導体スイッチ素子のみをターンオフさせ,残りの半導体スイッチ素子は最初にターンオフさせた半導体スイッチ素子のターンオフ時点より時間を遅らせてターンオフさせる。さらに全てがターンオフ完了後に、最初にターンオフさせた半導体スイッチ素子を所定時間ターンオンさせるようにしている。
この結果、主回路に部品を付加することなく直列接続された各半導体スイッチ素子に印加される電圧をより均等化させることが可能となる。
In the present invention, in the multilevel power conversion circuit, as a control method for turning off at least three semiconductor switch elements connected in series having the function of simultaneously maintaining the ON state and the OFF state, the semiconductor switch elements connected in series First, only one of the semiconductor switch elements is turned off, and the remaining semiconductor switch elements are turned off with a time delay from the turn-off time of the semiconductor switch element that was initially turned off. Further, after all the turn-off is completed, the semiconductor switch element that is turned off first is turned on for a predetermined time.
As a result, it is possible to equalize the voltages applied to the semiconductor switch elements connected in series without adding components to the main circuit.

本発明の実施例を示す制御アルゴリズムである。It is a control algorithm which shows the Example of this invention. 本発明の実施例を示す制御信号例を示すタイムチャート図である。It is a time chart figure which shows the example of the control signal which shows the Example of this invention. 図2に示す各時刻における各IGBTへの印加電圧を示す図である。It is a figure which shows the applied voltage to each IGBT in each time shown in FIG. 5レベル変換回路によるインバータ回路例である。It is an example of an inverter circuit by a 5-level conversion circuit. マルチレベル変換回路の基本形1である。This is a basic form 1 of a multilevel conversion circuit. マルチレベル変換回路の基本形2である。This is basic form 2 of the multilevel conversion circuit. マルチレベル変換回路の基本形に基づいた7レベル変換回路例である。It is an example of a 7 level conversion circuit based on the basic form of a multilevel conversion circuit. 双方向性スイッチ回路例である。It is an example of a bidirectional switch circuit. 5レベルインバータの出力線間電圧波形例である。It is an example of the output line voltage waveform of a 5-level inverter. 5レベルインバータの動作遷移図である。It is an operation | movement transition diagram of a 5 level inverter.

本発明の要点は、直流電源回路の正側端子と負側端子間に接続した半導体スイッチ素子を少なくとも8個直列接続した第1の半導体スイッチ素子直列回路と、前記直流電源回路の中間電位点に一方の端子が接続された双方向性スイッチ素子と、前記第1の半導体スイッチ素子直列回路の接続点の中の特定の二つの接続点間に接続される第2の半導体スイッチ素子直列回路と、前記第2の半導体スイッチ素子直列回路と並列接続されるコンデンサと、を備え、前記第2の半導体スイッチ素子直列回路の中間接続点に前記双方向性スイッチ素子の他方の端子を接続したマルチレベル電力変換回路であって、前記直流電源回路の正側端子又は負側端子に接続された同時にオン状態及びオフ状態を維持する機能を備えた少なくとも3個直列接続された半導体スイッチ素子群のターンオフ動作において,前記直列スイッチ素子群の内,最初にいずれか1個の半導体スイッチ素子のみをターンオフさせ,残りの半導体スイッチ素子は前記最初にターンオフさせた半導体スイッチ素子のターンオフ完了時点より時間を遅らせてターンオフさせ、さらに全ての半導体スイッチ素子がターンオフ完了した後、最初にターンオフさせた半導体スイッチ素子を短時間オンさせる点である。   The gist of the present invention is that a first semiconductor switch element series circuit in which at least eight semiconductor switch elements connected between the positive terminal and the negative terminal of the DC power supply circuit are connected in series, and an intermediate potential point of the DC power supply circuit. A bidirectional switch element having one terminal connected thereto, a second semiconductor switch element series circuit connected between two specific connection points among the connection points of the first semiconductor switch element series circuit; And a capacitor connected in parallel with the second semiconductor switch element series circuit, wherein the other terminal of the bidirectional switch element is connected to an intermediate connection point of the second semiconductor switch element series circuit. At least three converter circuits connected to the positive terminal or the negative terminal of the DC power supply circuit and having the function of simultaneously maintaining the on state and the off state are connected in series. In the turn-off operation of the conductor switch element group, only one of the series switch element groups is turned off first, and the remaining semiconductor switch elements are turned off. The point is that the semiconductor switch element is turned off with a delay from the time, and after all the semiconductor switch elements have been turned off, the semiconductor switch element that was turned off first is turned on for a short time.

図1に、図4に示す5レベル電力変換回路における本発明の実施アルゴリズム図を示す。
スタートブロックBL1後,ブロックBL3でS1(S1又はS4のターンオフ判断がなされた場合,ブロックBL4にてS1又はS4の中の所定の1素子のみをターンオフさせる。この時,IGBT側に電流が流れていた場合,電流の遮断動作が行われるので,この素子にはターンオフ損失が発生し,また電圧Edがコレクタ・エミッタ間に印加される。その後、所定時間後(タイマーブロックBL5による処理)に,ブロックBL6にてS1又はS4の直列接続されたその他のスイッチ素子をターンオフさせる。この時、電流の遮断動作はないため,ターンオフ損失は発生せず,また電圧も印加されない。その後、所定時間後(タイマーブロックBL7による処理)に,ブロックBL8にて最初にターンオフさせた素子を短時間オンさせる。この時,この素子には電圧印加がなくなると同時に,その他の素子にはEd/2ずつ電圧が印加される。その後ブロックBL9にてその他の通常のアルゴリズムが実行され,図8に示すように最終的にS1(S1a〜S1c)又はS4(S4a〜S4c)には最大で3Edが印加される。
FIG. 1 shows an implementation algorithm diagram of the present invention in the five-level power conversion circuit shown in FIG.
After the start block BL1, S1 in the block BL3 (when the turn-off judgment of S1 or S4 is made, only one predetermined element in S1 or S4 is turned off in the block BL4. At this time, current flows to the IGBT side. In this case, since the current is cut off, a turn-off loss is generated in the element, and the voltage Ed is applied between the collector and the emitter, and after a predetermined time (processing by the timer block BL5), the block At BL6, other switch elements connected in series with S1 or S4 are turned off, and at this time, since there is no current cut-off operation, no turn-off loss occurs and no voltage is applied. In the process of block BL7), the element that was first turned off in block BL8 is turned on for a short time. At this time, no voltage is applied to this element, and at the same time, a voltage is applied to the other elements by Ed / 2, and then another normal algorithm is executed in block BL9, as shown in FIG. Therefore, 3Ed is applied to S1 (S1a to S1c) or S4 (S4a to S4c) at the maximum.

最初にターンオフさせるスイッチ素子(IGBT)をS1aとした時の各IGBT(S1a〜S1c)の駆動信号例を図2に、各時刻における各IGBTの電圧を図3に、各々示す。図10に示す動作遷移図において、IGBTS1がオフして、電圧EdがIGBTS1a〜S1cに印加される動作モードで、IGBTS1a〜S1cがオンしている状態からS1へのオフ信号に基づいて、時刻t1で最初にIGBTS1aをオフさせ、各IGBTの電圧が静的に安定した時刻t2でIGBTS1bとS1cをオフさせる。その後IGBTS1bとS1cのオン状態が静的に安定した時刻t3で最初にオフしたIGBTS1aを短時間オンさせる。オン時間はIGBTS1aがオンして電圧が零となり、IGBTS1bとS1cがEd/2ずつ電圧を分担し安定するまでの時間で、短時間である。時刻t4でIGBTS1aをオフしてもこの状態は維持される。   FIG. 2 shows an example of a drive signal of each IGBT (S1a to S1c) when the switch element (IGBT) to be turned off first is S1a, and FIG. 3 shows the voltage of each IGBT at each time. In the operation transition diagram shown in FIG. 10, in the operation mode in which the IGBT TS1 is turned off and the voltage Ed is applied to the IGBTTS1a to S1c, the time t1 is based on the off signal from the state in which the IGBTTS1a to S1c is on to S1. First, the IGBTTS 1a is turned off, and the IGBTs 1b and S1c are turned off at time t2 when the voltage of each IGBT is statically stabilized. Thereafter, the IGBTTS1a that was initially turned off at time t3 when the on-states of the IGBTTS1b and S1c are statically stabilized is turned on for a short time. The on-time is a short period of time until the IGBT TS1a is turned on and the voltage becomes zero, and the IGBTTS1b and S1c share the voltage by Ed / 2 and stabilize. This state is maintained even if the IGBTTS1a is turned off at time t4.

この状態で、時刻t5で図10に示す動作遷移図において、IGBTS1(S1a〜S1c)に2Edが印加されるモードになると、IGBTS1aの電圧は零からEd/3に、IGBTS1bとS1cの電圧はEd/2+Ed/3=5Ed/6となる。さらに、時刻t6で図10に示す動作遷移図において、IGBTS1(S1a〜S1c)に3Edが印加されるモードになると、IGBTS1aの電圧はEd/3+Ed/3=2Ed/3に、IGBTS1bとS1cの電圧は5Ed/6+Ed/3=7Ed/6となる。   In this state, in the operation transition diagram shown in FIG. 10 at time t5, in a mode in which 2Ed is applied to IGBTTS1 (S1a to S1c), the voltage of IGBTTS1a changes from zero to Ed / 3, and the voltages of IGBTTS1b and S1c change to Ed. / 2 + Ed / 3 = 5Ed / 6. Further, in the operation transition diagram shown in FIG. 10 at time t6, when a mode in which 3Ed is applied to IGBTTS1 (S1a to S1c), the voltage of IGBTTS1a becomes Ed / 3 + Ed / 3 = 2Ed / 3, and the voltages of IGBTTS1b and S1c. Is 5Ed / 6 + Ed / 3 = 7Ed / 6.

従って、従来方式ではIGBTS1aに印加される電圧は5Ed/3、IGBTS1bとS1cに印加される電圧は2Ed/3であり、IGBT素子としては、5Ed/3に耐える素子が必要であるが、本提案ではIGBTS1aに印加される電圧は2Ed/3、IGBTS1bとS1cに印加される電圧は7Ed/6であり、IGBT素子としては、7Ed/6に耐える素子が必要なり、従来に比べて最大印加電圧値が軽減され、耐圧の低いIGBTを適用することが可能となる。   Therefore, in the conventional method, the voltage applied to the IGBT TS1a is 5Ed / 3, the voltage applied to the IGBTTS1b and S1c is 2Ed / 3, and an IGBT element that can withstand 5Ed / 3 is required. Then, the voltage applied to the IGBT TS1a is 2Ed / 3, the voltage applied to the IGBTTS1b and S1c is 7Ed / 6, and the IGBT element needs an element that can withstand 7Ed / 6. Can be reduced, and an IGBT having a low breakdown voltage can be applied.

また、図1で毎回同じスイッチ素子を最初にターンオフさせると,このスイッチ素子のみターンオフ損失が発生し,熱的なアンバランスが発生するので,これを防止するため,ブロックBL9では,最初にターンオフさせるスイッチ素子を毎回(もしくは数回ごとに),順次切り換え,熱的なアンバランスを低減させる。
また、IGBTS4a〜S4cについても同様の動作となるので、説明は省略する。
Further, when the same switch element is first turned off each time in FIG. 1, only the switch element causes a turn-off loss and a thermal imbalance occurs. Therefore, in order to prevent this, the block BL9 is first turned off. The switch elements are switched sequentially every time (or every few times) to reduce thermal imbalance.
Moreover, since it becomes the same operation | movement also about IGBTTS4a-S4c, description is abbreviate | omitted.

図7にフライングキャパシタを用いた7レベル変換回路の1相分の構成を示す。実施例1に示した5レベル変換回路を7レベルに拡張した構成である。DP1,DP2が直列に接続された直流電源(電圧は3Ed×2)で,正側電位をP,負側電位をN,中点電位をMとしている。   FIG. 7 shows the configuration of one phase of a seven-level conversion circuit using a flying capacitor. In this configuration, the 5-level conversion circuit shown in the first embodiment is expanded to 7 levels. In a DC power source (voltage is 3Ed × 2) in which DP1 and DP2 are connected in series, the positive potential is P, the negative potential is N, and the midpoint potential is M.

S1a〜S1d、S2、S3、S4、S5、S6a〜S6dが直流電源の正側電位Pと負側電位Nとの間に12個直列接続されているダイオードを逆並列接続したIGBTからなる第1の半導体スイッチ素子直列回路である。S9〜S12は,IGBTS1dとS2との接続点と,IGBTS5とS6aとの接続点との間に4個直列接続されたダイオードを逆並列接続したIGBTからなる第2の半導体スイッチ素子直列回路である。S7,S8は直流電源の中点電位であるM電位と,IGBTS10とS11との接続点との間に接続された双方向性のスイッチ素子で,図4に示すように逆耐圧を有するIGBTを逆並列接続するか,もしくは図8(a),図8(b)に示すように逆耐圧を有しないIGBTとダイオードとを組み合わせで構成できる。   S1a to S1d, S2, S3, S4, S5, and S6a to S6d are first IGBTs composed of 12 diodes connected in series between the positive side potential P and the negative side potential N of the DC power source and connected in reverse parallel. This is a semiconductor switch element series circuit. S9 to S12 are second semiconductor switch element series circuits composed of IGBTs in which four diodes connected in series are connected in reverse parallel between the connection point of IGBTs 1d and S2 and the connection point of IGBTs 5 and S6a. . S7 and S8 are bidirectional switch elements connected between the M potential, which is the midpoint potential of the DC power supply, and the connection point between the IGBTs 10 and S11. An IGBT having a reverse breakdown voltage as shown in FIG. They can be connected in reverse parallel, or can be configured with a combination of an IGBT and a diode having no reverse breakdown voltage as shown in FIGS. 8 (a) and 8 (b).

また、C3がフライングキャパシタと呼ばれるコンデンサで,第2の半導体スイッチ素子直列回路(IGBTS9〜S12の直列回路)と並列に接続される。コンデンサC3の両端の平均的な電圧は2Edに制御される。C2はIGBTS3とS4の直列回路と並列接続されたフライングキャパシタで、コンデンサC1の両端の平均的な電圧はEdに制御される。C4はIGBTS10とS11の直列回路と並列接続されたフライングキャパシタで、コンデンサC4の両端の平均的な電圧はEdに制御される。ここで直流電源のP電位又はN電位と,フライングキャパシタの正側電位又は負側電位間に接続されているIGBTS1a〜S1d又はS6a〜S6dが4直列となっている理由は,この間に印加される電圧の最大値に応じて,全てのIGBTを同一電圧定格とするためである。   Further, C3 is a capacitor called a flying capacitor and is connected in parallel with the second semiconductor switch element series circuit (series circuit of IGBTs 9 to S12). The average voltage across the capacitor C3 is controlled to 2Ed. C2 is a flying capacitor connected in parallel with the series circuit of IGBTs 3 and S4, and the average voltage across the capacitor C1 is controlled to Ed. C4 is a flying capacitor connected in parallel with the series circuit of the IGBTs 10 and S11, and the average voltage across the capacitor C4 is controlled to Ed. The reason why the IGBTs 1a to S1d or S6a to S6d connected between the P potential or N potential of the DC power source and the positive side potential or negative side potential of the flying capacitor is in series is applied during this period. This is because all IGBTs have the same voltage rating according to the maximum voltage value.

この様な構成においても、5レベル変換回路と同様に、図1に示す制御方式を適用可能である。図1のブロックBL3は「S1又はS6ターンオフ?」となる。詳細な説明は実施例1と同様であるので、省略するが、結果は下記となる。
例えば、IGBTS1aからS1dを従来のように一括で遮断すると、IGBTS1aが最初に遮断された場合、IGBTS1aの電圧はEd+3Ed/4=7Ed/4に、IGBTS1b〜S1dの電圧は3Ed/4となり、IGBTとしては7Ed/4に耐える素子が必要となる。また、本発明の制御方式を適用すると、IGBTS1aの電圧は3Ed/4に、IGBTS1b〜S1dの電圧はEd/3+3Ed/4=13Ed/12となり、IGBTとしては13Ed/12に耐える素子が必要となる。
実施例1と同様に、従来方式と比べて最大印加電圧値が軽減され、耐圧の低いIGBTを適用することが可能となる。
Even in such a configuration, the control method shown in FIG. 1 can be applied as in the case of the five-level conversion circuit. The block BL3 in FIG. 1 is “S1 or S6 turn off?”. Since the detailed description is the same as that of Example 1, it is omitted, but the result is as follows.
For example, when IGBTs 1a to S1d are collectively shut off as in the conventional case, when IGBTTS1a is shut off first, the voltage of IGBTTS1a becomes Ed + 3Ed / 4 = 7Ed / 4, and the voltages of IGBTTS1b to S1d become 3Ed / 4. Requires an element that can withstand 7 Ed / 4. In addition, when the control method of the present invention is applied, the voltage of the IGBT 1a becomes 3Ed / 4, the voltages of the IGBTs 1b to S1d become Ed / 3 + 3Ed / 4 = 13Ed / 12, and the IGBT needs an element that can withstand 13Ed / 12. .
Similar to the first embodiment, the maximum applied voltage value is reduced as compared with the conventional method, and an IGBT having a low breakdown voltage can be applied.

また、図1で毎回同じスイッチ素子を最初にターンオフさせると,このスイッチ素子のみターンオフ損失が発生し,熱的なアンバランスが発生するので,これを防止するため,ブロックBL9では,最初にターンオフさせるスイッチ素子を毎回(もしくは数回ごとに),順次切り換え,熱的なアンバランスを低減させる。
また、IGBTS6a〜S6dについても同様の動作となるので、説明は省略する。
Further, when the same switch element is first turned off each time in FIG. 1, only the switch element causes a turn-off loss and a thermal imbalance occurs. Therefore, in order to prevent this, the block BL9 is first turned off. The switch elements are switched sequentially every time (or every few times) to reduce thermal imbalance.
Moreover, since it becomes the same operation | movement also about IGBTTS6a-S6d, description is abbreviate | omitted.

本実施回路例では,5レベル変換回路と7レベル変換回路例の場合について示したが,図5又は図6の回路に基づき,直流電圧の中間電位点に双方向性のスイッチ素子を接続して構成した9レベル以上のマルチレベル変換器においても,適用可能である。   In this embodiment circuit example, the case of the 5-level conversion circuit and the 7-level conversion circuit example has been shown. However, based on the circuit of FIG. 5 or 6, a bidirectional switch element is connected to the intermediate potential point of the DC voltage. The present invention can also be applied to a multi-level converter having 9 levels or more.

本発明は、正側電位P,負側電位N,中点電位Mを備えた直流電源から5レベル以上のマルチレベルの変換回路を耐圧の同じ半導体素子で構成する場合の直列接続した半導体素子の電圧バランスを部品を追加せずに実現する制御方式であり、高電圧電動機駆動装置、系統連系用電力変換装置などへの適用が可能である。   The present invention relates to a semiconductor device connected in series in the case where a multi-level conversion circuit of five levels or more is constituted by a semiconductor device having the same breakdown voltage from a DC power source having a positive potential P, a negative potential N, and a midpoint potential M. It is a control method that realizes voltage balance without adding components, and can be applied to a high-voltage motor drive device, a grid interconnection power conversion device, and the like.

DP1、DP2、DP3、DP4・・・直流電源 ACM・・・交流電動機
S1、S1a〜S1d、S2〜S5、S4a〜S4c、S6a〜S6d・・・IGBT
S7〜S12・・・IGBT C1〜C4・・・コンデンサ
ACS1、ACS2・・・双方向性スイッチ素子
DP1, DP2, DP3, DP4 ... DC power supply ACM ... AC motor S1, S1a-S1d, S2-S5, S4a-S4c, S6a-S6d ... IGBT
S7 to S12 ... IGBT C1 to C4 ... Capacitors ACS1, ACS2 ... Bidirectional switch elements

Claims (4)

直流から交流,又は交流から直流に変換する電力変換回路であって,1相分の回路として,直流電源回路の正側端子と負側端子間に接続されたダイオードを逆並列接続した半導体スイッチ素子を少なくとも8個直列に接続した第1の半導体スイッチ素子直列回路と、前記直流電源回路の中間電位点に一方の端子が接続された双方向性にスイッチングが可能な双方向性スイッチ素子と、前記第1の半導体スイッチ素子直列回路の半導体スイッチ素子同士の接続点の中の特定の二つの接続点間に接続されるダイオードが逆並列接続された半導体スイッチ素子を直列接続した第2の半導体スイッチ素子直列回路と、前記第2の半導体スイッチ素子直列回路と並列接続されたコンデンサと、を備え、前記第2の半導体スイッチ素子直列回路の中間接続点に前記双方向性スイッチ素子の他方の端子を接続したマルチレベル電力変換回路であって、前記直流電源回路の正側端子又は負側端子に接続された同時にオン状態及びオフ状態を維持する機能を備えた少なくとも3個直列接続された半導体スイッチ素子群のターンオフ動作において,前記少なくとも3個直列接続された直列スイッチ素子群の内,最初にいずれか1個の半導体スイッチ素子のみをターンオフさせ,残りの半導体スイッチ素子は前記最初にターンオフした半導体スイッチ素子のターンオフ完了時点より時間を遅らせてターンオフさせることを特徴とするマルチレベル電力変換回路の制御方式。   A power conversion circuit for converting from direct current to alternating current or from alternating current to direct current, a semiconductor switching element in which a diode connected between a positive terminal and a negative terminal of a direct current power supply circuit is connected in reverse parallel as a circuit for one phase A first semiconductor switch element series circuit in which at least eight are connected in series, a bidirectional switch element capable of bidirectional switching in which one terminal is connected to an intermediate potential point of the DC power supply circuit, A second semiconductor switch element in which semiconductor switch elements connected in reverse parallel are connected in series between two specific connection points among the connection points of the semiconductor switch elements in the first semiconductor switch element series circuit An intermediate connection of the second semiconductor switch element series circuit, comprising: a series circuit; and a capacitor connected in parallel with the second semiconductor switch element series circuit. A multi-level power converter circuit connected to the other terminal of the bidirectional switch element, and connected to the positive terminal or the negative terminal of the DC power supply circuit and simultaneously maintaining the on state and the off state. In the turn-off operation of at least three semiconductor switch elements connected in series, first, only one of the at least three series switch elements connected in series is turned off, and the rest The control method of a multilevel power conversion circuit, wherein the semiconductor switch element is turned off with a time delay from a time point when the semiconductor switch element that was turned off first is turned off. 請求項1に記載のマルチレベル電力変換回路の制御方式において,前記直流の正側電位又は負側電位に接続された少なくとも3個直列接続された半導体スイッチ素子群が全てターンオフした後に,最初にターンオフさせた半導体スイッチ素子を所定時間ターンオンさせることを特徴とするマルチレベル電力変換回路の制御方式。   2. The control method for a multilevel power conversion circuit according to claim 1, wherein at least three semiconductor switch elements connected in series connected to the positive or negative DC potential are turned off and then turned off first. A control method for a multilevel power conversion circuit, wherein the semiconductor switch element is turned on for a predetermined time. 請求項1に記載のマルチレベル電力変換回路の制御方式において,前記直流の正側電位又は負側電位に接続された少なくとも3個直列接続された半導体スイッチ素子群の中で,最初にターンオフさせる半導体スイッチ素子を,順次切り換えることを特徴とするマルチレベル電力変換回路の制御方式。   2. The control system for a multilevel power conversion circuit according to claim 1, wherein the semiconductor is first turned off among at least three series-connected semiconductor switch elements connected to the DC positive potential or negative potential. A control method for a multi-level power conversion circuit, characterized by sequentially switching switch elements. 請求項1から請求項3の何れか1項に記載のマルチレベル電力変換回路の制御方式を、7レベル以上の電位で構成した交流電圧を出力するマルチレベル電力変換回路に適用することを特徴とするマルチレベル電力変換回路の制御方式。   The multilevel power conversion circuit control method according to any one of claims 1 to 3 is applied to a multilevel power conversion circuit that outputs an alternating voltage composed of a potential of 7 levels or more. Multilevel power conversion circuit control method.
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