JP2014157642A - Semiconductor device, semiconductor storage device, and control method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce malfunction.SOLUTION: A memory cell MC00 includes a fuse element EF connected between a node N11 of a bit line pair BL0 and a node N12 of an inverted bit line xBL0. An intermediate region of the fuse element EF is connected to a node N13 of a word line WL0. Thus, the fuse element EF electrically includes a first fuse element F1 connected between the bit line BL0 and the word line WL0, and a second fuse element F2 connected between the inverted bit line xBL0 and the word line WL0. A voltage application circuit 21 connected to the bit line pairs BL0, xBL0 causes an imbalance between the ohmic values of the first fuse element F1 and the second fuse element F2. The memory cell MC00 stores the state of input data DI0 by imbalance of the ohmic values of the first fuse element F1 and the second fuse element F2 that are included in the fuse element EF.

Description

  The present invention relates to a semiconductor device, a semiconductor memory device, and a semiconductor device control method.

  2. Description of the Related Art Conventionally, a semiconductor device has a fuse element electric fuse for storing data, setting a redundant circuit, and adjusting a resistance value (see, for example, Patent Document 1). The electric fuse is blown by the overcurrent supplied. Accordingly, one piece of information is stored in one electric fuse. The fuse circuit has a transistor connected in series with an electrical fuse, and depends on the on-resistance value of the transistor and the state of the electrical fuse (non-cut or low resistance conduction state, disconnection or high resistance non-conduction state) Level output signal is generated. Based on the level of the output signal, the information (“0” or “1”) stored in the electric fuse is determined.

JP 2007-073576 A

  By the way, the output signal of the fuse circuit described above has a level corresponding to the on-resistance value of the transistor and the resistance value of the electric fuse. The on-resistance value of the transistor changes according to process variations and the like. The resistance value of the electric fuse changes according to variations in the shape of the electric fuse, the state at the time of cutting, and the like. These variations affect the level of the output signal of the fuse circuit. The variation in the elements included in the fuse circuit affects the write margin in the write operation to the fuse circuit and the read margin in the determination of the output signal of the fuse circuit, resulting in malfunction.

  According to one aspect of the present invention, a memory cell including a pair of fuse elements connected in series between a first node and a second node, and the first node based on a program signal and input data And a second voltage lower than the write voltage is applied to one of the first node and the second node. A second voltage application circuit for applying a read voltage to the third node connected between the pair of fuse elements based on the read signal; and And a readout circuit for outputting output data corresponding to a voltage difference between the first node and the second node.

  According to one aspect of the present invention, malfunctions can be reduced.

1 is a schematic block diagram of a semiconductor memory device. 1 is a partial circuit diagram of a semiconductor memory device according to a first embodiment. It is a schematic plan view of a fuse element. It is a schematic sectional drawing of a fuse element. It is a schematic sectional drawing of a fuse element. It is a partial circuit diagram of the semiconductor memory device of the second embodiment. It is a schematic sectional drawing of a fuse element.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to the accompanying drawings.
As shown in FIG. 1, the semiconductor memory device includes a control unit 10, a voltage application unit 20, a memory cell array 30, and an output unit 40.

  The control unit 10 operates based on the high potential voltage VDD and the low potential voltage VSS. Although not shown, similarly, the voltage application unit 20 and the output unit 40 operate based on the high potential voltage VDD and the low potential voltage VSS.

  The control unit 10 includes a row decoder 11. The row decoder 11 selects one of a plurality (four in FIG. 1) of word lines WL0 to WL3 based on the address signal ADR. The row decoder 11 controls the potential of the selected word line based on the program signal PRG and the read signal RD. For example, the program signal PRG is at the high potential voltage VDD level (H level) during a program operation for writing data to the memory cell, and is at the low potential voltage VSS level (L level) at times other than the program operation. The read signal RD is at the H level during a read operation for reading data from the memory cell, and is at the L level during other than the read operation. The row decoder 11 sets the word line selected during the program operation to a high impedance state (non-connection state). The row decoder 11 supplies the high potential voltage VDD to the word line selected during the read operation, that is, the word line. The row decoder 11 is an example of a second voltage application circuit.

  The voltage application unit 20 includes a plurality (four in FIG. 1) of voltage application circuits 21 to 24. The voltage application circuit 21 is connected to the bit line pair BL0, xBL0. The voltage application circuit 21 is supplied with a program signal PRG, input data DI0, and a write voltage VBL. Based on the program signal PRG, the voltage application circuit 21 drives the bit line pair BL0, xBL0 during a program operation, and places the bit line pair BL0, xBL0 in a high impedance state (non-connection state) during other than the program operation. ). In the program operation, the voltage application circuit 21 connects one bit line of the pair of bit lines BL0 and xBL0 to a wiring for supplying the write voltage VBL according to the level of the input data DI0. The other bit line of the pair of bit lines BL0 and xBL0 is connected to a wiring for supplying the low potential voltage VSS.

  Similarly, the voltage application circuits 22 to 24 drive the bit line pairs BL1, xBL1 to BL3, xBL3 during the program operation based on the program signal PRG, and the bit line pairs BL1, BL1 at times other than the program operation. xBL1 to BL3 and xBL3 are set to a high impedance state. The voltage application circuits 22 to 24 connect one bit line corresponding to the input data DI1 to DI3 to the wiring of the write voltage VBL during the program operation, and the other bit corresponding to the input data DI1 to DI3. The line is connected to the wiring of the low potential voltage VSS. The voltage application circuits 21 to 24 are examples of a first voltage application circuit.

The memory cell array 30 includes, for example, a plurality (16 in FIG. 1) of memory cells (memory cells) MC00 to MC33 arranged in a matrix.
A plurality (four in FIG. 1) of memory cells MC00 to MC03 arranged in the row direction are connected to the word line WL0. Similarly, the plurality of memory cells MC10 to MC13 are connected to the word line WL1. The plurality of memory cells MC20 to MC23 are connected to the word line WL2. The plurality of memory cells MC30 to MC33 are connected to the word line WL3.

  A plurality (three in FIG. 1) of memory cells MC00 to MC20 arranged in the column direction are connected to the bit line pair BL0, xBL0. Similarly, the plurality of memory cells MC01 to MC21 are connected to the bit line pair BL1, xBL1. The plurality of memory cells MC02 to MC22 are connected to the bit line pair BL2, xBL2. The plurality of memory cells MC03 to MC23 are connected to the bit line pair BL3, xBL3.

  Each of the memory cells MC00 to MC33 includes an electrically programmable fuse (Electrical Programmable Fuse) element. The memory cell MC00 stores “0” or “1” information according to the potential of the bit line pair BL0, xBL0. Similarly, the memory cells MC10 to MC30 store a state of “0” or “1” depending on the potential of the bit line pair BL0, xBL0. Similarly, the memory cells MC01 to MC33 store information of “0” or “1” according to the potentials of the bit line pairs BL1, xBL1 to BL3, xBL3, respectively.

  The output unit 40 includes a plurality (four in FIG. 1) of readout circuits 41 to 44. A read signal RD is supplied to the read circuits 41 to 44. Based on the read signal RD, the read circuit 41 outputs the output data DO0 having a level corresponding to the potential difference between the bit line pair BL0 and the inverted bit line xBL0 during the read operation. Similarly, the read circuits 42 to 44 output the output data DO1 to DO3 of a level corresponding to the potential difference between the bit line pairs BL1 to BL3 and the inverted bit lines xBL0 to xBL3 during the read operation.

Next, an example of each circuit will be described.
FIG. 2 shows an example of a circuit related to writing to and reading from the memory cell MC00. Note that the circuit related to writing and reading to the memory cells MC01 to MC33 shown in FIG. 1 is the same as the circuit to the memory cell MC00. For this reason, the drawings and description of the circuits for the memory cells MC01 to MC33 are omitted.

  As shown in FIG. 2, the row decoder 11 includes a transistor T11. The transistor T11 is, for example, a P channel MOS transistor. The source terminal of the transistor T11 is connected to the power supply wiring VDD, and the drain terminal is connected to the word line WL0. The row decoder 11 supplies the word line control signal WC0 to the gate terminal of the transistor T11.

  The row decoder 11 generates the word line control signal WC0 based on the address signal ADR and the read signal RD. For example, during the read operation, the row decoder 11 selects the word line WL0 based on the address signal ADR, and generates the H-level word line control signal WC0 according to the word line WL0.

  The transistor T11 is turned on in response to the L-level word line control signal WC0 and turned off in response to the H-level word line control signal WC0. The word line WL0 is connected to the power supply wiring VDD via the turned on transistor T11. Therefore, the transistor T11 that is turned on supplies the high potential voltage VDD to the word line WL0. When the transistor T11 is turned off, the word line WL0 is in a high impedance state.

  The program signal PRG is supplied to the buffer circuit 51, and the buffer circuit 51 outputs a program signal SPG having the same level as the program signal PRG. The buffer circuit 51 is included in, for example, the voltage application unit 20 illustrated in FIG. The buffer circuit 51 may be included in the control unit 10 shown in FIG.

The voltage application circuit 21 includes a decoder circuit 60 and a bridge circuit 70.
The decoder circuit 60 generates control signals SC1 to SC4 for controlling the bridge circuit 70 based on the input data DI0 and the program signal PRG.

  The bridge circuit 70 is connected to a wiring to which a write voltage VBL is supplied and a wiring to which a low potential voltage VSS is supplied (hereinafter simply referred to as a power supply wiring VSS). The bridge circuit 70 is connected to the bit line pair BL0, xBL0.

  Based on the control signals SC1 to SC4, the bridge circuit 70 supplies the write voltage VBL to any one of the bit line pairs BL0 and xBL0 and supplies the other bit line to the power supply wiring VSS. Connecting.

The decoder circuit 60 includes inverter circuits 61 and 62, NOR circuits 63 and 64, and NAND circuits 65 and 66.
The inverter circuit 61 outputs a signal xD0 obtained by logically inverting the input data DI0. The inverter circuit 62 outputs a signal zD0 obtained by logically inverting the signal xD0.

  The NOR circuit 63 outputs a control signal SC3 having a level corresponding to a result obtained by performing a NOR operation on the inverted level of the program signal SPG and the signal xD0. The NOR circuit 64 outputs a control signal SC4 having a level corresponding to a result obtained by performing a NOR operation on the inverted level of the program signal SPG and the signal zD0.

  The NAND circuit 65 outputs a control signal SC1 having a level corresponding to a result obtained by performing a NAND operation on the program signal SPG and the signal xD0. The NAND circuit 66 outputs a control signal SC2 having a level corresponding to a result obtained by performing a NAND operation on the program signal SPG and the signal zD0.

The bridge circuit 70 includes transistors T21 to T24.
The transistors T21 and T22 are, for example, P channel MOS transistors. The transistors T23 and T24 are, for example, N channel MOS transistors.

  The source terminal of the transistor T21 is connected to a wiring to which the write voltage VBL is supplied, the drain terminal of the transistor T21 is connected to the drain terminal of the transistor T23, and the control signal SC1 is supplied to the gate terminal of the transistor T21. The source terminal of the transistor T23 is connected to a wiring (hereinafter simply referred to as a power supply wiring VSS) to which a low potential voltage VSS (for example, 0 V (zero volt)) is supplied. A control signal SC3 is supplied to the gate terminal of the transistor T23.

  The source terminal of the transistor T22 is connected to the wiring to which the write voltage VBL is supplied, the drain terminal of the transistor T22 is connected to the drain terminal of the transistor T24, and the control signal SC2 is supplied to the gate terminal of the transistor T22. The source terminal of the transistor T24 is connected to the power supply wiring VSS. A control signal SC4 is supplied to the gate terminal of the transistor T24.

  A node N01 between the drain terminal of the transistor T21 and the drain terminal of the transistor T23 is connected to the bit line BL0. A node N02 between the drain terminal of the transistor T22 and the drain terminal of the transistor T24 is connected to the inverted bit line xBL0.

  A memory cell MC00 is connected between the bit line BL0 and the inverted bit line xBL0. Memory cell MC00 includes a fuse element EF. The first terminal of the fuse element EF is connected to the node N11 of the bit line pair BL0, and the second terminal of the fuse element EF is connected to the node N12 of the inverted bit line xBL0. In the fuse element EF, the third terminal corresponding to the intermediate region between the first terminal and the second terminal is connected to the node N13 of the word line WL0. Therefore, the fuse element EF is electrically connected to the first fuse element F1 connected between the bit line BL0 and the word line WL0 and the second fuse element EF connected between the inverted bit line xBL0 and the word line WL0. A fuse element F2 is included.

  In the initial state (before programming), the resistance values of the first fuse element F1 and the second fuse element F2 are substantially the same. The current flowing through the fuse elements F1 and F2 in accordance with the voltage supplied to the bit line pair BL0 and xBL0 in the program operation makes the resistance values of the fuse elements F1 and F2 different from each other. That is, the resistance values of the pair of fuse elements F1 and F2 are imbalanced. The imbalance of the resistance values of the fuse elements F1, F2 corresponds to the voltage supplied to the bit line pair BL0, xBL0, that is, the state (level) of the input data DI0. That is, in the memory cell MC00, in the fuse element EF, the resistance value of the portion on the bit line BL0 side (first fuse element F1) from the intermediate region and the portion on the inverted bit line xBL0 side (second fuse element) from the intermediate region. By making the resistance value of F2) different from each other, information of “0” or “1” is stored according to the input data DI0.

  The read signal RD is supplied to the inverter circuit 52. The inverter circuit 52 is included in, for example, the output unit 40 shown in FIG. The inverter circuit 52 may be included in the control unit 10 shown in FIG. The inverter circuit 52 outputs an inverted read signal xRD having a level obtained by logically inverting the read signal RD.

  The read circuit 41 includes a sense amplifier 81 and transistors T41 to T44. The transistors T41 and T42 are, for example, P channel MOS transistors. The transistors T43 and T44 are, for example, N channel MOS transistors.

  The inverted read signal is supplied to the gate terminals of the transistors T41 and T42. The source terminal of the transistor T41 is connected to the bit line BL0, and the drain terminal of the transistor T41 is connected to the inverting input terminal of the sense amplifier 81 and the drain terminal of the transistor T43. The drain terminal of the transistor T41 is connected to the drain terminal of the transistor T43 and the gate terminal of the transistor T43, and the source terminal of the transistor T43 is connected to the power supply wiring VSS.

  The source terminal of the transistor T42 is connected to the inverted bit line xBL0, and the drain terminal of the transistor T42 is connected to the non-inverting input terminal of the sense amplifier 81 and the drain terminal of the transistor T44. The drain terminal of the transistor T42 is connected to the drain terminal of the transistor T44 and the gate terminal of the transistor T44, and the source terminal of the transistor T44 is connected to the power supply wiring VSS.

  The transistor T41 is turned on / off based on the read signal RD (inverted read signal xRD). The turned-on transistor T41 connects the bit line BL0, the sense amplifier 81, and the transistor T43 to each other. Similarly, the transistor T42 is turned on / off based on the read signal RD (inverted read signal xRD). The turned-on transistor T42 connects the inverted bit line xBL0, the sense amplifier 81, and the transistor T44 to each other. The transistors T41 and T42 are an example of a switch element. Transistors T43 and T44 are examples of load elements. The sense amplifier 81 detects the potential of the inverting input terminal and the potential of the non-inverting input terminal, that is, the potential difference between the bit line BL0 and the inverted bit line xBL0, and outputs the output data DO0 having a level corresponding to the detected potential difference.

Next, an outline of the memory cell will be described with reference to FIGS.
3 and 4 are for explaining the outline of the structure and do not represent the actual size. In the plan view, hatching is given to a part in order to easily distinguish the members. In the cross-sectional view, some hatchings are omitted for easy understanding of the cross-sectional structure of each member. The same applies to the drawings referred to thereafter.

  As shown in FIG. 3, the fuse element EF is formed on the insulator 101 of the semiconductor memory device. The insulator 101 is an insulator for element isolation such as STI (shallow trench isolation).

  The fuse element EF has a wiring part 111 and a first terminal part 112 and a second terminal part 113 connected to both ends of the wiring part 111. The wiring part 111 is formed in a rectangular shape in plan view extending along a predetermined direction (left-right direction in FIG. 3). The first terminal portion 112 and the second terminal portion 113 are formed in a rectangular shape in plan view. In addition, the fuse element EF has a connection part 114 having one end connected to the central part of the wiring part 111 and a third terminal part 115 connected to the tip of the connection part 114. The connection part 114 is formed in a rectangular shape in plan view extending along a direction orthogonal to the wiring part 111. Similar to the first terminal portion 112 and the second terminal portion 113, the third terminal portion 115 is formed in a rectangular shape in plan view.

  As shown in FIG. 4, the fuse element EF includes a polysilicon film 121 and a metal silicide film 122. The metal element contained in the metal silicide film 122 is, for example, cobalt (Co). The metal silicide film 122 is formed by, for example, a salicide process.

  Note that it is desirable that no impurity be added to the polysilicon film 121. Polysilicon to which impurities are not added has a larger resistance value than polysilicon to which impurities are added. As described above, the polysilicon film 121 to which no impurity is added becomes a factor for expanding the circuit margin.

  As shown in FIG. 3, the first terminal portion 112 is connected to the bit line BL <b> 0 formed above the first terminal portion 112 through the contact plug 131. The second terminal portion 113 is connected to an inverted bit line xBL0 formed above the second terminal portion 113 through a contact plug 132. The third terminal portion 115 is connected via a contact plug 133 to a wiring 134 formed in the same wiring layer (metal layer) as the bit line pair BL0, xBL0. The wiring 134 is connected via a contact plug 135 to a word line WL0 formed above the wiring 134. The material of the bit line pair BL0, xBL0, the word line WL0, and the wiring 134 is, for example, copper (Cu). The material of the contact plugs 131, 132, 133, 135 is, for example, tungsten (W).

  The wiring part 111a between the first terminal part 112 and the connection part 114 is electrically the first fuse element F1 shown in FIG. The wiring part 111b between the second terminal part 113 and the connection part 114 is electrically the second fuse element F2 shown in FIG.

Next, the operation of the semiconductor memory device will be described.
[Program operation]
For example, in FIG. 2, “1” input data DI0 is supplied. Then, an H level program signal PRG is supplied. Decoder circuit 60 generates H level control signals SC1, SC3 and L level control signals SC2, SC4 based on input data DI0 and program signal PRG.

  The transistor T21 is turned off in response to the H level control signal SC1, and the transistor T23 is turned on in response to the H level control signal SC3. The transistor T22 is turned on in response to the L level control signal SC2, and the transistor T24 is turned off in response to the L level control signal SC4. As a result, the bridge circuit 70 supplies the write voltage VBL to the inverted bit line xBL0 and supplies the low potential voltage VSS to the bit line BL0.

  The potential difference between the bit line BL0 and the inverted bit line xBL0 generates an electron flow from the node N11 of the bit line BL0 to the node N12 of the inverted bit line xBL0 via the fuse element EF. That is, in FIG. 4, the first terminal portion 112 is a cathode and the second terminal portion 113 is an anode, and an electron flow from the first terminal portion 112 to the second terminal portion 113 through the wiring portion 111 is generated. Due to the electron flow thus generated, the metal material of the metal silicide film 122 moves toward the anode side, that is, toward the second terminal portion 113. As a result, as shown in FIG. 5, the metal element 122 a is unevenly distributed on the second terminal portion 113 side in the wiring portion 111. As a result, the wiring portion 111a between the central region and the first terminal portion 112 becomes a high resistance portion having polysilicon that does not contain a metal element, and the resistance value is higher than that before programming. On the other hand, the wiring part 111b between the central region 111c and the second terminal part 113 contains more metal elements than before programming, and the resistance value is lower than before programming. Such a writing process causes an imbalance between the resistance value of the first fuse element F1 and the resistance value of the second fuse element F2.

  The imbalance of the resistance values of the fuse elements F1 and F2 corresponds to “0” and “1” of the input data DI0. That is, the memory cell MC00 stores the state of the input data DI0 due to an imbalance of the resistance values of the first fuse element F1 and the second fuse element F2 included in the fuse element EF.

  A semiconductor memory device using one fuse element as a memory cell stores the state of input data DI0 by cutting or not cutting that fuse element. The cutting state of one fuse element varies depending on the write voltage supplied to the fuse element, the shape of the fuse element, the variation in the transistors supplying the write voltage to the fuse element, and the like. This variation in the cutting state of one fuse element affects the write margin.

  The memory cell MC00 of this embodiment stores the state of the input data DI0 due to an imbalance of the resistance values of the first fuse element F1 and the second fuse element F2. Therefore, even if the write voltage VBL, the shape of the fuse element EF, and the like vary, the state of the input data DI0 is reliably stored. This reduces the process-dependent parameters for the program operation and reduces the impact on the write margin.

  In addition, when information is stored simultaneously in a plurality of memory cells including one fuse element, the write voltage varies according to the information. For example, when a memory cell whose fuse element is not cut stores information “1”, the fuse element of the memory cell is cut to store information “0”. Therefore, when information is stored in a plurality of memory cells, a voltage drop occurs according to the number of fuse elements to be cut, and the write voltage varies. The fluctuation of the write voltage may cause a defect such as insufficient cutting in the fuse element, which affects the write margin.

  The voltage application circuit 21 of this embodiment supplies the write voltage VBL and the low potential voltage VSS to the bit line pair BL0, xBL0 according to the input data DI0. That is, the voltage application circuit 21 changes the direction of the electron flow generated in the fuse element EF according to the input data DI0. Therefore, when information is simultaneously written to a plurality of memory cells, the variation of the write voltage VBL becomes constant regardless of the state of the input data DI0 to DI3. Therefore, it does not depend on information written to a plurality of memory cells at the same time. This reduces the influence on the write margin and stabilizes the writing of information to a plurality of memory cells.

[Read operation]
For example, in FIG. 2, the transistors T21 to T24 of the bridge circuit 70 are turned off in response to control signals SC1 to SC4 generated based on the L level program signal PRG.

  The transistor T11 of the row decoder 11 is turned on in response to the L-level word line control signal WC0 and supplies the high potential voltage VDD to the word line WL0. The high potential voltage VDD at this time is an example of a read voltage. The transistors T41 and T42 of the read circuit 41 are turned on based on the H level read signal RD, and connect the sense amplifier 81 and the transistors T43 and T44 to the bit line pair BL0 and xBL0.

  Thereby, the potential of the bit line BL0 becomes a value obtained by dividing the potential difference between the potential of the word line WL0 (high potential voltage VDD) and the low potential voltage VSS by the first fuse element F1, the transistor T41, and the transistor T43. Similarly, the potential of the inverted bit line xBL0 is a value obtained by dividing the potential difference between the potential of the word line WL0 (high potential voltage VDD) and the low potential voltage VSS by the second fuse element F2, the transistor T42, and the transistor T44. . Therefore, the potential difference between the bit line pair BL0 and xBL0 is a value corresponding to the resistance value of the first fuse element F1 and the resistance value of the second fuse element F2. The sense amplifier 81 outputs output data DO0 having a level obtained by amplifying the potential difference between the bit line pair BL0 and xBL0.

  A semiconductor memory device using a single fuse element as a memory cell has a power supply voltage based on a resistance value corresponding to the state of the fuse element (cut or uncut) and a resistance value of a transistor connected in series to the fuse element. A divided voltage is generated. By comparing this divided voltage with, for example, a threshold value, output data corresponding to the stored state is output. The divided voltage is affected by the variation in the resistance value of the transistor, such as the disconnection state of the fuse element, the write voltage supplied to the fuse element, the shape of the fuse element, the variation in the transistors supplying the write voltage to the fuse element, etc. receive. These variations affect the difference between the divided voltage and the threshold, that is, the read margin.

  In the read circuit 41 of the present embodiment, the output data DO0 corresponding to the potential difference generated in the bit line pair BL0, xBL0 due to the imbalance of the resistance values of the first fuse element F1 and the second fuse element F2 included in the memory cell MC00. Is output. Therefore, even if the shape of the fuse element EF and the on-resistance value of the transistor vary, it is possible to reliably generate the output data DO0 corresponding to the state of the memory cell MC00. This reduces the process-variable parameters for the read operation and reduces the impact on the read margin.

As described above, according to the present embodiment, the following effects can be obtained.
(1-1) The memory cell MC00 has a fuse element EF connected between the node N11 of the bit line pair BL0 and the node N12 of the inverted bit line xBL0. An intermediate region of fuse element EF is connected to node N13 of word line WL0. Therefore, the fuse element EF is electrically connected to the first fuse element F1 connected between the bit line BL0 and the word line WL0 and the second fuse element EF connected between the inverted bit line xBL0 and the word line WL0. A fuse element F2 is included.

  The fuse element EF includes a polysilicon film 121 and a metal silicide film 122. The voltage application circuit 21 connected to the bit line pair BL0, xBL0 causes an imbalance in the resistance values of the first fuse element F1 and the second fuse element F2. The memory cell MC00 stores the state of the input data DI0 due to an imbalance of resistance values of the first fuse element F1 and the second fuse element F2 included in the fuse element EF. Therefore, even if the write voltage VBL and the shape of the fuse element EF vary, the influence on the write margin can be reduced and the state of the input data DI0 can be reliably stored. That is, malfunctions in the program operation can be reduced.

  (1-2) The transistor T11 of the row decoder 11 is turned on in response to the L-level word line control signal WC0, and supplies the high potential voltage VDD to the word line WL0. The transistors T41 and T42 of the read circuit 41 are turned on based on the H level read signal RD, and connect the sense amplifier 81 and the transistors T43 and T44 to the bit line pair BL0 and xBL0. Therefore, the potential of the bit line BL0 is a value obtained by dividing the potential difference between the potential of the word line WL0 (high potential voltage VDD) and the low potential voltage VSS by the first fuse element F1, the transistor T41, and the transistor T43. The potential of the inverted bit line xBL0 is a value obtained by dividing the potential difference between the potential of the word line WL0 (high potential voltage VDD) and the low potential voltage VSS by the second fuse element F2, the transistor T42, and the transistor T44. The potential difference between the bit line pair BL0 and xBL0 is a value corresponding to the resistance value of the first fuse element F1 and the resistance value of the second fuse element F2, and the sense amplifier 81 has a potential difference between the bit line pair BL0 and xBL0. The output data DO0 of the level obtained by amplifying the signal is output. Therefore, the read circuit 41 detects the potential difference between the bit line pair BL0 and xBL0 and outputs the output data DO0 corresponding to the potential difference. Thereby, even if process variations occur, the influence on the read margin can be reduced, and the output data DO0 corresponding to the state stored in the memory cell MC00 can be generated reliably. That is, malfunctions in the read operation can be reduced.

  (1-3) The voltage application circuit 21 changes the direction of the electron flow generated in the fuse element EF according to the input data DI0. Therefore, when information is simultaneously written to a plurality of memory cells, the variation of the write voltage VBL becomes constant regardless of the state of the input data DI0 to DI3. Therefore, since it does not depend on information written to a plurality of memory cells at the same time, the influence on the write margin can be reduced.

(Second embodiment)
Hereinafter, a second embodiment will be described with reference to the accompanying drawings.
In addition, in this embodiment, the same code | symbol is attached | subjected about the same component as the said embodiment, and the description is abbreviate | omitted.

  As shown in FIG. 6, the row decoder 11a included in the semiconductor memory device of this embodiment includes a transistor T12 connected to the word line WL0. The transistor T12 is, for example, an N channel MOS transistor. The source terminal of the transistor T12 is connected to the power supply wiring VSS, and the drain terminal of the transistor T12 is connected to the word line WL0. The row decoder 11a supplies a word line control signal WA0 to the gate terminal of the transistor T12.

  The row decoder 11a generates the word line control signal WA0 based on the address signal ADR and the program signal PRG. For example, during the program operation, the row decoder 11a selects the word line WL0 based on the address signal ADR, and generates the H-level word line control signal WA0 according to the word line WL0.

  The transistor T12 is turned on in response to the H-level word line control signal WA0 and turned off in response to the L-level word line control signal WA0. The word line WL0 is connected to the power supply line VSS via the transistor T12 that is turned on. Therefore, the node N13 of the word line WL0 to which the third terminal of the fuse element EF included in the memory cell MC00 is connected is at the low potential voltage VSS level during the program operation.

  In the program operation, for example, based on the input data DI0 of “1”, the voltage application circuit 21 connects the bit line BL0 to the power supply line VSS and supplies the write voltage VBL to the inverted bit line xBL0. The word line WL0 is connected to the power supply wiring VSS. Therefore, an electron flow from the word line WL0 to the inverted bit line xBL0 through the second fuse element F2 is generated by the potential difference between the inverted bit line xBL0 and the word line WL0. As shown in FIG. 7, the metal material of the metal silicide film 122 between the central region 111 c and the second terminal portion 113 moves toward the anode side, that is, toward the second terminal portion 113 by the electron flow thus generated. To do. As a result, a high resistance portion 123 not including metal silicide is formed between the central region 111c and the second terminal portion 113, and the resistance value of the wiring portion 111b becomes higher than that before programming. Such a writing process causes an imbalance between the resistance value of the first fuse element F1 and the resistance value of the second fuse element F2.

  An electron flow in a fuse element having a polysilicon film and a metal silicide film may cause aggregation (agglomeration). The occurrence of agglomeration increases the resistance value of the fuse element.

  In the case of the present embodiment, no electron current flows through the metal silicide film 122 between the first terminal portion 112 and the central region 111c in the program operation. Therefore, during the program operation, the resistance value of the wiring portion 111a (first fuse element F1) does not change. That is, in the present embodiment, in the pair of fuse elements F1 and F2 connected between the bit line pair BL0 and xBL0, the resistance value of the other fuse element F2 is changed without changing the resistance value of the one fuse element F1. Can be changed.

As described above, according to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.
(2-1) The row decoder 11a supplies the low potential voltage VSS to the word line WL0 during the program operation based on the address signal ADR and the program signal PRG. The voltage application circuit 21 supplies the write voltage VBL and the low potential voltage VSS to the bit line pair BL0, xBL0 according to the input data DI0. Accordingly, an electron flow is generated in the fuse element between the bit line to which the write voltage VBL is supplied and the word line WL0, and the resistance value is changed by the electron flow. On the other hand, since the electron current does not flow through the fuse element between the bit line to which the low potential voltage VSS is supplied and the word line WL0, the resistance value does not change. Therefore, in the pair of fuse elements F1 and F2 connected between the bit line pair BL0 and xBL0, the resistance value of the other fuse element F2 is changed without changing the resistance value of the one fuse element F1, thereby efficiently. The resistance value can be imbalanced.

In addition, you may implement each said embodiment in the following aspects.
-The number of memory cells may be changed as appropriate. For example, the number of memory cells may be one.

The metal material of the metal silicide film 122 may be, for example, nickel (Ni), titanium (Ti), or tungsten.
-The material of the word lines WL0 to WL3 may be aluminum. Similarly, the material of the bit line pairs BL0, xBL0 to BL3, xBL3 may be aluminum.

  A barrier metal may be provided on the contact plugs 131 to 133, 135. Examples of the barrier metal include titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), and tantalum nitride (TaN).

The insulator 101 may be an interlayer insulating film formed between wiring layers, LOCOS (local oxidation of silicon).
In the readout circuit 41, the transistors T43 and T44 may be resistance elements.

In the read operation, the voltage supplied to the word line WL0 may be changed as appropriate.
-You may change the conductivity type of each transistor suitably. It goes without saying that the logic of each signal is changed in accordance with the change in conductivity type.

DESCRIPTION OF SYMBOLS 11 Row decoder 21 Voltage application circuit 41 Read-out circuit EF Fuse element F1, F2 Fuse element MC00 Memory cell (memory cell)
WL0 Word line BL0, xBL0 Bit line pair N11 to N13 Node DI0 Input data DO0 Output data PRG Program signal RD Read signal VBL Write voltage VSS Low potential voltage VDD High potential voltage

Claims (10)

A memory cell including a pair of fuse elements connected in series between a first node and a second node;
Based on a program signal and input data, a write voltage is applied to one of the first node and the second node, and one of the first node and the second node is applied to the other. A first voltage application circuit for applying a second voltage lower than the write voltage;
A second voltage application circuit for applying a read voltage to a third node connected between the pair of fuse elements based on a read signal;
A read circuit that outputs output data according to a voltage difference between the first node and the second node based on the read signal;
A semiconductor device comprising: The first voltage application circuit includes:
A decoder circuit for generating a control signal based on the program signal and the input data;
A bridge including a plurality of switch elements to which the control signal is supplied, and applying the write voltage and the second voltage to the first node and the second node by turning on and off the plurality of switch elements. Circuit,
The semiconductor device according to claim 1, comprising: The readout circuit includes:
A pair of load elements;
A pair of switch elements for contacting and separating the pair of load elements with respect to the first node and the second node based on a read signal;
A sense amplifier that compares the potential of a node between the pair of switch elements and the pair of load elements to generate the output data;
The semiconductor device according to claim 1, further comprising:   4. The semiconductor device according to claim 1, further comprising a third voltage application circuit that applies the second voltage to the third node based on the program signal. 5. . The memory cell includes a linear wiring portion, a first terminal and a second terminal connected to both ends of the wiring portion, a connection portion having one end connected to a central region of the wiring portion, and Including a fuse element having a third terminal connected to the tip;
One of the pair of fuse elements is the wiring portion between the first terminal and the central region,
The other of the pair of fuse elements is the wiring portion between the second terminal and the central region,
The semiconductor device according to claim 1, wherein:   6. The semiconductor device according to claim 5, wherein the wiring part includes a polysilicon film and a metal silicide film containing a metal element. Multiple word lines,
A plurality of bit line pairs intersecting the plurality of word lines;
A memory cell connected to the word line and the bit line pair, including a pair of fuse elements connected in series between the pair of bit lines, and between the pair of fuse elements connected to the word line When,
Each of the plurality of bit line pairs is provided with a write voltage applied to any one bit line of the bit line pair based on a program signal and input data, and either bit of the bit line pair. A plurality of voltage application circuits for applying a second voltage lower than the write voltage to the line;
A row decoder that selects one word line from a plurality of word lines based on an address signal and applies a read voltage to the selected one word line based on a read signal;
A plurality of read circuits provided in each of the plurality of bit line pairs and outputting output data corresponding to a voltage difference between the bit line pairs based on the read signal;
A semiconductor memory device comprising:   8. The semiconductor memory device according to claim 7, wherein the row decoder applies the second voltage to the selected one word line based on the program signal. A method for controlling a semiconductor device having a memory cell, comprising:
The memory cell includes a pair of fuse elements connected in series between a first node and a second node,
Based on a program signal and input data, a write voltage is applied to one of the first node and the second node, and one of the first node and the second node is applied to the other. Applying a second voltage lower than the write voltage;
Based on a read signal, a read voltage is applied to a third node connected between the pair of fuse elements, and an output corresponding to a voltage difference between the first node and the second node Outputting data,
A method for controlling a semiconductor device.   The method for controlling a semiconductor device according to claim 9, wherein the second voltage is applied to the third node based on the program signal.