JP2014153935A - Parallel distributed processing control device, parallel distributed processing control system, parallel distributed processing control method, and parallel distributed processing control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate parallel distributed processing efficiently using I/O performance of a disk.SOLUTION: A parallel distributed processing control device includes a division unit, an allocation unit, and an integration unit. The division unit divides a received task into the number of subtasks according to the number of operation parts. The allocation unit assigns the subtasks to the operation parts. The integration unit integrates a processing result of parallel execution of the subtasks in the operation parts in which the subtasks are assigned.

Description

  The present invention relates to a parallel distributed processing control device, a parallel distributed processing control system, a parallel distributed processing control method, and a parallel distributed processing control program.

  Conventionally, in order to process a large amount of data at high speed, a technique is known in which data is distributed and allocated to a plurality of information processing apparatuses, and processing is executed in parallel in the plurality of information processing apparatuses. For example, as one of large-scale distributed processing technologies, a technology for efficiently processing data by distributing a large amount of data (big data) such as Web crawl data and access logs to a large number of commodity servers is known. ing.

  Among them, a technology widely used as a decentralization framework is MapReduce, proposed by Google. MapReduce provides a framework that allows a large amount of data to be distributed over a computer cluster using a simple programming model. Hadoop (registered trademark) is one of the open source software implementations of MapReduce. At the heart of Hadoop is MapReduce, a framework that distributes large amounts of data and enables parallel processing, and HDFS (Hadoop Distributed File System), a distributed file system that enables access to high-throughput application data. Registered trademark)).

  In MapReduce, parallel distributed processing is realized by describing two functions called Map and Reduce. First, the data to be processed is divided and assigned to each Map task. The Map task processes the assigned data and generates a Key-Value pair that is a combination of Key and Value. Then, the data collected for each key is passed to the Reduce task. In the Reduce task, processing is performed for each key and the result is output.

Jeffrey Dean and Sanjay Ghemawat, MapReduce: Simplified Data Processing on Large Clusters, Proceedings of the 6th Symposium on Operating Systems Design and Implementation (OSDI '04), December 6-8, 2004 Hiroyuki Yamada, Kazuo Aida, Yuu Kitsuregawa, “Experimental Study on I / O Performance Evaluation of Parallel Data Intensive Processing Platform”, 4th Forum on Data Engineering and Information Management (DEIM 2012), D6-4, 2012 3 Moon Matei Zaharia, Mosharaf Chowdhury, Tathagata Das, Ankur Dave, Justin Ma, Murphy McCauley, Michael J. Franklin, Scott Shenker, Ion Stoica, Resilient Distributed Datasets: A Fault-Tolerant Abstraction for In-Memory Cluster Computing, Technical Report No. UCB / EECS-2011-82, July 19, 2011

  However, conventionally, the entire processing of each Map task has been executed as a single process and a single thread. Each Map task includes, for example, a series of processes such as data loading from a disk (storage device), deserialization of loaded data, generation of key-value pairs, and sorting by key. When these are executed as a single thread, the processing speed is limited by the performance of the CPU (Central Processing Unit) to be executed.

  Also, when processing is distributed and multiple Map tasks are executed simultaneously in parallel to process a large amount of data in a short time, the number of Map tasks executed in parallel is the core of the CPU such as the server that performs the processing. Performance improvement by increasing the degree of parallelism to only a few is expected. For this reason, performance improvement by parallel processing is restricted by the number and performance of CPUs mounted on the server. Conventionally, it is known that the load on the CPU is large due to data deserialization when loading data.

  As described above, in the conventional technology, the CPU performance becomes a bottleneck, and the I / O performance of the disk cannot be fully utilized. In other words, even if there is a margin in the disk I / O performance, the amount of processing is restricted by the CPU performance, and the disk I / O performance cannot be fully utilized.

  Conventionally, since the I / O performance of a magnetic hard disk drive (HDD) used for distributed processing is lower than the processing performance of a CPU, the above-mentioned problem is not remarkable. However, when a disk with high I / O performance such as SSD (Solid State Drive) is replaced with HDD, the above-mentioned problem becomes remarkable.

  An embodiment of the disclosure has been made in view of the above, and a parallel distributed processing control apparatus capable of realizing high speed parallel distributed processing by efficiently using disk I / O performance. An object is to provide a distributed processing control system, a parallel distributed processing control method, and a parallel distributed processing control program.

  In order to solve the above-described problems and achieve the object, the embodiment according to the present invention divides the received task into a number of subtasks corresponding to the number of arithmetic units, assigns the subtasks to the arithmetic units, The processing units obtained by executing the subtasks in parallel in the arithmetic unit to which are assigned are integrated.

  A parallel distributed processing control apparatus, a parallel distributed processing control system, a parallel distributed processing control method, and a parallel distributed processing control program according to an embodiment of the present invention efficiently use disk I / O performance. There is an effect that high speed can be realized.

FIG. 1 is a diagram illustrating an example of a configuration of a parallel and distributed processing control apparatus according to the first embodiment. FIG. 2 is a flowchart illustrating an example of a processing flow in the parallel and distributed processing control apparatus according to the first embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a parallel distributed processing control system according to the second embodiment. FIG. 4 is a flowchart showing an example of the flow of MapReduce processing in the parallel distributed processing control system according to the second embodiment. FIG. 5 is a diagram illustrating an example of the configuration of the slave and the accelerator according to the second embodiment. FIG. 6 is a diagram illustrating an example of the flow of a Map task execution process in the second embodiment. FIG. 7 is a diagram for explaining subtask execution processing in the accelerator according to the second embodiment. FIG. 8 is a flowchart illustrating an example of the processing flow of the Map subtask according to the second embodiment. FIG. 9 is a flowchart illustrating an example of a process flow of the merge sort subtask according to the second embodiment. FIG. 10 is a diagram for explaining the processing of the Map task in the parallel and distributed processing control system according to the third embodiment. FIG. 11 is a diagram for explaining a transfer mode of data to be processed in the third embodiment. FIG. 12 is a diagram illustrating that information processing by the parallel distributed processing control program, which is a program for executing a series of processes in the parallel distributed processing control system, is specifically realized using a computer.

  Hereinafter, embodiments of a parallel distributed processing control device, a parallel distributed processing control system, a parallel distributed processing control method, and a parallel distributed processing control program according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Moreover, each embodiment can be combined suitably.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a configuration of a parallel and distributed processing control apparatus according to the first embodiment. With reference to FIG. 1, an example of the configuration of the parallel distributed processing control apparatus according to the first embodiment will be described.

[Example of Configuration of Parallel Distributed Processing Control Device 10]
The parallel distributed processing control device 10 illustrated in FIG. 1 includes a control unit 110, a storage unit 120, an accelerator 130, and a storage device (disk) 140.

  The control unit 110 controls processing in the parallel distributed processing control device 10. The control unit 110 includes a task division unit 111, a subtask assignment unit 112, a subtask activation unit 113, and an integration unit 114.

  The task dividing unit 111 divides a task assigned to the parallel distributed processing control device 10 into subtasks. For example, the task dividing unit 111 divides a task into a number of subtasks depending on the number of arithmetic units (for example, a core such as a CPU) included in an accelerator 130 (described later). The task division unit 111 divides the task so that the number of blocks of processing target data in each subtask is substantially equal.

  The subtask assignment unit 112 assigns the subtask obtained by the division in the task division unit 111 to the arithmetic unit included in the accelerator 130.

  The subtask activation unit 113 activates the subtask obtained by the division by the task division unit 111 in the arithmetic unit to which the subtask allocation unit 112 has assigned the subtask.

  When the execution of all the subtasks activated by the subtask activation unit 113 is completed, the integration unit 114 integrates the execution results stored in the storage unit 120 and generates output data.

  The storage unit 120 stores result data obtained as a result of the execution of the subtask in the accelerator 130. The result data stored in the storage unit 120 is integrated by the integration unit 114 when all the subtasks are completed, and output data is generated. The output data is stored in the storage device 140. The execution result of each subtask stored in the storage unit 120 may be in a partially integrated state in which a part of the integration process is executed in each arithmetic unit.

  The accelerator 130 is a processor having a plurality of arithmetic units. As the accelerator 130, for example, a many-core processor on which a large number of CPUs are mounted, a reconfigurable FPGA (Field-programmable gate array), or the like can be used. In FIG. 1, the accelerator 130 is illustrated as being disposed inside the parallel distributed processing control device 10. In practice, a many-core processor board may be connected to an existing server via a PCI bus, such as adding a many-core processor to an existing server.

  The storage device 140 stores data to be processed by the parallel distributed processing control device 10 and data generated as a result of the processing. The storage device 140 is, for example, a hard disk drive (HDD) or a solid state drive (SDD).

[Flow of Processing in Parallel Distributed Processing Control Device 10]
FIG. 2 is a flowchart illustrating an example of a processing flow in the parallel distributed processing control apparatus 10 according to the first embodiment. First, the parallel distributed processing control device 10 receives a task execution request (step S201). Then, the task dividing unit 111 divides the task into a plurality of subtasks (step S202). The subtask assignment unit 112 assigns each of the divided subtasks to the calculation unit of the accelerator 130 (step S203). And the subtask starting part 113 starts a subtask in the calculating part to which the subtask was allocated (step S204). The arithmetic units that have started up the subtask each execute the subtask in parallel, and send the processing result to the storage unit 120 for storage (step S205). When the processing in all the arithmetic units is completed, the integration unit 114 integrates the processing results stored in the storage unit 120 to generate output data (step S206). The output data generated by the integration unit 114 is stored in the storage device 140 (step S207). Thereby, the process in the parallel distributed processing control device 10 is completed.

[Effect of the first embodiment]
As described above, the parallel distributed processing control device 10 according to the first embodiment includes a dividing unit that divides an accepted task into a number of subtasks corresponding to the number of arithmetic units, an assigning unit that allocates subtasks to arithmetic units, and a subtask. And an integration unit that integrates the processing results obtained by executing the subtasks in parallel in the operation unit to which is assigned. For this reason, even when the amount of processing by one task is large or when the processing capability of the arithmetic unit to which the task is assigned is low, the processing can be divided into subtasks and executed in parallel by a plurality of arithmetic units. For this reason, it is possible to increase the speed of parallel distributed processing by efficiently using the I / O performance of the storage device without being affected by the restriction of the processing capability of the arithmetic unit. In addition, since the processing is executed in parallel using the operation unit of the accelerator, the accelerator can be connected and expanded by a PCI bus or the like as necessary, and the processing speed can be flexibly increased.

  The parallel distributed processing control device 10 can be applied as a server constituting a distributed file system, for example.

(Second Embodiment)
Next, as a second embodiment, an example of performing parallel processing of Map subtasks in a server that executes MapReduce in a Hadoop environment will be described.

  In the conventional MapReduce, each Map task executes the entire process up to “loading data from disk, generating key-value pairs, sorting output files”.

  In contrast, in the second embodiment, data loading from the disk, data deserialization, key-value pair generation, and output file sorting are first divided into two processes in MapReduce Map processing. That is, it is divided into two processes: “data loading from disk, data deserialization, generation of key-value pair, part of sorting” and sorting of the output file (whole). Then, the processing of the former “data loading from disk, data deserialization, generation of key-value pairs, part of sorting” is executed in parallel, thereby speeding up the processing.

[Example of configuration of parallel distributed processing control system 1]
An example of the parallel distributed processing control system according to the second embodiment will be described with reference to FIG. FIG. 3 is a diagram illustrating an example of a configuration of the parallel distributed processing control system 1 according to the second embodiment. As shown in FIG. 3, the parallel distributed processing control system 1 includes a master 100, slaves 200A to 200G (hereinafter collectively referred to as slave 200), and accelerators 300A to 300G (hereinafter also collectively referred to as accelerator 300). . The parallel distributed processing control system 1 includes storage devices 400A to 400H (hereinafter, collectively referred to as a storage device 400).

  Each of master 100 and slaves 200A to 200G is an information processing apparatus such as a commodity server. The master 100 and slaves 200A to 200G are connected to each other via a network and transmit / receive data to / from each other. The slaves 200A to 200G are connected to the accelerators 300A to 300G, respectively, by a PCI bus or the like. The master 100 and the slaves 200A to 200G are connected to the storage device 400H and the storage devices 400A to 400G, respectively, and store data in the subordinate storage devices.

  Although FIG. 3 shows one master, seven slaves, and seven accelerators, these numbers are not limited to 1, 7, and 7, respectively. You may comprise a master and a slave by ten or more servers. Furthermore, the process control system 1 may be constructed across a plurality of data centers to form an intercloud system.

  The parallel distributed processing control system 1 is a distributed file system that stores data distributed to a plurality of nodes. In this distributed file system, data to be written is divided into blocks and stored in storage devices 400A to 400H under the servers (master 100 and slaves 200A to 200G). Further, in order to ensure redundancy for one block, for example, three identical blocks are stored in the storage device 400 under a plurality of different servers (master 100 and slaves 200A to 200G). Information on the data storage location is managed by the master 100. When executing MapReduce, data is read from the storage device 400 storing the data, and Map tasks are executed in parallel on a plurality of servers. The execution results are integrated in the server that executes the Reduce task, and a final output file is generated.

  For example, the master 100 operates as a job tracker and a name node. The job tracker accepts job input and divides it into a plurality of tasks, and assigns the divided tasks to nodes. The name node manages HDFS. The name node distributes write target data to each node and manages information such as the position of a file (data block) stored in each node.

  Each of the slaves 200A to 200G operates as a task tracker and a data node. The task tracker manages the execution of tasks assigned to the job tracker. The data node reads the data distributed from the name node from the designated location and stores it.

[Example of MapReduce process flow]
Next, an example of the flow of MapReduce processing will be described with reference to FIG. FIG. 4 is a flowchart showing an example of the flow of MapReduce processing in the parallel distributed processing control system 1 according to the second embodiment.

  First, the master 100 receives a job (step S401). That is, the master 100 accepts designation of data to be subjected to MapReduce processing. Next, the master 100 divides the received job into a plurality of Map tasks for parallel execution (step S402). That is, the master 100 assigns processing target data to each Map task. The data assigned to one Map task is also called input split below. Then, the master 100 selects the slave 200 that executes each Map task, and assigns the Map task to the selected slave 200 (step S403).

  In assigning a Map task, the master 100 assigns to each slave 200 a Map task whose processing target is data stored in the storage device 400 (local disk) under the slave. However, the master 100 may assign a Map task for processing data stored in a storage device under another slave. In that case, the slave reads the processing target data from the corresponding storage device via the network, and executes the processing.

  The slave 200 to which the Map task is assigned executes the Map task (Step S404). Then, the execution result of the Map task is passed to the slave that executes the Reduce task. Like the Map task, the Reduce task is assigned to a predetermined slave 200 by the master 100.

  The slave assigned the Reduce task executes the Reduce task (step S405). Then, the slave outputs the execution result as an output file (step S406). This completes the MapReduce process.

  Next, the Map task process (step S404 in FIG. 4) in the second embodiment will be described. In the second embodiment, the Map task assigned to the slave 200 is further divided into a plurality of Map subtasks. Then, the slave 200 assigns a plurality of Map subtasks to a plurality of processing units (described later) provided in the accelerator 300 and executes them in parallel. First, the configuration of the slave 200 and the accelerator 300 will be described.

[Example of configuration of slave 200]
FIG. 5 is a diagram illustrating an example of the configuration of the slave 200A and the accelerator 300A according to the second embodiment. In FIG. 5, a configuration of the slave 200A is shown as an example of a configuration common to the slaves 200A to 200G. Further, the configuration of the accelerator 300A is shown as an example of a configuration common to the accelerators 300A to 300G. As illustrated in FIG. 5, the slave 200 </ b> A includes a control unit 210, a storage unit 220, and a communication unit 230.

  The control unit 210 controls processing in the slave 200A. The control unit 210 is, for example, a CPU mounted on a commodity server. The control unit 210 includes a task division unit 211, a subtask assignment unit 212, a subtask activation unit 213, and an integration unit 214.

  The task division unit 211 divides the Map task activated in the slave 200A into a plurality of Map subtasks. The task division unit 211 generates a number of Map subtasks that is at least one less than the number of cores of the accelerator 300A. In addition, the task division unit 211 generates a Map subtask so that the number of processing target blocks allocated to each core is equal.

  Here, the reason why the number of subtasks is set to be smaller than the number of cores of the accelerator 300A is to cause at least one core to execute a merge sort subtask that integrates the results of the Map subtask.

  The subtask assignment unit 212 determines a core that executes the subtask generated by the task division unit 211. That is, the subtask assignment unit 212 determines the core to which the Map subtask and the merge sort subtask are assigned.

  The subtask activation unit 213 activates the subtask so that the subtask generated by the task division unit 211 is executed in the core determined by the subtask allocation unit 212.

  The integration unit 214 reads and copies the key-value pair generated by the execution of the subtask in the accelerator 300A and stored in the storage unit 220. Furthermore, the integration unit 214 sorts the copied key-value pairs for each key. The integration unit 214 stores the sorted result in the storage device 400A. Thereafter, the stored result is read by the slave to which the Reduce task is assigned.

  Storage unit 220 temporarily stores the execution result of the subtask in accelerator 300A.

  The communication unit 230 is an interface that transmits and receives data and the like between the slave 200A, the master 100, and the slaves 200B to 200G. For example, the communication unit 230 transmits data generated by the processing of the control unit 210 to the master 100.

[Example of configuration of accelerator 300A]
The accelerator 300A is a processing unit that executes a subtask obtained by dividing the Map task activated in the slave 200A. The accelerator 300A is configured by, for example, a substrate on which a many-core processor including a large number of CPUs (cores), a reconfigurable FPGA, and the like are mounted. In FIG. 5, the accelerator 300A is shown as a many-core processor having ten cores C1 to C10.

  The accelerator 300A includes local buffers LB1 to LB10 and a global buffer GB (see FIG. 5). Local buffers LB1 to LB10 are allocated to the cores C1 to C10, respectively. The global buffer GB stores the processing results of a plurality of cores in an integrated manner.

  Here, it is assumed that the accelerator 300A is an apparatus including a larger number of CPUs (cores) than the number of CPUs (cores) included in the slave 200A. For example, a many-core processor of Tilera (registered trademark) or Intel (registered trademark) Xeon Phi can be employed. Also, it is possible to implement the Map subtask by using FPGA as hardware.

[Example of Map task execution process in slave 200A]
With reference to FIG. 6, the Map task execution process (step S404 in FIG. 4) in the slave 200A will be described. FIG. 6 is a diagram illustrating an example of the flow of a Map task execution process in the second embodiment.

  First, a Map task is assigned to the slave 200A, and the Map task is activated (step S601). The task dividing unit 211 of the slave 200A divides the Map task into a Map subtask and a merge sort subtask (Step S602). Then, the subtask assignment unit 212 determines the core of the accelerator 300A to which the Map subtask and the merge sort subtask are assigned (Step S603). Then, the subtask activation unit 213 activates the subtask in the core to which the Map subtask and the merge sort subtask are assigned, and causes the subtask to be executed (step S604). The integration unit 214 integrates the processing results of the subtasks (Step S605). That is, the integration unit 214 copies the processing results and sorts the processing results for each key. The sorted processing results are stored in the storage device 400 (step S606).

[Flow of subtask execution process in accelerator 300A]
Next, the flow of the subtask execution process (step S604 in FIG. 6) in the accelerator 300A to which the subtask is assigned will be described. FIG. 7 is a diagram for explaining subtask execution processing in the accelerator 300A according to the second embodiment. FIG. 8 is a flowchart illustrating an example of the processing flow of the Map subtask according to the second embodiment. FIG. 9 is a flowchart illustrating an example of a process flow of the merge sort subtask according to the second embodiment. An example of subtask execution processing in the accelerator 300A will be described with reference to FIGS.

  First, a subtask is activated in each core of the accelerator 300A (step S801). When the subtask is activated, the core to which the Map subtask is assigned (described here as the core C1) reads the target data of the Map subtask (step S802). For example, in the example of FIG. 7, one Map task is divided into four Map subtasks and a merge sort subtask, and the four blocks of data B1 to B4 that have been processed by the Map task are each processed by the Map subtask. It is targeted. The core C1 reads the block B1. In the second embodiment, each core reads the processing target block directly from the storage device 400A without using the slave 200A.

  Then, the core C1 deserializes the read block B1 (step S803, ★ in FIG. 7). Next, the core C1 extracts the data of the read block B1 one record at a time, and generates a key-value pair (step S804). The generated key-value pair is stored in the local buffer LB1 assigned to the core C1.

  Next, the core C1 determines whether or not the local buffer LB1 is full (step S805). When it is determined that the local buffer LB1 is not full (No at Step S805), the core C1 determines whether or not all records have been processed (Step S806). If it is determined that all the records have not been processed (No at Step S806), the core C1 reads the next record (Step S807) and returns to Step S804.

  On the other hand, if it is determined in step S805 that the local buffer LB1 is full (step S805, affirmative) and if it is determined in step S806 that all the records have been processed (step S806, affirmative), step The process proceeds to S808. In step S808, the core C1 sorts the key-value pairs in the area LB1 based on the key, and sends the result to the global buffer GB for storage (step S809). Then, the core C1 determines whether or not all the records have been processed (step S810). If it is determined that all the records have not been processed (No at Step S810), the core C1 returns to Step S807. On the other hand, if it is determined that all the records have been processed (Yes at step S810), the core C1 passes the processing to the core (here, core C10) to which the merge sort subtask is assigned (step S811). This completes the processing of the Map subtask in the core C1.

  During the execution of the Map subtask in the core C1, the other cores C2 to C4 (see FIG. 7) to which the Map subtask is assigned also execute the processes of Steps S801 to S811 in parallel.

  While the Map subtask is being executed in the cores C1 to C4, the core C10 is executing the merge sort subtask (see FIG. 7). That is, as shown in FIG. 9, the core C10 determines whether or not the global buffer GB is full every predetermined time (step S901). When it is determined that the global buffer GB is not full (No at Step S901), the core C10 determines whether or not a notification that the Map subtask has been completed is received from all the cores C1 to C4 (Step S902). . If it is determined that it has not been received from all the cores C1 to C4 (No at Step S902), the core C10 waits for a predetermined time (Step S903), and then returns to Step S901.

  When it is determined that the global buffer GB is full (Yes at Step S901) and when it is determined that the completion notification is received from all the cores C1 to C4 (Yes at Step S902), the core C10 proceeds to Step S904. In step S904, the core C10 integrates the information of the key-value pairs accumulated in the global buffer GB and sorts based on the key (step S904). The core C10 transmits the sorted information to the slave 200 to which the Map subtask is assigned (Step S905). This completes the process.

  The subtask processes shown in FIGS. 8 and 9 are executed in the accelerator 300A as shown in FIG. The information generated by the core C10 of the accelerator 300A is transmitted to the slave 200A.

  In this way, key-value pair data (output result) is sent from the core C10 to the slave 200A each time the global buffer GB becomes full. The integration unit 214 of the slave 200A further integrates the plurality of output results transmitted and accumulated in this manner based on the key, and generates a final map task output file (see FIG. 7).

[Effects of Second Embodiment]
As described above, the parallel distributed processing control system 1 according to the second embodiment includes a plurality of information processing apparatuses and an accelerator having a plurality of cores. One information processing apparatus among the plurality of information processing apparatuses includes a division unit that divides the Map task into a number of subtasks corresponding to the number of cores included in the accelerator. One information processing apparatus includes an assigning unit that assigns subtasks to a plurality of accelerator cores, and an integration unit that integrates the processing results of the subtasks. The accelerator executes subtasks in parallel in a plurality of cores. For this reason, parallel distributed processing can be speeded up by efficiently using the I / O performance of the storage device without being affected by the restriction of the processing capability of the core. In addition, since the processing is performed in parallel using the core provided in the accelerator, it is possible to connect and increase the accelerator by a PCI bus or the like as necessary, so that the processing speed can be flexibly increased.

(Third embodiment)
In the second embodiment, the example in which the core of the accelerator 300A directly accesses the storage device 400A that stores the processing target data and acquires the data has been described. In the third embodiment, the processing target data is once read into the storage unit 220 of the slave 200A in which the Map task is activated. Then, the data is further transferred from the storage unit 220 of the slave 200A to the memory on the accelerator 300A. Thereafter, the core executing the subtask reads out necessary data from the memory on the accelerator 300A and executes the processing. In other respects, the configuration and function of the parallel distributed processing control system 2 of the third embodiment are the same as those of the parallel distributed processing control system 1 of the second embodiment.

  FIG. 10 is a diagram for explaining map task processing in the parallel distributed processing control system 2 according to the third embodiment. With reference to FIG. 10, an example of the processing of the Map task in the third embodiment will be described.

  First, the Map task is activated in the slave 200A (step S1001). Then, the slave 200A reads the input split that is the processing target of the Map task from the storage device 300A, and transfers it to the accelerator 300A via the storage unit 220. That is, reading from the storage device 300A to the storage unit 220 and sending to the accelerator 300A are repeated (step S1002). At this time, direct memory access (DMA) is used for data transfer.

  Next, the task dividing unit 211 of the slave 200A divides the Map task into a number of subtasks according to the processing content and the number of cores on the accelerator 300A (step S1003). Then, the subtask assignment unit 212 determines the core to which the subtask is assigned (Step S1004). At this time, the subtask assignment unit 212 determines the assignment destination of the merge sort subtask together with the assignment destination of the Map subtask obtained by dividing the Map task.

  Then, the subtask activation unit 213 activates the corresponding subtask at the allocation destination determined by the subtask allocation unit 212 (step S1005). Each core in which the subtask is activated accesses the memory on the accelerator 300A, reads the processing data for the subtask, and executes the subtask (step S1006). That is, data deserialization, generation of key-value pairs, sorting based on keys, and the like are executed. Thereafter, when all subtasks are completed, the slave 200A integrates the processing results and stores the results in the storage device 400A (step S1007).

  As described above, in the third embodiment, the core on the accelerator 300A does not directly read the processing target data from the storage device 400A under the slave 200A, but reads the data from the memory on the accelerator 300A. FIG. 11 is a diagram for explaining a transfer mode of data to be processed in the third embodiment. As shown in FIG. 11, the processing target data stored in the storage device 400A is transferred to the storage unit 220 on the slave 200A. At this time, transfer is performed by direct memory access. Further, the processing target data is transferred from the storage unit 220 on the slave 200A to the memory on the accelerator 300A. Transfer is also performed by direct memory access. Thereafter, when each core executes the Map subtask, data is read from the memory on the accelerator 300A and loaded to execute deserialization, generation of a key-value pair, and the like.

[Effect of the third embodiment]
As described above, in the third embodiment, the processing target data is once transferred to the storage unit 220 on the slave 200A and then transferred to the accelerator 300A, and each core reads the target data from the memory on the accelerator 300A for processing. Execute. Therefore, the processing target data can be handled as the file system of the own device from the slave 200A to which the Map task is assigned. Therefore, the processing operation by the administrator is facilitated.

  The second and third embodiments have been described on the premise of a distributed file system operating in a Hadoop environment. However, the system is not limited to Hadoop as long as it is a system using MapReduce, and can be applied to other frameworks. can do.

(Fourth embodiment)
Although the embodiments of the present invention have been described so far, the present invention may be implemented in other embodiments besides the above-described embodiments. Other embodiments will be described below.

[System configuration]
Also, among the processes described in this embodiment, all or part of the processes described as being performed automatically can be performed manually, or the processes described as being performed manually can be performed. All or a part can be automatically performed by a known method. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.

  Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. That is, the specific form of distribution / integration of each device is not limited to the one shown in the figure, and all or a part of the distribution / integration may be functionally or physically distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, in the example shown in FIG. 5, the task division unit 211 and the subtask allocation unit 212 are arranged in the slave 200A. However, the information processing apparatus integrates a plurality of slave task division units and subtask allocation units by separating them. May be arranged so that the information processing apparatus manages allocation of functions in the accelerator.

[program]
FIG. 12 is a diagram showing that information processing by the parallel distributed processing control program, which is a program for executing a series of processes in the parallel distributed processing control systems 1 and 2, is specifically realized using a computer. As illustrated in FIG. 12, the computer 3000 includes, for example, a memory 3010, a CPU (Central Processing Unit) 3020, a hard disk drive 3080, and a network interface 3070. Each part of the computer 3000 is connected by a bus 5100.

  The memory 3010 includes a ROM 3011 and a RAM 3012 as illustrated in FIG. The ROM 3011 stores a boot program such as BIOS (Basic Input Output System).

  Here, as illustrated in FIG. 12, the hard disk drive 3080 stores, for example, an OS 3081, an application program 3082, a program module 3083, and program data 3084. In other words, the parallel distributed processing control program according to the disclosed technique is stored in, for example, the hard disk drive 3080 as the program module 3083 in which instructions executed by the computer are described. For example, the hard disk drive 3080 stores a program module 3083 in which the control unit included in the master 100, the control unit 210 included in the slave 200A, and the procedures for executing the same information processing as each unit of the cores C1 to C10 are described.

  Further, data used for information processing by the parallel distributed processing control program, such as data stored in the storage unit 220, the local buffer LB, and the global buffer GB, is stored as program data 3084, for example, in the hard disk drive 3080. The CPU 3020 reads the program module 3083 and program data 3084 stored in the hard disk drive 3080 to the RAM 3012 as necessary, and executes various procedures.

  Note that the program module 3083 and the program data 3084 related to the parallel distributed processing control program are not limited to being stored in the hard disk drive 3080. For example, the program module 3083 and the program data 3084 may be stored in a removable storage medium. In this case, the CPU 3020 reads data via a removable storage medium such as a disk drive. Similarly, the program module 3083 and the program data 3084 may be stored in another computer connected via a network (LAN (Local Area Network), WAN (Wide Area Network), etc.). In this case, the CPU 3020 reads various data by accessing another computer via the network interface 3070.

[Others]
The parallel distributed processing control program described in this embodiment can be distributed via a network such as the Internet. The parallel distributed processing control program may be recorded on a computer-readable recording medium such as a hard disk, a flexible disk (FD), a CD-ROM, an MO, or a DVD, and executed by being read from the recording medium by the computer. it can.

DESCRIPTION OF SYMBOLS 1 Parallel distributed processing control system 10 Parallel distributed processing control apparatus 100 Master 110 Control part 111 Task division part 112 Subtask allocation part 113 Subtask starting part 114 Integration part 120 Storage part 130 Accelerator 140 Storage apparatus 200A-200G Slave 210 Control part 211 Task division Unit 212 Subtask allocation unit 213 Subtask activation unit 214 Integration unit 220 Storage unit 230 Communication unit 300 Accelerator 400 Storage device C1 to C10 Core GB Global buffer LB1 to LB10 Local buffer

Claims (8)

A division unit that divides the received task into a number of subtasks according to the number of arithmetic units;
An assigning unit for assigning the subtask to the computing unit;
An integration unit that integrates processing results obtained by executing the subtasks in parallel in the calculation unit to which the subtasks are assigned;
A parallel distributed processing control device. A parallel distributed processing control system comprising a plurality of information processing devices and an accelerator having a plurality of cores,
One information processing apparatus among the plurality of information processing apparatuses is:
A division unit that divides the Map task into a number of subtasks according to the number of cores included in the accelerator;
An assigning unit that assigns the subtask to a plurality of cores of the accelerator;
An integration unit for integrating the processing results of the subtasks by the core;
With
The parallel distributed processing control system, wherein the accelerator executes the subtasks in parallel in the plurality of cores.   The plurality of cores of the accelerator each read a data block that is a processing target of an assigned subtask directly from a storage device that stores the data block under an information processing device. Parallel distributed processing control system.   Each of the plurality of cores of the accelerator sends a data block to be processed by the assigned subtask from a storage device under the information processing apparatus that stores the data block to a memory on the accelerator via the memory of the information processing apparatus. The parallel distributed processing control system according to claim 2, wherein the subtask is executed by reading from the memory on the accelerator after being transferred to the accelerator.   The plurality of cores of the accelerator have a storage area allocated to each of the accelerators, and when the storage area is filled with a key-value pair generated by execution of the subtask, the accelerator is stored in the storage area. 5. The parallel distributed processing control according to claim 2, wherein the key-value pairs are sorted based on the key, and the sorting result is stored in a global buffer on the accelerator. 6. system. The dividing unit divides a part of processing among loading of data blocks to be processed, deserialization of loaded data, generation of key-value pairs and sorting of key-value pairs into the subtasks,
6. The parallel distributed processing control according to claim 2, wherein the allocating unit allocates the processing target blocks of the subtasks allocated to each of the plurality of cores of the accelerator so as to be substantially equal. 6. system. A parallel distributed processing control method executed by a parallel distributed processing control system including a plurality of information processing devices and an accelerator including a plurality of cores,
A division step of dividing a Map task into a number of subtasks according to the number of cores included in the accelerator by one information processing device among the plurality of information processing devices;
An assigning step of assigning the subtask to a plurality of cores of the accelerator by the one information processing apparatus;
An execution step of executing the subtasks in parallel by a plurality of cores of the accelerator;
An integration step of integrating the processing results of the subtasks by the one information processing apparatus;
A parallel distributed processing control method comprising: On the computer,
A division step of dividing the Map task into a number of subtasks according to the number of cores included in the accelerator;
Assigning the subtasks to a plurality of cores of the accelerator;
An execution step of causing the plurality of cores of the accelerator to execute the subtasks in parallel;
An integration step of integrating the processing results of the subtasks by the core;
Parallel distributed processing control program to execute.

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