JP2014146366A - Multi-core processor system, and control method and control program of multi-core processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the processing capability of a multi-core processor by enhancing the utilization efficiency of a cache even when parallel processing and multitask processing are executed.SOLUTION: In the case that each CPU simultaneously executes processing with the same priority set therein executable in parallel as in a left multi-core processor system 100, a scheduler 110 preferentially arranges shared data of processing of a high priority in a memory area having a high access speed first. On the other hand, in the case that each CPU simultaneously executes processing having a different priority executable in parallel as in a right multi-core processor system 100, the scheduler 110 arranges shared data of processing set to a high priority in the same manner as the left multi-core processor system 100. After that, the scheduler 110 arranges shared data of a task #2 and a task #3 set to a low priority in the rest memory.

Description

  The present invention relates to a multicore processor system, a control method for a multicore processor system, and a control program when performing multitask processing by parallel processing using a plurality of cores.

  Conventionally, a hierarchical memory configuration such as a cache memory, a main memory, and a file system has been adopted as a memory area for storing data used by a processor during processing execution. The hierarchical memory configuration is expected to increase the system speed in order to improve the access speed to data. In the case of a hierarchical memory configuration, a cache memory that operates at a higher speed than other memories has a limited memory capacity. Therefore, data stored in the cache memory is an algorithm such as LRU (Least Recently Used). Is used for replacement (see, for example, Patent Document 1 below).

  In recent years, multi-core processor systems having a plurality of processors have been widely adopted. Since the multi-core processor system causes tasks to be executed in parallel by each processor, the processing performance can be greatly improved (see, for example, Patent Document 1 below). On the other hand, in a multi-core processor system, when tasks are executed in parallel, when data in the cache memory of each processor is rewritten, processing for synchronizing data in the cache memory of other processors is required.

  Specifically, a data synchronization method includes a snoop cache mechanism that is a mechanism for achieving cache coherency between processors. The snoop cache mechanism operates when data on a cache memory that is shared by one processor with another processor is rewritten. Rewriting of data on the cache memory is detected by a snoop controller mounted on the cache memory of another processor. Then, the snoop controller reflects the rewritten new value in the cache memory of another processor via the bus between the cache memories (see, for example, Patent Document 2 below).

  Further, even in an embedded system, parallel execution of a plurality of applications is required, and a technique for realizing parallel execution is provided. Specifically, multitask processing that switches tasks executed on one processor by time division, distributed processing that executes a plurality of tasks on a plurality of processors, and processing that combines these processing are disclosed. (For example, refer to Patent Document 3 below.)

JP-A-6-175923 JP-A-10-240698 JP-A-11-212869

  However, in the case of a multi-core processor system, synchronization processing between cache memories and frequent rewriting of cache memory that occurs when multitask processing is executed, which are necessary when executing parallel tasks by multiple processors, cause performance degradation. Sometimes it was.

  FIG. 20 is an explanatory diagram illustrating an example of snoop operation in multi-core parallel processing. In the case of the multi-core processor system 2000, in the multi-core (for example, CPU # 0, CPU # 1 as shown in FIG. 20), parallel processing in which each CPU executes processing simultaneously is performed. In parallel processing, particularly when a task using common data is executed on each CPU at the same time, data in one cache memory (for example, one of the cache L1 $ 0 and the cache L1 $ 1) is rewritten. Then, the synchronization process is performed by the snoop 120. Specifically, when the value of the variable a in the data arranged in the cache L1 $ 0 is rewritten by the CPU # 0, the snoop 120 transfers the data of the variable a in the cache L1 $ 1 via the bus. rewrite.

  If data rewriting by the snoop 120 frequently occurs, the bus connecting the cache L1 $ 0 and the cache L1 $ 1 is congested, resulting in performance degradation. Furthermore, bus transactions increase due to frequent rewrite processing. Further, frequent rewrite processing occupies the snoop 120 bus. If an execution request for another process with a real-time constraint occurs in such a state, access to the cache memory of another process with a real-time constraint may be hindered, which may cause a serious performance problem. It was.

  FIG. 21 is an explanatory diagram of an example of cache rewriting in multitask processing. When the multi-core processor system 2000 performs multi-task processing, a task switch that switches a task to be executed is performed according to the task execution status. For example, in FIG. 21, the multi-core processor system 2000 performs multi-task processing for task # 0 to task # 2.

  Then, as shown in the left side of FIG. 21, it is assumed that a task switch occurs in a state where task # 0 is executed by CPU # 0 and task # 2 is executed by CPU # 1. When a task switch occurs, the task executed by CPU # 0 is switched from task # 0 to task # 1 as shown on the right side of FIG. When the task to be executed is switched, the content of the data arranged in the cache L1 $ 0 is also rewritten from the data used by the task # 0 to the data used by the task # 1.

  After the data arranged in the cache L1 $ 0 is rewritten, when returning to the execution of the process executed before the rewriting, the CPU # 0 needs to read the data used by the task # 0 from the memory 140 again. is there. For example, even if the data placed in the target cache memory is rewritten due to the occurrence of a task switch, the data placed in the cache memory by the CPU is not often used thereafter. In this way, the rewriting process of data having no reusability has a problem that it causes performance degradation for the CPU using the cache memory.

  In order to solve the above-described problems caused by the prior art, the disclosed technology improves the processing efficiency of the multi-core processor system by improving the use efficiency of the cache even when parallel processing and multi-task processing are executed. An object of the present invention is to provide a multicore processor system, a control method for the multicore processor system, and a control program.

  In order to solve the above-described problem and achieve the object, the disclosed technology includes a plurality of cores that respectively process tasks, and a plurality of caches that respectively store data that is accessed when the plurality of cores process tasks. A first core of the plurality of cores, the priority of the task assigned to any one of the plurality of cores is equal to or higher than a predetermined value. Before executing the process, the data is stored in a cache corresponding to the core to which the task is assigned.

  According to the control method and control program of the multi-core processor system and the multi-core processor system, even when parallel processing and multi-task processing are executed, the use efficiency of the cache is improved and the processing capability of the multi-core processor system is improved. There is an effect that can be.

It is explanatory drawing which shows an example of the scheduling process concerning this Embodiment. It is explanatory drawing which shows an example of a hierarchical memory structure. It is explanatory drawing which shows an example of a multitask process. It is explanatory drawing which shows the procedure (the 1) of normal cache coherency. It is explanatory drawing which shows the procedure (the 2) of normal cache coherency. It is explanatory drawing which shows the procedure (the 3) of normal cache coherency. It is explanatory drawing which shows the procedure (the 4) of normal cache coherency. It is explanatory drawing which shows the procedure of the cache coherency in a low priority parallel task. It is a block diagram which shows the functional structure of a scheduler. It is a flowchart which shows the procedure of arrangement | positioning processing of shared data. It is a flowchart which shows the procedure of a task table creation process. It is a data table which shows the example of a data structure of a task table. It is a data table which shows the example of a setting of a task table. It is a flowchart which shows the procedure (the 1) of a task execution process. It is a flowchart which shows the procedure (the 2) of a task execution process. It is a flowchart which shows the procedure (the 3) of a task execution process. It is a flowchart which shows the procedure (the 4) of a task execution process. It is explanatory drawing which shows the example of execution of the parallel task of the same priority. It is explanatory drawing which shows the execution example of the parallel task from which a priority differs. It is explanatory drawing which shows the operation example of the snoop in the multi-core parallel processing. It is explanatory drawing which shows the example of cache rewriting in multitask processing.

  Exemplary embodiments of a multicore processor system, a control method of the multicore processor system, and a control program according to the present invention will be explained below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram illustrating an example of a scheduling process according to the present embodiment. In the present embodiment, a plurality of processes can be executed in parallel by a plurality of processors provided in the multi-core processor system 100. Therefore, in the multi-core processor system 100, it is possible to extract processing groups (for example, parallel tasks) that can be executed in parallel from applications and perform efficient parallel processing.

  Also, in this embodiment, by setting the priority related to the execution order to the processing to be executed as high priority and low priority, data with high reusability is selected and placed in the cache memory. be able to. The priority is set based on the frequency of accessing the data once stored in the cache memory when the process is executed and the deadline time. The setting contents of the priority of each task are stored in the task table 111. In FIG. 1 and subsequent figures, blocks representing high priority tasks are displayed larger than blocks representing low priority tasks.

  Therefore, the scheduler 110 of the multi-core processor system 100 refers to the priority set for the processes to be executed in parallel, and each accesses data (hereinafter referred to as “shared data”) when executing each process. Place it in the optimal memory area. Further, the scheduler 110 selects what method is used as cache coherency for synchronizing shared data according to priority when the same shared data is arranged in a plurality of cache memories.

  Specifically, as in the left multi-core processor system 100, when the CPUs simultaneously execute parallel executable processes with the same priority set, the scheduler 110 stores the shared data of the high priority processes. Arrange preferentially from the memory area with fast access speed. For example, the shared data of tasks # 0, 1 and tasks # 3, 4 that can be set in parallel with high priority are arranged in a memory area with a high access speed in order from the cache L1 $. Then, the shared data of task # 2 and task # 5 set to the low priority is arranged in the remaining memory after the shared data of the high priority processing is arranged.

  On the other hand, when the CPUs simultaneously execute processes that can be executed in parallel with different priorities as in the right multi-core processor system 100, the scheduler 110 increases the priority as in the left multi-core processor system 100. The shared data of the set process is arranged in the cache L1 $. After that, the scheduler 110 arranges shared data of task # 2 and task # 3 set to low priority in the remaining memory.

  In the case of the left multi-core processor system 100, the scheduler 110 performs cache coherency at the timing when a new value is written in a normal cache memory. On the other hand, in the case of the multi-core processor system 100 on the right side, the scheduler 110 does not reflect the writing of a new value from the CPU after a new value is written in a certain cache memory (for example, the cache L1 $ 0). Cache coherency is performed at the timing when reading into the memory (cache L1 $ 1) occurs.

  As described above, the multi-core processor system 100 according to the present embodiment preferentially arranges shared data that is frequently used in a cache memory having a high access speed, so that the processing speed can be improved. In addition, for the shared data of the process set to the low priority, the synchronization process by the cache coherency is postponed until an access request from the CPU is generated. Therefore, it is possible to avoid an operation that causes a decrease in processing performance, such as writing shared data having no reusability to the cache memory. The detailed configuration and processing procedure of the multi-core processor system 100 according to this embodiment will be described below.

(Hierarchical memory configuration)
FIG. 2 is an explanatory diagram illustrating an example of a hierarchical memory configuration. As illustrated in FIG. 2, the multi-core processor system 100 according to the present embodiment includes a plurality of types of memory areas. Since each memory area has a different access speed and memory capacity from the processor, data corresponding to each application is stored.

  As shown in FIG. 2, each processor (CPU # 0, CPU # 1) of the multi-core processor system 100 includes a cache L1 $ (cache memory installed in each processor) and a cache L2 $ (cache installed in the snoop 120). Four types of memory areas are prepared: a memory), a memory 140, and a file system 150.

  The higher the memory area closer to each processor, the faster the access speed and the smaller the memory capacity. On the other hand, the lower the memory area that is farther connected to each processor, the slower the access speed and the larger the memory capacity. Therefore, in the multi-core processor system 100, as described with reference to FIG. 1, shared data used by a task to be preferentially processed or shared data that is frequently used is arranged in a higher-level memory.

(Multitask processing)
FIG. 3 is an explanatory diagram illustrating an example of multitask processing. Multitask processing in the multicore processor system 100 according to the present embodiment means processing in which a plurality of tasks are executed in parallel by a plurality of processors.

  For example, in FIG. 3, task # 0 to task # 5 are prepared as tasks to be executed by the multi-core processor system 100. Then, under the control of the scheduler 110, the CPU # 0 and the CPU # 1 each execute the dispatched task. The scheduler 110 causes each task to be executed in parallel while appropriately switching a task to be executed from among a plurality of tasks by time slicing or the like.

(Cash coherency)
Next, a procedure of cache coherency executed by the snoop 120 of the multi-core processor system 100 according to the present embodiment will be described. As described with reference to FIG. 1, the snoop 120 is set to either a normal cache coherency or a cache coherency in a low priority parallel task in accordance with an instruction from the scheduler 110.

<Normal cache coherency (update at write)>
4 to 7 are explanatory diagrams showing a normal cache coherency procedure. In the multi-core processor system 100 illustrated in FIG. 4, the cache memory (cache L1 $ 0 and cache L1 $ 1) of the CPU # 0 and CPU # 1 that execute parallel tasks is based on the description 400 of the task to be executed. The latest data is stored.

  Thereafter, as shown in FIG. 5, it is assumed that one CPU of the multi-core processor system 100 rewrites the contents of the variable a in the description 400. For example, in FIG. 5, the value of the variable a of the cache L1 $ 0 is rewritten by the CPU # 0. Then, the variable a of the cache L1 $ 1 in which the same data is stored becomes old data, and even the same variable a has a different value.

  Therefore, in the case of normal cache coherency, the value of the variable a of the cache L1 $ 1 in which old data is stored is first purged based on the description 400 as shown in FIG.

  Thereafter, as shown in FIG. 7, the value of the variable a in the cache L1 $ 0 is stored as the value of the variable a in the cache L1 $ 1 via the bus of the snoop 120. As described above, in the case of normal cache coherency, consistency between the cache L1 $ 0 and the cache L1 $ 1 is maintained by performing the processing illustrated in FIGS.

<Cache coherency in low-priority parallel tasks (update during read)>
FIG. 8 is an explanatory diagram showing a procedure of cache coherency in a low priority parallel task. FIG. 8 shows a coherency procedure when the multi-core processor system 100 executes a parallel task set to a low priority.

  First, in the multi-core processor system 100, CPU # 0 and CPU # 1 execute parallel tasks, and the same data is arranged in the cache L1 $ 0 and the cache L1 $ 1 (step S801).

  Thereafter, when the CPU # 0 of the multi-core processor system 100 rewrites the contents of the variable a (step S802), the variable a of the cache L1 $ 1 is purged (step S803). In this way, even in the case of cache coherency in a low priority parallel task, the same procedure as normal cache coherency is performed until rewriting of the variable a stored in the cache memory is detected and old data is purged. Is called.

  Thereafter, when the process of accessing the variable a is executed by the CPU # 1 of the multi-core processor system 100, the snoop 120 changes the value of the latest variable a stored in the cache L1 $ 0 via the bus. Store in the cache L1 $ 1 (step S804).

  As described above, in the cache coherency in the low priority parallel task, the snoop 120 controls when the access request to the variable a of the cache L1 $ 1 in which the latest rewrite content is not reflected by the CPU # 1 is generated. And coherence is taken. Therefore, redundant bus transactions such as normal cache coherency can be avoided.

  As described above, in normal cache coherency, the operation starts at the timing when the variable a is updated. On the other hand, in the cache coherency in the low priority parallel task, after the CPU # 0 updates the variable a of the cache L1 $ 0, the operation starts only when the CPU # 1 issues a read request to the variable a. To do. Specifically, the snoop 120 reads the value of the variable a in the cache L1 $ 0 where the latest variable a is arranged, and arranges the read value as the variable a in the cache L1 $ 1.

  In step S804 illustrated in FIG. 8, data to be accessed by the CPU # 0 is arranged in the cache L1 $ 0. However, depending on the task executed by the cache L1 $ 0, the data is stored in another memory area. In some cases, the data being accessed is the target of access. For example, it is assumed that CPU # 0 accesses data arranged in the cache L2 $, the memory 140, and the file system 150. In such a case, the snoop 120 can read out the target data from each data area and place it in the cache memory L1 $.

  The functional configuration and operation contents of the scheduler 110 of the multi-core processor system 100 that implements the scheduling processing according to the present embodiment shown in FIG. 1 will be described below.

(Functional configuration of scheduler)
FIG. 9 is a block diagram showing a functional configuration of the scheduler. In FIG. 9, the multi-core 901 includes n CPUs (Central Processing Units) and controls the entire multi-core processor system 100. The multi-core 901 is a processor or a group of processors on which a plurality of cores are mounted. If a plurality of cores are mounted, a single processor having a plurality of cores may be used, or a processor group in which single core processors are arranged in parallel may be used. In the present embodiment, in order to simplify the explanation, a processor group in which single-core processors are arranged in parallel will be described as an example.

  The scheduler 110 includes a determination unit 1001, a first arrangement unit 1002, a second arrangement unit 1003, a third arrangement unit 1004, a specifying unit 1005, an extraction unit 1006, and an allocation unit 1007. It is. Specifically, the determination unit 1001 to the allocation unit 1007 specify, for example, a program stored in another memory 1008 of the multi-core processor system 100 (a memory other than a cache memory installed in the CPU) in the multi-core 901. The function is realized by causing the CPU to execute the function.

  The determination unit 1001 has a function of determining whether or not the priority set for a process to be executed (hereinafter referred to as “execution target process”) is equal to or higher than a threshold value in the multi-core processor system 100. Specifically, the determination unit 1001 determines whether the priority of the execution target process assigned to each processor in the processing group assigned to each processor (CPU # 0 to CPU #n) of the multi-core processor system 100 and executed. Judge whether or not it is greater than or equal to the value. The determination result by the determination unit 1001 is temporarily stored in a storage area such as another memory 1008.

  The priority is set based on the operation result obtained by the simulation of the execution target process. For example, the deadline of each execution target process may be compared, and the execution target process having a shorter time to the deadline may be set to have a higher priority. The scheduler 110 according to the present embodiment ends the processing once the shared data of the execution target process set with a high priority is placed in a memory (cache L1 $ or cache L2 $) having a high access speed. Keep locked until Therefore, an execution target process with a high priority is executed with higher priority than other execution target processes.

  In addition, referring to the operation result, the execution target process having a larger number of updates of the shared data arranged in the cache memory may be set to have a higher priority. Since the scheduler 110 according to the present embodiment preferentially places shared data with high reusability in the cache memory (cache L1 $) of each processor, the utilization efficiency of the cache memory can be maintained at a high value. .

  In addition, the threshold value that is a determination criterion in the determination unit 1001 can be adjusted. If the priority set for each execution target process is equal to or higher than the threshold value, the determination unit 1001 sets the execution target process with a high priority, and the set priority level does not satisfy the threshold value. For example, the execution target process has a low priority. Therefore, an optimal value can be set according to the application to be executed. In addition, an arbitrary unit such as a task, a process, or a thread can be selected as the unit of the execution target process. In the present embodiment, as an example, a task is described as a unit of execution target processing.

  The first arrangement unit 1002 has a function of arranging data in a cache memory mounted on each CPU in accordance with the determination result of the determination unit 1001. Specifically, the first arrangement unit 1002 is a shared data that is accessed by the determination unit 1001 during execution of a high-priority execution target process that is determined to have a priority level equal to or higher than a threshold among the execution target processes. Are placed in the cache memory of the target CPU.

  For example, when task A, which is a high-priority execution target process, is executed by CPU # 1 in multi-core 901, shared data accessed by task A at the time of execution is cache memory 1 by first arrangement unit 1002. Placed in. Similarly, when task B, which is a high-priority execution target process, is executed by CPU # 0 in multi-core 901, shared data accessed by task B at the time of execution is cached by first allocation unit 1002. 0.

  Depending on the application 1000, the determination unit 1001 may determine that there is no high priority execution target process in the execution target process. In such a case, if the cache memory is left empty, the utilization efficiency of the cache memory is lowered. Therefore, the first arrangement unit 1002 arranges shared data in the cache memory mounted on each CPU even for processes other than the high priority execution target process (for example, the low priority execution target process described later). To do. Thereafter, when a high priority execution target process appears, the first placement unit 1002 preferentially places the shared data of the high priority process in the cache memory of the target CPU.

  Further, as described above, when the first placement unit 1002 places the shared data of the high priority execution target process in the cache memory of the target processor, the execution of the high priority execution target process ends. Until this is done, overwriting of the shared data can be prohibited (locked). Therefore, the first arrangement unit 1002 can prevent the shared data of the high priority execution target process from being overwritten by non-reusable data.

  The second arrangement unit 1003 has a function of arranging data in another memory 1008 having an access speed slower than the cache memory of each processor in accordance with the determination result of the determination unit 1001. Specifically, the second arrangement unit 1003 transfers the shared data accessed by the low priority execution target process, which is determined by the determination unit 1001 as not having a priority equal to or higher than the threshold, to the other memory 1008. Deploy.

  As described with reference to FIG. 2, the memory 1008 other than the cache memory is provided with a plurality of types of memories hierarchically according to the access speed and the memory capacity. Therefore, the second arrangement unit 1003 sequentially stores data for a capacity that can be arranged in the order of high access speed memories. For example, in the case of FIG. 9, data is arranged in the order of cache L2 $ → memory 140 → file system 150. In addition, as for data, data having a high update frequency specified from a prior simulation is preferentially arranged in a memory having a high access speed.

  The third placement unit 1004 has a function of placing shared data requested to be accessed from the multi-core 901 in a cache memory mounted on the requesting CPU. Specifically, the third placement unit 1004 stores the memory 1008 in the memory 1008 when an access request to the shared data placed in the memory 1008 occurs in any of the CPUs (for example, CPU # 1) in the multi-core 901. The arranged shared data is arranged in the cache memory 1 of the CPU # 1.

  The identifying unit 1005 identifies the capacity of the rewritable area in the cache memory of each CPU of the multi-core 901 when the determining unit 1001 determines whether the priority of the execution target process is equal to or higher than the threshold value. Has the function of The rewritable area means an overwritable area.

  Therefore, the area where the shared data of the executed process is arranged and the area where the shared data of the low priority process is arranged can be overwritten, and thus are specified as a rewritable area. The identification result by the identification unit 1005 is temporarily stored in a storage area such as another memory 1008.

  In addition, the first arrangement unit 1002 can adjust the arrangement process according to the capacity of the rewritable area specified by the specifying unit 1005. For example, when the capacity of the rewritable area is smaller than the capacity of the shared data accessed during execution of the high priority execution target process, the first placement unit 1002 cannot place all the shared data in the cache memory. Therefore, the first arrangement unit 1002 arranges the shared data in a capacity that can be arranged in the cache memory in the order of data with the highest update frequency. Then, the second arrangement unit 1003 arranges the shared data that could not be arranged in the cache memory in another memory 1008 area.

  On the other hand, the capacity of the rewritable area may be larger than the capacity of the shared data accessed by the high priority execution target process at the time of execution. In such a case, the first placement unit 1002 first places the shared data, which is accessed at the time of execution by the high priority execution target process, in the cache memory as usual. Thereafter, the first arrangement unit 1002 arranges the shared data accessed at the time of execution of the low priority execution target process in the free capacity in the cache memory in the order of the data with the highest update frequency.

  The extraction unit 1006 has a function of extracting a process that satisfies a specific condition from the execution target processes included in the application 1000. Specifically, the extraction unit 1006 extracts a process (for example, a parallel task) that has common data to be accessed during execution from the execution target processes. Whether or not the data to be accessed at the time of execution is common refers to the identifier of the shared data set in each execution target process (for example, the shared data ID described in FIG. 13 described later). The extraction result by the extraction unit 1006 is temporarily stored in a storage area such as the memory 1008.

  The allocation unit 1007 has a function of allocating execution target processing to each CPU of the multi-core 901. If there is no instruction from the scheduler 110, the allocating unit 1007 allocates each execution target process to the optimum CPU based on the dependency and execution order set in advance and the current processing load of each CPU. .

  Further, when there is a process extracted by the extraction unit 1006, the allocation unit 1007 allocates each process extracted as a process with common shared data to the same CPU in the multi-core 901. Further, the assigning unit 1007 may assign a process with the same priority among the processes extracted by the extracting unit 1006 to the same CPU (for example, CPU # 1) in the multi-core 901. it can.

  Below, the case where the multi-core processor system 100 performs the parallel task which comprises the application 100 in parallel by each CPU as an example of an execution object process is demonstrated.

(Shared data placement process)
FIG. 10 is a flowchart showing a procedure of shared data arrangement processing. The flowchart of FIG. 10 represents a procedure for determining in which cache memory (cache L1 $ or cache L2 $) the shared data is to be placed. By executing each process of FIG. 10, the shared data used when executing each task can be arranged in an appropriate cache memory corresponding to the contents of the cache coherency process.

  In FIG. 10, tasks to be executed are sequentially input to the scheduler 110. Therefore, the scheduler 110 first determines whether or not the task to be executed is a high priority task (step S1001). If it is determined in step S1001 that the task to be executed is a high priority task (step S1001: Yes), the scheduler 110 determines that the total shared data size of the task to be executed is larger than the cache L1 $ size. It is determined whether or not it is smaller (step S1002).

  If it is determined in step S1002 that the total shared data size is smaller than the cache L1 $ size (step S1002: Yes), the scheduler 110 places all shared data in L1 $ (step S1003), and a series of End the process. That is, in step S1003, the scheduler 110 accesses all shared data if the task to be executed is a high priority task and all shared data of the task to be executed can be stored in the CPU cache memory. Place in the fast cache L1 $.

  If it is determined in step S1002 that the total shared data size is not smaller than the cache L1 $ size (step S1002: No), the scheduler 110 cannot place all the shared data in the cache L1 $. Therefore, the scheduler 110 arranges the shared data of the task to be executed in the caches L1 $ and L2 $ in the order of update frequency (step S1004). That is, in step S1004, the scheduler 110 arranges the shared data in the cache L1 $ in order from the data with the highest update frequency, and when the cache L1 $ runs out of capacity, the update frequency of the remaining shared data is subsequently updated. Arrange in the cache L2 $ in order from the highest data.

  The processing in steps S1002 to S1004 described above represents a procedure in the case of arranging shared data of high priority tasks. On the other hand, shared data of tasks other than high priority tasks (low priority tasks) is arranged in an empty area of the cache L1 $ for data with a high update frequency.

  If it is determined in step S1001 that the task to be executed is not a high-priority task (step S1001: No), the scheduler 110 performs arrangement processing on data with high update frequency among the shared data. First, the scheduler 110 determines whether or not the shared data size of the update frequency among the shared data of the task to be executed is smaller than the unlocked cache L1 $ size (step S1005). The unlocked cache L1 $ size means the capacity of an area other than the lock area in which shared data of other execution target tasks is already arranged among all areas of the cache L1 $.

  When it is determined in step S1005 that the size of all shared data with a high update frequency is smaller than the size of the unlocked cache L1 $ (step S1005: Yes), the scheduler 110 stores all shared data with a high update frequency in the cache L1 $. Judge that it can be placed in. Therefore, the scheduler 110 places shared data with a high update frequency in the cache L1 $ (step S1006), and ends a series of processing.

  On the other hand, if it is determined that the size of all shared data with high update frequency is not smaller than the size of the unlocked cache L1 $ (step S1005: No), the scheduler 110 stores all shared data with high update frequency in the cache L1 $. Can not be placed. Therefore, the scheduler 110 arranges frequently updated data among the shared data of the task to be executed in order in the caches L1 $ and L2 $ (step S1007). That is, similarly to step S1004, the scheduler 110 arranges the shared data in the cache L1 $ in order from the data with the highest update frequency. When the capacity of the cache L1 $ is exhausted, the scheduler 110 subsequently arranges the remaining shared data in the cache L2 $ in order from the data with the highest update frequency.

  As described above, in the case of shared data of low priority tasks, the scheduler 110 efficiently arranges shared data of low priority tasks in a memory area where shared data of high priority tasks is not arranged. Can do. Even if it is arranged in a memory area with a high access speed (for example, cache L1 $), unlike the case where the shared data of the high priority task is arranged, the shared data of the low priority task is not locked. It is possible to prevent a situation that disturbs the processing of the priority task.

(Task table creation process)
FIG. 11 is a flowchart showing a procedure of task table creation processing. The flowchart of FIG. 11 represents a procedure for performing a simulation of a task that constitutes an application to be executed by the multi-core processor system 100 and creating a task table 111 that represents the priority of the task based on the simulation result. By executing each process of FIG. 11, the scheduler 110 can create a task table 111 necessary for appropriately arranging the shared data of each task.

  In FIG. 11, the scheduler 110 first analyzes each data size in each task to be executed (step S1101). Subsequently, the scheduler 110 performs deadline analysis of each task (step S1102). Furthermore, the scheduler 110 performs data dependency analysis between tasks (step S1103). Through steps S1101 to S1103 described above, the scheduler 110 can acquire data necessary for specifying the configuration of each task. The data acquired in steps S1101 to S1103 is stored in the task table 111, and is used for simulation for setting priorities described later.

  Subsequently, the scheduler 110 determines whether or not an unsimulated parallel task exists in each task (step S1104). If it is determined in step S1104 that an unsimulated parallel task exists (step S1104: Yes), the scheduler 110 executes a simulation of any one of the unsimulated parallel tasks (step S1105).

  After that, the scheduler 110 measures the update frequency of data with dependency analysis (step S1106), and determines whether the update frequency of data with dependency relationship is larger than a threshold value (step S1107). Step S1107 is processing for determining whether or not priority setting is necessary.

  In step S1107, when the update frequency of the dependent data is larger than the threshold (step S1107: Yes), the scheduler 110 sets the priority based on the deadline stored in the task table 111 ( Step S1108). On the other hand, if the update frequency of the dependent data is not greater than the threshold value (step S1107: No), the scheduler 110 does not determine the priority because the update frequency is low even once stored in the cache. Then, the process proceeds to step S1109.

  Next, the scheduler 110 sets the parallel task being processed as a simulated task (step S1109), returns to the process of step S1104, and determines whether there is an unsimulated parallel task.

  As long as it is determined in step S1104 that an unsimulated parallel task exists, the scheduler 110 repeats the simulation by the processing in steps S1105 to S1109 and sets the priority of the parallel task. If it is determined in step S1104 that there are no unsimulated parallel tasks (step S1104: No), the scheduler 110 ends the series of processes because the simulation of all parallel tasks is completed.

  As described above, the scheduler 110 can create the task table 111 by executing each process of FIG. The task table creation process described above is executed mainly by the scheduler 110, but may be executed in advance by another compiler or simulator as the execution subject.

  For example, the analysis in steps S1101 to S1103 can be executed by a general compiler. In addition, the simulation in step S1105 using the analysis results in steps S1101 to S1103 can also be executed by a known simulator that estimates the execution time and the number of updates when each task is executed (see, for example, JP 2000-276381 A). .)

  FIG. 12 is a data table showing an example of the data structure of the task table. FIG. 13 is a data table showing a setting example of the task table. A data table 1200 in FIG. 12 represents an example of the data structure of the task table 111 created by the task table creation process described in FIG.

  The task table 111 includes the following information group field representing task information and the following information group field representing shared data information, like the data table 1200 of FIG. In the task table 111, a value with a blank value such as a task name, a task ID, and a deadline is input with a different value for each task. In addition, in the fields such as the priority and the coherence mode that are binary values such as ◯ / ×, any one of the binary values is input.

<Task information>
-Task name: (task name)
Task ID: (task identifier)
-Deadline: (analysis result of step S1102)
Priority: high / low (set contents in step S1108)
・ Coherence mode: Update at Write / Update at read ・ Fork to other CPU: Permit / Disallow

<Shared data information>
-Shared data name: (Data name)
-Shared data ID: (Data ID)
Update count: (measurement result of step S1106)
Cache level to be arranged: L1 (cache L1 $) / L2 (cache L2 $)
Data size: (analysis result of step S1101)

  Among the above task information, the coherence mode, the fork to other CPUs, and the cache level to be arranged are determined at the time of task execution. Specifically, the coherence mode and the fork to another CPU are determined by a task execution process described with reference to FIGS. The cache level to be arranged is determined by the shared data arrangement process described with reference to FIG. FIG. 13 illustrates a data table 1200 in which specific numerical values of the task table 111 are set.

(Task execution process)
14 to 17 are flowcharts showing the procedure of the task execution process. 14 to 17 show procedures when the scheduler 110 causes each processor to execute a parallel task to be executed. By executing each process of FIGS. 14 to 17, the parallel task to be executed is based on the coherence method according to the priority set in the task table 111 and the priority of other parallel tasks being executed. Executed.

  In FIG. 14, the scheduler 110 first determines whether or not a state transition has occurred in the task to be executed (step S1401). The state transition in step S1401 means “task generation”, “task end”, and “task switch”. Therefore, if it is determined in step S1401 that a state transition has occurred, the scheduler 110 further determines which of the above three types has been reached.

  In step S1401, the scheduler 110 is in a standby state until a state transition occurs (step S1401: No loop). If it is determined in step S1401 that task generation has occurred in the state transition (step S1401: Yes task generation), the scheduler 110 determines whether the task to be executed is a parallel task (step S1402).

  If it is determined in step S1402 that the task to be executed is a parallel task (step S1402: Yes), the scheduler 110 determines whether or not the newly generated parallel task is a master thread (step S1403). . The master thread is a thread that is preferentially executed.

  If it is determined in step S1403 that the newly generated parallel task is a master thread (step S1403: Yes), the scheduler 110 further determines whether or not the newly generated parallel task is a high priority task. Is determined (step S1404). In step S1404, whether or not the task is a high priority task can be determined with reference to the task table 111.

  If it is determined in step S1404 that the newly generated parallel task is a high priority task (step S1404: Yes), the scheduler 110 further determines whether or not the CPU is executing the high priority task. Determination is made (step S1405).

  If it is determined in step S1405 that the high priority task is being executed (step S1405: Yes), the scheduler 110 performs a preparation process for moving the execution target task to execution. That is, the scheduler 110 migrates (executes data migration) the parallel task being executed to the CPU having the smallest load among the CPUs that are executing the parallel threads, and forks the new thread to other CPUs (newly) Copy generation of a thread) is prohibited (step S1406).

  Further, in step S1406, the scheduler 110 locks the cache area in which the shared data of the migrated task is placed (step S1407). Then, the scheduler 110 sequentially executes the migrated task (step S1408), prohibits the forking of the thread to another CPU in the newly generated parallel task, and assigns it to the CPU with the smallest load (step S1409).

  After that, the scheduler 110 locks the cache area where the newly generated shared data of the parallel task is arranged, and starts executing the task (step S1410). When the process of step S1410 ends, the scheduler 110 returns to the process of step S1401 and enters a standby state until a new state transition occurs.

  If it is determined in step S1403 that the newly generated parallel task is not a master thread (step S1403: No), the scheduler 110 determines whether or not thread forking is prohibited (step S1411). ). In step S1403, the thread that is the determination criterion is a thread that constitutes a newly generated task.

  If it is determined in step S1403 that the forking of the newly generated task thread is prohibited (step S1411: Yes), the scheduler 110 sets the newly generated task to the CPU on which the master thread is executed. Queue to the same CPU (step S1412). The task queued by the process of step S1412 is executed by the queuing destination CPU after the currently executing task is completed. When the process of step S1412 ends, the scheduler 110 returns to the process of step S1401 and enters a standby state until a new state transition occurs.

  Further, the scheduler 110 determines that the newly generated task is not a parallel task (step S1402: No), or determines that thread forking is not prohibited (step S1411: No). The task is queued to the CPU with the smallest load (step S1413). The task queued in step S1413 is a task determined to be newly generated in step S1401. When the process of step S1413 ends, the scheduler 110 returns to the process of step S1401 and enters a standby state until a new state transition occurs.

  The flowchart of FIG. 15 shows the scheduler in the case where it is determined in step S1401 that a task end has occurred (1401: Yes task end) and in the case where it is determined that a task switch has occurred (step S1401: Yes task switch). 110 processes.

  In FIG. 15, when it is determined in step S1401 that task termination has occurred (1401: Yes task termination), the scheduler 110 first releases a cache area in which shared data of locked parallel tasks is arranged. (Step S1501).

  Thereafter, the scheduler 110 determines whether there is a task waiting for execution (step S1502). If it is determined in step S1502 that there is a task waiting for execution (step S1502: Yes), the scheduler 110 proceeds to step S1503 and performs processing for executing the task waiting for execution. On the other hand, if it is determined in step S1502 that there is no task waiting to be executed (step S1502: No), the scheduler 110 returns to the process of step S1401 in FIG. 14 and enters a standby state until the next state transition occurs. .

  On the other hand, if it is determined in step S1401 that a task switch has occurred (1401: Yes task switch), the scheduler 110 determines whether it is a low-priority parallel task that passes the task execution right (step S1401). S1503). If it is determined in step S1502 that there is a task waiting to be executed (step S1502: Yes), the scheduler 110 performs the determination process in step S1503.

  If it is determined in step S1503 that the task execution right is transferred to the low-priority parallel task (step S1503: Yes), the scheduler 110 executes the cache coherence method when executing the low-priority parallel task. Is adopted. That is, the scheduler 110 sets the CPU cache coherence method to a mode in which the snoop mechanism operates when another CPU accesses the data (step S1504).

  In step S1503, when it is determined that it is not a low priority parallel task that passes the task execution right (step S1503: No), or when the process of step S1504 ends, the scheduler 110 becomes an execution target. Task execution is started (step S1505). When the task is executed in step S1505, the scheduler 110 returns to the process in step S1401 and is in a standby state until a state transition of the next task occurs.

  The flowchart of FIG. 16 represents the process of the scheduler 110 when it is determined in step S1404 that the newly generated parallel task is not a high priority task (step S1404: No).

  In FIG. 16, the scheduler 110 first determines whether or not the parallel task newly generated in step S1404 is not a high priority task (step S1404: No). Is determined (step S1601). In step S1601, it is determined whether a high priority task is currently being executed in the CPU that executes the newly generated task.

  If it is determined in step S1601 that a high priority task is being executed (step S1601: Yes), the scheduler 110 employs a cache coherence method when executing a low priority parallel task. That is, the scheduler 110 sets the cache coherence method of the parallel task being executed to a mode in which the snoop mechanism of the snoop 120 operates when another CPU accesses data (step S1602).

  Thereafter, the scheduler 110 queues the task to be executed to the CPU with the smallest load (step S1603), and proceeds to the processing of step S1401. In step S1603, the queued task is executed after the currently executing task is completed. The CPU with the smallest load means a CPU with the smallest processing amount of the queued task. Note that the scheduler 110 that has shifted to step S1401 is in a standby state until the next transition state occurs.

  If it is determined in step S1601 that the high priority task is not being executed (step S1601: No), the scheduler 110 adopts a cache coherence method when executing the high priority parallel task. That is, the scheduler 110 migrates the parallel task being executed to the CPU having the smallest load among the other CPUs executing the parallel threads included in the parallel task, and the new thread included in the parallel task during the execution. Forking to another CPU is prohibited (step S1604).

  Further, the scheduler 110 sequentially executes the tasks migrated in step S1604 (step S1605). Then, in the newly generated parallel task, the scheduler 110 prohibits the forking of the thread included in the parallel task to another CPU and queues it to the CPU with the smallest load (step S1606).

  In step S1606, the queued task is executed after the currently executing task is completed. When step S1606 ends, the scheduler 110 shifts to the process of step S1401 and enters a standby state until a new state transition occurs.

  The flowchart of FIG. 17 represents the processing of the scheduler 110 when it is determined in step S1405 that the newly generated parallel task is not executing the high priority task (step S1405: No).

  In FIG. 17, when it is determined that the target CPU is not executing the high priority task in step S1405 (step S1405: No), the scheduler 110 first sets the newly generated task to the minimum load. The CPU is assigned (step S1701).

  Then, the scheduler 110 determines whether or not the newly generated parallel task does not satisfy the deadline constraint in the sequential execution (step S1702). In step S <b> 1702, the scheduler 110 determines whether the deadline constraint is not satisfied based on the deadline constraint set in the task table 111.

  If it is determined in step S1702 that the deadline constraint is not satisfied (step S1702: Yes), the scheduler 110 further determines whether or not a low-priority parallel task is currently being executed (step S1703).

  If it is determined in step S1703 that a low-priority parallel task is being executed (step S1703: Yes), the scheduler 110 employs a cache coherence method for executing the low-priority parallel task. That is, the scheduler 110 sets the coherence method of the parallel task being executed to a mode in which the snoop mechanism operates when another CPU accesses data (step S1704).

  When the process of step S1704 ends, the scheduler 110 locks the cache area in which the newly generated shared data of the parallel task is arranged (step S1705). If it is determined in step S1703 that the low-priority parallel task is not being executed (step S1703: No), the scheduler 110 employs a normal coherence method, and thus does not perform the process of step S1704. The process proceeds to step S1705.

  When the process of step S1705 ends, the scheduler 110 starts execution of the newly generated parallel task (step S1706), returns to the process of step S1401, and enters a standby state until a next task state transition occurs. .

  On the other hand, if it is determined in step S1702 that the deadline constraint is satisfied (step S1702: No), the scheduler 110 locks the cache area in which the newly generated shared data of the parallel task is placed (step S1707). .

  Then, the scheduler 110 starts sequential execution of the newly generated parallel task (step S1708). Thereafter, the scheduler 110 returns to the process of step S1401 and enters a standby state until a state transition of the next task occurs.

  As described above, the scheduler 110 determines what priority (high priority / low priority) is set for each task specified as a parallel task, and the parallel tasks have the same priority. Depending on the degree, it can be scheduled to be executed by an optimal CPU. In addition, since the scheduler 110 sets a cache coherence method for shared data in accordance with the priority of each task, it is possible to prevent a decrease in usage efficiency of the cache memory (cache L1 $).

(Application example)
Next, an operation example when the scheduling process according to the present embodiment is applied to a communication device will be described. Specifically, parallel tasks executed respectively by a portable communication device such as a smartphone and a fixed communication device such as a server will be described.

<For parallel tasks with the same priority>
FIG. 18 is an explanatory diagram of an execution example of parallel tasks having the same priority. In FIG. 18, the smartphone 1801 communicates with another smartphone 1802 in accordance with a WLAN (Wireless LAN) standard. Furthermore, the smartphone 1801 performs communication based on the LTE (Long Term Evolution) standard with the server 1803.

  The task (WLAN # 0, 1) that conforms to the WLAN standard and the task (LTE # 0, 1) that conforms to the LTE standard are both high priority tasks due to real-time restrictions. Therefore, the smartphone 1801 executes WLAN # 0, 1 and LTE # 0, 1 as parallel tasks having the same priority. Since the snoop 120 of the smartphone 1801 executes parallel tasks with the same priority, a snoop method for performing normal cache coherency is adopted.

<For parallel tasks with different priorities>
FIG. 19 is an explanatory diagram of an execution example of parallel tasks having different priorities. In FIG. 19, the smartphone 1801 communicates with the server 1803 in accordance with the LTE standard. In the smartphone 1801, a task (driver # 0, 1) for a driver application that does not require communication is executed.

  The driver application executed by the smartphone 1801 is a low-priority task because no real-time constraint is provided. Therefore, the smartphone 1801 executes LTE # 0, 1 as a high priority parallel task, and executes driver # 0, 1 as a low priority parallel task. Since parallel tasks with different priorities are executed, the snoop 120 of the smartphone 1801 employs a snoop method that performs cache coherency in the low priority parallel tasks for LTE # 0,1.

  As described above, according to the multi-core processor system, the control method and control program for the multi-core processor system, the shared data that is frequently used is preferentially arranged in the cache memory having a high access speed, so that the processing speed is improved. be able to.

  In the case of shared data for processing set to low priority, the synchronization processing by cache coherency is postponed until an access request from the CPU is generated. That is, it is possible to avoid a process that causes a decrease in the processing performance of the multi-core processor system, such as writing shared data without reusability to the cache memory. Therefore, even when parallel processing and multitask processing are executed, it is possible to improve the use efficiency of the cache and improve the processing capability of the multicore processor system.

  Further, when there is no high priority task and there is an empty area in the cache memory, the shared data of the low priority task may be arranged in the cache memory of each CPU. Therefore, even when there is no post-high priority task, the cache memory can be used efficiently.

  Further, the shared data accessed when executing the high priority task arranged in the cache memory may be set to be locked until the high priority task is completed. Locking shared data prevents high-priority task shared data from being overwritten by shared data of other tasks even if a task switch occurs, and efficiently executes high-priority tasks Can be made.

  Also, if the shared data accessed by the high-priority task is larger than the capacity of the cache memory and cannot be allocated in the cache memory, the memory area other than the cache memory will have a higher access speed. Shared data may be arranged. In addition, when a plurality of memory areas exist when the shared memory is arranged, the shared data is arranged in order from the memory with the higher access speed. Therefore, since the shared data of the high priority task is preferentially arranged in a memory area with a high access speed, efficient processing can be expected.

  Furthermore, when the shared data accessed by the high priority task is smaller than the capacity of the cache memory and the cache memory has room, the shared data of the low priority task may be arranged in the surplus area. . By arranging the shared data of the low priority task in the surplus area, it is possible to prevent free space in the cache memory and maintain high utilization efficiency.

  Further, when a plurality of memory areas are prepared as other memory areas of the cache memory of each CPU, the shared data may be arranged in order from the memory area with the fast access speed. Regardless of the priority, each task can be efficiently executed by preferentially arranging the shared data of each task in a memory area having a high access speed.

  Furthermore, parallel tasks may be extracted from tasks to be executed and assigned to the same processor. Further, parallel tasks having the same priority among the parallel tasks may be extracted and assigned to the same processor. By assigning parallel tasks having the same priority to the same processor, shared data once placed in the cache memory can be used efficiently.

   The control method of the multi-core processor system described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The control program of the multi-core processor system is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, the control program of the present multi-core processor system may be distributed via a network such as the Internet.

DESCRIPTION OF SYMBOLS 100 Multi-core processor system 110 Scheduler 120 Snoop 130 Memory controller 140 Memory 150 File system 1000 Application 1001 Judgment part 1002 1st arrangement part 1003 2nd arrangement part 1004 3rd arrangement part 1005 Identification part 1006 Extraction part 1007 Allocation part

Claims (3)

Multiple cores to handle each task,
A plurality of caches each storing data to be accessed when the plurality of cores process a task, wherein a first core of the plurality of cores includes:
When the priority of the task assigned to any of the plurality of cores is equal to or higher than a predetermined value, the data is stored in a cache corresponding to the core to which the task is assigned before executing the processing of the task. Multi-core processor system. A control method for a multi-core processor system, comprising: a plurality of cores each processing a task; and a plurality of caches each storing data to be accessed when the plurality of cores process a task. The first core of
Determining whether the priority of the task assigned to any of the plurality of cores is greater than or equal to a predetermined value;
A multi-core processor system for executing a process of storing the data in a cache corresponding to a core to which the task is allocated before executing the process of the task when the priority of the task is equal to or higher than the predetermined value. Control method. A control program for a multi-core processor system, comprising: a plurality of cores each processing a task; and a plurality of caches each storing data to be accessed when the plurality of cores process a task. To the first core of
Determining whether the priority of the task assigned to any of the plurality of cores is greater than or equal to a predetermined value;
When the priority of the task is equal to or higher than the predetermined value, a process of storing the data in a cache corresponding to a core to which the task is allocated before executing the process of the task is executed. Control program.

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