JP2014142725A - Simulation program, simulation method, and simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of a simulation for evaluating the performance of a system.SOLUTION: A simulation device 100 executes a simulation for evaluating the performance of a system at a level of abstraction higher than that of an RTL such as an ESL. The simulation device 100 executes a reference source RS and an architecture model AM with different threads, thereby executing a simulation for simulating the behavior of a block depending on an algorithm of the reference source RS. Then, the simulation device 100 outputs a simulation result SR.

Description

  The present invention relates to a simulation program, a simulation method, and a simulation apparatus.

  Conventionally, there is a case where a system performance evaluation is performed by creating a simulation model at a higher level of abstraction than RTL (Register Transfer Level) such as ESL (Electronic System Level). Further, the system performance may be estimated by manual calculation by a user using spreadsheet software or the like.

  Related prior art includes, for example, reading a source code description to generate a composite intermediate form stored in memory, searching the composite intermediate form in memory to find an array for each process, and GUI (Graphical There is a technology listed in User Interface. Further, there is a technique for obtaining an optimum architecture configuration when searching for a system architecture in an upstream process of design, targeting a simulation with a high level of abstraction. In addition, there is a technology that supports system design by comprehensively applying conditions from bus architecture design to logic synthesis.

JP 2009-093682 A JP 2010-039677 A JP 2006-215852 A

  However, according to the prior art, there is a problem that it takes time and labor to create a simulation model for evaluating the performance of the system. For example, even in ESL, it may take several months to create a simulation model, and it is difficult to evaluate the performance of the system at a stage prior to the design stage such as during a business talk with a customer.

  In recent years, SoC (System on a Chip) is often designed by combining various hardware blocks, and various functions have been included. For this reason, in order to estimate the performance of the system by manual calculation using spreadsheet software or the like, a large number of specialists will make use of experience and intuition, and desk work will be required, which will increase work time and cost.

  In one aspect, an object of the present invention is to provide a simulation program, a simulation method, and a simulation apparatus for improving the efficiency of simulation for evaluating the performance of a system.

  According to one aspect of the present invention, an architecture is provided that includes a reference source that describes a system function in a programming language, a plurality of blocks that simulate the operation of the system, and a control unit that controls the plurality of blocks. A model is acquired, and a loop process of a series of processes including a process whose contents change by a conditional branch based on data sequentially selected from a data string to be processed is executed based on the reference source, and the series of processes is performed. Each time execution of the included processing is completed, the parameter value set according to the processing content of the processing is written into a buffer accessed by a block that realizes the processing among the plurality of blocks, and the control unit When the execution of the series of processes is completed, the process executed first in the series of processes is realized. Activating the locking, by the block, by to read the parameter values from the buffer in which the block is accessed, a simulation program for executing the calculation processing based on the parameter value, a simulation method and simulation apparatus is proposed.

  According to one aspect of the present invention, it is possible to improve the efficiency of simulation for evaluating the performance of a system.

FIG. 1 is an explanatory diagram of an example of the simulation method according to the embodiment. FIG. 2 is an explanatory diagram illustrating a description example in which the reference source RS is described in pseudo code. FIG. 3 is an explanatory diagram (part 1) of a specific example of the architecture model AM. FIG. 4 is an explanatory diagram showing an example of an operation sequence of the architecture model AM. FIG. 5 is an explanatory diagram illustrating a description example of the control unit. FIG. 6 is an explanatory diagram showing an example of block description. FIG. 7 is an explanatory diagram illustrating a main description example of the simulation model. FIG. 8 is a block diagram illustrating a hardware configuration example of the simulation apparatus 100. FIG. 9 is a block diagram illustrating a functional configuration example of the simulation apparatus 100. FIG. 10A is an explanatory diagram (part 1) of a description example of the reference source RS. FIG. 10B is an explanatory diagram (part 2) of a description example of the reference source RS. FIG. 11 is an explanatory diagram showing a specific example of an input file. FIG. 12 is an explanatory diagram showing a specific example of an output file. FIG. 13 is an explanatory diagram of an example of inserting a preceding access description. FIG. 14A is an explanatory diagram (part 1) of a description example of a connection portion between the reference source RS and the architecture model AM. FIG. 14B is an explanatory diagram (part 2) of a description example of a connection portion between the reference source RS and the architecture model AM. FIG. 15 is an explanatory diagram (part 2) of a specific example of the architecture model AM. FIG. 16 is an explanatory diagram of an example of inserting a prober function. FIG. 17A is an explanatory diagram (part 1) of a description example of a component. FIG. 17B is an explanatory diagram (part 2) of a description example of a component. FIG. 17C is an explanatory diagram (part 3) of a description example of a component. FIG. 17D is an explanatory diagram (part 4) of a description example of a component. FIG. 18 is an explanatory diagram illustrating a description example of the connection relationship between components. FIG. 19 is an explanatory diagram showing a description example for starting the reference source RS. FIG. 20 is an explanatory diagram showing a software structure between the reference source RS and the architecture model AM. FIG. 21 is an explanatory diagram of a specific example of the simulation result SR. FIG. 22 is a flowchart illustrating an example of a simulation processing procedure of the simulation apparatus 100. FIG. 23 is a flowchart illustrating an example of a processing procedure of the reference source RS. FIG. 24 is a flowchart illustrating an example of a processing procedure of the control unit CT. FIG. 25 is a flowchart illustrating an example of the processing procedure of the block Bi.

  Exemplary embodiments of a simulation program, a simulation method, and a simulation apparatus according to the present invention will be described below in detail with reference to the drawings.

(One Example of Simulation Method)
FIG. 1 is an explanatory diagram of an example of the simulation method according to the embodiment. In FIG. 1, a simulation apparatus 100 is a computer that executes a simulation for evaluating the performance of a system at a higher level of abstraction than RTL such as ESL. The system to be evaluated is, for example, a system in which a plurality of hardware blocks are connected via a bus. The simulation is for, for example, evaluating whether the performance of the system does not fail based on how busy the bus is when each hardware block throws a transaction on the bus.

  The hardware block is, for example, a model that performs calculation processing by accessing a memory via a bus. Specifically, for example, the hardware block is a model that reads / writes data for a specified size and generates a delay time for a specified cycle to reproduce the calculation time. In the following description, a hardware block in the system may be simply referred to as “block”.

  Based on the reference source RS and the architecture model AM, the simulation apparatus 100 executes a simulation that simulates the behavior of the block depending on the algorithm of the reference source RS, and outputs a simulation result SR. The reference source RS is created, for example, for the purpose of algorithm evaluation / development, and describes the function of the system to be realized in a programming language such as C language. The architecture model AM indicates the configuration of blocks and buses in the system.

  Here, the parameter value input to the block in the architecture model AM depends on the function of the system. Examples of parameter values input to the block include a data size per access, an access interval, and the number of accesses. For this reason, it is possible to observe or predict a change in the parameter value input to the model in the architecture model AM from the reference source RS.

  Therefore, in the present embodiment, the simulation apparatus 100 uses the reference source RS and the architecture model AM to reproduce the behavior of the architecture model AM in accordance with the behavior of the reference source RS. There is a moving image processing as a typical example of simulation using the reference source RS. The moving image processing has a feature that a certain process is repeatedly performed, and the reference source RS is also described in a repeated sentence.

  FIG. 2 is an explanatory diagram illustrating a description example in which the reference source RS is described in pseudo code. As shown by the pseudo code 200 in FIG. 2, the reference source RS, for example, (1) opens a file to be processed, (2) parses the file, extracts data for one process, and (3) It is described that a desired process is repeated for the extracted data for one process. On the other hand, the main purpose of the architecture model AM is to model the data transfer function. Here, a specific example of the architecture model AM will be described.

  FIG. 3 is an explanatory diagram (part 1) of a specific example of the architecture model AM. In FIG. 3, the architecture model 300 includes a control unit 301, a block 302, a block 303, a block 304, a RAM (Random Access Memory) 305, and a data transfer unit 306.

  In the architecture model 300, the blocks 302 to 304 operate in accordance with instructions from the control unit 301, and the control unit 301, the blocks 302 to 304, and the RAM 305 operate while sharing the data transfer unit 306. Specifically, for example, when the access function to the data transfer unit 306 is set to access (int byte_num) and the bus width specified to the data transfer unit 306 is set to n [bytes], it takes time of byte_num / n + α cycles. Thus, writing to the RAM 305 is performed from the block that called the access function.

  FIG. 4 is an explanatory diagram showing an example of an operation sequence of the architecture model AM. FIG. 4 shows an operation sequence of the architecture model 300 (see FIG. 3). Specifically, the control unit 301 activates each of the blocks 302 to 304, and each of the blocks 302 to 304 accesses the RAM 305 as appropriate. Then, each block 302 to 304 returns a done to the control unit 301 after completing all desired accesses. Here, a description example of the control unit 301 will be described.

  FIG. 5 is an explanatory diagram illustrating a description example of the control unit. In FIG. 5, a description example 500 is a description example of the control unit 301 when the process shown in FIG. 4 is repeated ten times. In the description example 500, to_tar [i] is a communication path with block i (blocks 302 to 304), and an activation signal is sent with to_tar [i]-> start ().

  to_tar [i]-> get_done_event () is a function for extracting a done event, and in the description example 500, it waits for an event to be extracted. Also, to_tar [i]-> get_done () is a function for extracting a flag indicating whether or not a done state, and when the expression inside () of while (...) becomes true, do {...} Exit from while () to exit from the event waiting state. In this way, the control unit 301 synchronizes with the blocks 302 to 304.

  Next, description examples of the blocks (blocks 302 to 304) will be described. However, here, a method of describing parameter values to be given to a block in the block description will be described. For the RAM 305 and the data transfer unit 306, for example, an existing memory model or bus model can be used.

  FIG. 6 is an explanatory diagram showing an example of block description. In the description example 600 illustrated in FIG. 6, block 0 has a communication port from_ini with the control unit 301 and a communication port transaction with the data transfer unit 306. th0 is the part that implements the data transfer function. Here, description in th0 will be described.

  (0) is a description waiting for an activation signal from the control unit 301. (1) is a description defining that processing is performed 1000 times per activation. (2) is a description for generating a delay corresponding to the processing time required for this processing. Here, a uniform processing time of 40 [ns] is required. (3) is a description expressing access to the data transfer unit 306. Here, access for 100 bytes of data is expressed.

  When the processes (1) to (3) are performed 1000 times, the for sentence is exited and the process proceeds to (4). (4) is a description for sending an end signal to the control unit 301. The end signal is realized by calling done () of from_ini. In this way, a model for causing the data transfer unit 306 to generate data access in cooperation with the control unit 301 can be realized.

  However, in the description example 600, the user needs to describe the parameter value given to block 0 in the description example 600. In the example of FIG. 6, for example, the number of times of small processing (value of 1000 in (1) above), the processing time of small processing (value of 40 [ns] in (2) above), and the amount of access generated in small processing ( The above (3) value of 100 bytes) needs to be described in the description example 600 by the user. Although this method can perform simulation based on the user's expectation and is convenient and convenient, there is a problem that the user specifies important parameter values.

  Therefore, in the present embodiment, the simulation apparatus 100 determines a parameter value to be given to a block (for example, the blocks 302 to 304 shown in FIG. 3) by executing the reference source RS. Specifically, the simulation apparatus 100 executes the reference source RS and the architecture model AM in separate threads.

  FIG. 7 is an explanatory diagram illustrating a main description example of the simulation model. In FIG. 7, as shown in the main description 700, the simulation apparatus 100 simultaneously executes a thread 0 that executes the reference source RS and a thread 1 that executes the architecture model AM.

  In the simulation, the reference source RS and the architecture model AM communicate using the shared memory MM. Data is sent from the reference source RS to the architecture model AM. Specifically, when the probe function embedded in the reference source RS is called, the simulation apparatus 100 writes the value of the corresponding argument in a FIFO (First In First Out) buffer on the shared memory MM. As a result, the probed values accumulate in the FIFO buffer.

  On the other hand, on the architecture model AM side, each block retrieves a value to be referred to from the FIFO buffer in a timely manner, and executes an architecture simulation using the retrieved value as a parameter value. Thereby, the parameter value generated by the reference source RS can be used in the architecture simulation, and can be executed in one execution format. However, if the architecture model AM operates ahead of the reference source RS, the simulation fails.

  Therefore, in the present embodiment, a variable area representing the preceding amount preceded by the reference source RS with respect to the architecture model AM is prepared on the shared memory MM. Hereinafter, this variable may be referred to as a “preceding degree variable”.

  The reference source RS side increments the leading degree variable by 1 when a series of processing ends. In the example of FIG. 2, the leading degree variable is incremented by 1 when (3) is completed. On the other hand, on the architecture model AM side, for example, the control unit 301 shown in FIG. In the example of FIG. 5, before (1), the process advances when the leading degree variable is 1 or more and waits until it becomes 1 when 0. Next, 1 is subtracted from the leading degree variable. The example so far is an example using only variables, but the example described later is an implementation example using FIFO. In this case, the reference source RS side sends an appropriate value (for example, the number of loop executions) to the FIFO. The architecture model AM side extracts a value if the FIFO is not empty, and if the FIFO is empty, waits for the FIFO to be empty and extracts the value. In this way, the previous leading degree can be expressed by the size of the FIFO.

  Thereby, after all parameters necessary for calculation of a series of processes are stored in the FIFO buffer on the shared memory MM, it is possible to control the operation of the architecture model AM side. When the memory amount of the FIFO buffer is limited, for example, an upper limit N of the preceding amount is determined, and when the preceding amount exceeds the upper limit N, the reference source RS side is set until the preceding amount becomes the upper limit N or less. You may decide to put control which delays execution.

  As described above, in this embodiment, a function (probe function) for passing a parameter value necessary for processing by each block in the architecture model AM to the shared memory MM is embedded in the reference source RS. In addition, each block in the architecture model AM embeds a function for extracting necessary data from the shared memory MM in the architecture model AM. As a result, an architecture simulation based on the reference source RS becomes possible, and the performance can be evaluated without creating a complicated model in which the source is divided and a function is included for each block.

(Hardware configuration example of simulation apparatus 100)
FIG. 8 is a block diagram illustrating a hardware configuration example of the simulation apparatus 100. In FIG. 8, a simulation apparatus 100 includes a CPU 801, a ROM (Read-Only Memory) 802, a RAM 803, a magnetic disk drive 804, a magnetic disk 805, an optical disk drive 806, an optical disk 807, and an I / F (Interface). ) 808, a display 809, a keyboard 810, and a mouse 811. Each component is connected by a bus 812.

  Here, the CPU 801 governs overall control of the simulation apparatus 100. The ROM 802 stores a program such as a boot program. The RAM 803 is used as a work area for the CPU 801. The magnetic disk drive 804 controls reading / writing of data with respect to the magnetic disk 805 according to the control of the CPU 801. The magnetic disk 805 stores data written under the control of the magnetic disk drive 804.

  The optical disk drive 806 controls reading / writing of data with respect to the optical disk 807 according to the control of the CPU 801. The optical disk 807 stores data written under the control of the optical disk drive 806, and causes the computer to read data stored on the optical disk 807.

  The I / F 808 is connected to a network 820 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to another computer via the network 820. The I / F 808 controls an internal interface with the network 820 and controls input / output of data from other computers. For example, a modem or a LAN adapter may be employed as the I / F 808.

  A display 809 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 809, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The keyboard 810 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 811 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  Note that the simulation apparatus 100 may not include, for example, the optical disk drive 806 or the optical disk 807 among the above-described configurations. The simulation apparatus 100 may include, for example, a scanner or a printer in addition to the above-described components.

(Functional configuration example of the simulation apparatus 100)
FIG. 9 is a block diagram illustrating a functional configuration example of the simulation apparatus 100. In FIG. 9, the simulation apparatus 100 is configured to include an acquisition unit 901, a first execution unit 902, a second execution unit 903, and an output unit 904. Specifically, for example, each function unit causes the CPU 801 to execute a program stored in a storage device such as the ROM 802, the RAM 803, the magnetic disk 805, and the optical disk 807 illustrated in FIG. 8, or by the I / F 808. Realize its function. In addition, the processing result of each functional unit is stored in a storage device such as the RAM 803, the magnetic disk 805, and the optical disk 807, for example.

  The acquisition unit 901 has a function of acquiring the reference source RS. Here, the reference source RS is a source code describing the function of the system to be evaluated in a programming language. The reference source RS includes, for example, a conditional branch such as an “if” statement, sequentially selects data from the data string to be processed described in the input file, performs a series of processing with the implemented algorithm, and outputs the processing result It is what you write to a file.

  Specifically, for example, the acquisition unit 901 acquires the reference source RS by a user operation input using the keyboard 810 and the mouse 811 illustrated in FIG. The acquisition unit 901 may receive the reference source RS from an external computer. Specific examples of the reference source RS will be described later with reference to FIGS. 10A, 10B, 13 and 16.

  Also, an input file in which a data string to be processed is described in the reference source RS is acquired by a user operation input using the keyboard 810 or the mouse 811, for example. A specific example of the input file will be described later with reference to FIG.

  The acquisition unit 901 has a function of acquiring the architecture model AM. Here, the architecture model AM indicates the configuration of blocks and buses in the system to be evaluated, and includes, for example, a plurality of blocks and a control unit that controls the plurality of blocks. The block is a model that simulates the operation of the system, and is a calculation block that performs a calculation process by accessing a memory via a bus.

  In the following description, a plurality of blocks included in the architecture model AM may be referred to as “blocks B1 to Bn”, and an arbitrary block among the blocks B1 to Bn may be referred to as “block Bi”. In addition, the control unit that controls the blocks B1 to Bn may be referred to as “control unit CT”.

  Specifically, for example, the acquisition unit 901 acquires the architecture model AM by a user operation input using the keyboard 810 and the mouse 811. The acquisition unit 901 may receive the architecture model AM from an external computer. Note that the architecture model AM is created, for example, by a user operation input using the keyboard 810 or the mouse 811, or by reusing or combining block models, interface models, and the like registered in the database. You may decide.

  The first execution unit 902 has a function of executing the reference source RS. Specifically, for example, the first execution unit 902 executes a loop process of a series of processes using an algorithm implemented in the reference source RS. Here, the series of processing is repeatedly executed while changing the value of the argument, for example, moving image processing for compressing a moving image.

  More specifically, for example, the first execution unit 902 sequentially selects data from the data string described in the input file, and includes a series of processes including a process whose process contents change depending on a conditional branch based on the selected data. Execute. Note that a series of processing corresponds to, for example, a function calc and a function calc2 described later.

  Further, each time the execution of the process included in the series of processes is completed, the first execution unit 902 changes the parameter value set according to the processing content of the process to the process among the blocks B1 to Bn. The realized block Bi has a function of writing in a buffer to be accessed. Here, the parameter value is a parameter value used in the calculation process of the block Bi.

  The parameter value is described in the reference source RS in association with the processing content of each process included in the series of processes. Specific examples of the parameter value include, for example, the number of cycles for calculation processing, the amount of read data, the amount of write data, the operating frequency of the block Bi, and the like. The buffer accessed by the block Bi is, for example, a FIFO structure buffer provided for each block Bi on the shared memory MM.

  The first execution unit 902 has a function of writing information indicating that execution of a series of processes is completed to a buffer accessed by the control unit CT every time execution of the series of processes is completed. Here, the information indicating that the execution of the series of processes is completed is, for example, a leading degree variable that represents a leading amount that the reference source RS precedes the architecture model AM.

  Further, the buffer accessed by the control unit CT is, for example, a FIFO structure buffer provided on the shared memory MM. Specifically, for example, each time the execution of a series of processes is completed, the first execution unit 902 increments the leading degree variable and writes it to the FIFO structure buffer accessed by the control unit CT.

  In addition, when a predetermined number N or more of leading degree variables are stored in the FIFO structure buffer accessed by the control unit CT, the first execution unit 902 sets the leading degree variable stored in the buffer to a predetermined value. You may decide to stop execution of a loop process until it becomes less than the number N. As a result, when the preceding amount of the reference source RS with respect to the architecture model AM exceeds the upper limit N, it is possible to prevent the leading degree variable from being accumulated in the buffer having the FIFO structure, and to limit the memory amount of the buffer. .

  The second execution unit 903 has a function of executing an architecture simulation of the architecture model AM. Specifically, for example, the second execution unit 903, when the execution of a series of processes by the first execution unit 902 is completed, is executed first by the control unit CT among the series of processes. The block Bi that realizes is activated.

  More specifically, for example, the second execution unit 903, when the leading degree variable is stored in the buffer of the FIFO structure accessed by the control unit CT by the control unit CT, The start command is output to the block Bi that implements the processing executed in the above. That is, when there is an unread precedence variable in the FIFO structure buffer, it is guaranteed that the reference source RS precedes the architecture model AM.

  Further, the second execution unit 903 causes the block Bi to read the parameter value from the buffer accessed by the block Bi, thereby executing the calculation process based on the parameter value. Specifically, for example, the second execution unit 903 causes the block Bi that has received the activation command from the control unit CT to execute a calculation process based on the parameter value stored in the buffer accessed by the block Bi.

  Further, when the execution of the calculation process based on the parameter value is completed by the block Bi, the second execution unit 903 outputs a start instruction to the block Bj that realizes the next process in the series of processes (j ≠ i). Then, the second execution unit 903 executes calculation processing based on the parameter value stored in the buffer accessed by the block Bj by the block Bj that has received the activation command from the block Bi. In addition, when the block Bj is the block that realizes the last process in the series of processes, the second execution unit 903 sends a completion notification indicating that the execution of the series of processes is completed by the block Bj. To output.

  The output unit 904 has a function of outputting the execution result executed by the first execution unit 902. Specifically, for example, the output unit 904 may output an output file 1200 as shown in FIG. The output unit 904 has a function of outputting the execution result executed by the second execution unit 903. Specifically, for example, the output unit 904 may output a simulation result SR as shown in FIG.

  As an output format of the output unit 904, for example, storage in a storage device such as the RAM 803, the magnetic disk 805, and the optical disk 807, display on the display 809, print output to a printer (not shown), external by the I / F 808 Sending to other computers.

(Example of reference source RS description)
10A and 10B are explanatory diagrams illustrating a description example of the reference source RS. 10A and 10B, the reference source RS includes a function calc, a function calc2, and a debug function print_result. “main” is a method that opens an input file and an output file, analyzes the input file, extracts data, and passes the data to the function calc and the function calc2.

  When the function calc and the function calc2 are executed, the result is stored in the buffer result, the result stored in the buffer result is passed to the function print_result, and the result is output. As described above, the reference source RS reads the data described in the input file, performs processing using the implemented algorithm, and writes the processing result to the output file.

  Here, an input file and an output file to be processed by the reference source RS will be described with reference to FIGS. 11 and 12.

  FIG. 11 is an explanatory diagram showing a specific example of an input file. In FIG. 11, an input file 1100 describes data to be processed by the reference source RS. In the input file 1100, a line with one element represents “the number of data to be processed”, and a line with three elements represents “data”. Further, the data represents an operation type, a numerical value 0, and a numerical value 1.

  In the reference source RS, a unit (for example, reference numeral 1101) indicating the number of data to be processed is processed as a lump. Specifically, in the reference source RS, data is stored in the two-dimensional array data, and the number of data is stored in times. After that, “times”, “data”, and “result” (for storing the calculation result) are passed to the function “calc” and the function “calc2”, the calculation is performed, and the result is passed to the function “print_result” to output an output file.

  The function calc performs calculation depending on the operation type. Specifically, the function calc calculates the sum of the numerical value 0 and the numerical value 1 when the operation type is 0, calculates the product of the numerical value 0 and the numerical value 1 when the operation type is 1, and stores the result in the array result. Write in the designated place. The function calc2 is a process subsequent to the function calc. Specifically, the function calc2 shifts the result value to the left by 1 bit and writes the result back to the result.

  FIG. 12 is an explanatory diagram showing a specific example of an output file. In FIG. 12, an output file 1200 is output data indicating a processing result obtained by sequentially processing data described in the input file 1100 (see FIG. 11) by an algorithm implemented in the reference source RS.

(Example of preceding access description)
Next, the preceding access description inserted into the reference source RS will be described. The preceding access description is for controlling the reference source RS to operate earlier than the architecture model AM, and corresponds to the control using the preceding degree variable.

  FIG. 13 is an explanatory diagram of an example of inserting a preceding access description. In FIG. 13, the preceding access description 1300 inserted in the reference source RS is shown. The preceding access description 1300 is a description example in which the reference source RS may precede any number of times for the architecture model AM. That is, it is a description example in which even one reference source RS only needs to precede the architecture model AM.

  When the preceding access description 1300 is inserted into the reference source RS, for example, the user uses namespace to prevent the name from batting, and the description example of the reference source RS illustrated in FIGS. 10A and 10B is a namespace. Copy inside. Next, the user inserts a preceding access description 1300 (hereinafter may be referred to as “separator”) into the reference source RS.

  In the case of an application to be implemented as hardware, there are many algorithms that are repeatedly executed in a loop statement as in the description example of the reference source RS shown in FIGS. 10A and 10B. Therefore, a “cut” (separator) is put in this loop. The separator (preceding access description 1300) ensures that the simulation on the architecture model AM side does not fail if the processing up to the separator is completed. Pipe_t is a component that connects the reference source RS and the architecture model AM.

(Description example of the connection part between the reference source RS and the architecture model AM)
14A and 14B are explanatory diagrams illustrating a description example of a connection part between the reference source RS and the architecture model AM. 14A and 14B, the description example 1400 includes a class function for the reference source RS and a class function for the architecture model AM. Specifically, the pipe_t class is a collection of communication parts of the reference source RS part and the architecture model AM part.

  The class variable m_separator is a buffer for notifying the arrival of the separator from the reference source RS part to the architecture model AM part. Of the member variables, static member variables are called static member variables or class variables. Here, it is implemented using a STL (Standard Template Logic) request. Furthermore, the maximum value of the issued ID is stored with m_separator_id.

  In addition, a class function separator () is defined in this class. This is a function (preceding access description 1300) called in the reference source RS shown in FIG. This function is also defined in the description example 1400. The first time is skipped, and after the second time, the current m_separator_id is pushed to m_separator, and m_separator_id is incremented.

  Further, in add_end_marker (), −1 is added to the end of an arbitrary buffer described later. -1 indicates "end". Finally, pthread_cond_broadcast is performed to wake up the source waiting for the reference source RS to reach the separator.

  Note that the variable of the critical section such as the shared memory MM corresponds to the class variable of the description example 1400. Since all public functions disclosed by pipe_t are surrounded by exclusive control (lock (), unlock ()), the critical section can be controlled.

  M_separator in the class variable is a shared memory used for transmitting the separator from the reference source RS to the architecture model AM. Further, m_buffer prepares a request for each ID, and a parameter value calculated by the reference source RS is stored in the request.

  FIG. 15 is an explanatory diagram (part 2) of a specific example of the architecture model AM. In FIG. 15, the architecture model AM includes a control unit CT, a block B1, and a block B2. In FIG. 15, a part of the architecture model AM is extracted and shown (for example, portions corresponding to the RAM 305 and the data transfer unit 306 shown in FIG. 3 are omitted).

  Here, it is assumed that the processing of the function calc is realized by the block B1, and the processing of the function calc2 is realized by the block B2. In this case, the user inserts a prober function into the reference source RS so that the parameter values used in the calculation processing of the block B1 and the block B2 can be passed to the architecture model AM.

  FIG. 16 is an explanatory diagram of an example of inserting a prober function. In FIG. 16, prober functions 1601 to 1603 inserted in the reference source RS are shown. In FIG. 16, a part of the reference source RS is extracted and shown.

  Here, the prober functions 1601 to 1603 are functions for writing the parameter values used for the calculation processing of the block Bi to the FIFO buffer corresponding to the block Bi. In the reference source RS shown in FIG. 16, a plurality of transfer paths are prepared for data transfer from the reference source RS to the architecture model AM, and an ID number is assigned to each. In the example of FIG. 16, ID = 0 is allocated for the block B1, and ID = 1 is allocated for the block B2. Here, an example is shown in which the number of calculation cycles is passed.

  The user subjectively analyzes the source and estimates the approximate number of cycles. In the example of FIG. 16, it is assumed that addition takes 10 cycles, multiplication takes 100 cycles, and shift operation takes 50 cycles. In addition, after each calculation is finished, pipe_t :: send_param is to be called. Here, the first argument is an ID number, and the second argument is the number of cycles. In this way, the parameter value can be sent from the reference source RS.

(Description example of architecture model AM)
Next, description examples of the architecture model AM shown in FIG. 15 will be described. The architecture model AM includes, for example, a description example 1700 shown in FIGS. 17A, 17B, 17C, and 17D and a description example 1800 shown in FIG.

  FIG. 17A, FIG. 17B, FIG. 17C, and FIG. 17A, FIG. 17B, FIG. 17C, and FIG. 17D, a description example 1700 is a description example of components included in the architecture model AM shown in FIG. MODULE (CONT) in the description example 1700 is a description corresponding to the control unit CT. This description is a loop, and the state on the reference source RS side is checked with pipe_t :: wait_separator ().

  When the state on the reference source RS side is OK, it indicates that the parameter value necessary for the next architecture simulation is stored in the memory inside the pipe_t, and it does not fail even if the architecture simulation is performed. Show. Note that the state on the reference source RS side is, for example, OK if a value is stored in m_separator, and NG if no value is stored in m_separator.

  In pipe_t :: wait_separator (), if the state on the reference source RS side is OK, the process proceeds. If it is NG, the process on the reference source RS side waits until it becomes OK. After that, there is a description of starting block B1 and waiting for completion from block B2.

  MODULE (A) in the description example 1700 is a description corresponding to the block B1. In this description, execution starts based on a start (start command) sent from the control unit CT, and when all parameter values sent from the reference source RS are used up, the next start command is waited (run). ()).

  A loop function is called from run (), but the main process is defined in loop (). The loop performs processing corresponding to the parameter value sent from the reference source RS. First, one piece of data with ID = 0 is extracted by pipe_t :: get_param (0). If the extracted data is positive, it is processed because it is a value to be processed.

  Here, one cycle is 10 [ns]. For this reason, the processing time of the block B1 is the extracted value data * 10 [ns]. This processing time is realized by using a wait statement. When this process is finished, the handshake with block B2 is checked. It is checked whether the block B2 enters the next process, that is, whether req = true. In this way, the calculation time corresponding to the received parameter value is expressed.

  MODULE (B) in the description example 1700 is a description corresponding to the block B2. In this description, block B2 waits until either TRIGGER or FINISH is sent from block B1. When a TRIGGER or FINISH is sent, the block B2 lowers req and notifies the block B1 that it has started task processing.

  Thereafter, the data is extracted with pipe_t :: get_param (1) as in the block B1. If the extracted data is positive, it is a valid parameter, and the corresponding processing is performed. Here, since the data is the number of cycles, similarly to the block B1, the block B2 performs a process of waiting for data * 10 [ns].

  When this process is completed, the block B2 notifies req to true, that is, the next work can be performed, returns to the beginning, and waits for the next ack. On the other hand, if the data is negative, it represents the end of the process on the reference source RS, so that the block B2 detects the end of the series of processes and notifies the control unit CT of the end.

  FIG. 18 is an explanatory diagram illustrating a description example of the connection relationship between components. In FIG. 18, a description example 1800 is a description example showing a connection relationship between components included in the architecture model AM shown in FIG. According to the description example 1800, the architecture model AM shown in FIG. 15 can be realized using MODULE (CONT), MODULE (A), and MODULE (B). Further, in the description example 1800, a part denoted by reference numeral 1801 is a description for calling the function of the namespace shown in FIG.

  FIG. 19 is an explanatory diagram showing a description example for starting the reference source RS. In FIG. 19, void run () is a process for running a thread. Also, run_base () is a function that becomes a thread. argc and argv are variables for passing argc and argv received as an argument of sc_main () to ref :: main. In this way, a thread for executing the reference source RS can be activated from the architecture model AM.

(Software structure between reference source RS and architecture model AM)
FIG. 20 is an explanatory diagram showing a software structure between the reference source RS and the architecture model AM. In FIG. 20, the reference source RS includes a separator SP, a prober PB1, and a prober PB2. The shared memory MM includes a separator FIFO (m_separator) and parameter FIFOs (m_buffer). The parameter FIFOs (m_buffer) include a 0th FIFO and a 1st FIFO. The architecture model AM includes a control unit CT, a block B1, and a block B2.

  Here, when the execution of the functions calc and calc2 is completed, the separator SP writes m_separator_id to m_separator and increments m_separator_id. When the function calc is executed, the prober PB1 writes the parameter value used for the calculation process of the block B1 into the 0th FIFO.

  Specifically, when the processing content of the function calc is “addition”, the calculation cycle number “10” is written in the 0th FIFO. When the processing content of the function calc is “product”, the number of calculation cycles “100” is written in the 0th FIFO. When the function calc2 is executed, the prober PB2 writes the parameter value (number of calculation cycles “50”) used for the calculation process of the block B2 to the first FIFO.

  When the control unit CT reads a value (m_separator_id) from m_separator, the control unit CT outputs an activation command to the block B1. When receiving an activation command from the control unit CT, the block B1 reads a parameter value from the 0th FIFO and performs a calculation process based on the parameter value.

  In addition, when the execution of the calculation process is completed, the block B1 outputs a start command (for example, TRIGGER) to the block B2. When the block B2 receives an activation command from the block B1, the parameter value is read from the first FIFO and calculation processing based on the parameter value is performed. Then, the block B2 outputs a completion notification to the control unit CT when the execution of the calculation process is completed.

(Specific example of simulation result SR)
FIG. 21 is an explanatory diagram of a specific example of the simulation result SR. In FIG. 21, the simulation result SR is a simulation result simulating the behavior of the block depending on the algorithm of the reference source RS based on the reference source RS and the architecture model AM. Specifically, the simulation result SR is a result of outputting is_run of each module of the control unit CT, the block B1, and the block B2 in the architecture model AM shown in FIG.

(Simulation processing procedure of the simulation apparatus 100)
Next, a simulation processing procedure of the simulation apparatus 100 will be described.

  FIG. 22 is a flowchart illustrating an example of a simulation processing procedure of the simulation apparatus 100. In the flowchart of FIG. 22, the simulation apparatus 100 determines whether or not the input of the reference source RS and the architecture model AM has been received (step S2201).

  Here, the simulation apparatus 100 waits for the input of the reference source RS and the architecture model AM (step S2201: No). When the simulation apparatus 100 receives input of the reference source RS and the architecture model AM (step S2201: Yes), the preceding access description is inserted into the reference source RS (step S2202).

  Next, the simulation apparatus 100 inserts a prober function into the reference source RS (step S2203). Then, the simulation apparatus 100 generates a thread description for executing thread execution of the reference source RS (step S2204). Next, the simulation apparatus 100 generates a thread description for threading the architecture model AM (step S2205).

  Then, the simulation apparatus 100 generates a main description (step S2206). Next, the simulation apparatus 100 compiles the thread description of the reference source RS, the thread description of the architecture model AM, and the main description to generate an execution format (step S2207).

  Then, the simulation apparatus 100 executes a simulation (step S2208), outputs a simulation result SR (step S2209), and ends a series of processes according to this flowchart.

  As described above, by associating the reference source RS with the architecture model AM, it is possible to perform a performance evaluation simulation of a system to be evaluated. At this time, the user only has to insert a preceding access description or a prober function into the reference source RS, and the reference source RS is analyzed and divided into modules, and rewritten so that each operates as a hardware model and simulated. Work man-hours can be reduced.

  Also, since parameter values corresponding to the processing contents can be given to each block Bi, there is no need to embed parameter values in the block description of each block Bi. As a result, it is possible to reduce the work man-hours required for the simulation while maintaining the same accuracy as the method of embedding the parameter value in the block description of each block Bi.

  In the above description, the case where the input of the architecture model AM is received has been described as an example. However, the architecture model AM may be created by a user operation input using the keyboard 810 or the mouse 811.

  In the above description, the case where the preceding access description and the prober function accept the input of the reference source RS that has not been inserted has been described as an example, but the reference source RS (for example, the preceding access description and the prober function that has been inserted) You may decide to receive the input of FIG.

(Processing procedure of reference source RS)
Next, the processing procedure of the reference source RS executed in the simulation of step S2208 shown in FIG. 22 will be described. Here, the processing procedure of the reference source RS executed for each data selected from the data string described in the input file (for example, the input file 1100) will be described.

  FIG. 23 is a flowchart illustrating an example of a processing procedure of the reference source RS. In the flowchart of FIG. 23, the simulation apparatus 100 determines whether or not the operation type specified from the data selected from the data string described in the input file is 0 (step S2301).

  Here, when the calculation type is 0 (step S2301: Yes), the simulation apparatus 100 calculates the sum of the numerical value 0 and the numerical value 1 specified from the data selected from the data string described in the input file ( Step S2302). Then, the simulation apparatus 100 sends the calculation cycle number “10” to the FIFO buffer with “ID = 0” (step S2303).

  On the other hand, when the calculation type is not 0 (step S2301: No), the simulation apparatus 100 calculates the product of the numerical value 0 and the numerical value 1 specified from the data selected from the data string described in the input file ( Step S2304). Then, the simulation apparatus 100 sends the calculation cycle number “100” to the FIFO buffer with “ID = 0” (step S2305).

  Next, the simulation apparatus 100 shifts the calculation result (step S2306) and sends the calculation cycle number “50” to the FIFO buffer of “ID = 1” (step S2307). Then, the simulation apparatus 100 sends m_separator_id to m_separator (step S2308), increments m_separator_id (step S2309), and ends the series of processing according to this flowchart.

  Thereby, a series of processes including a process whose process contents change by a conditional branch based on data selected from the data string described in the input file can be executed. Also, parameter values set according to the processing contents of the processing included in the series of processing can be sent to the FIFO buffer of the block Bi that realizes the processing.

(Processing procedure of the control unit CT in the architecture model AM)
Next, the processing procedure of the control unit CT in the architecture model AM executed in the simulation of step S2208 shown in FIG. 22 will be described. Here, a processing procedure of the control unit CT corresponding to one execution of a series of processing (function calc, function calc2) subjected to loop processing will be described.

  FIG. 24 is a flowchart illustrating an example of a processing procedure of the control unit CT. In FIG. 24, the control unit CT determines whether m_separator has a value (step S2401). Here, when there is no value in m_separator (step S2401: No), the control unit CT waits for a value to be written in m_separator.

  On the other hand, when m_separator has a value (step S2401: Yes), the control unit CT outputs an activation command to the block B1 (step S2402). Next, the control unit CT determines whether or not a completion notification has been received from the block B2 (step S2403).

  Here, the control unit CT waits to receive a completion notification from the block B2 (step S2403: No), and when it receives a completion notification from the block B2 (step S2403: Yes), ends the series of processes according to this flowchart. To do. As a result, the architecture model AM can be prevented from operating earlier than the reference source RS, and the simulation can be prevented from failing.

(Processing procedure of block Bi in architecture model AM)
Next, the processing procedure of the block Bi in the architecture model AM executed in the simulation of step S2208 shown in FIG. 22 will be described. Here, the processing procedure of the block Bi (block B1, block B2) corresponding to one processing of calc and calc2 to be loop-processed will be described.

  FIG. 25 is a flowchart illustrating an example of the processing procedure of the block Bi. In FIG. 25, the block Bi reads the parameter value from the FIFO buffer corresponding to the block Bi (step S2501). Then, the block Bi performs a calculation process using the read parameter value (step S2502), and ends a series of processes according to this flowchart. Thereby, a calculation process can be performed using the parameter value determined by execution of the reference source RS.

  As described above, the simulation apparatus 100 according to the embodiment includes the process (for example, the function calc) in which the process contents change according to the conditional branch based on the data sequentially selected from the input file based on the reference source RS. A loop process of a series of processes (for example, the function calc and the function calc2) can be executed. Further, according to the simulation apparatus 100, each time the execution of each process included in the series of processes is completed, the parameter value set according to the processing content of the process is changed to the FIFO buffer of the block Bi that realizes the process. (For example, the 0th FIFO and the 1st FIFO) can be written.

  Further, according to the simulation apparatus 100, when execution of a series of processes is completed, the control unit CT in the architecture model AM activates the block Bi that realizes the first process executed in the series of processes. be able to. Further, according to the simulation apparatus 100, the block Bi can read the parameter value from the FIFO buffer provided for the block Bi and execute the calculation process.

  Thereby, it is possible to cause the block Bi to perform a calculation process using the parameter value determined by the execution of the reference source RS, and to reproduce the behavior of the block Bi depending on the algorithm of the reference source RS.

  Further, according to the simulation apparatus 100, each time a series of processes is completed, a FIFO buffer (for example, the control unit CT) accesses a leading degree variable (for example, m_separator_id) indicating that the series of processes is completed. , M_separator). Further, according to the simulation apparatus 100, the control unit CT determines whether or not a series of processes has been executed based on the leading degree variable stored in the FIFO buffer (for example, m_separator), When it is determined that the execution of the process is completed, the block Bi can be activated.

  As a result, the architecture model AM can be prevented from operating earlier than the reference source RS, and the simulation can be prevented from failing.

  Further, according to the simulation apparatus 100, when a predetermined number N or more of the leading degree variables are stored in the FIFO structure buffer accessed by the control unit CT, the leading degree variable stored in the buffer is the predetermined number N. Execution of the loop process can be stopped until the value becomes less than. As a result, when the preceding amount of the reference source RS with respect to the architecture model AM exceeds the upper limit N, it is possible to prevent the leading degree variable from being accumulated in the buffer having the FIFO structure, and to limit the memory amount of the buffer. .

  As described above, according to the simulation program, the simulation method, and the simulation apparatus according to the embodiment, it is possible to perform the architecture simulation by reproducing the behavior of the architecture model AM according to the algorithm of the reference source RS. In addition, the system performance can be evaluated without creating a complex model that divides the reference source RS and contains functions for each block, reducing the number of simulation model creation steps and shortening the simulation period. Can be made.

  The simulation method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The simulation program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The simulation program may be distributed via a network such as the Internet.

  In addition, the simulation apparatus 100 described in the present embodiment includes a specific cell IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic) such as an FPGA. It can also be realized by Device). Specifically, for example, the function of the simulation apparatus 100 (acquisition unit 901 to output unit 904) is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to manufacture the simulation apparatus 100. can do.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1)
Get a reference source that describes the system functions in a programming language.
Obtaining an architecture model including a plurality of blocks for simulating the operation of the system and a control unit for controlling the plurality of blocks;
Based on the reference source, execute a loop process of a series of processes including a process whose process contents change by conditional branching based on data sequentially selected from a data string to be processed,
Each time execution of the processing included in the series of processing is completed, the parameter value set according to the processing content of the processing is written to the buffer accessed by the block that realizes the processing among the plurality of blocks. ,
When the execution of the series of processes is completed by the control unit, the block that realizes the process executed first in the series of processes is activated,
Causing the block to perform a calculation process based on the parameter value by causing the parameter value to be read from a buffer accessed by the block;
A simulation program characterized by causing processing to be executed.

(Supplementary note 2)
Each time the execution of the series of processes is completed, information indicating that the execution of the series of processes is completed is written in a buffer accessed by the control unit,
The control unit determines whether or not the execution of the series of processes is completed based on information stored in a buffer accessed by the control unit,
When the control unit determines that the execution of the series of processes is completed, the block is activated.
The simulation program according to appendix 1, wherein the process is executed.

(Supplementary Note 3) The buffer accessed by the control unit is a FIFO (First In First Out) structure buffer.
In the computer,
The control unit activates the block when the information is stored in a buffer accessed by the control unit.
The simulation program according to appendix 2, wherein the process is executed.

(Supplementary note 4)
When a predetermined number or more of the information is stored in a buffer accessed by the control unit, a process for stopping execution of the loop process is executed until the information stored in the buffer becomes less than a predetermined number The simulation program according to appendix 3, characterized by:

(Appendix 5) The computer
Get a reference source that describes the system functions in a programming language.
Obtaining an architecture model including a plurality of blocks for simulating the operation of the system and a control unit for controlling the plurality of blocks;
Based on the reference source, execute a loop process of a series of processes including a process whose process contents change by conditional branching based on data sequentially selected from a data string to be processed,
Each time execution of the processing included in the series of processing is completed, the parameter value set according to the processing content of the processing is written to the buffer accessed by the block that realizes the processing among the plurality of blocks. ,
When the execution of the series of processes is completed by the control unit, the block that realizes the process executed first in the series of processes is activated,
Causing the block to perform a calculation process based on the parameter value by causing the parameter value to be read from a buffer accessed by the block;
A simulation method characterized by executing processing.

(Supplementary Note 6) A reference source that describes a system function in a programming language, an acquisition unit that acquires an architecture model including a plurality of blocks that simulate the operation of the system and a control unit that controls the plurality of blocks;
Based on the reference source, a loop process of a series of processes including a process whose contents change by a conditional branch based on data sequentially selected from a data string to be processed is executed, and the processes included in the series of processes are executed A first execution unit that writes a parameter value set according to the processing content of the processing to a buffer accessed by a block that realizes the processing among the plurality of blocks,
When the execution of the series of processes is completed by the control unit, the block that implements the process to be executed first of the series of processes is activated, and the parameter is set by the block from the buffer accessed by the block. A second execution unit that executes a calculation process based on the parameter value by reading the value;
A simulation apparatus comprising:

(Appendix 7)
Get a reference source that describes the system functions in a programming language.
Obtaining an architecture model including a plurality of blocks for simulating the operation of the system and a control unit for controlling the plurality of blocks;
Based on the reference source, execute a loop process of a series of processes including a process whose process contents change by conditional branching based on data sequentially selected from a data string to be processed,
Each time execution of the processing included in the series of processing is completed, the parameter value set according to the processing content of the processing is written to the buffer accessed by the block that realizes the processing among the plurality of blocks. ,
When the execution of the series of processes is completed by the control unit, the block that realizes the process executed first in the series of processes is activated,
Causing the block to perform a calculation process based on the parameter value by causing the parameter value to be read from a buffer accessed by the block;
A computer-readable recording medium on which a simulation program for executing processing is recorded.

DESCRIPTION OF SYMBOLS 100 Simulation apparatus 901 Acquisition part 902 1st execution part 903 2nd execution part 904 Output part RS reference source AM Architecture model

Claims (5)

On the computer,
Get a reference source that describes the system functions in a programming language.
Obtaining an architecture model including a plurality of blocks for simulating the operation of the system and a control unit for controlling the plurality of blocks;
Based on the reference source, execute a loop process of a series of processes including a process whose process contents change by conditional branching based on data sequentially selected from a data string to be processed,
Each time execution of the processing included in the series of processing is completed, the parameter value set according to the processing content of the processing is written to the buffer accessed by the block that realizes the processing among the plurality of blocks. ,
When the execution of the series of processes is completed by the control unit, the block that realizes the process executed first in the series of processes is activated,
Causing the block to perform a calculation process based on the parameter value by causing the parameter value to be read from a buffer accessed by the block;
A simulation program characterized by causing processing to be executed. In the computer,
Each time the execution of the series of processes is completed, information indicating that the execution of the series of processes is completed is written in a buffer accessed by the control unit,
The control unit determines whether or not the execution of the series of processes is completed based on information stored in a buffer accessed by the control unit,
When the control unit determines that the execution of the series of processes is completed, the block is activated.
The simulation program according to claim 1, wherein the process is executed. The buffer accessed by the control unit is a FIFO (First In First Out) structure buffer,
In the computer,
The control unit activates the block when the information is stored in a buffer accessed by the control unit.
The simulation program according to claim 2, wherein the process is executed. Computer
Get a reference source that describes the system functions in a programming language.
Obtaining an architecture model including a plurality of blocks for simulating the operation of the system and a control unit for controlling the plurality of blocks;
Based on the reference source, execute a loop process of a series of processes including a process whose process contents change by conditional branching based on data sequentially selected from a data string to be processed,
Each time execution of the processing included in the series of processing is completed, the parameter value set according to the processing content of the processing is written to the buffer accessed by the block that realizes the processing among the plurality of blocks. ,
When the execution of the series of processes is completed by the control unit, the block that realizes the process executed first in the series of processes is activated,
Causing the block to perform a calculation process based on the parameter value by causing the parameter value to be read from a buffer accessed by the block;
A simulation method characterized by executing processing. A reference source describing a function of the system in a programming language; and an acquisition unit that acquires an architecture model including a plurality of blocks that simulate the operation of the system and a control unit that controls the plurality of blocks;
Based on the reference source, a loop process of a series of processes including a process whose contents change by a conditional branch based on data sequentially selected from a data string to be processed is executed, and the processes included in the series of processes are executed A first execution unit that writes a parameter value set according to the processing content of the processing to a buffer accessed by a block that realizes the processing among the plurality of blocks,
When the execution of the series of processes is completed by the control unit, the block that implements the process to be executed first of the series of processes is activated, and the parameter is set by the block from the buffer accessed by the block. A second execution unit that executes a calculation process based on the parameter value by reading the value;
A simulation apparatus comprising:

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