JP2014137833A - Semiconductor memory and method of outputting number of error correction bits - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which even when the number of internal error correction bits increases, the number of bits of a signal that outputs it to the outside can be reduced.SOLUTION: A semiconductor memory includes: a memory array 11; a page buffer 12 that has a plurality of latches that are connected to each bit line of the memory array 11; an error correction circuit 16 that reads a plurality of predetermined bits from the page buffer 12 as an error correction unit, corrects error bits which are included in the read data, and writes it back to the page buffer 12; a determination unit 18 that includes an accumulation circuit, which outputs a result of arithmetic processing over a plurality of units of the error correction unit while holding a result of predetermined processing which is based on the number of error correction bits for each error correction unit, and a comparison circuit which performs comparison between the output of the accumulation circuit and a predetermined reference value and outputs a comparison result; and an output buffer 17 that outputs the comparison result obtained by the comparison circuit.

Description

  The present invention relates to a semiconductor memory and an error correction bit number output method.

  A NAND flash memory having a configuration in which a plurality of memory cells are connected in series is excellent in terms of high integration. On the other hand, the flash memory has a limited number of write operations due to its structure. For this reason, a technique has been developed in which an internal flash memory chip or an external flash memory controller has an error correction function using, for example, ECC (Error Correcting Code). In addition, a technique has been developed in which a bit in which written data and read data do not match (that is, a fail bit) is counted, and a block in which defective cells are generated to a certain extent is replaced with a redundant block or the like.

  For example, the semiconductor memory described in Patent Document 1 has a configuration in which an expected value input from the outside is compared with data read from a memory cell and the number of fail bits is counted. In addition, the semiconductor memory described in Patent Document 2 has a configuration in which data at the time of programming is true, the read data is compared, and a fail bit is counted. These two semiconductor memories have a function for determining whether a cell defect is within a range allowed by a system (mainly ECC) using the number of fail bits. On the other hand, the semiconductor memories described in Patent Document 3 and Patent Document 4 described below are provided with an ECC correction function inside the semiconductor chip.

  For example, a semiconductor memory described in Patent Document 3 includes an error correction circuit and a configuration for replacing an address of a defective cell in a chip. This semiconductor memory stores the row coordinates and column coordinates of memory cells that have been error-corrected by an error correction circuit. When the number of error correction bits on one column line exceeds a predetermined value, one column line is replaced with a redundant cell.

  The semiconductor memory described in Patent Document 4 includes an error correction circuit inside the chip, and has a configuration for outputting an error correction status (that is, a state) to the outside. When a status read command is input from the outside, the number of bits corrected using the lower 3 bits of the input / output terminal and data indicating that error correction is impossible are output (for example, paragraph 0220 of Patent Document 4). To 0221, 0261 to 0262, Table 4, etc.). Further, the operation of the error correction circuit can be confirmed externally by outputting check data and parity data (paragraph 0226 of Patent Document 4).

JP 2002-197898 A JP 2009-134849 A JP 2007-052884 A JP 2001-014888 A

  In a NAND flash memory that does not have an ECC correction function inside, it is difficult to guarantee complete data with a single chip. Therefore, data has been guaranteed by adding an ECC (error correction) function to the outside (mainly a NAND controller). However, as the manufacturing process is miniaturized, the error rate of the NAND chip alone increases as the memory cell size decreases. In the case of using a NAND chip with further miniaturization, it is necessary to change to an ECC system having a high correction capability corresponding to a high error rate. This system change naturally involves development costs and modification risks. Providing NAND chips with low error rates (those that are not miniaturized) so that there is no need to change the system leads to an increase in manufacturing costs.

  As one of the solutions, there is a method of mounting an ECC function on a NAND chip on-chip. This makes it possible to reduce the error rate by error correction even in a NAND chip that has been miniaturized. If this on-chip ECC / NAND flash memory is used, it is possible to replace the leading-edge process with a NAND flash memory without changing the external ECC system (or without the ECC system).

  For example, when an external ECC in a NAND controller or the like has a lower capability than an on-chip ECC, the correction capability by the ECC is determined by the on-chip ECC. In this case, the on-chip ECC / NAND flash memory is basically premised on an error-free operation.

  On the other hand, the NAND controller is provided with various management functions in order to maintain data reliability. It is well known that a block in which erasing / writing is repeated a predetermined number of times is made unusable because deterioration is predicted. For example, when the maximum number of bits that can be corrected by ECC is reached (approached), the reliability of data can be maintained by performing processing such as replacement with another block after correction. Consider a combination of a NAND controller with a relatively small number of ECC correction bits and a NAND flash memory with a large number of correction bits. In this case, in the case of an on-chip ECC / NAND flash memory, the on-chip ECC / NAND flash memory operates error-free when viewed from the NAND controller. For this reason, it is difficult for the NAND controller to predict data deterioration from the frequency of error occurrence. Therefore, the management function described above does not substantially function. As a result, even if the data is deteriorated (that is, even if the number of error correction bits is increased), the replacement is not performed, and the deterioration progresses and an uncorrectable error occurs. In this state, the on-chip ECC / NAND flash memory is expected to output more error bits than the built-in ECC maximum correction capability number. Of course, in this state, the external system does not have a means for correcting these many error bits, and it can be expected that a situation of data destruction will occur. The problem is that since it operates as error free before error correction becomes impossible, the degree of data degradation is unknown from the outside and cannot be managed. For this reason, there is a problem in that the deterioration progresses over time, and many error bits that cannot be corrected suddenly are generated.

  In addition, in the semiconductor memory described in Patent Document 3, column (Column) lines in which errors frequently occur in ECC are replaced. This configuration is expected to be effective as a means for improving reliability. However, in order to replace the column line, it is necessary to write the replacement information into the memory cell. In particular, in the NAND flash memory, writing takes longer than the read operation. Therefore, when and at what timing the replacement information is written becomes a problem.

  Further, the semiconductor memory described in Patent Document 3 has a problem that a device busy period for writing replacement information occurs, and there is a high possibility that an inconvenience occurs in an existing system.

  On the other hand, in the semiconductor memory described in Patent Document 4, a signal indicating the number of bits in which an error has occurred is output as a status signal. Therefore, when the number of bits that can be corrected is increased, there is a problem that the number of signals for outputting the status increases.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory and an error correction bit number output method capable of solving the above-described problems.

  In order to solve the above problems, a semiconductor memory according to the present invention includes a memory array, a page buffer having a plurality of latches connected to each bit line of the memory array, and a predetermined plurality of bits from the page buffer as error correction units. An error correction circuit that corrects an error bit included in the read data and writes it back to the page buffer, while holding a result of a predetermined calculation process based on the number of error correction bits for each error correction unit, An accumulation circuit that outputs a result of arithmetic processing over a plurality of units of the error correction unit, a comparison circuit that compares the output of the accumulation circuit with a predetermined reference value and outputs a comparison result, and the comparison circuit And an output circuit for outputting a comparison result.

  In another semiconductor memory according to the present invention, the predetermined arithmetic processing is processing for obtaining a maximum value of the number of error correction bits for each of the plurality of error correction units.

  In another semiconductor memory of the present invention, the predetermined calculation process is a process for obtaining a total value of the number of error correction bits for each of the plurality of error correction units.

  In another semiconductor memory of the present invention, the comparison circuit compares the output of the accumulation circuit with a predetermined plurality of reference values, and outputs the comparison result as a signal indicating the degree of a plurality of stages. It is characterized by doing.

  Another semiconductor memory of the present invention is characterized in that the memory array is plural and the accumulation circuits are plural.

  Another semiconductor memory according to the present invention is characterized in that the accumulation circuit is shared by a fail bit counter for counting the number of fail bits.

  In another semiconductor memory of the present invention, the output circuit outputs a comparison result by the comparison circuit by using predetermined bits of the plurality of bits of data read from the page buffer as error data. It is characterized by doing.

  In another semiconductor memory of the present invention, the output circuit outputs a comparison result by the comparison circuit in response to a status command input from the outside.

  According to another aspect of the present invention, there is provided an error correction bit number output method comprising: a memory array; a page buffer having a plurality of latches connected to each bit line of the memory array; and a predetermined plurality of bits from the page buffer as error correction units. An error correction circuit that corrects an error bit included in the read data and writes it back to the page buffer, while holding a result of a predetermined calculation process based on the number of error correction bits for each error correction unit, Using an accumulation circuit that outputs a result of arithmetic processing over a plurality of units of the error correction unit, and a comparison circuit that compares the output of the accumulation circuit with a predetermined reference value and outputs a comparison result, The comparison result of the comparison circuit is output from the output circuit.

  In the semiconductor memory of the present invention, the accumulation circuit outputs the result of the arithmetic processing over a plurality of units of the error correction unit while holding the result of the predetermined arithmetic processing based on the number of error correction bits for each error correction unit. The comparison circuit compares the output of the accumulation circuit with a predetermined reference value and outputs a comparison result. Then, the output circuit outputs a comparison result by the comparison circuit. According to this configuration, the comparison result from the comparison circuit is output from the output circuit. Therefore, even if the number of error correction bits increases, the number of bits of the output signal, which is a signal indicating the error correction state, can be easily reduced by reducing the number of bits of the signal indicating the comparison result by the comparison circuit. Can do.

  Note that the above effect can be obtained when the predetermined arithmetic processing is processing for obtaining the maximum number of error correction bits for each of a plurality of error correction units, or when the predetermined arithmetic processing is performed for error correction for a plurality of error correction units. The same applies to the processing for obtaining the total value of the number of bits.

  Further, when the comparison circuit compares the output of the accumulation circuit with a plurality of predetermined reference values and outputs the comparison result as a signal indicating the degree of a plurality of stages, the signal indicates an error correction state. By appropriately setting the number of bits of the output signal, it is possible to output the error correction state in more detail without greatly increasing the number of bits.

  Further, by providing a plurality of memory arrays and a plurality of accumulation circuits, it is possible to appropriately output an error correction state to the outside even in a large-capacity semiconductor memory in which the number of memory cells is increased.

  Further, when the accumulation circuit is shared by a fail bit counter that counts the number of fail bits, the circuit area and the like can be easily reduced as compared with the case where both are configured separately.

  In another semiconductor memory of the present invention, the output circuit outputs a comparison result by the comparison circuit by using predetermined bits of the plurality of bits of data read from the page buffer as error data. According to this configuration, when the management function by an external flash memory controller or the like having an ECC correction function and a block replacement function at the time of data deterioration and the semiconductor memory of the present invention are combined, the following effects are obtained. . That is, with this configuration, for example, a number of bits different from the number of error correction bits detected in the semiconductor memory can be forcibly output as error data. For example, when the error correction capability of the external management function is lower than the error correction capability of the error correction circuit included in the semiconductor memory of the present invention, the number of error bits to be output is within the external error correction capability and the deterioration is to some extent. Set the number of bits as it occurs. In this case, the error can be corrected by an external management function, and processing such as block replacement can be performed.

  In addition, the output circuit outputs the comparison result by the comparison circuit according to the status command input from the outside, so that the output of the comparison result can be used without significant change in the management function by the external flash memory controller etc. Is possible.

1 is a block diagram illustrating a configuration of a semiconductor memory according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a plurality of page buffer units provided in the page buffer 12 illustrated in FIG. 1. FIG. 2 is an explanatory diagram showing an example of an error correction unit used in the semiconductor memory 1 shown in FIG. 1. It is the block diagram which showed the structural example of the determination part 18 shown in FIG. 5 is a timing chart for explaining an operation example of a determination unit 18 shown in FIG. 4. It is the block diagram which showed the other structural example (In FIG. 6, the determination part 18a) of the determination part 18 shown in FIG. It is a timing chart for demonstrating the operation example of the determination part 18a shown in FIG. It is the graph which showed the other example of the output signal of the determination part 18a shown in FIG. 2 is a block diagram illustrating an example of a combination of a determination unit 18 and an error correction circuit 16 illustrated in FIG. 1 and a fail bit detection block 21 (not illustrated in FIG. 1). FIG. 2 is a circuit diagram illustrating a configuration example of an output buffer 17 illustrated in FIG. 1. 6 is a chart showing another example of an output signal of the output buffer 17 shown in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a NAND flash memory according to an embodiment of the present invention. A NAND flash memory 1 includes a memory array 11, a page buffer (PB (Page Buffer)) 12, a column coding circuit A (Column Coding A) 13, and a column coding circuit B (Column Coding B). 14, an address control circuit (Address Control) 15, an error correction circuit (ECC) 16, an output buffer 17, a determination unit 18, and an input / output pad (I / O PAD) 19.

  The memory array 11 includes a plurality of memory cells (that is, memory cell transistors) arranged in an array. The drains and sources of the plurality of memory cells are connected in series, and the drains and sources at both ends are connected to the bit line and the source line via a selection transistor. The gates of the plurality of memory cells in each column are connected by a plurality of word lines in the row direction.

  The page buffer 12 includes a plurality of latches and sense amplifiers respectively connected to a plurality of bit lines included in the memory array 11. The page buffer 12 is composed of, for example, about 512 to several thousand page buffer units. However, the number of page buffer units changes as the memory capacity changes. FIG. 2 illustrates the configuration of the page buffer unit. Each page buffer unit 50 shown in FIG. 2 is connected with eight bit lines (BL) of the memory array 11. There are latches 51_0 to 51_7 for each bit line, and each of the latches 51_0 to 51_7 holds data to be written from the memory array 11 to the read / memory array 11. Each of the latches 51_0 to 51_7 is connected to a multiplexer (MUX) 52, and is one of eight bit lines according to a sub bit line coding signal (Sub BL Coding) generated by an internal control circuit (not shown). Is selected and connected to a page buffer control circuit (PB Control Circuit) 53. The page buffer control circuit 53 connects the multiplexer 52 and the error correction circuit 16 or the input / output pad 19 in accordance with a coding signal (Coding). The page buffer control circuit 53 is a circuit combining a part of the column coding circuit A13 and a part of the column coding circuit B14. The coding signal (Coding) is generated based on the address A signal (Address A) or the address B signal (Address B).

  The column coding circuit A13 is a circuit that selects the page buffer unit 50 in the page buffer 12 corresponding to the input address A signal (Address A) and inputs / outputs data. The column coding circuit A13 is a circuit corresponding to a plurality of page buffer control circuits 53 in FIG.

  Note that data is transferred between the column coding circuit A13 and the input / output pad 19 and between the column coding circuit A13, the input / output pad 19 and the output buffer 17, for example, by a bus composed of about 8 (or 16) signal lines. Done with.

  The address control circuit 15 generates an address A signal representing an address at which data is to be read / written and sends the signal to the column coding circuit A13.

  The input / output pad 19 exchanges data (Data) with an external device such as a NAND controller. Data input from the input / output pad 19 is sent to the column coding circuit A13. The data output from the output buffer 17 is output from the input / output pad 19.

  The error correction circuit 16 reads a predetermined plurality of bits as an error correction unit from the page buffer 12 via the column coding circuit B14, corrects the error bits included in the read data, and again passes through the column coding circuit B14. This is a circuit for writing back to the page buffer 12. For example, as shown in FIG. 3, the error correction unit may be a sector obtained by dividing a page in the memory array 11 into a predetermined plurality. Here, FIG. 3 is an explanatory diagram for explaining an error correction unit. FIG. 3 schematically shows data of one page (that is, a plurality of memory cells selected by the same word line) stored in the page buffer 12 as a unit of reading from the memory array 11. ing. In the example shown in FIG. 3, one page (P0) of the memory array 11 is divided into four ECC sectors (ECC Sector) 0 to 3 (ES0 to ES3). The error correction circuit 16 reads data from the page buffer 12 via the column coding circuit B14 for each ECC sector in order from the ECC sector 0 to the ECC sector 3, and corrects error bits included in the read data, The data is written back to the page buffer 12 again through the column coding circuit B14.

  The error correction circuit 16 generates an address signal B representing a read / write address in the page buffer 12 and outputs it to the column coding circuit B14. By this address signal B, one of ECC sectors 0 to 3 to be processed is selected. In this embodiment, the error correction circuit 16 outputs the number of errors per sector ED [3: 0] to the determination unit 18. The number of errors per sector ED [3: 0] is a signal representing the number of error correction bits (that is, the number of error detection bits) for each error correction unit. For example, the number of errors per sector ED [3: 0] is a binary 4-bit signal including the third to 0th bits. Further, the error correction circuit 16 outputs an ECC clock signal ECC_CLK indicating the update timing of the number of errors per sector ED [3: 0] to the determination unit 18. For example, when error detection / correction is continuously performed for a number of ECC sectors, this clock signal is used to synchronize with the timing at which the number of errors per sector ED [3: 0] is switched on a sector basis. Can do.

  The number of bits that can be corrected by the error correction circuit 16 varies depending on the error correction method and the number of redundant bits. The number of error bits is two in the Hamming code, 0 bit or 1 bit. In BCH (Bose-Chudhuri-Hocquenhem) code, the number of bits that can be detected with errors varies. In this embodiment, a BCH code capable of detecting an error of up to 8 bits per sector is used as an example, and the number of error correction bits (= number of detected bits) is a 4-bit binary number ED [3: 0] as described above. It shall be expressed as

  For example, when ED [3: 0] = 0000b, a 0-bit error occurs, and when ED [3: 0] = 0101b, a 5-bit error occurs. Here, b after the number indicates a binary number. It is known that the number of error bits can be calculated from the syndrome, and a description of the mechanism is omitted.

  The column coding circuit B14 is a circuit that selects the page buffer unit 50 in the page buffer 12 corresponding to the input address B signal (Address B) and inputs / outputs data.

  The output buffer 17 is a circuit for outputting the determination result of the determination unit 18 to the input / output pad 19 and outputting the data read from the page buffer 12 via the column coding circuit A13 to the input / output pad 19. .

  The determination unit 18 performs predetermined arithmetic processing based on the error detection bit number ED [3: 0], and compares the result of the arithmetic processing with a predetermined reference value (that is, a threshold value), thereby obtaining data (that is, a memory cell). This is a circuit for determining whether or not the battery has deteriorated. For example, the determination unit 18 holds a result of a predetermined arithmetic processing based on the number of error detection bits (that is, the number of error correction bits) for each error correction unit (that is, for each sector), and performs arithmetic processing over a plurality of error correction units. The accumulation circuit that outputs the result of the above and the comparison circuit that compares the output of the accumulation circuit with a predetermined reference value and outputs the comparison result can be used. FIG. 4 shows an example of the configuration of the determination unit 18.

  FIG. 4 is a block diagram illustrating a configuration example of the determination unit 18 illustrated in FIG. The determination unit 18 illustrated in FIG. 4 includes an accumulation counter 181 and a comparison circuit 182. The accumulation counter 181 includes an arithmetic unit 1811 and a register 1812. The arithmetic unit 1811 is a circuit that performs addition processing, and adds the data stored in the register 1812 (that is, the output data of the register 1812) and the number of errors per sector ED [3: 0], and the result of addition is added. Is output. The register 1812 is an 8-bit storage circuit and stores the output of the arithmetic unit 1811 in synchronization with the ECC clock signal ECC_CLK. The output of the register 1812 becomes an 8-bit signal AC [7: 0] representing the number of accumulated errors.

  On the other hand, the comparison circuit 182 compares the accumulated error number AC [7: 0] with the 8-bit signal AC_Fail_Bit [7: 0] representing the deterioration determination reference value, and uses the comparison result as the deterioration determination flag AC_Fail signal. Output. The deterioration determination flag AC_Fail signal is a 1-bit signal, and is set to the “Hi” level when the accumulated error number AC [7: 0] is equal to or greater than the deterioration determination reference value AC_Fail_Bit [7: 0].

  Here, with reference to FIG. 5, the operation example of the determination part 18 shown in FIG. 4 is demonstrated. FIG. 5 is a timing chart showing changes in signals of the respective units shown in FIG. 4, and the horizontal axis is a time axis. The signals are, in order from the top, the ECC clock signal ECC_CLK, the number of errors per sector ED [3: 0], the number of accumulated errors AC [7: 0], the degradation determination criterion AC_Fail_Bit [7: 0], and the degradation determination flag AC_Fail. It is. In this case, the degradation criterion AC_Fail_Bit [7: 0] is set to “11” (decimal) = “Bh” (h represents a hexadecimal number). The degradation criterion AC_Fail_Bit [7: 0] can be set, for example, by using a fuse circuit in the manufacturing stage, or by holding a value in a predetermined storage circuit according to a signal input from the outside. Can be.

  The ECC clock signal ECC_CLK changes in synchronization with the switching timing of the number of errors per sector ED [3: 0], and the register 1812 holds the output of the arithmetic unit 1811 (that is, an adder) at the rising timing of the ECC clock signal. . In this example, the number of errors per sector ED [3: 0] is “0” (= 0000b) bits in sector 0, “2” (= 0010b) bits in sector 1, and “8” (= 1000b) in sector 2. It is assumed that the bit is changed to “1” (= 0001b) bit in the sector 3. In this case, at the rising timing of the ECC clock signal ECC_CLK, the accumulated error number AC [7: 0] that is the value held in the register 1812 (ie, the output value) is “0h”, “2h”, “Ah”, and , “Bh”. When the accumulated error number AC [7: 0] becomes “Bh”, since AC [7: 0] ≧ AC_Fail_Bit [7: 0], the comparison circuit 182 sets the deterioration determination flag AC_Fail to the “Hi” level. Output.

  As described with reference to FIGS. 4 and 5, the configuration of the determination circuit 18 compares the total number of error correction bits over a plurality of sectors (that is, error correction units) with a predetermined reference value. It is not limited to the configuration. Furthermore, another configuration example of the determination circuit 18 will be described with reference to FIGS. 6 and 7.

  FIG. 6 is a block diagram showing another configuration example of the determination unit 18 shown in FIG. The determination unit 18a shown in FIG. 6 (configuration corresponding to the determination unit 18 in FIG. 1) includes a maximum value holding register 181a and a comparison circuit 182a. The maximum value holding register 181a includes an arithmetic unit 1811a and a register 1812a. The arithmetic unit 1811a is a circuit that outputs the larger one of the input pair of signals, and the data stored in the register 1812a (that is, the output data of the register 1812a) and the number of errors per sector ED [3 : 0], the larger signal is output. The register 1812a is a 4-bit storage circuit and stores the output of the arithmetic unit 1811a in synchronization with the ECC clock signal ECC_CLK. The output of the register 1812a becomes a 4-bit signal MaxED [3: 0] representing the maximum number of errors for each sector.

  On the other hand, the comparison circuit 182a compares the maximum value MaxED [3: 0] of the number of errors with a 4-bit signal MaxED_Fail_Bit [3: 0] representing the deterioration determination reference value, and compares the comparison result with the deterioration determination flag MaxED_Fail signal. Output as. The deterioration determination flag MaxED_Fail signal is a 1-bit signal, and is set to the “Hi” level when the maximum error number MaxED [3: 0] is equal to or greater than the deterioration determination reference value MaxED_Fail_Bit [3: 0]. This deterioration determination criterion MaxED_Fail_Bit [3: 0] can be set, for example, selectively using a fuse circuit in the manufacturing stage, or can be set by holding a value in a predetermined storage circuit in accordance with an externally input signal. Can be.

  Here, with reference to FIG. 7, an operation example of the determination unit 18a illustrated in FIG. 6 will be described. FIG. 7 is a timing chart showing changes in signals of the respective units shown in FIG. 6, and the horizontal axis is a time axis. The signals are, in order from the top, the ECC clock signal ECC_CLK, the number of errors per sector ED [3: 0], the maximum number of errors MaxED [3: 0], the degradation determination criterion MaxED_Fail_Bit [3: 0], and the degradation determination flag MaxED_Fail. is there. In this case, the degradation determination criterion MaxED_Fail_Bit [3: 0] is set to “0111b” (binary number) = “7” (decimal number).

  The ECC clock signal ECC_CLK changes in synchronization with the switching timing of the number of errors per sector ED [3: 0], and the register 1812a holds the output of the arithmetic unit 1811a at the rising timing of the ECC clock signal ECC_CLK. In this example, the number of errors per sector ED [3: 0] is “0” (= 0000b) bits in sector 0, “2” (= 0010b) bits in sector 1, and “8” (= 1000b) in sector 2. It is assumed that the bit is changed to “1” (= 0001b) bit in the sector 3. In this case, the maximum error number MaxED [3: 0], which is the value held in the register 1812a (ie, the output value), changes to “0000b”, “0010b”, and “1000b” at the rising timing of the ECC clock signal ECC_CLK. After that, “1000b” is constant. When the maximum error number MaxED [3: 0] becomes “1000b”, MaxED [3: 0] ≧ MaxED_Fail_Bit [3: 0], so the comparison circuit 182a outputs the “Hi” level to the deterioration determination flag MaxED_Fail. To do.

  The maximum value holding register 181a holds and outputs the maximum number of error bits detected in each ECC sector. The comparison circuit 182a determines a pass / fail (Pass / Fail) based on a threshold value MaxED_Fail_Bit [3: 0], in which the maximum value is a fail value (Fail = deteriorated) in advance, and the determination result is a 1-bit flag. Output as MaxED_Fail. However, the maximum value Max ED [3: 0] can be output to the outside via, for example, the output buffer 17 of FIG.

  In this example, when an error of 7 bits or more is detected, it is determined as a failure. The existence of a sector causing an error close to the maximum number of bits that can be corrected is considered likely to become uncorrectable in the future. The configuration shown in FIG. 6 is excellent in that it is possible to construct a configuration that can screen for the existence of such a sector.

  Note that the configuration of the determination unit 18 illustrated in FIG. 1 is not limited to the configuration example described with reference to FIGS. 4 and 6. For example, it can be configured to include both the determination unit 18 shown in FIG. 4 and the determination unit 18a shown in FIG.

  Further, instead of (or in conjunction with) outputting the comparison result as a 1-bit flag from the comparison circuit 182 or the comparison circuit 182a, the comparison result can be output as a multi-bit signal. That is, the comparison circuit 182 or the comparison circuit 182a compares the output of the accumulation counter 181 or the maximum value holding register 181a with a plurality of predetermined reference values, and outputs the comparison result as a signal indicating the degree of a plurality of stages. Can be. For example, if the above-mentioned MaxED [3: 0] is output as it is, 4 bits are required. However, as shown in the correspondence table of FIG. 8, the comparison circuit 182a corresponds to the 2-bit fail status signal FailStatus [ 1: 0]. In this case, the value of 4-bit MaxED [3: 0] can be output in four stages by only 2 bits of FailStatus [1: 0], and the approximate state can be transmitted to the outside. Further, a more detailed state can be expressed than simply outputting as a 1-bit flag.

  The adoption of the configuration of the determination unit 18 does not exclude a configuration in which the number of errors per sector ED [3: 0] itself is output to the outside. That is, for example, by directly connecting the number of errors per sector ED [3: 0] to the output buffer 17, it is possible to output it by including it in a status signal output in accordance with an external predetermined command. . In this case, it becomes possible for the external system to observe ED [3: 0], which is the number of bits detected in the ECC processing process, and it becomes possible to predict data deterioration in detail. Actually, it is preferable that the ECC clock signal ECC_CLK is also output in terms of ease of synchronization.

  Further, the following configuration can be adopted for the determination unit 18 described with reference to FIG. That is, as shown in FIG. 9, the accumulation counter 181 included in the determination unit 18 shown in FIG. 4 can be shared with the fail bit counter that counts the number of fail bits described with reference to Patent Document 1 and the like. Is possible.

  The fail bit detection block 21 shown in FIG. 9 receives the 8-bit expected value data Despect_ext [7: 0] input from the outside at a predetermined address and the 8-bit read from the page buffer 12 when the fail bit is detected. Data Dsense [7: 0] is logically compared, and the number of mismatched bits is output as FBC_ED [3: 0]. The fail bit detection block 21 outputs a plurality of FBC_ED [3: 0] while increasing the address, for example. By summing the number of mismatched bits FBC_ED [3: 0] in a fixed address range, the quality of the address range is determined. Note that the fail bit count clock signal FBC_CLK toggles in synchronization with the timing of address increase or the like. This fail bit detection is performed, for example, in a test mode before product shipment, and is not used during normal operation. Therefore, in the configuration shown in FIG. 9, the counter that sums up the number of mismatched bits FBC_ED [3: 0] is performed by the cumulative counter 181 described with reference to FIG. .

  In the configuration shown in FIG. 9, the ECC clock signal ECC_CLK and the number of errors per sector ED [3: 0], which are the two input signals of the determination unit 18 described with reference to FIG. The signal is input to the determination unit 18 via the multiplexer 23. The outputs of the multiplexer 22 and the multiplexer 23 are connected to the a input side when the selection signal FBC_Mode is at the “Lo” level. On the other hand, the outputs of the multiplexer 22 and the multiplexer 23 are connected to the b input side when the selection signal FBC_Mode is at the “Hi” level. The signal FBC_Mode is a signal set to the “Hi” level when fail bit detection is performed.

  The ECC clock signal output from the error correction circuit 16 is input to the a side input of the multiplexer 22. The number of errors per sector ED [3: 0] output from the error correction circuit 16 is input to the a side input of the multiplexer 23. Further, the fail bit counter clock FBC_CLK output from the fail bit detection block 21 is input to the b-side input of the multiplexer 22. The mismatched bit number FBC_ED [3: 0] output from the fail bit detection block 21 is input to the b-side input of the multiplexer 23.

  In the configuration shown in FIG. 9, when the signal FBC_Mode is at the “Lo” level, the multiplexers 22 and 23 are connected to the a side. In this case, the ECC clock signal ECC_CLK output from the error correction circuit 16 and the number of errors per sector ED [3: 0] are input to the accumulation counter 181. Therefore, the determination unit 18 operates as a deterioration determination mechanism by ECC described with reference to FIGS. 4 and 5.

  On the other hand, when operating as a fail bit counter, a predetermined signal is input to enter the fail bit count mode, and the FBC_Mode signal is set to the “Hi” level. In order to set the FBC_Mode signal to the “Hi” level, a predetermined flag signal may be changed by an external command input, or may be performed by a rewrite operation to a test mode register or the like. When the FBC_Mode signal becomes “Hi” level, the multiplexers 22 and 23 are connected to the b side, that is, the fail bit detection block 21 side. Therefore, the accumulation counter 181 has a bit number that does not match the fail bit counter clock FBC_CLK. FBC_ED [3: 0] is input. The accumulation counter 181 accumulates the number of mismatched bits FBC_ED [3: 0] at the rising timing of the fail bit counter clock FBC_CLK.

  In the configuration example shown in FIG. 9, the reference value for deterioration determination, that is, AC_Fail_Bit [7: 0] that is a fail / path threshold value can also be shared. For example, the initial value may be set to the ECC threshold value, and when entering the fail bit count mode, the fail bit count value may be overwritten in the volatile register storing the AC_Fail_Bit. In this way, it is possible to share the deterioration determination mechanism by ECC and the fail bit count (FBC) with a configuration in which new circuit additions are suppressed to about the multiplexer (MUX).

  Next, a configuration example of the output buffer 17 shown in FIG. 1 will be described with reference to FIG. In the output buffer 17 shown in FIG. 10, the determination unit 18 of FIG. 1 includes the configuration of FIG. 4 and the configuration of FIG. 6, and the determination unit 18 outputs the deterioration determination flag AC_Fail and the deterioration determination flag MaxED_Fail. This is a configuration example. The output buffer 17 shown in FIG. 10 has a state where at least one of the deterioration determination flag AC_Fail or the deterioration determination flag MaxED_Fail becomes “Hi” level (that is, when it is determined that the data read from the memory cell has deteriorated). In this circuit configuration, an error is output to a specific bit (Bit) of a specific address (Address) during a read operation. Specifically, if data deterioration is determined, an error is output to the input / output bits IO0 and IO1 at address 000h, and an error is also output to the input / output bits IO0 and IO1 at address 001h.

  In the circuit of FIG. 10, the signal AC_Fail and the signal MaxED_Fail are input to the two-input OR (OR) circuit 171. The output of the OR circuit 171 is input to one input terminal of a 2-input AND (AND) circuit 173 as a signal ECC_Fail. Further, the signal Add_Match_000h and the signal Add_Match_001h are input to the 2-input OR circuit 172. The output of the OR circuit 172 is input to the other input terminal of the 2-input AND circuit 173 as a signal Add_Match. The output of the 2-input AND circuit 173 is input to one terminal of each of the 2-input exclusive OR circuit 174 and the 2-input exclusive OR circuit 175 as the signal ErrorMake. The signal Data_pre_IO [0] is input to the other terminal of the 2-input exclusive OR circuit 174. The signal Data_pre_IO [1] is input to the other terminal of the 2-input exclusive OR circuit 175. One terminal of each of the six 2-input exclusive OR circuits (group) 176 is connected to the ground (GND), and each other input terminal has one bit of the 6-bit signal Data_pre_IO [7: 2]. Signal is input. The 8-bit exclusive OR circuits 174, 175, and 176 output an 8-bit signal Data_IO [7: 0].

  In the configuration example of the output buffer 17 shown in FIG. 10, the determination of data deterioration is made by correcting the error bit in error correction using the AC_Fail signal and ECC code that becomes “Hi” when the number of accumulated correction bits reaches a certain value. This is realized by OR of the MaxED_Fail signal which becomes “Hi” when the number reaches a specified value (that is, a threshold value), and its output is ECC_Fail.

  Further, the configuration for determining the specific address (Address) is realized by OR of the signal Add_Match_000h which becomes “Hi” when the address during the read operation is 000h and the signal Add_Match_001h which becomes “Hi” when the address is 001h. The output is the signal Add_Match.

  An output obtained by ANDing the signal ECC_Fail and the signal Add_Match is set as a signal ErrorMake. When this is “Hi”, a bit error is forcibly generated. The signal ErrorMake is set to “Hi” when a condition for outputting an error (Error) (ECC_Fail = “Hi” (that is, “degraded” and signal Add_Match = “Hi” (that is, “specific address”)) is satisfied. Become.

  If the signal ErrorMake is at the “Lo” level, the 8-bit data Data_pre_IO [7: 0] read from the page buffer 12 and the 8-bit data Data_IO [7: 0] output to the input / output pad 19 are the same, and error correction is performed. The output data is output to the input / output pad 19 as it is, and the error becomes zero.

  On the other hand, if the signal ErrorMake is at “Hi” level, the polarity of the data Data_pre_IO [7: 0] read from the page buffer 12 is inverted by IO0 and IO1 (that is, Data_pre_IO [0] and Data_pre_IO [1]) and Data_IO [7: 0] and output to the input / output pad 19. Inverting the bits of the corrected true data Data_pre_IO [7: 0] will output an error. In this way, a 2-bit error can be output to 8-bit data of Address000h, and a 2-bit error can also be output to 8-bit data of Address001h.

  In the configuration shown in FIG. 10, an address for outputting an error can be freely designed by changing an address matching condition (that is, a condition that Add_Match is “Hi”). By changing the address range, for example, the number of error bits output in the same block can be changed. In this example, only IO [1: 0] is a circuit that inverts data. However, the number of output error bits can be changed by increasing or decreasing the number of inversion IOs.

  As shown in FIG. 10, the configuration of the output buffer 17 is such that a specific bit is inverted to generate an error. For example, a circuit as shown in FIG. By using it, it is also possible to provide a circuit that outputs a signal representing a deterioration state by switching to normal data in accordance with a specific external command. That is, when a specific command is input from the outside, the data path and the fail status during normal reading and the input / output are switched by switching the deterioration status flag AC_Fail, the deterioration determination flag MaxED_Fail, or the fail status signal FailStatus [1: 0]). It is possible to output to the pad 19.

  Note that the output buffer 17 shown in FIG. 10 is configured to intentionally output erroneous data according to the determination result and degree of deterioration, instead of outputting a status based on the result of deterioration determination. This configuration has a remarkable effect in combination with the following device such as an external NAND controller. This item will be described in detail below with an example of the technical background.

  First, a case where the configuration shown in FIG. 10 is not used will be described. For example, it is assumed that the system A is designed by a NAND controller having a 4-bit / 512-byte ECC (that is, an error correction function capable of correcting a 4-bit error using 512 bytes as an error correction unit) in a certain era. Thereafter, miniaturization of advanced NAND products has progressed, the bit error rate has increased, and an ECC equivalent to 8 bits / 512 bytes has been required to maintain reliability. This advanced NAND product is inexpensive and should be adopted in System A, but for that purpose, it is necessary to replace a NAND controller or the like. However, since this system A is on the market and high compatibility is required, there is a risk in changing the system.

  There is a so-called error-free (Error Free) product that is equipped with ECC inside the NAND flash memory chip, and the price is cheaper than the NAND flash memory chip currently installed in the system A. I decided to replace it. This error-free (Error Free) has a high correction capability that can withstand the error rate (Error Rate) of the leading-edge NAND, for example, ECC such as 8 bit / 512 Byte, in the chip. In this case, the system A has a (relatively low) correction capability such as 4 bits / 512 bytes as described above, a replacement function with a redundant block, and the like by error detection correction of 3 bits or more. Block replacement can be performed.

  However, in the case of an error-free NAND product, errors up to 8 bits / 512 bytes are corrected inside the chip. Therefore, in system A, it is desirable that deterioration progresses inside the memory chip and that the block replacement function is activated. Even in such a state, error detection or correction of 3 bits or more is not performed, and block replacement by the NAND controller substantially does not function.

  On the other hand, when the configuration shown in FIG. 10 is used (in this case, it is assumed that the number of bits to be inverted when an error is intentionally generated is set to 3 bits), as follows: Block replacement by the NAND controller of System A can be expected. That is, in the semiconductor memory of the present invention having the configuration shown in FIG. 10, when the data deterioration is recognized by the ECC function inside the NAND flash memory chip, Bit inversion is performed so that an error is intentionally generated at the time of data reading. And output to the input / output terminal as data IO. In the above setting example, since the system A is a block replacement method based on error detection of 3 bits or more, when the on-chip ECC (that is, the error correction circuit 16) and the determination unit 18 detect the deterioration of the data Data, For example, the data Data is inverted by 3 bits by the output buffer 17 and output to the outside. If the external system has a 3-bit error, it can be corrected and block replacement will be performed.

  It should be noted that how much data Data is to be modified (that is, inverted), for example, in which address area, how many bits are inverted is selectively determined by the ECC capacity of the external system and the configuration of the ECC sector (or ECC code). It is desirable to be able to set. For example, a setting circuit such as a fuse circuit can be provided in the peripheral circuit of the output buffer 17 so that it can be electrically changed in advance.

  The above-described embodiment can be further modified as follows. That is, when the semiconductor memory 1 includes, for example, a plurality of memory arrays 11 that can operate in parallel, or, for example, a configuration including a plurality of memory spaces (memory mat (Mat) or memory bank (Bank)), A plurality of determination units 18, accumulation counters 181 or maximum value holding registers 181a can be provided for each memory array 11 and memory mat (or bank). In this case, even if the semiconductor memory 1 includes a plurality of memory arrays 11 and memory mats, it is possible to hold and output a signal indicating a deterioration state for each memory array 11 and mat (or bank).

  In addition to the determination performed by the determination unit 18, for example, the accumulated result of the number of error bits and the comparison result of the comparison circuit are held in page units, block units, memory array 11 units, memory mat units, and the like. By providing the register, it is possible to output the degradation determination result in page units, block units, memory array 11 units, memory mat units, or the like.

  Note that, as described above, the output buffer 17 can be a circuit that switches and outputs a signal representing a deterioration state with normal data in accordance with a specific external command. In this case, for example, as shown in FIG. 11, a signal indicating a degradation state can be output using unused bits of output data for an existing status read command. Since this configuration is an extended configuration (that is, upward compatible) of the current general specification, a highly compatible system can be provided. That is, a status command is generally prepared for a memory product such as a NAND flash memory. Also, in a general NAND flash memory, a plurality of bits are unused in 8-bit data output in response to a status command. Therefore, the output buffer 17 outputs information indicating the deterioration state calculated according to the number of error corrections (or the number of detections) on unused bits. In the example shown in FIG. 11, the data output signals IO [0], [1], [2], [3], [4], and [5] are not used at the time of reading. Thus, it is defined that information indicating the degree of deterioration of the data Data is output to the outside. In this case, since an area not originally defined in the specification is used, even a controller that does not support this extended function has a low possibility of inducing a malfunction.

  In the example of assignment shown in FIG. 11, data signals IO [0], [1], [2], [3], [4], [5] are output as status data output at the time of reading for the status command (“70h”). ] Is defined as follows. IO [0] represents the result of accumulating the number of error corrections in the entire chip as Pass / Fail (Pass: “0”, Fail: “1”). IO [1] and IO [2] are error corrections, assuming that the semiconductor memory has two memory mats, IO [1] for the first mat and IO [2] for the second mat. The result of accumulating the number is expressed as Pass / Fail (Pass: “0”, Fail: “1”). IO [5: 3] represents the maximum number of error corrections for each page as 3-bit data. Here, “Pass” indicates no deterioration, and “Fail” indicates deterioration detection. According to the allocation shown in FIG. 11, the maximum number of error bits in the ECC sector in the page is output as IO [5: 3]. In this way, deterioration information can be output in a so-called Pass / Fail format, or information according to a more detailed number of error detection bits can be output.

  According to the configuration of the embodiment of the present invention described above, the following effects can be obtained. That is, when an error correction circuit (ECC) is mounted on-chip in a semiconductor memory and operated without error, the result of performing a predetermined accumulation process on the number of error detection bits (or the number of correction bits) is further obtained. Based on the result of comparison with a predetermined reference value, the degree of deterioration of internal data (ie, memory cell) can be output to an external system by the occurrence of a status signal or intentional bit error. The NAND brush memory deteriorates when Erase / Program is repeated. However, if error correction is performed on-chip, the NAND brush memory behaves as error-free and cannot be estimated from data Data that appears outside. However, if the present invention is used, it can be output to the outside when a data error starts to occur to some extent. At this time, even if the number of error correction bits increases, the number of bits of data to be output to represent the status can be reduced. Therefore, the replacement function by an external NAND controller can be used effectively.

  The embodiments of the present invention are not limited to the above-described ones. For example, changes such as providing a plurality of circuit blocks to operate in parallel or increasing or decreasing the number of bits of each signal described are appropriately implemented. can do.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory 11 Memory array 12 Page buffer 13 Column coding circuit A
14 Column coding circuit B
15 Address control circuit 16 Error correction circuit 17, 17a Output buffer 18, 18a Determination unit 19 I / O pad 174, 175 2-input exclusive OR circuit 181 Accumulation counter 181a Maximum value holding register 182, 182a Comparison circuit 21 Fail bit detection block

Claims (9)

A memory array;
A page buffer having a plurality of latches connected to each bit line of the memory array;
An error correction circuit that reads a predetermined plurality of bits from the page buffer as an error correction unit, corrects an error bit included in the read data, and writes the error bit back to the page buffer;
An accumulation circuit that outputs a result of arithmetic processing over a plurality of units of the error correction unit while holding a result of predetermined arithmetic processing based on the number of error correction bits for each error correction unit;
A comparison circuit that compares the output of the accumulation circuit with a predetermined reference value and outputs a comparison result;
An output circuit for outputting a comparison result by the comparison circuit. The semiconductor memory according to claim 1, wherein the predetermined arithmetic processing is processing for obtaining a maximum value of the number of error correction bits for each of the plurality of error correction units. The semiconductor memory according to claim 1, wherein the predetermined calculation process is a process of obtaining a total value of the number of error correction bits for each of the plurality of error correction units. The comparison circuit compares the output of the accumulation circuit with a predetermined plurality of reference values, and outputs the comparison result as a signal representing the degree of a plurality of stages. The semiconductor memory according to any one of the above. A plurality of the memory arrays;
The semiconductor memory according to claim 1, wherein there are a plurality of accumulation circuits. The semiconductor memory according to claim 1, wherein the accumulation circuit is shared by a fail bit counter that counts the number of fail bits. 7. The output circuit outputs a comparison result by the comparison circuit by setting predetermined bits of a plurality of bits of data read from the page buffer as error data. The semiconductor memory according to any one of the above. The semiconductor memory according to claim 1, wherein the output circuit outputs a comparison result by the comparison circuit in accordance with a status command input from the outside. A memory array;
A page buffer having a plurality of latches connected to each bit line of the memory array;
An error correction circuit that reads a predetermined plurality of bits from the page buffer as an error correction unit, corrects an error bit included in the read data, and writes the error bit back to the page buffer;
An accumulation circuit that outputs a result of arithmetic processing over a plurality of units of the error correction unit while holding a result of predetermined arithmetic processing based on the number of error correction bits for each error correction unit;
A comparison circuit that compares the output of the accumulation circuit with a predetermined reference value and outputs a comparison result,
A method for outputting the number of error correction bits, wherein the comparison result by the comparison circuit is output from a predetermined output circuit.

Images