JP2014137831A - Memory device, method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device that can arbitrarily set an initial value and can write and read data.SOLUTION: A memory device 1 comprises: a memory cell array 10 having a plurality of memory cells; a write amplifier 50 that writes data to the memory cell array 10; and a sense amplifier 60 that can read the data from the memory cell array 10. The plurality of memory cells comprise: a plurality of rewritable first memory cells whose storage content is initialized to one logic level when an initialization signal RES becomes active; and a plurality of second memory cells whose storage content is initialized to the other logic level when the initialization signal RES becomes active.

Description

  The present invention relates to a memory device that stores data.

  Conventionally known as a memory device for storing data are an SRAM (Static Random Access Memory) capable of reading and writing data, a ROM (Read Only Memory) capable of reading only, and a flip-flop. In particular, for SRAM, since the data becomes undefined when the power is turned on, a technique for clearing the entire stored contents is known (see Patent Document 1).

Japanese Patent Laid-Open No. 4-92291

By the way, in the digital filter calculation, there is a case where it is desired to change the coefficient data from the initial value. Further, in an electronic device provided with a CPU (Central Processing Unit), the CPU activates the electronic device according to a boot program read from the memory device. In this case, it may be desired to read / write data from / to the address space assigned to the boot program after startup.
However, since ROM cannot write data, the coefficient data cannot be changed even if the initial value of the coefficient data can be set, and the data is not stored in the address space where the boot program is stored. Could not write. In addition, in the SRAM, even if the entire stored contents could be cleared, the initial value could not be freely set in each memory cell, so it was necessary to write the coefficient data once in the SRAM. In order to write and read data to and from the address space assigned to the boot program after startup, change the mapping from the ROM to SRAM after mapping the boot program read from the ROM to the address space. There was a drawback that processing was necessary. In addition, the flip-flop can read and write data and can set an initial value freely, but has a disadvantage that the area is larger than that of SRAM or ROM.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a memory device or the like in which an initial value is arbitrarily set and data can be written and read.

In order to solve the above problems, a memory device according to the present invention is capable of reading and writing data, and includes a memory cell array having a plurality of memory cells, and a writing capable of writing data to the memory cell array. And a read unit capable of reading data from the memory cell array, and the plurality of memory cells have a plurality of rewritable plurals whose stored contents are initialized to one logic level when an initialization signal is activated. It has a first memory cell and a plurality of rewritable second memory cells whose stored contents are initialized to the other logic level when the initialization signal becomes active.
According to the present invention, when the initialization signal becomes active, the plurality of memory cells include the first memory cell initialized to one logic level and the second memory cell initialized to the other logic level. Prepare. Therefore, by arranging the first memory cell and the second memory cell in the memory cell array in a predetermined pattern, the desired data can be developed in the memory device without writing the desired data. In addition, since data can be rewritten in the first memory cell and the second memory cell, data can be read / written after initialization and reading of desired data.

  More specifically, each of the plurality of memory cells is connected between the first bit line and the first node, and controlled to one of an on state and an off state according to the potential of the word line. A second transistor connected between the second bit line and the second node and controlled to one of an on state and an off state according to the potential of the word line; A latch unit provided between the first node and the second node, and each of the plurality of first memory cells receives a logic of the first node when the active initialization signal is supplied. A first initialization unit that initializes the level to one logic level, and each of the plurality of second memory cells is configured to change the logic level of the first node to the other when the active initialization signal is supplied. The second initialization unit that initializes to the logic level of It is preferable to provide.

  The latch unit includes an inverter having an input terminal connected to the first node and an output terminal connected to the second node, an inverter having an input terminal connected to the second node and an output terminal connected to the first node; May be provided. The first initialization unit may be a transistor provided between the second node and a node to which one power supply potential is supplied, or a node to which the first power supply potential and the other power supply potential are supplied. May be a transistor provided between the two. The second initialization unit may be a transistor provided between the second node and the node to which the other power supply potential is supplied, or the node to which the first power supply potential is supplied. May be a transistor provided between the two.

  Next, the method for manufacturing a memory device according to the present invention specifies predetermined data to be held in the memory device when the initialization signal becomes active, and determines the data according to the value of the predetermined data. A pattern for arranging the first memory cell and the second memory cell in a memory cell array is determined, a mask is created based on the determined pattern, a semiconductor chip is created using the mask, and the semiconductor chip is The memory device is manufactured by using the memory device. According to the present invention, it is possible to manufacture a memory device having a memory cell array in which first memory cells and second memory cells are arranged so that predetermined data is retained in the memory device after initialization.

  Next, an electronic apparatus according to the present invention includes the above-described memory device, an initialization signal supply unit that supplies the initialization signal that is active to the memory device when the power is turned on, and a control unit. The controller is configured to read the predetermined initial data from the plurality of first memory cells and the plurality of second memory cells of the memory cell array after supplying the initialization signal to the memory device. The write unit to execute a predetermined process using the predetermined initial data and write data to some or all of the plurality of first memory cells and the plurality of second memory cells. It is characterized by controlling.

  According to the present invention, when the power is turned on, the initialization signal is activated to initialize the memory cell array. Since the memory cell array includes a first memory cell that holds one logic level by initialization and a second memory cell that holds the other logic level, the memory cell array can be read without writing predetermined initial data. Further, since the first memory cell and the second memory cell can be written and read, desired data can be written after the initialization. For example, a boot program corresponds to the predetermined initial data. In this case, the boot program is read and predetermined processing is executed, and new data can be read and written in the memory area where the boot program is expanded by initialization, so that the memory area can be effectively used.

1 is a block diagram showing a configuration of a memory device according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing a first memory cell and its peripheral configuration. FIG. 4 is a circuit diagram showing a second memory cell and its peripheral configuration. It is explanatory drawing which shows an example of the pattern which has arrange | positioned the 1st memory cell and the 2nd memory cell in the memory cell array. It is a flowchart which shows the processing content of a mask creation process. FIG. 11 is an explanatory diagram showing an internal state of the first memory cell in the initialization period. It is explanatory drawing which shows the internal state of the 2nd memory cell in an initialization period. FIG. 6 is an explanatory diagram showing an internal state of a first memory cell in an initial value reading period. It is explanatory drawing which shows the internal state of the 2nd memory cell in an initial value reading period. It is a block diagram which shows the structure of a mobile telephone.

Embodiments according to the present invention will be described below with reference to the drawings.
<1. Configuration of Memory Device>
FIG. 1 is a block diagram showing a main configuration of a memory device 1 according to an embodiment of the present invention. The memory device 1 can read and write data, and is composed of, for example, an SRAM.

The memory device 1 includes a memory cell array 10 provided with a plurality of memory cells corresponding to intersections of a plurality of word lines 13 and a plurality of bit lines 11, and a row address for selecting a word line 13 by decoding a row address Radd. The decoder 20 includes a column address decoder 30 that selects the bit line 11 by decoding the column address Cadd. That is, by selecting the word line 13 and the bit line 11 by the row address decoder 20 and the column address decoder 30, a target memory cell is selected from the plurality of memory cells of the memory cell array 10, and the memory cell is selected. On the other hand, data can be read and written.
In the memory cell array 10, one word line 13 and two bit lines 11 are arranged corresponding to one memory cell. In the following description, when the two bit lines 11 are distinguished, they are referred to as a first bit line 11a and a second bit line 11b.

  Further, the memory device 1 includes an input / output circuit 40 connected to the bit line 11 of the memory cell array 10 and a write signal obtained by amplifying input data Din at the time of writing via the input / output circuit 40 and the bit line 11. And a sense amplifier for amplifying a differential read signal read from the memory cell via the bit line 11 and the input / output circuit 40 and outputting single-ended output data Dout. And an amplifier 60.

  The memory cell array 10 is supplied with an initialization signal RES. The memory cell array 10 includes a first memory cell 10A that is initialized to an initial value “0” and a second memory cell 10B that is initialized to an initial value “1” when the initialization signal RES becomes active. ing. Therefore, according to the memory device 1, when the initialization signal RES is activated, the initial data is held in the memory cell array 10 without writing the input data Din. In other words, the first memory cell 10A and the second memory cell 10B are allocated so that desired initial data can be expanded in the memory cell array 10 when the memory device 1 is initialized.

  FIG. 2 shows the first memory cell 10A and its peripheral configuration. The first memory cell 10A includes a first transistor 14 provided between the first bit line 11a and the first node N1, and a second transistor 15 provided between the second bit line 11b and the second node N2. An inverter 16 having an input terminal connected to the first node N1 and an output terminal connected to the second node N2, an inverter 17 having an input terminal connected to the second node N2 and an output terminal connected to the first node N1, and A transistor 18A is connected to the second node N2 and the drain, and the source is supplied with the low power supply potential VSS.

  In the first memory cell 10A, when the logic level of the second node N2 is L level and the logic level of the first node is H level, the value of data held by the first memory cell 10A is “1”. Become. Conversely, when the logic level of the second node N2 is H level and the logic level of the first node is L level, the value of data held in the first memory cell 10A is “0”.

  Inverters 16 and 17 constitute a latch circuit and hold data. An initialization signal RES that is active at the H level is supplied to the gate of the transistor 18A. When the initialization signal RES becomes active, the transistor 18A is turned on, the second node N2 becomes the low power supply potential VSS, and the logic level of the second node N2 becomes L level. Further, when the initialization signal RES becomes active, the logic level of the first node N1 becomes H level. Therefore, when the initialization signal RES becomes active, the first memory cell 10A holds the initial value “1”. Here, the transistor 18A functions as a first initialization unit that initializes the logic level of the first node N1 to the H level (one logic level) when the active initialization signal RES is supplied. Instead of the transistor 18A, a P-channel transistor may be provided between the first node N1 and a node to which the high power supply potential VDD is supplied, and an initialization signal that is active at the L level may be supplied to the transistor. Good.

The memory cell array 10 includes a precharge circuit 19. One precharge circuit 19 is provided in one row of memory cells. The precharge circuit 19 includes P-channel transistors 191 to 193. A precharge signal PRE that is active at the L level is supplied to the gates of the transistors 191 to 193. When the precharge signal PRE becomes active, the transistors 191 to 193 are turned on, and the high power supply potential VDD is supplied to the first bit line 11a and the second bit line 11b. As a result, the first bit line 11a and the second bit line 11b are precharged.
The first bit line 11 a is connected to the positive input terminal of the sense amplifier 60, and the second bit line 11 b is connected to the negative input terminal of the sense amplifier 60.

  FIG. 3 shows the configuration of the second memory cell 10B. The second memory cell 10B is configured in the same manner as the first memory cell 10A, except that the transistor 18B connected to the first node is used instead of the transistor 18A connected to the second node N2. When the initialization signal RES becomes active, the transistor 18B is turned on, the first node N1 becomes the low power supply potential VSS, and the logic level of the first node N1 becomes L level. When the initialization signal RES becomes active, the logic level of the second node N2 becomes H level. Therefore, when the initialization signal RES becomes active, the second memory cell 10B holds the initial value “0”. Here, when the active initialization signal RES is supplied, the transistor 18B functions as a second initialization unit that initializes the logic level of the first node N1 to the L level (the other logic level). Instead of the transistor 18B, a P-channel transistor may be provided between the second node N2 and a node to which the high power supply potential VDD is supplied, and an initialization signal that is active at the L level may be supplied to the transistor. Good.

  FIG. 4 shows an example of an arrangement pattern in the memory cell array 10 in which the first memory cell 10A and the second memory cell 10B are arranged. In the figure, the memory cell indicated by “1” is the first memory cell 10A, and the memory cell indicated by “0” is the second memory cell 10B. Thus, in the memory cell array 10, when the initialization signal RES is activated, the first memory cell 10A and the second memory cell 10B are arranged so as to hold a desired initial value. Even without writing, it is possible to develop desired initial data in the memory device 1.

<2. Manufacturing Method of Memory Device>
Next, a method for manufacturing the memory device 1 will be described. The manufacturing method of the memory device 1 is roughly divided into a mask creation process, a semiconductor process process, and a mold process. In the mask creation process, a mask used in the semiconductor process is created. In semiconductor process processing, transistors and wirings are formed on a silicon substrate using the created mask to manufacture a semiconductor chip. In the molding process, the semiconductor device and the terminal are connected by wire bonding, and then the memory device 1 is manufactured by molding with a mold.

  The mask creation process is performed using a mask creation system. In this process, a mask pattern used for manufacturing a semiconductor chip of the memory device 1 is created. FIG. 5 shows a flowchart of a mask creation process executed by the mask creation system. The CPU of the mask creation system reads initial data (step S1). The initial data is data held in the memory cell array 10 by supplying the initialization signal RES to the memory cell array 10.

  Next, the CPU determines whether to arrange the first memory cell 10A or the second memory cell 10B according to the initial data values “1” and “0” (step S2). Thereafter, the CPU generates mask data (step S3). The mask creation system stores mask pattern data corresponding to basic circuit blocks. The first memory cell 10A and the second memory cell 10B are included in the circuit block described above. Therefore, when the arrangement of the first memory cell 10A and the second memory cell 10B is determined in step S2, the mask data of the memory cell array 10 is determined accordingly. Thereafter, the CPU performs exposure according to the mask data to create a mask (step S4). The mask thus created is used for semiconductor process processing.

<3. Operation of Memory Device>
Next, the operation of the memory device 1 will be described.
FIG. 6 shows the internal state of the first memory cell 10A in the initialization period. First, in the initialization period, the initialization signal RES becomes active (H level), and the transistor 18A is turned on. As a result, the logic level of the second node N2 becomes L level, while the logic level of the first node N1 becomes H level. In the initialization period, the precharge signal PRE is active (L level), and the transistors 191 to 193 are turned on in the precharge circuit 19 shown in FIG. As a result, as shown in FIG. 6, the first bit line 11a and the second bit line 11b are precharged with an H level potential. In the initialization period, the word line 13 is not selected, and the potential of the word line 13 is at the L level. As a result, the first transistor 14 and the second transistor 15 are turned off.
On the other hand, in the second memory cell 10B, as shown in FIG. 7, the transistor 18B is turned on, while the first transistor 14 and the second transistor 15 are turned off. As a result, the logic level of the first node N1 becomes L level, while the logic level of the second node N2 becomes H level.

FIG. 8 shows the internal state of the first memory cell 10A in the initial value reading period. In the initial value reading period following the initialization period, the initialization signal RES is inactive (L level), and the transistor 18A is turned off. In addition, since the word line 13 is selected and its potential becomes H level, the first transistor 14 and the second transistor 15 are turned on. As a result, the potential of the first bit line 11a becomes the same H level as that of the first node N1, while the potential of the second bit line 11b becomes the same L level as that of the second node N2.
FIG. 9 shows the internal state of the second memory cell 10B in the initial value reading period. In the initial value reading period, the transistor 18B is turned off, while the first transistor 14 and the second transistor 15 are turned on. As a result, the potential of the first bit line 11a becomes the same L level as that of the first node N1, while the potential of the second bit line 11b becomes the same H level as that of the second node N2.

  As described above, the first memory cell 10A can read a signal whose output data Dout has a value of “1”, and the second memory cell 10B can output a signal whose output data Dout has a value of “0”. Can be read. When writing predetermined data to the first memory cell 10A and the second memory cell 10B, the initialization signal RES and the precharge signal PRE are deactivated to select the word line 13. When the data value “1” is written, the write amplifier 50 supplies an H level write signal to the first bit line 11 a via the input / output circuit 40 based on the input data Din. On the other hand, an L level write signal is supplied to the second bit line 11b. On the other hand, when the data value “0” is written, an L level write signal is supplied to the first bit line 11a, while an H level write signal is supplied to the second bit line 11b. Thereby, predetermined data can be written into the memory cell array 10.

  As described above, the memory device 1 is composed of an SRAM that can rewrite data, and holds the predetermined data in the memory cell array 10 without writing data by activating the initialization signal RES. can do. Further, since the first memory cell 10A and the second memory cell 10B are rewritable, after the retained data is used for processing, the memory area can be released and other data can be read and written. For this reason, the memory area can be used effectively.

<4. Electronic equipment>
Next, an electronic apparatus using the memory device 1 described above will be described. In this embodiment, a mobile phone is taken as an example of an electronic device, but the present invention is not limited to the mobile phone.
FIG. 10 shows a block diagram of the mobile phone 100. As shown in the figure, the mobile phone 100 functions as a control center for the memory device 1, the communication device 2 that communicates with the mobile communication network including the base station, the display 3, the speaker 4, and the mobile phone 100. A CPU 5 and an initialization circuit 6 are provided.

  When the power is turned on, the initialization circuit 6 detects this and supplies an initialization signal RES to the memory device 1. When the power is turned on, the initialization signal RES becomes active and the memory device 1 is initialized. Predetermined data is expanded in the memory device 1 by initialization. In this example, when the initialization signal RES is supplied, the arrangement of the first cell array 10A and the second cell array 10B is determined so that the boot program is expanded in the memory device 1. After the memory device 1 is initialized and the boot program is expanded in the memory cell array 10, the CPU 5 reads the boot program from the memory device 1 and executes processing.

  In general, a boot program is required immediately after power-on, and is not required during normal operation of an electronic device. Therefore, the CPU 5 uses part or all of the memory area where the boot program is expanded by initialization as an operation area as necessary, and stores various calculation results.

  Also, what is expanded by initialization is not limited to the boot program. For example, in the calculation of the digital filter, there are cases where it is desired to make the coefficient variable instead of fixing the coefficient. When the memory device 1 is composed of a simple SRAM, it cannot be initialized, so that it is necessary to write coefficient data first even if the data can be rewritten. On the other hand, in the electronic apparatus according to the present embodiment, the initial value of the coefficient data can be expanded in the memory cell array 10 only by initializing the memory device 1, and the coefficient data is rewritten as necessary. be able to.

  In the above-described embodiment, the first memory cell 10A and the second memory cell B having the initialization function are assigned to all of the memory cell array 10, but the present invention is not limited to this, and the memory The first memory cell 10 </ b> A and the second memory cell 10 </ b> B may be assigned to a part or all of the cell array 10. When the first memory cell 10A and the second memory cell 10B are allocated to a part of the memory cell array 10, a memory cell having no initialization function may be allocated to the other part of the memory cell array 10. Such a memory cell may be configured by removing the transistor 18A from the first memory cell 10A shown in FIG.

DESCRIPTION OF SYMBOLS 1 ... Memory device, 10 ... Memory cell array, 40 ... I / O circuit, 50 ... Write amplifier (writing part), 60 ... Sense amplifier (reading part), RES ... Initialization signal, 10A ... ... 1st memory cell, 10B ... 2nd memory cell, 11 ... Bit line, 11a ... 1st bit line, 11b ... 2nd bit line, 13 ... Word line, 14 ... 1st transistor, 15 2nd transistor 16, 17 ... Inverter, 18A, 18B ... Transistor (initialization unit), N1 ... 1st node, N2 ... 2nd node.

Claims (4)

A memory device capable of reading and writing data,
A memory cell array having a plurality of memory cells;
A writing unit capable of writing data to the memory cell array;
A reading unit capable of reading data from the memory cell array,
The plurality of memory cells include
When the initialization signal becomes active, a plurality of rewritable first memory cells whose stored contents are initialized to one logic level, and
A plurality of rewritable second memory cells whose stored contents are initialized to the other logic level when the initialization signal is activated;
A memory device. Each of the plurality of memory cells includes
A first transistor connected between the first bit line and the first node and controlled to one of an on state and an off state according to the potential of the word line;
A second transistor connected between the second bit line and the second node and controlled to one of an on state and an off state in accordance with the potential of the word line;
A latch unit provided between the first node and the second node;
Each of the plurality of first memory cells includes:
A first initialization unit configured to initialize the logic level of the first node to one logic level when the active initialization signal is supplied;
Each of the plurality of second memory cells includes:
A second initialization unit that initializes the logic level of the first node to the other logic level when the active initialization signal is supplied;
The memory device according to claim 1. A manufacturing method of a memory device according to claim 1,
The predetermined signal to be held in the memory device is specified by the initialization signal being activated,
Determining a pattern for arranging the first memory cell and the second memory cell in the memory cell array according to a value of the predetermined data;
Create a mask based on the determined pattern,
Using the mask, create a semiconductor chip,
Manufacturing the memory device using the semiconductor chip;
A method of manufacturing a memory device. A memory device according to claim 1;
An initialization signal supply unit for supplying the active initialization signal to the memory device when the power is turned on;
A control unit,
The controller is
After supplying the initialization signal to the memory device, the reading unit is controlled to read predetermined initial data from the plurality of first memory cells and the plurality of second memory cells of the memory cell array,
Performing predetermined processing using the predetermined initial data;
Controlling the writing unit to write data to some or all of the plurality of first memory cells and the plurality of second memory cells;
An electronic device characterized by that.

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