JP2014134998A - Data recording device and data recording method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a data recording device that shortens processing time required for writing when parallel writing is carried out in a plurality of NAND flash memories and that prevents missing of data.SOLUTION: A data recording device comprises: a writing function part configured to write data in parallel on a plurality of recording mediums connected on the same bus; an empty block management part configured to register, in an empty block management table, whether a plurality of blocks into which the plurality of recording mediums are divided are empty blocks in which data can be written; and an empty block management part for parallel writings, configured such that empty blocks, informed from the empty block management part, for the number of parallel writings are registered as one group in the empty block management table, empty blocks for the number of parallel writings are acquired from the empty block management table for parallel writings according to a request from the writing function part, and information about the empty blocks is provided.

Description

  The present invention relates to a data recording apparatus for writing in parallel to a plurality of storage media connected to the same bus.

  For example, an artificial satellite is equipped with a data recording device because observation data generated by an observation device needs to be held in the artificial satellite while flying in a range where it cannot communicate with a ground station. The range incapable of communicating with the ground station is, for example, the back side of the earth with respect to the position of the ground station. Since the observation equipment cannot store observation data inside the equipment, it is difficult to realize flow control for data transmission with the data recording device. In addition, with the increase in the definition of observation equipment, the observation data input to the data recording device has increased in size and the amount of data per unit time has increased. However, since the memory that can normally operate in the space environment is limited, the data recording device cannot hold a large-capacity buffer memory. In addition, since the vacuum is used, there is a limitation that heat dissipating means is scarce and the electronic device cannot be operated at high speed.

  Therefore, a large capacity and low power consumption nonvolatile memory such as a NAND flash memory is being mounted on the data recording device. However, the NAND flash memory requires more time for data writing than data reading. Therefore, as the amount of data per unit time transmitted from the observation equipment increases, the data recording time is not in time for one device chip. Therefore, the data recording performance is improved by connecting a plurality of NAND flash memories to the same memory bus and writing in parallel to the plurality of NAND flash memories.

  On the other hand, the file system writes and reads data to and from the NAND flash memory. The file system simply deletes the file on the file management information when deleting the file, and does not erase the actual data itself written in the NAND flash memory. Since the NAND flash memory performs processing without recognizing unnecessary data, the writing speed is reduced and the number of rewrites is increased.

  In Patent Document 1, the file system and the NAND flash memory recognize data management units from each other. Therefore, when writing data, the file system notifies the NAND flash memory of data that can be discarded, and the write speed is improved by suppressing unnecessary data copy processing.

International Publication No. 2009/001514

  However, when writing to a plurality of NAND flash memories in parallel, it is necessary to search for empty blocks in the NAND flash memory by the number of parallel writes, which increases processing time. Also in Patent Document 1, the processing time increases when writing in parallel to a plurality of NAND flash memories. Therefore, when the next data write is requested during the data write, there is a problem that data is lost if there is not enough buffer memory.

  The present invention has been made to solve the above-described problems, and when writing in parallel to a plurality of NAND flash memories, the processing time required for writing is shortened, and data loss does not occur. The object is to obtain a data recording device.

  Write function that writes data to multiple recording media connected on the same bus in parallel, and registers whether or not it is a free block where data can be written for multiple blocks divided into multiple recording media. Register the number of parallel writes for the free block management unit to be used and the free block notified from the free block management unit as one set in the free block management table for parallel writing, and for parallel writing in response to a request from the write function unit An empty block management unit for parallel writing that acquires and notifies empty blocks for the number of parallel writes from the empty block management table.

  According to the present invention, when writing to a plurality of NAND flash memories in parallel, the processing time required for writing can be shortened and data loss can be prevented.

1 is a block diagram showing a basic configuration and connection form of a device chip of a NAND flash memory. 1 is a block diagram showing a basic configuration of a NAND flash memory. The figure which shows the order of the writing process of the data from a data recording device to a device chip. The block diagram which shows the form which connected the several device chip to the data recording device. The figure which shows the order of the write-in process of the data to a several device chip from a data recording device. 1 is a block diagram showing a configuration of a data recording apparatus according to Embodiment 1. FIG. The figure which shows the empty block management table for parallel writing which concerns on Embodiment 1. FIG. 5 is a flowchart showing a flow of processing in an empty block management unit and a parallel writing empty block management unit according to the first embodiment. 5 is a flowchart showing a flow of a search process for a parallel writing free block management table in the parallel writing free block management unit according to the first embodiment; The figure which shows the empty block management table for parallel writing which concerns on Embodiment 1. FIG. The figure which shows the empty block management table for parallel writing which concerns on Embodiment 2. FIG. 12 is a flowchart showing a flow of a search process for a parallel writing free block management table in a parallel writing free block management unit according to the second embodiment; The figure which shows the empty block management table for parallel writing which concerns on Embodiment 2. FIG. The figure which shows the empty block management table for parallel writing which concerns on Embodiment 3. FIG. 10 is a flowchart showing the flow of processing in an empty block management unit and a parallel writing empty block management unit according to the third embodiment. 14 is a flowchart showing a flow of a search process for a parallel writing free block management table in a parallel writing free block management unit according to the third embodiment; The figure which shows the empty block management table for parallel writing which concerns on Embodiment 3. FIG.

Embodiment 1 FIG.
First, the basic structure and control method of the NAND flash memory will be described.

  FIG. 1 is a block diagram showing a basic configuration and connection form of a device chip 11 of a NAND flash memory. The device chip 11 is connected to the data recording device 13 via the memory bus 12. The data recording device 13 records data on the device chip 11. Further, the data recording device 13 reads data from the device chip 11 and erases the data if it is unnecessary.

  The device chip 11 includes a memory interface unit 14, a command processing unit 15, a page buffer 16, and a NAND flash memory 17. The memory interface unit 14 is connected to the data recording device 13 via the memory bus 12 and serves as an input / output interface. The command processing unit 15 processes a command. The page buffer 16 temporarily holds data. In the NAND flash memory 17, memory elements that actually hold data are arranged.

  When a command is input from the data recording device 13, the memory interface unit 14 outputs the command to the command processing unit 15. The command is write, erase or read. The command processing unit 15 controls the page buffer 16 according to the contents of the input command. As a result, data transfer between the page buffer 16 and the NAND flash memory 17 is controlled.

  When the command is a write command, the memory interface unit 14 outputs the command to the command processing unit 15 and outputs data added to the command to the page buffer 16. The page buffer 16 temporarily stores the data, and then writes the data to the NAND flash memory 17 according to an instruction from the command processing unit 15. When the command is erasure, the page buffer 16 erases data from the NAND flash memory 17 according to an instruction from the command processing unit 15.

  When the command is read, the page buffer 16 reads data from the NAND flash memory 17 in accordance with an instruction from the command processing unit 15. The page buffer 16 temporarily stores the data and then outputs the data to the memory interface unit 14. The memory interface unit 14 outputs the data input from the page buffer 16 to the memory bus 12.

  FIG. 2 is a block diagram showing a basic configuration of the NAND flash memory 17. The NAND flash memory 17 is composed of a plurality of blocks 21a to 21j. Each of the blocks 21a to 21j is composed of a plurality of pages. For example, the block 21a is composed of k pages 22a1 to ak.

  At present, the general recording capacity of a block is about 64 to 256 kilobytes. The general recording capacity of a page is about 1 to 4 kilobytes. Data is written and read in units of pages. Data is erased in units of blocks. In the NAND flash memory 17, when new data is recorded, it is necessary to erase already written data.

  FIG. 3 is a diagram showing the order of data writing processing from the data recording device 13 to the device chip 11. In FIG. 3, time advances from the left to the right, and 31 to 34 denote processes. The length of the processes 31 to 34 represents time. However, the time required for processing is an example. Processing is performed in the order of first command transmission 31, write data transfer 32, second command transmission 33, and in-chip write processing.

  First, the data recording device 13 transmits the first command 31 to the device chip 11. Normally, the first command 31 includes the block number of the NAND flash memory 17 of the device chip 11 that is the write destination. Next, the data recording device 13 transfers one page of data to the device chip 11. The device chip 11 temporarily stores the transferred data in the page buffer 16.

  Next, the data recording device 13 transmits a second command 33 to the device chip 11. The device chip 11 performs an in-chip write process 34 when the second command 33 is received. The device chip 11 transfers the data stored in the page buffer 16 to the NAND flash memory 17 and writes it. Data is written to the block specified by the first command. The data recording apparatus 13 needs to wait for completion of the in-chip write process 34 in the device chip 11 and start another process.

FIG. 4 is a block diagram showing a form in which a plurality of device chips are connected to the data recording device 13. The data recording device 13 is connected to a plurality of device chips 11a to 11n via a memory bus 41.
FIG. 5 is a diagram showing the order of data write processing from the data recording device 13 to the plurality of device chips 11a-b. In FIG. 5, time advances from left to right. Reference numerals 31a to 34a denote processes for the device chip 11a. Reference numerals 31b to 34b denote processes for the device chip 11b.

  While the in-chip write process 34a for the device chip 11a is being performed, the memory bus 41 is in an empty state. During this time, the data recording device 13 performs the processing 31b to 33b for the device chip 11b connected to the same memory bus 41. Thus, by performing the process for the device chip 11a and the process for the device chip 11b in parallel, the writing performance as a whole can be improved.

  For example, the time required for the second command transmission 33a from the first command transmission 31a to the device chip 11a, the time required for the in-chip write processing 34a for the device chip 11a, and the second command transmission from the first command transmission 31b to the device chip 11b When the time required for 33b and the time required for the in-chip write process 34b for the device chip 11b are equal, the data recording device 13 can write data in 3/4 time when parallel processing is not performed. Normally, the time required for the in-chip write processing 34a-b is longer than the time required from the first command transmission 31a-b to the second command transmission 33a-b.

Hereinafter, the present embodiment will be described.
FIG. 6 is a block diagram showing a configuration of the data recording device 60 according to the first embodiment. The data recording device 60 is connected to device chips 11a to 11n of a plurality of NAND flash memories via a memory bus 61. The data recording device 60 includes a command interface unit 62, a write function unit 63, an erase function unit 64, a read function unit 65, an empty block management unit 66, an empty block management unit 67 for parallel writing, an address conversion unit 68, and a memory interface unit. 69.

  The command interface unit 62 distributes commands from a host system (not shown) in the data recording device 60 to the write function unit 63, the erase function unit 64, or the read function unit 65. Further, the command interface unit 62 outputs the processing result of the write function unit 63, the erase function unit 64, or the read function unit 65 to the host system.

  The write function unit 63 writes data to the device chips 11a to 11n. The erase function unit 64 erases data held in the device chips 11a to 11n. The read function unit 65 reads data held in the device chips 11a to 11n.

  The empty block management unit 66 manages the states of all the blocks of the NAND flash memory of the device chips 11a to 11n. The block state is either data written and in use or data erased and empty. The parallel writing free block management unit 67 holds a parallel writing free block management table, and manages the free blocks by setting blocks corresponding to the number of parallel writings as one set. The address conversion unit 68 stores a correspondence between the logical address recognized by the host system and the block number of the NAND flash memory of the device chips 11a to 11n.

  The memory interface unit 69 outputs commands from the write function unit 63, the erase function unit 64, or the read function unit 65 to the device chips 11a to 11n. The memory interface unit 69 outputs the processing results input from the device chips 11a to 11n of the NAND flash memory to the write function unit 63, the erase function unit 64, or the read function unit 65.

Next, the data write operation will be described.
When the write function unit 63 receives a write command from the command interface unit 62, the write function unit 63 requests a free block for the number of parallel writes from the parallel write free block management unit 67. The parallel writing free block management unit 67 acquires the number of free blocks corresponding to the number of parallel writings from the parallel writing free block management table and notifies the writing function unit 63 of the number.

  The write function unit 63 divides the write data into the number of parallel writes, and notifies the memory interface unit 69 of the write command together with the empty block number. The memory interface unit 69 transmits a write command to each device chip for the number of parallel writes. The interface unit 69 performs control so that a write command is transmitted to another device chip when the memory bus is available during the writing process to the device chip, and performs writing to a plurality of device chips in parallel. The device chip performs a write process on the designated block of the NAND flash memory, and notifies the memory interface unit 69 when the process is completed.

  When writing to one device chip, the write function unit 63 requests and acquires an empty block from the empty block management unit 66. The write function unit 63 notifies the write command to the memory interface unit 69 together with the empty block number. The memory interface unit 69 transmits a write command to the device chip. Whether to write to a plurality of device chips in parallel or to write to one device chip may be processed according to an instruction from the host system, or it may be determined which processing is performed by the writing function unit 63 Good.

  The memory interface unit 69 notifies the write function unit 63 that the writing process to the device chip is completed. The writing function unit 63 notifies the address conversion unit 68 of the block number of the device chip to which writing has been performed and the logical address recognized by the host system. The address conversion unit 68 stores the notified block number of the device chip and the logical address in association with each other. The writing function unit 63 notifies the command interface unit 62 that the writing process has been completed. The command interface unit 62 notifies the host system that the writing process has been completed, and the writing process is completed.

Next, the data erasing operation will be described.
When the erase function unit 64 receives an erase command from the command interface unit 62, the erase function unit 64 notifies the address converter 68 of the designated logical address. The address conversion unit 68 notifies the erase function unit 64 of the block number of the device chip corresponding to the designated logical address. The erase function unit 64 designates the block number of the device chip and transmits an erase command to the memory interface unit 69.

  The memory interface unit 69 transmits an erase command to the device chip. The device chip that has received the erase command erases the data of the designated block, and notifies the memory interface unit 69 when the processing is completed. The memory interface unit 69 notifies the erasing function unit 64 that the device chip erasing process has been completed.

  The erasing function unit 64 notifies the address conversion unit 68 to delete the association between the block and the logical address. Further, the erasing function unit 64 notifies the empty block management unit 66 that the block is empty. The free block management unit 66 notifies the free block management unit 67 for parallel writing of the free block for which the erasure process has been completed. The erase function unit 64 notifies the command interface unit 62 that the erase process has been completed. The command interface unit 62 notifies the host system that the erasure process has been completed.

Next, the data reading operation will be described.
When the read function unit 65 receives a read command from the command interface unit 62, the read function unit 65 notifies the address conversion unit 68 of the designated logical address. The address conversion unit 68 converts the designated logical address into the block number of the device chip and notifies the read function unit 65 of it. The read function unit 65 designates the block number of the device chip and transmits a read command to the memory interface unit 69.

  The memory interface unit 69 transmits a read command to the device chip. The device chip that has received the read command reads the data of the designated block and notifies the memory interface unit 69 of it. The memory interface unit 69 notifies the read function unit 65 that the device chip read processing has been completed. The read function unit 65 notifies the command interface unit 62 that the read process has been completed. The command interface unit 62 notifies the upper system of the read data.

  Next, operations in the empty block management unit 66 and the parallel writing empty block management unit 67 will be described.

  FIG. 7 is a diagram showing the parallel writing free block management table 71 according to the first embodiment. The parallel writing free block management table 71 is a table for storing one or more sets, each of which has a device chip and its block number corresponding to the number of parallel writes. The number 72 at the left end of the parallel writing free block management table 71 is an index indicating a set number. Each index stores as many entries as the number of parallel writes. In the present embodiment, since the number of parallel writes is 3, three entries 73a to 73c are stored. In each entry, device chip numbers 74a to 74c and block numbers 75a to 75c are stored. The device chip numbers 74a to 74c are identifiers for identifying device chips, and the block numbers 75a to 75c are identifiers for identifying blocks.

  In the parallel writing free block management table 71, the device chip numbers 74b to 74c and the block numbers 75b to 75c are "-", indicating that they are not registered. For example, the device chip number of entry 1 of index 7 is 1 and the block number of 50 is registered, and the device chip number and block number of entry 2 and entry 3 are not registered. Note that different block numbers of the same device chip cannot be registered in entries of the same index.

FIG. 8 is a flowchart showing the flow of processing in the empty block management unit 66 and the parallel writing empty block management unit 67 according to the first embodiment.
The empty block management unit 66 starts processing from step S81 when notified by the erasing function unit 64 of a block that has been erased. In step S81, the empty block management unit 66 notifies the parallel writing empty block management unit 67 of the block, and the process proceeds to step S82.

  In step S82, the parallel writing free block management unit 67 searches the parallel writing free block management table 71 for a free entry that can register the block. Details of step S82 will be described later. The process proceeds to step S83. In step S83, the parallel writing free block management unit 67 proceeds to step S84 if the block can be registered in the parallel writing free block management table 71.

  In step S84, the parallel writing free block management unit 67 registers the block in the parallel writing free block management table 71, and proceeds to step S85. In step S85, the parallel writing free block management unit 67 notifies the free block management unit 66 of “use” in order to use the block for parallel writing. In step S87, the free block management unit 66 registers the block as being used in the block management table, and ends the process.

  In step S83, the parallel writing free block management unit 67 proceeds to step S86 if the block cannot be registered in the parallel writing free block management table 71. In step S86, the parallel writing free block management unit 67 notifies the free block management unit 66 of “not used” because the block is not used for parallel writing. In step S88, the empty block management unit 66 registers the block as empty in the empty block management table, and ends the process.

  FIG. 9 is a flowchart showing a flow of search processing of the parallel writing free block management table 71 in the parallel writing free block management unit 67 according to the first embodiment. The flowchart in FIG. 9 shows the details of the processing in step S82 in FIG. When the free block management unit 67 for parallel writing is notified of the free block from the free block management unit 66, the process starts from step S91.

  Processing when the notified empty block is the block number 80 of the device chip # 2 will be described. In step S91, the parallel writing free block management unit 67 refers to the index 1 of the parallel writing free block management table 71. Since there is no empty entry in index 1 of the parallel writing empty block management table 71, the parallel writing empty block management unit 67 proceeds to step S93. In step S93, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S94.

  In step S94, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S91. In step S 91, the parallel writing free block management unit 67 refers to the index 2 of the parallel writing free block management table 71. Since there is no empty entry from index 2 to index 5, the parallel writing empty block management unit 67 repeats the processing of step S91, step S93 and step S94 as in the case of index 1.

  In step S 91, the parallel writing free block management unit 67 refers to the index 6 of the parallel writing free block management table 71. Since index 6 has an empty entry, the process proceeds to step S92. In step S92, since device chip # 2 is registered in entry 2 of index 6, the process proceeds to step S93. In step S93, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S94. In step S94, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S91.

  In step S <b> 91, the parallel writing free block management unit 67 refers to the index 7 of the parallel writing free block management table 71. Since there is an empty entry in index 7, the process proceeds to step S92. In step S92, since the device chip # 2 is not registered in the index 7, the parallel writing free block management unit 67 can register a free block in the entry 2 of the index 7. The parallel writing free block management unit 67 ends the processing.

  FIG. 10 is a diagram showing the parallel writing free block management table 101 according to the first embodiment. The registered parallel writing free block management table 101 is a table in which the block number 80 of the device chip # 2 is registered in the entry 2 of the index 7 of the parallel writing free block management table 71. In FIG. 10, the shaded portion is entry 2 of index 7. The block number 80 of the device chip # 2 is used as an empty block for parallel writing.

Next, processing in the case where the notified empty block is the block number 30 of the device chip # 1 will be described with reference to the flowchart of FIG.
In step S91, the parallel writing free block management unit 67 refers to the index 1 of the parallel writing free block management table 71. Since there is no empty entry in index 1 of the parallel writing empty block management table 71, the parallel writing empty block management unit 67 proceeds to step S93. In step S93, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S94.

  In step S94, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S91. In step S 91, the parallel writing free block management unit 67 refers to the index 2 of the parallel writing free block management table 71. Since there is no empty entry from index 2 to index 5, the parallel writing empty block management unit 67 repeats the processing of step S91, step S93 and step S94 as in the case of index 1.

  In step S 91, the parallel writing free block management unit 67 refers to the index 6 of the parallel writing free block management table 71. Since index 6 has an empty entry, the process proceeds to step S92. In step S92, since device chip # 1 is registered in entry 1 of index 6, the process proceeds to step S93. In step S93, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S94. In step S94, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S91.

  In step S <b> 91, the parallel writing free block management unit 67 refers to the index 7 of the parallel writing free block management table 71. Since there is an empty entry in index 7, the process proceeds to step S92. In step S92, since device chip # 1 is registered in entry 1 of index 7, the process proceeds to step S93. In step S93, the parallel writing free block management unit 67 ends the process because all indexes have been searched.

  The block number 30 of the device chip # 1 is not registered in the parallel writing free block management table 71. The block number 30 of the device chip # 1 is used as an empty block assigned to each block in the empty block management unit 66.

  In the present embodiment, the case where the number of parallel writes is 3 is shown, but the number of parallel writes may be another value. When the number of device chips is N, the number of parallel writes is a natural number equal to or less than N. The number of entries in the parallel write free block management table may be the same value as the number of parallel writes.

  In the present embodiment, the number of indexes in the parallel writing free block management table 71 is set to 7, but other values may be used. The data recording device 60 may determine in advance in consideration of a communication frequency of input data that requires parallel writing and a ratio with the number of blocks necessary for allocation for each block. Further, the data recording device 60 determines the upper limit value and the lower limit value of the number of indexes, and changes it according to the change in the ratio of the communication frequency of input data requiring parallel writing and the number of blocks necessary for allocation for each block. Also good.

  Furthermore, the data recording device 60 may hold a plurality of parallel writing empty block management units having different numbers of parallel writing, and write data to the device chip with different numbers of parallel writing.

  Therefore, in the present embodiment, the writing function unit 63 that writes data in parallel to a plurality of recording media connected on the same bus, and an empty block in which data can be written to a plurality of blocks obtained by dividing the plurality of recording media, respectively. Whether or not the empty block notified from the empty block management unit 66 is registered in the parallel write empty block management table 71 as one set for the number of parallel writes. A parallel writing free block management unit 67 that acquires and notifies the free blocks for the number of parallel writings from the parallel writing free block management table 71 in response to a request from the writing function unit 63, The block management unit 67 associates the identifier of the recording medium with the block number for identifying the block. When the free blocks of different recording media corresponding to the number of parallel writes are registered as one set in the parallel write free block management table 71 and the free block is notified from the free block management unit 66, the parallel write free block management table When a block of the same recording medium as the empty block is not registered in a group in which empty blocks corresponding to the number of parallel writes of 71 are not registered, the empty block is registered, so that a plurality of NAND flash memories are connected in parallel. When data is written, the processing time can be shortened and data loss can be prevented.

  By searching the empty block management table 71 for parallel writing once, a set of empty blocks suitable for parallel writing can be taken out, so the processing amount is the same as that for taking out one empty block from the conventional empty block management unit 66. Parallel write processing can be performed. Therefore, continuous input data can be recorded without loss.

Embodiment 2. FIG.
In the first embodiment described above, the parallel write free block management unit 67 searches each entry of each index for a free entry in the parallel write free block management table. Shows an embodiment in which the number of allocated blocks is assigned to the parallel writing free block management table to search for a free entry.
In the present embodiment, since the blocks other than the parallel writing free block management unit 67 are the same as those in the first embodiment, description thereof will be omitted.
In the present embodiment, it is assumed that the number of device chips of all NAND flash memories connected to the memory bus 61 is 5, and the number of parallel writes is 3.

  FIG. 11 is a diagram showing the parallel writing free block management table 111 according to the second embodiment. Reference numeral 112 denotes an index. 113 indicates the number of allocated blocks in each index. 114a to 114e are entries corresponding to the respective device chips. The number of entries corresponds to the number of device chips connected to the memory bus 61 and is five. Reference numeral 114a denotes an entry for the device chip # 1. Reference numeral 114b denotes an entry for the device chip # 2. Reference numeral 114c denotes an entry for the device chip # 3. Reference numeral 114d denotes an entry for the device chip # 4. Reference numeral 114e denotes an entry for the device chip # 5.

  The number of allocated blocks indicates the number of entries in which block numbers are registered in each index. The number of allocated blocks is a natural number equal to or less than the number of parallel writes. In each entry, an empty block number is registered. When the block number is “−”, it indicates that it is not registered.

  FIG. 12 is a flowchart showing a flow of search processing of the parallel writing free block management table 111 in the parallel writing free block management unit 67 according to the second embodiment. The flowchart in FIG. 12 shows details of the processing in step S82 in FIG. When the empty block management unit 67 for parallel writing is notified of the empty block from the empty block management unit 66, the process starts from step S121.

  Processing when the notified empty block is the block number 80 of the device chip # 2 will be described. In step S121, the parallel writing free block management unit 67 refers to the index 1 of the parallel writing free block management table 111. The number of allocated blocks of index 1 is 3. Since the number of allocated blocks of index 1 is not smaller than the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S123. In step S123, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S124.

  In step S124, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S121. In step S121, the parallel writing free block management unit 67 refers to the index 2 of the parallel writing free block management table 111. Since the number of allocated blocks from index 2 to index 5 is not smaller than the number of parallel writes, the parallel write free block management unit 67 repeats the processing of step S121, step S123, and step S124 as in the case of index 1.

  In step S121, the parallel write free block management unit 67 refers to the index 6 of the parallel write free block management table 71. Since the number of allocated blocks of index 6 is smaller than the number of parallel writes, the process proceeds to step S122. In step S122, since another block number has already been registered in entry 2 for device chip # 2, the process proceeds to step S123. In step S123, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S124. In step S124, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S121.

  In step S121, the parallel writing free block management unit 67 refers to the index 7 of the parallel writing free block management table 71. Since the number of allocated blocks of index 7 is smaller than the number of parallel writes, the process proceeds to step S122. In step S122, since the entry 2 for the device chip # 2 is free, the parallel writing free block management unit 67 can register a free block in the entry 2 of the index 7. The parallel writing free block management unit 67 ends the processing.

  FIG. 13 is a diagram showing the parallel write free block management table 131 according to the second embodiment. The parallel writing free block management table 131 is a table in which the block number 80 of the device chip # 2 is registered in the entry 2 of the index 7 of the parallel writing free block management table 111. In FIG. 13, the shaded part is entry 2 of index 7. The block number 80 of the device chip # 2 is used as an empty block for parallel writing.

Next, processing in the case where the notified empty block is the block number 30 of the device chip # 1 will be described with reference to the flowchart of FIG.
In step S121, the parallel writing free block management unit 67 refers to the index 1 of the parallel writing free block management table 111. The number of allocated blocks of index 1 is 3. Since the number of allocated blocks of index 1 is not smaller than the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S123. In step S123, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S124.

  In step S124, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S121. In step S121, the parallel writing free block management unit 67 refers to the index 2 of the parallel writing free block management table 111. Since the number of allocated blocks from index 2 to index 5 is not smaller than the number of parallel writes, the parallel write free block management unit 67 repeats the processing of step S121, step S123, and step S124 as in the case of index 1.

  In step S121, the parallel writing free block management unit 67 refers to the index 6 of the parallel writing free block management table 111. Since the number of allocated blocks of index 6 is smaller than the number of parallel writes, the process proceeds to step S122. In step S122, since another block number is already registered in entry 1 for device chip # 1, the process proceeds to step S123. In step S123, the parallel writing free block management unit 67 has not searched all the indexes, and thus proceeds to step S124. In step S124, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S121.

  In step S121, the parallel writing free block management unit 67 refers to the index 7 of the parallel writing free block management table 111. Since the number of allocated blocks of index 7 is smaller than the number of parallel writes, the process proceeds to step S122. In step S122, since another block number is already registered in entry 1 for device chip # 1, the process proceeds to step S123. In step S123, the parallel writing free block management unit 67 ends the process because all indexes have been searched.

  The block number 30 of the device chip # 1 is not registered in the parallel writing free block management table 111. The block number 30 of the device chip # 1 is used as an empty block assigned to each block in the empty block management unit 66.

  Therefore, in the present embodiment, the writing function unit 63 that writes data in parallel to a plurality of recording media connected on the same bus, and an empty block in which data can be written to a plurality of blocks obtained by dividing the plurality of recording media, respectively. A free block management unit 66 for registering in the free block management table, and a free block notified from the free block management unit 66, the number of parallel writes is registered as one set in the free block management table 111 for parallel writing, A parallel writing free block management unit 67 that acquires and notifies the free blocks for the number of parallel writings from the parallel writing free block management table 111 in response to a request from the writing function unit 63, The block management unit 67 assigns the identifier and block number of the recording medium to one set. The number of allocated blocks is associated with each other, and free blocks of different recording media corresponding to the number of parallel writes are registered as one set in the parallel write free block management table 111, and the free block management unit 66 notifies the free blocks. If the block of the same recording medium as the empty block is not registered in the set in which the number of allocated blocks is smaller than the number of parallel writes, the empty block is registered. By referring only to the entries corresponding to the number of allocated blocks and the device chip number of each index in the free block management table 111 for writing, it is possible to determine whether a free block can be registered. Therefore, the processing amount of the parallel writing free block management unit 67 can be suppressed.

Embodiment 3 FIG.
In the second embodiment described above, the number of allocated blocks is assigned to the parallel writing free block management table to search for a free entry. In this embodiment, wear leveling is performed. Embodiments are shown. Wear leveling is to equalize the number of erasures. The memory element deteriorates when data writing and erasing are repeated, and data cannot be written. In order to prevent data writing and erasing from being concentrated on a specific block and making it impossible to perform writing, the number of times of erasing is equalized.

  In the present embodiment, it is assumed that the number of device chips of all NAND flash memories connected to the memory bus 61 is 5, and the number of parallel writes is 3.

  FIG. 14 is a diagram showing the parallel writing free block management table 141 according to the third embodiment. Reference numeral 142 denotes an index of the parallel writing free block management table 141. Reference numeral 143 denotes the number of allocated blocks in each index. The number of allocated blocks is a natural number equal to or less than the number of parallel writes. 144 is an average value of the number of times of erasure of empty blocks registered in each index. Only when the number of allocated blocks is equal to the number of parallel writes, a value is registered in the average value of the number of erasures.

  Reference numerals 145a to 145e denote entries corresponding to the respective device chips. The number of entries corresponds to the number of device chips connected to the memory bus 61 and is five. Reference numeral 145a denotes an entry for the device chip # 1. Reference numeral 145b denotes an entry for the device chip # 2. Reference numeral 145c denotes an entry for the device chip # 3. Reference numeral 145d denotes an entry for the device chip # 4. Reference numeral 145e denotes an entry for the device chip # 5.

  In each entry, the empty block number of the corresponding device chip and the erase count of the block are registered. Reference numerals 146a to 146e indicate empty block numbers of the entries. Reference numerals 147a to 147e indicate the number of times of erasing the corresponding block of each entry. “-” Indicates that no value is registered.

FIG. 15 is a flowchart showing the flow of processing in the empty block management unit 66 and the parallel writing empty block management unit 67 according to the third embodiment.
The empty block management unit 66 starts processing from step S150 when notified from the erasing function unit 64 of a block that has been erased. Let the notified block be block X. In step S150, the empty block management unit 66 notifies the parallel writing empty block management unit 67 of the block X, and the process proceeds to step S151.

  In step S151, the parallel write free block management unit 67 searches the parallel write free block management table 141 for an entry that can register the block X, and registers it if it can be registered. Details of the processing in step S151 will be described later. As a result of the processing in step S151, there may be a case where a free block that cannot be registered remains in the parallel write free block management table 141. The process proceeds to step S152. In step S152, if there is a free block that cannot be registered in the parallel write free block management table 141 in step S152, the parallel write free block management unit 67 proceeds to step S153.

  In step S153, if the empty block is the block X, the parallel writing empty block management unit 67 proceeds to step S154. In step S154, since the parallel writing free block management unit 67 does not use the block X for parallel writing, it notifies the free block management unit 66 of “not used”, and proceeds to step S155. In step S155, the empty block management unit 66 registers the block X as empty in the empty block management table, and ends the process.

  In step S153, if the empty block for parallel writing 67 is not the empty block X, the parallel writing empty block management unit 67 proceeds to step S156. Let the empty block be block Y. In step S156, the parallel writing free block management unit 67 notifies the free block management unit 66 of “not used” because the block Y is not used for parallel writing. In addition, the parallel writing free block management unit 67 notifies the free block management unit 66 of “use” in order to use the block X for parallel writing, and proceeds to step S157.

  In step S157, the empty block management unit 66 registers the block Y as empty in the block management table, and proceeds to step S158. In step S158, the empty block management unit 66 registers the block X as being used in the empty block management table, and ends the process.

  In step S152, when there is no empty block, the parallel writing empty block management unit 67 proceeds to step S159. In step S159, the parallel writing free block management unit 67 notifies the free block management unit 66 of “use” in order to use the block X for parallel writing, and proceeds to step S158. In step S158, the empty block management unit 66 registers the block X as being used in the empty block management table, and ends the process.

  FIG. 16 is a flowchart showing a flow of search processing for the parallel writing free block management table 141 in the parallel writing free block management unit 67 according to the third embodiment. The flowchart in FIG. 16 shows details of the process in step S151 in FIG. When the empty block management unit 67 for parallel writing is notified of the empty block from the empty block management unit 66, the process starts from step S161.

  In step S161, the parallel writing free block management unit 67 refers to the index 1 of the parallel writing free block management table 141. When the number of allocated blocks of index 1 is equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S162. If the number of allocated blocks of index 1 is not equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S163.

  In step S162, the parallel writing free block management unit 67 refers to the average value of the number of erasures. If the average value of the number of erases is larger than the number of empty blocks erased, the process proceeds to step S163. If the average value of the erase count is not larger than the erase count of the empty block, the process proceeds to step S166. In step S163, the parallel writing free block management unit 67 proceeds to step S164 if it is already registered in the device block entry of the free block.

  In step S164, the parallel writing free block management unit 67 proceeds to step S165 when the erase count of the registered block is larger than the erase count of the empty block. When the erase count of the registered block is not larger than the erase count of the empty block, the process proceeds to step S166. In step S165, the parallel writing free block management unit 67 replaces the registered block with the free block, and the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 ends the process when all the indexes have been searched.

  In step S166, the parallel writing free block management unit 67 proceeds to step S167 if not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  In step S163, the parallel writing free block management unit 67 registers a free block if it is not already registered in the device chip entry of the free block, and ends the process.

  A process when the notified empty block is the block number 30 of the device chip # 1 will be described. The number of erases is 45. In step S161, the parallel writing free block management unit 67 refers to the index 1 of the parallel writing free block management table 141. The number of allocated blocks of index 1 is 3. Since the number of allocated blocks of index 1 is equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S162.

  In step S162, the parallel writing free block management unit 67 refers to the average value of the number of erasures. Since the average value 41 of erasure times is not larger than the erasure number 45 of empty blocks, the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 proceeds to step S167 because not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  In step S161, the parallel writing free block management unit 67 refers to the index 2 of the parallel writing free block management table 141. The number of allocated blocks of index 2 is 3. Since the number of allocated blocks of index 2 is equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S162. In step S162, the parallel writing free block management unit 67 refers to the average value of the number of erasures. Since the average value 59 of erase times is larger than the erase number 45 of empty blocks, the process proceeds to step S163.

  In step S163, the parallel write free block management unit 67 proceeds to step S164 because entry 1 of index 2 is registered. In step S164, the parallel writing free block management unit 67 refers to the number of erasures of the entry 1 for the device chip # 1. Since the erase count 45 of entry 1 is not larger than the erase count 45 of empty blocks, the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 proceeds to step S167 because not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  In step S161, the parallel writing free block management unit 67 refers to the index 3 of the parallel writing free block management table 131. The number of allocated blocks of index 3 is 3. Since the number of allocated blocks of index 3 is equal to the number of parallel writes, the parallel write free block management unit 67 proceeds to step S162.

  In step S162, the parallel writing free block management unit 67 refers to the average value of the number of erasures. Since the average value 50 of the erase count is larger than the erase count 45 of empty blocks, the process proceeds to step S163. In step S163, the parallel writing free block management unit 67 proceeds to step S164 because entry 1 of index 3 is registered. In step S164, the parallel writing free block management unit 67 refers to the number of erasures of the entry 1 for the device chip # 1. Since the erase count 60 of entry 1 is larger than the empty block erase count 45, the process advances to step S165.

  In step S165, the parallel writing free block management unit 67 replaces the notified free block with the block number 35 registered in the entry 1 of the index 3. The parallel writing free block management unit 67 calculates the average value of the number of times of erasure of the entry 3, the entry 5, and the block number 30. The parallel writing free block management unit 67 registers the average value 45 of the calculated number of erasures and proceeds to step S166. In step S166, the parallel writing free block management unit 67 proceeds to step S167 because not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  The parallel writing vacant block management unit 67 continues the processing by setting the vacant block as the block number 35 of the device chip # 1 and the erasure count 60. In step S161, the parallel writing free block management unit 67 refers to the index 4 of the parallel writing free block management table 131. The number of allocated blocks of index 4 is 3. Since the number of allocated blocks of index 4 is equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S162.

  In step S162, the parallel writing free block management unit 67 refers to the average value of the number of erasures. Since the average value 33 of the erase count is not larger than the blank block erase count 60, the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 proceeds to step S167 because not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  In step S161, the parallel writing free block management unit 67 refers to the index 5 of the parallel writing free block management table 141. The number of allocated blocks of index 5 is 3. Since the number of allocated blocks of index 5 is equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S162.

  In step S162, the parallel writing free block management unit 67 refers to the average value of the number of erasures. Since the average value 42 of the erase count is not larger than the blank block erase count 60, the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 proceeds to step S167 because not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  In step S161, the parallel writing free block management unit 67 refers to the index 6 of the parallel writing free block management table 141. The number of allocated blocks of index 6 is 2. Since the number of allocated blocks of index 6 is not equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S163.

  In step S163, the parallel writing free block management unit 67 is registered in the entry 1 of the index 6 of the parallel writing free block management table 141, and thus proceeds to step S164. In step S164, the parallel writing free block management unit 67 refers to the number of erasures of the entry 1 for the device chip # 1. Since the erase count 70 of entry 1 is larger than the empty block erase count 60, the process advances to step S165.

  In step S165, the parallel writing free block management unit 67 replaces the block number 22 registered in the entry 1 of the index 6 with the free block, and the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 proceeds to step S167 because not all indexes have been searched. In step S167, the parallel writing free block management unit 67 increments the index to be referred to, and proceeds to step S161.

  The parallel writing free block management unit 67 continues the processing by setting the free block as the block number 22 of the device chip # 1 and the number of times of erasure 70. In step S161, the parallel writing free block management unit 67 refers to the index 7 of the parallel writing free block management table 141. The number of allocated blocks of index 7 is 1. Since the number of allocated blocks of index 7 is not equal to the number of parallel writes, the parallel writing free block management unit 67 proceeds to step S163.

  In step S163, the parallel writing free block management unit 67 is registered in the entry 1 of the index 7 in the parallel writing free block management table 141, and thus the process proceeds to step S164. In step S164, the parallel writing free block management unit 67 refers to the number of erasures of the entry 1 for the device chip # 1. Since the erase count 50 of entry 1 is not larger than the erase count 70 of empty blocks, the process proceeds to step S166. In step S166, the parallel writing free block management unit 67 ends the process because all indexes have been searched.

  FIG. 17 is a diagram showing the parallel writing free block management table 171 according to the third embodiment. The registered parallel writing free block management table 171 is a table in which the average value of the number of erasures of the index 3 of the parallel writing free block management table 141 and new values are registered in the entry 1 and the entry 1 of the index 6. . In FIG. 17, the shaded portions are the average value of the number of deletions of index 3, entry 1, and entry 1 of index 6.

  The block number 30 of the device chip # 1 is used as an empty block for parallel writing. In addition, the block number 22 of the device chip # 1 is used as a free block allocated to each block in the free block management unit 66.

  Therefore, in the present embodiment, the writing function unit 63 that writes data in parallel to a plurality of recording media connected on the same bus, and an empty block in which data can be written to a plurality of blocks obtained by dividing the plurality of recording media, respectively. A free block management unit 66 that registers whether or not to register in the free block management table, and the free block notified from the free block management unit 66 is registered in the parallel write free block management table 141 as one set for the number of parallel writes, A parallel writing empty block management unit 67 which acquires empty blocks for the number of parallel writings from the parallel writing empty block management table 141 in response to a request from the writing function unit 63 and notifies the parallel writing empty block management unit 67; The block management unit 67 assigns the identifier of the recording medium, the block number, and one set. The number of assigned blocks is further correlated with the number of erases of the block and the average value of the number of erases of the blocks assigned to one set, and the free blocks of different recording media corresponding to the number of parallel writings are paralleled as one set. When a free block is registered in the write free block management table 141 and a free block is notified from the free block management unit 66, the average value of the number of erases is equal to the number of allocated blocks equal to the number of parallel writes. If a smaller block of the same recording medium as the empty block is registered and the erase count is larger than the erase count of the empty block, the registered block is replaced with the empty block. Are easily used as free blocks for parallel writing. Therefore, the number of times of erasing each block can be equalized.

11 Device chip 12, 41 Memory bus 13, 60 Data recording device 14, 69 Memory interface unit 15 Command processing unit 16 Page buffer 17 NAND flash memory 21 Block 22 Page 31 First command transmission 32 Write data transfer 33 Second command transmission 34 In-chip write processing 62 Command interface unit 63 Write function unit 64 Erase function unit 65 Read function unit 66 Free block management unit 67 Free block management unit for parallel writing 68 Address conversion units 71, 101, 111, 131, 141, 171 Parallel write Free block management table 72, 112, 142 Index 73, 145 entry 74 Device chip number 75, 114, 146 Block number 113, 143 Allocated block number 144 Erasing count average Value 147 number of erasures

Claims (10)

A writing function unit for writing data in parallel to a plurality of recording media connected on the same bus;
An empty block management unit for registering in the empty block management table whether or not data writing is possible for a plurality of blocks obtained by dividing a plurality of recording media;
The free block notified from the free block management unit is registered in the parallel write free block management table as one set for the number of parallel writes, and in response to a request from the write function unit, the parallel write free block management table Free block management unit for parallel writing to obtain and notify free blocks for the number of parallel writes from,
A data recording apparatus comprising: The parallel writing free block management unit associates an identifier of a recording medium with a block number for identifying a block, and sets the free blocks of different recording media as many as the number of parallel writing as one set, the parallel writing free block management table. Registered with
When an empty block is notified from the empty block management unit, a block of the same recording medium as the empty block is registered in a set in which empty blocks corresponding to the number of parallel writes in the empty block management table for parallel writing are not registered. 2. The data recording apparatus according to claim 1, wherein the empty block is registered if not. The parallel writing free block management unit associates the identifier and block number of the recording medium with the number of allocated blocks assigned to one set, and sets one free block of different recording media corresponding to the number of parallel writing. Registered in the free block management table for parallel writing as
When a free block is notified from the free block management unit, if a block of the same recording medium as the free block is not registered in a set in which the number of allocated blocks is smaller than the number of parallel writes, the free block is registered. The data recording apparatus according to claim 2, wherein: The parallel writing vacant block management unit includes the identifier of the recording medium, the block number, the number of allocated blocks assigned to one set, the number of block erases, and the number of block erases assigned to one set. Corresponding to the average value, register the free blocks of different recording media for the number of parallel writing as one set in the free block management table for parallel writing,
When an empty block is notified from the empty block management unit, a recording medium having the same number of erased blocks as the number of allocated blocks is equal to the number of parallel writes, and the average value of the erased block is larger than the erased number of empty blocks. 4. The data recording apparatus according to claim 3, wherein when the number of erasures is registered and the number of erasures is larger than the number of erasures of the empty blocks, the registered blocks are replaced with the empty blocks.   The parallel writing empty block management unit replaces the block that has been changed from registration to empty into a set in which the number of allocated blocks in the parallel writing empty block management table is smaller than the number of parallel writing from registration to empty. 5. The data recording apparatus according to claim 4, wherein when a block of the same recording medium as the block is not registered, the block is registered. The parallel write free block management unit, when registering the free block notified from the free block management unit in the parallel write free block management table, notifies the free block management unit to use the block,
6. The data recording apparatus according to claim 1, wherein the empty block management unit registers the block as being in use in the empty block management table. When there is an empty block not registered in the parallel writing empty block management table, the parallel writing empty block management unit notifies the empty block management unit that the block is not used,
7. The data recording apparatus according to claim 1, wherein the empty block management unit registers the block as empty in an empty block management table. An erasing function unit for erasing data from a recording medium and notifying a block of the recording medium on which the data was recorded as an empty block to the empty block management unit;
A read function unit for reading data from a recording medium,
When writing data in parallel, the write function unit writes empty blocks for the number of parallel writes from the parallel write empty block management unit and writes data, and when writing data one block at a time, the empty block management unit The data recording apparatus according to claim 1, wherein an empty block is acquired from the data and data is written. Equipped with a plurality of parallel write free block managers with different numbers of parallel writes,
9. The data recording apparatus according to claim 1, wherein the writing function unit acquires empty blocks for the number of parallel writings from different parallel writing empty block management units according to the number of parallel writings. . A writing function step for writing data in parallel to a plurality of recording media connected on the same bus;
A free block management step for registering in the free block management table whether or not data writing is possible for a plurality of blocks obtained by dividing a plurality of recording media, and
The free block notified from the free block management unit is registered in the parallel write free block management table as one set for the number of parallel writes, and in response to a request from the write function unit, the parallel write free block management table Free block management step for parallel writing to acquire and notify free blocks for the number of parallel writes from,
A data recording method comprising:

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