JP2014132403A - Verification support device and verification support method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which many hardware description languages used for digital circuit design are languages which are different from description languages of software and in which connection relations of circuits around a flip-flop are described, so in verification of a digital circuit programmed therein, a coverage standard based upon the flip-flop in the center, namely, a coverage standard for measuring an operation coverage of the flip-flop is necessary.SOLUTION: A verification support device extracts, from a logic circuit program, conditions under which a flip-flop operates to update a state to 0, to update the state to 1, to maintain a current state, and to update the current state to an inverted value, and then measures whether those operations are activated through logic simulation.

Description

  The present invention relates to a verification support apparatus and a verification support method, and more particularly to a verification support apparatus and a verification support method in digital circuit design.

  In verification of a digital circuit, there is a concept of coverage as an index for evaluating whether or not a test pattern to be executed is sufficiently executed. Coverage is an index originally designed for software programs, but with the practical application of logic synthesis technology, digital circuits have been designed in a software-like manner by programming in a hardware description language. Coverage has also become common in the field of verification in circuit design.

  A hardware description language used for programming digital circuits is significantly different from a sequential execution description language used for software design. A description language generally called RTL (Register Transfer Level) is used to describe a digital circuit. Whereas the software programming language is a sequential execution type operation description, the RTL expresses the connection relationship of circuits with a flip-flop (hereinafter referred to as FF) as the center, and operates in parallel. Therefore, due to the difference between these characteristics, in the verification of the digital circuit, attention that should not be considered in the verification of the software is necessary.

  As a background art of this technical field, there is Patent Document 1. Patent Document 1 focuses on hardware-specific parallel operability against the above-mentioned differences in hardware and software characteristics, and how much the circuit configuration assuming a race condition that can be caused by this is activated by logic simulation. Disclosed is a technique for measuring as a coverage.

  Non-Patent Document 1 describes a simple explanation of coverage. Non-Patent Document 2 introduces various existing coverage standards in addition to well-known coverage standards such as statement coverage and branch coverage.

JP 2011-138428 A

Lee Copeland, “First-time Software Testing Techniques”, Nikkei Business Publications, 2011 Steve Cornett, "Code Coverage Analysis", [online], Bullseye Testing Technology, [searched December 5, 2012], Internet <http://www.bullseye.com/coverage.html>

  The present invention measures the coverage from a viewpoint different from that of Patent Document 1 with respect to the difference in character of the description language described above. The hardware description language is described with a focus on FF. Therefore, in verification of a digital circuit programmed by a hardware description language, a coverage standard centering on the FF, that is, a coverage standard for measuring the coverage rate of the FF operation is necessary. However, there is no such coverage standard in conventional digital circuit verification. For this reason, it is difficult to comprehensively verify the operation of the FF, and in this respect, even with a software coverage standard that does not have a viewpoint for a wiring description program centered on the FF, even with 100% coverage, Even if the above is achieved, there is still a risk of causing a verification failure.

  In order to prevent the above-mentioned verification failures from occurring, in the large-scale and complex logic that constitutes the system, for each FF frequently used in the circuit, grasp all the operating conditions centering on each one without omission There is a need. However, due to the large number and complexity of conditions, it is practically impossible for humans to grasp this. In addition, it is extremely difficult to manually extract these conditions.

  The present invention has been made in view of the above-described situation. That is, an object of the present invention is to provide a verification support apparatus and a verification support method for performing comprehensive verification focusing on the operation of the FF.

  The above-mentioned problems are the logic simulation of the flip-flop operation condition calculation unit that calculates the operation condition of the flip-flop in the logic circuit, the flip-flop operation specification display instruction unit that displays each operation condition of the flip-flop, and the logic circuit program. A simulation unit that monitors the success or failure of each operation condition of the flip-flop, a coverage totaling unit that totals whether or not each flip-flop operation is activated based on the monitor information obtained by the condition monitoring, and a coverage totalization result This can be achieved by a verification support apparatus including a coverage display instruction unit to be displayed, and a display unit that outputs information according to instructions from the flip-flop operation specification display unit and the coverage display instruction unit.

  A step of receiving a logic circuit program described in a hardware description language; a step of calculating a logical expression representing a logic cone centered on the flip-flop from the logic circuit program; and a transition table of the flip-flop from the logical expression. And a step of calculating the input condition of the flip-flop operation based on the transition table.

  According to the present invention, it is possible to obtain an objective verification quality index that pays attention to the FF operation, which should be noted in a digital circuit described in a hardware description language.

It is a hardware block diagram of a verification assistance apparatus. It is a functional block diagram of a verification assistance apparatus. It is a flowchart explaining the process of FF operation condition calculation. It is a figure explaining the concept of a logic cone. It is a figure explaining a single logic cone. It is a circuit diagram of a single logic cone. It is a figure explaining the logic cone which has the autoregression from FF. It is a figure explaining the reason why the input condition for each FF operation can be calculated from the logicalized circuit description. A logic circuit program written in a hardware description language. It is a figure which shows the conversion result to FF transition table. It is a flowchart explaining the conversion method to FF transition table. It is a figure which shows the calculation result of the input conditional expression with respect to each operation | movement of FF. It is a figure which shows the conversion result to FF transition table in case there exist many input signals. It is a figure which shows the calculation result of the input conditional expression with respect to each operation | movement of FF in case there exist many input signals. It is a figure explaining the 1st display which a verification assistance apparatus outputs. It is a figure explaining the 2nd display which a verification assistance apparatus outputs. It is a figure explaining the 3rd display which a verification assistance apparatus outputs. It is a figure explaining the 4th display which a verification assistance apparatus outputs. It is a figure explaining the 5th display which a verification assistance apparatus outputs. It is a figure explaining the 6th display which a verification assistance apparatus outputs.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings using examples. The same reference numerals are assigned to substantially the same parts, and the description will not be repeated.

  The hardware configuration of the verification support apparatus will be described with reference to FIG. In FIG. 1, the verification support apparatus 100 includes a memory 110, a CPU 120, a storage device 130, an input device 140, an output device 150, and a bus 160.

  The memory 110 stores a program executed by the CPU 120. The CPU 120 performs logic simulation, FF operation specification calculation, and coverage information calculation by executing a program stored in the memory 110. The storage device 130 is an auxiliary storage device such as an HD (hard disk), and stores logic circuit programs, test patterns, FF operation specification calculation results, coverage information calculation results, and the like. The input device 140 reads a logic circuit program and a test pattern. The output device 150 displays the output result of coverage. The bus 160 interconnects the memory 110, the CPU 120, the storage device 130, the input device 140, and the output device 150.

  The functional configuration of the verification support apparatus will be described with reference to FIG. In FIG. 2, the verification support apparatus 100 includes an FF operation condition calculation unit 201, an FF operation specification display instruction unit 202, a simulation unit 203, a coverage aggregation unit 204, a coverage display instruction unit 205, and a display unit 206. Composed.

  The FF operation condition calculation unit 201 acquires the logic circuit program 207 and calculates the input condition information 209 for each FF operation for all FFs in the logic circuit. Here, the logic circuit program 207 is a program in which a logic circuit to be verified is described in a hardware description language. The FF operation specification display instruction unit 202 performs processing for causing the display unit 206 to output the input condition information 209 of each FF operation calculated by the FF operation condition calculation unit 201.

  The simulation unit 203 acquires the input condition information 209 of each FF operation calculated by the FF operation condition calculation unit 201, and monitors whether or not each condition is executed by a logic simulation. The coverage tabulation unit 204 acquires monitor information obtained by the condition monitoring of the simulation unit 203, and tabulates whether or not each condition is executed, that is, whether or not each FF operation is activated as a coverage tabulation result 210. To do. The coverage display instructing unit 205 performs a process of causing the display unit 206 to output the coverage aggregation result 210 that has been aggregated by the coverage aggregation unit 204. The display unit 206 displays the input condition information 209 and coverage count result 210 for each FF operation.

  With reference to FIG. 3, the processing of the FF operation condition calculation unit will be described. In FIG. 3, the FF operation condition calculation unit 201 reads a logic circuit program (S31). The FF operating condition calculation unit 201 determines whether calculation of operating conditions for all FFs has been completed (S32). When the FF is not included in the logic circuit to be verified (YES), the FF operation condition calculation unit 201 ends the process.

  In step 32, if calculation of the operating conditions of all the FFs is not completed (NO), the FF operating condition calculating unit 201 determines one FF to be processed this time from unprocessed FFs ( S33). The FF operation condition calculation unit 201 calculates the FF logical expression of the target FF from the input logic circuit program 207 (S34). The FF operation condition calculation unit 201 converts the calculated FF logical expression into an FF transition table (S35). The FF operation condition calculation unit 201 calculates input conditions for each FF operation based on the obtained FF transition table (S36). The FF operation condition calculation unit 201 stores the obtained input condition information of each FF operation in the storage device 130 (S37), and returns to step 32.

  The calculation of the FF logical expression in step 34 will be described in more detail below. The logic circuit can be divided into logical structure groups called logic cones centered on each FF. The logic cone is used for generating the FF logical expression, and this extraction method will be described.

  The concept of the logic cone will be described with reference to FIG. In FIG. 4, a logic cone 450 is a conical logic structure group with the output of the FF 440 as a vertex and the output port of the input port 410 or FF 440 as a bottom surface. The logic cone 450 can extract the connection relationship of the combinational logic circuit 430 existing on the input side of the FF 440 by returning from the output of another FF or the output of its own FF, or going back to the input port. . A logic circuit can be uniquely expressed by designating each logic cone 450 and its connection.

With reference to FIG. 5, a simple abstract view of a single logic cone will be described. In FIG. 5, the logic cone 450 includes a combinational logic circuit 430 having the FF 440 as a vertex. In the combinational logic circuit 430, the output Qn is simply determined only by the inputs a, b, and c. Therefore, this can be expressed by the logical function f as in (Equation 1).
Qn = f (a, b, c) (Formula 1)
A specific circuit of the logic cone of FIG. 5 will be described with reference to FIG. In FIG. 6, the logic cone 450 includes a NOT gate 610, an AND gate 620, an OR gate 630, and an FF 640. In this circuit, the logical function f of (Expression 1) is expressed by (Expression 2).
Qn =! a & (b | c) (Formula 2)
Here, “!” Is a logical symbol representing logical negation and indicates the NOT gate 610. “&” Is a logical symbol representing a logical product, and indicates the AND gate 620. “|” Is a logical symbol representing a logical sum and indicates the OR gate 630. Also, the variables “b” and “! A” and the negation of the variables are called literals.

With reference to FIG. 7, a logic cone having an operation of maintaining the current state or an operation of updating the current state to an inverted value will be described. In FIG. 7, the logic cone 450 </ b> A has autoregression from the FF 440. When the FF 440 has an operation for holding the current state or an operation for updating the current state to an inverted value, the output Qn−1 of the FF 440 always has a logical configuration that returns to the input of the combinational logic circuit 430 on the input side. Here, when the output Qn of the combinational logic circuit 430 is expressed by the logic function f, (Equation 3) is obtained.
Qn = f (a, b, c, Qn-1) (Formula 3)
With reference to FIG. 8 and (Equation 4), the reason why each FF operation and a conditional expression for establishing each operation can be calculated from the logicalized circuit description will be described.
Qn
= F1 (a, b, c) | f2 (a, b, c) & Qn-1 | f3 (a, b, c) & (! Qn-1) (Formula 4)
(Equation 4) is obtained from (Equation 3) to Qn-1 and! This is a logical expression that enumerates literals of Qn-1. f2 is a logical expression that is a coefficient for Qn-1. f3! It is a logical expression that is a coefficient for Qn-1. f1 is Qn-1 and! This is a logical expression that is the result of summing up literals of Qn-1. Each of f1, f2, and f3 is a logical expression in which a logical value of 0 or 1 is uniquely determined only by the current input signals a, b, and c. A logic cone that does not have FF autoregression as shown in FIG. 5 can also be expressed by assuming that the logic values of f2 and f3 are always 0 in (Equation 4). That is, (Equation 4) can always be expressed with any logic cone. Therefore, according to (Equation 4), the operation of each FF can be obtained by calculation only from the current input condition regardless of the logic cone.

  The reason will be specifically described with reference to FIG. In FIG. 8, the condition and result table 820 includes a condition 821, a Qn calculation result 822, and a meaning 823. In FIG. 8, when the logical value of f1 is 1, or when the logical value of f1 is 0 and both of the logical values of f2 and f3 are 1, the logical value of Qn is always 1. This means that the next state is always updated to 1 regardless of the current state of the FF.

When the logical values of f1 and f3 are 0 and the logical value of f2 is 1, the logical value of Qn is always equal to Qn-1. This represents holding the current state of the FF.
If the logical values of f1 and f2 are 0 and the logical value of f3 is 1, the value of Qn is always! It becomes equal to Qn-1. This represents that the next state of the FF is updated to a value obtained by inverting the current state.
In other cases, the logical value of Qn is always 0. This means that the next state is always updated to 0 regardless of the current state of the FF.

  With reference to FIG. 9, the calculation of the FF logical expression from the logic circuit program will be described. FIG. 9 is a logic circuit program in which a logic circuit to be verified is described in a hardware description language. In FIG. 9, the logic circuit program is composed of line numbers 001 to 008 :, control statements, and command statements. Here, “a”, “b”, and “c” represent signal names of the input signals. “Ff1” represents the identification name of the FF. "1'b0" and "1'b1" represent 1-bit logical values 0 and 1, respectively. The symbol “<=” represents an instruction for updating the state of the FF indicated by the left side to the value indicated by the right side.

In the logic circuit program of FIG. 9, the circuit description converted into the FF logic formula for “ff1” is (Formula 5). The logic circuit program of FIG. 9 and the logic expression of (Equation 5) represent the same circuit structure regardless of the difference in expression method. Extracting a logical expression from a logic circuit program can be easily realized by using a commercially available logic design support tool or the like.
ff1 = (ff1 | (b | c)) & (! a) (Formula 5)
Here, “ff1” on the right side of (Expression 5) represents the current state of “ff1”, that is, Qn−1 on the right side of (Expression 3). On the other hand, “ff1” on the left side represents the next state after “ff1”, that is, Qn on the left side of (Expression 3).

  With reference to FIGS. 10 and 11, the FF transition table conversion in step 35 of FIG. 3 will be described. FIG. 10 is a table in which “ff1” in the FF logical expression of (Expression 5) is converted into an FF transition table. In the FF transition table 1000, a column 1010, b column 1020, and c column 1030 represent logical values of input signals a, b, and c, respectively. The Qn column 1040 represents the next state of the FF.

Specifically, in the row 1050, when the combination of the input signals a, b, and c is (Expression 6), the next state Qn of the FF becomes the current state Qn−1 of the FF, that is, the current It means to keep the state.
(a, b, c) = (0, 0, 0) (Formula 6)
Similarly, the row 1060 updates the next state to 1 regardless of the current state of the FF when the combination of the input signals a, b, and c is (Expression 7).
(a, b, c) = (0, 0, 1), (0, 1, 0), (0, 1, 1) (Expression 7)
The row 1070 updates the next state to 0 regardless of the current state of the FF when the combination of the input signals a, b, and c is (Expression 8).
(a, b, c)
= (1, 0, 0), (1, 0, 1), (1, 1, 0), (1, 1, 1) (Formula 8)
In the FF logical expression of (Expression 5), a calculation result that inverts the current state is not obtained.

  A procedure for creating the FF transition table shown in FIG. 10 will be described with reference to FIG. In FIG. 11, the FF operation condition calculation unit 201 determines whether or not Qn has been calculated for all combinations of input signals (S111). When the calculation of Qn has been completed for all input signals, the FF operation condition calculation unit 201 ends the process.

  If calculation of Qn has not been completed for all combinations of input signals, the FF operation condition calculation unit 201 determines a combination of input signals to be calculated this time from among uncalculated input signal combinations (S112). ). The FF operation condition calculation unit 201 substitutes the combination of input signals into the FF logical expression, and calculates the logical value of Qn (S113). The FF operation condition calculation unit 201 determines which value the calculation result of Qn has reached (S114).

  The calculation results of Qn include Qn = Qn−1, Qn =! There are four types, Qn-1, Qn = 1, and Qn = 0. When Qn = Qn−1, the FF operation condition calculation unit 201 inputs “Qn−1” in a column corresponding to the combination of input signals used for the current calculation in the Qn column 1040 of the FF transition table. (S115). Qn =! When it is Qn−1, the FF operation condition calculation unit 201 inputs “! Qn−1” in the corresponding column (S116). When Qn = 1, the FF operation condition calculation unit 201 inputs “1” in the corresponding field (S117). When Qn = 0, the FF operation condition calculation unit 201 inputs “0” in the corresponding field (S118). After the input, the FF operation condition calculation unit 201 returns to Step 111.

  With reference to FIG. 12, the FF operation condition calculation in step 36 of FIG. 3 will be described. In step 36, input conditions for each FF operation are calculated based on the FF transition table created in step 35. FIG. 12 is a table in which the input conditions for each FF operation are calculated based on the FF transition table 1000 of FIG. Here, in FIG. 12, “set” of the FF operation 1210 defines an operation of updating the FF state to 1. “Reset” defines the operation of updating the FF state to 0. “Hold” defines an operation for holding the current state of the FF. “Invert” defines the operation of updating the FF state to a value obtained by inverting the current state.

The input condition 1220 will be described for the input condition of the set operation. Since the input patterns for the FF to perform the set operation are the three patterns represented by the row 1060 in FIG. 10, these are converted into logical expressions. Since the FF performs a set operation when the input a is 0 and the input b or the input c is 1, when this input condition is expressed by a logical expression, it can be expressed by (Expression 9).
f (a, b, c) =! a & (b | c) (Formula 9)
The logical expressions for reset and hold are as shown in FIG. In the input condition 1220, “−” for the inversion operation means that the condition does not exist, and means that the inversion operation cannot occur at “ff1”.

  Although a description has been given here of a three-input logic cone, in practice, as shown in FIG. 13, the transition table 1000A expands as the number of input signals increases. When calculation is performed based on the transition table 1000A, the conditional expression becomes redundant as shown in FIG. Therefore, the conditional expressions are organized using a simplified method such as the Carnot projection or the Quine-Macrasky method. Thereby, the redundancy of the conditional expression is suppressed and the subsequent processing is efficiently performed.

  With reference to FIG. 15 and FIG. 16, the display which the FF operation specification display instruction | indication part 202 makes the display part 206 output is demonstrated in detail.

  With reference to FIG. 15, a display screen in which the FF operation specification display instruction unit 202 first instructs output will be described. In FIG. 15, the output result 1500 displays the block-specific FF number 1510 of block 1 to block N and the total FF number 1520.

  FIG. 16 shows a display that is output when the user selects a block for which information is desired from among block 1 to block N of the output result 1500. In FIG. 16, the output result 1600 displays the input conditions 1620 for each of the set, reset, hold, and inversion operations for all the FFs 1610 included in the block selected by the user. If there is no corresponding input condition, “-” is displayed. The description of (Condition 1.1) to (Condition N.4) is actually a logical expression. If “ff1” is applied to FIG. (B | c) ”and (condition 1.2) are“ a ”from condition 1222, and (condition 1.3) are“! A &! B &! C ”and (condition 1.4) are from condition 1223, From the condition 1224, “−” is obtained.

  From the output result 1600, it is possible to confirm whether or not the operation of each FF matches the specification considered by the designer. As a result, it is possible to suppress bugs that occur due to carelessness such as a description error and omission of consideration.

The display that the coverage display instruction unit 205 outputs to the display unit 206 will be described in detail with reference to FIGS.
With reference to FIG. 17, a display screen in which the coverage display instruction unit 205 first instructs output will be described. In FIG. 17, the output result 1700 includes the number of FFs 1710 for each block of block 1 to block N, the total number of FFs 1720, the number of all conditions 1730 to be monitored in each block, and among them, a logic simulation The number of conditions executed 1740 and the coverage rate 1750 are displayed. The coverage rate 1750 is calculated as a ratio of the number of conditions 1740 executed by the logic simulation to the number of conditions 1730 to be monitored, and is displayed as a percentage.

  According to the output result 1700, the sufficiency of verification can be accurately and quantitatively evaluated using as an evaluation measure how much all the operations that can occur in the FF in the design circuit are activated by the logic simulation. .

  With reference to FIG. 18, a display output by the user selecting a block for which information is desired from among block 1 to block N of the output result 1700 will be described. In FIG. 18, the output result 1800 includes an FF 1810, an input condition monitoring result 1820, and an FF operation coverage rate 1830.

  The FF 1810 displays all the FFs included in the block selected by the user. The input condition monitoring result 1820 displays, for the FF 1810, input conditions for each of the set, reset, hold, and inversion FF operations, and monitors whether these conditions are executed by logic simulation. The result is displayed as “◯” and “×”. If there is a pattern that matches the condition even once in the logic simulation, it becomes “◯”, and if there is no pattern that matches at all, it becomes “X”. If there is no corresponding input condition, “-” is displayed.

  The description of (Condition 1.1) to (Condition N.4) is actually a logical expression. If “ff1” is applied to FIG. 12, (condition 1.1) is “! A & (b | c)” from condition 1221, and (condition 1.2) is “a” from condition 1222 (condition 1). .3) is the condition 1223 "! A &! B &! C".

  The FF operation coverage rate 1830 displays, for each FF, the number 1831 of all possible FF operations, and the number 1832 of FF operations activated by the logic simulation.

  According to the output result 1800, for the logic circuit determined to be insufficiently verified as a result of coverage measurement, specifically, which FF of which operation is not activated, and the operation In order to activate, it is possible to confirm what conditions are necessary, and to obtain detailed information for feedback to the verification design.

  With reference to FIG. 19, the display output when the user requests more detailed information for the output result 1800 will be described. In FIG. 19, the output result 1900 includes an FF 1910 and an input condition execution coverage rate 1920. The input condition execution coverage ratio 1920 is the number of combinations 1921 of all input signals constituting the conditions for the input conditions of each FF operation, and the number of combinations of input signals executed by the logic simulation. 1922 and a result 1923 of calculating the ratio thereof as a percentage are displayed. When the corresponding input condition does not exist, the input condition execution coverage rate 1920 displays “−”.

  According to the output result 1900, for each FF operation, it can be confirmed how much of the input cases that cause the operation is executed by the logic simulation. As a result, it is possible to quantitatively determine the bias of verification contents, and efficient verification design is possible.

  With reference to FIG. 20, the display output when the user desires detailed information for a specific FF from ff1 to ffN of the output result 1900 will be described. In FIG. 20, the output result 2000 includes an FF operation 2010, an input signal 2020, and a monitoring result 2030. The FF operation 2010 displays all possible FF operations in the FF selected by the user. The input signal 2020 displays all input signal combinations that satisfy the input conditions for the FF operation 2010. The monitoring result 2030 displays by “◯” and “×” whether or not the combination of the input signals indicated by the input signal 2020 is executed by the logic simulation. If there is a pattern that matches the condition even once in the logic simulation, it becomes “◯”, and if there is no pattern that matches at all, it becomes “X”. Here, a logical expression without inversion is shown.

  According to the output result 2000, it is possible to individually know what input patterns are not specifically tested for complex input conditions, and more direct clues for examining test patterns. Can be obtained.

  According to the embodiment described above, it is possible to obtain an objective verification quality index that pays attention to the operation of the FF in the digital circuit described in the hardware description language. Thus, it is possible to suppress the omission of verification, which has conventionally been overlooked only by human subjectivity, and to perform highly efficient verification without waste.

  DESCRIPTION OF SYMBOLS 100 ... Verification support apparatus, 110 ... Memory, 120 ... CPU, 130 ... Storage device, 140 ... Input device, 150 ... Output device, 160 ... Bus, 200 ... Verification support apparatus, 201 ... FF operation condition calculation part, 202 ... FF Operation specification display instruction unit, 203 ... simulation unit, 204 ... coverage totaling unit, 205 ... coverage display instruction unit, 206 ... display unit, 207 ... logic circuit program, 208 ... test pattern, 209 ... input condition information for each FF operation, 210 ... Coverage count result.

Claims (5)

A flip-flop operation condition calculation unit for calculating an operation condition of the flip-flop in the logic circuit;
Flip-flop operation specification display instruction unit for displaying each operation condition of the flip-flop,
A logic unit that performs a logic simulation of the logic circuit program and monitors the success or failure of each operation condition of the flip-flop;
A coverage counting unit that counts whether or not each flip-flop operation is activated by monitor information obtained by condition monitoring;
Coverage display instruction part for displaying coverage totalization results,
A display unit that outputs information in accordance with instructions from the flip-flop operation specification display unit and the coverage display instruction unit;
A verification support apparatus comprising: Receiving a logic circuit program written in a hardware description language;
Calculating a logical expression representing a logic cone centered on a flip-flop from the logic circuit program;
Creating a transition table of the flip-flop from the logical expression;
Calculating an input condition of the operation of the flip-flop based on the transition table;
Verification support method including The verification support method according to claim 2,
The verification support method is characterized in that the operation is an operation to update the state to 1, an operation to update the state to 0, an operation to hold the current state, and an operation to update the current state to an inverted value. The verification support method according to claim 2,
The verification support method further includes the step of displaying the input condition as an operation specification of the flip-flop. The verification support method according to claim 2,
Furthermore, monitoring the success or failure of condition execution by logic simulation for the input condition;
A step of aggregating monitor information obtained by monitoring;
Displaying the coverage information obtained by the aggregation;
Verification support method including

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