JP2014126969A - Semiconductor device and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device allowing reduction in the number of terminals which are of a controller for controlling the semiconductor device and receive a signal for indicating an operational state of the semiconductor device, in order to reduce influences on a substrate area of a memory controller and costs due to an increase in the number of the terminals for receiving RY/BY signal caused by an increase in the number of semiconductor devices to be controlled by the controller.SOLUTION: The semiconductor device outputs a second signal indicating the operational state of itself on the basis of a first signal indicating the operational state of other semiconductor devices.

Description

  The present invention relates to a semiconductor device and an information processing system. In particular, the present invention relates to a semiconductor device including a terminal for notifying the outside of an operation state and an information processing system including the semiconductor device.

  A semiconductor device such as a NAND flash memory has an output terminal for notifying the outside of the operation state inside the chip (for example, during program operation / erasure operation / read operation). Such an output terminal is usually referred to as a ready / busy terminal (RY / BY terminal).

  A memory controller that controls the semiconductor device grasps whether or not a program operation or the like in the semiconductor device is completed based on a signal output from the RY / BY terminal. That is, the memory controller instructs the semiconductor device to perform the next operation after recognizing that the operation being executed in the semiconductor device is completed.

  Here, Patent Documents 1 and 2 disclose a system including a plurality of semiconductor memories and a memory controller for controlling the semiconductor memories. Each of the semiconductor memories in the systems disclosed in Patent Documents 1 and 2 includes an RY / BY terminal, and the memory controller uses a plurality of semiconductors based on RY / BY signals supplied from these RY / BY terminals. Controls data transfer to memory.

JP 2004-046854 A JP 2011-018222 A

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis was made by the present inventors.

  As described above, in the systems disclosed in Patent Documents 1 and 2, the RY / BY terminals of the semiconductor memory are provided independently of the memory controller. In other words, the memory controller needs to accept RY / BY signals output from the respective semiconductor memories. However, such a configuration requires many terminals for receiving the RY / BY signal in the memory controller. For example, in the system shown in FIG. 3 of Patent Document 1, the memory controller requires two terminals for receiving the RY / BY signal. Similarly, in the system shown in FIG. 1 of Patent Document 2, two terminals for receiving the RY / BY signal are required.

  As disclosed in Patent Documents 1 and 2, when the number of semiconductor memories to be controlled by the memory controller is small, the influence of an increase in the number of terminals for receiving RY / BY signals is negligible. However, if the number of semiconductor memories to be controlled by the memory controller increases, an increase in terminals for receiving RY / BY signals becomes a problem. This is because the increase in the number of terminals directly affects the board area and cost of the memory controller. Therefore, a semiconductor device and an information processing system that reduce the number of terminals in the memory controller that receive signals for notifying the operation state of the semiconductor device are desired.

  According to a first aspect of the present invention, there is provided a semiconductor device that outputs a second signal indicating its own operating state to the outside based on a first signal indicating the operating state of another semiconductor device.

  According to the second aspect of the present invention, an input terminal that receives a first signal indicating an operation state of another semiconductor device, and a second signal indicating its own operation state based on the first signal. A plurality of semiconductor devices including a circuit for generating and outputting the second signal from an output terminal, and connecting the input terminal and the output terminal of each of the plurality of semiconductor devices in series, A plurality of semiconductor devices are cascade-connected, and a controller that controls data transfer to the plurality of semiconductor devices based on the second signal output from the last-stage semiconductor device among the plurality of cascade-connected semiconductor devices Is provided.

  According to each aspect of the present invention, there is provided a semiconductor device and an information processing system that contribute to reducing the number of terminals that are terminals in a controller that controls a semiconductor device and that receive a signal for notifying an operation state of the semiconductor device. Provided.

It is a figure which shows an example of the internal structure of the non-volatile memory device 5 which concerns on 1st Embodiment. 1 is a diagram illustrating an example of an information processing system including a semiconductor device according to a first embodiment. It is a timing chart which shows an example of operation of the information processing system concerning a 1st embodiment. It is a figure which shows another example of the information processing system containing the semiconductor device which concerns on 1st Embodiment. It is a figure which shows an example of the information processing system containing a non-volatile memory device.

  An outline of one embodiment will be described. As shown in FIGS. 1 and 2, the semiconductor device (for example, the nonvolatile memory device 5 in FIG. 1) has a first signal (for example, the RY / BY_In terminal in FIG. 1) indicating the operation state of another semiconductor device. Based on the received signal), a second signal indicating its own operating state (for example, a signal output from the RY / BY_Out terminal in FIG. 1) is output to the outside.

  When a semiconductor device outputs a second signal indicating its own operating state to the outside, the semiconductor device superimposes information included in the first signal indicating the operating state of another semiconductor device on the second signal. For example, even if the operation state of itself is the Ready state, the operation state of the other semiconductor device is not the Ready state (that is, if the operation state of the other semiconductor device is the Busy state), Is not output as a Ready state. On the other hand, when both its own operating state and the operating state of another semiconductor device are in the Ready state, it notifies the outside that its own operating state is in the Ready state.

  By connecting such semiconductor devices in cascade as in the information processing system shown in FIG. 2, the operation state of the preceding semiconductor device can be sequentially transmitted to the succeeding semiconductor device. In other words, the second signal output from the last-stage semiconductor device includes information on the operating states of all the cascade-connected semiconductor devices. As a result, in order for a controller that controls a plurality of semiconductor devices to grasp the operating state of these semiconductor devices, it is only necessary to receive the second signal output from the semiconductor device at the final stage, and the number of necessary terminals. Is one terminal. That is, it is possible to reduce the number of terminals in the controller that receive a signal for notifying the operation state of the semiconductor device.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment will be described in more detail with reference to the drawings.

  FIG. 2 is a diagram illustrating an example of an information processing system including the semiconductor device according to the present embodiment. Referring to FIG. 2, the information processing system includes a host interface 1, an MPU (Micro Processing Unit) 2, a RAM (Random Access Memory) 3, a nonvolatile memory controller 4, and nonvolatile memory devices 5-1 to 5. -4.

  In the following description, when it is not necessary to distinguish the nonvolatile memory devices 5-1 to 5-4, they are expressed as “nonvolatile memory device 5”. Further, in the present embodiment, the nonvolatile memory device 5 will be described by taking a resistance change type memory having a resistance change element as a memory cell as an example, but the nonvolatile memory device 5 is limited to the resistance change type memory. is not. For example, the nonvolatile memory device 5 may be a NAND flash memory or the like. Further, the number of the nonvolatile memory devices 5 included in the information processing system is not limited to four, and a plurality of nonvolatile memory devices 5 may be included.

  The host interface 1, MPU 2, RAM 3, and nonvolatile memory controller 4 are each connected via a system bus 100.

  The host interface 1 is connected to a host system such as a personal computer. The MPU 2 implements data transfer between the host system and the nonvolatile memory device 5 by executing a program stored in the RAM 3. The RAM 3 includes an area for storing a program to be executed by the MPU 2 and a primary storage area for storing data when the MPU 2 executes the program.

  The nonvolatile memory controller 4 controls data transfer in the four nonvolatile memory devices 5. More specifically, the nonvolatile memory controller 4 sends a command COM to each nonvolatile memory device 5-1, 5-2, 5 using a control signal input terminal and input / output terminals IO0 to IO31 described later. -3, 5-4, respectively. In addition, the input / output terminals IO0 to IO31 are used to supply an address ADD corresponding to data related to input / output, thereby realizing transmission / reception of data (DATA). The nonvolatile memory controller 4 is independently connected to the control terminals and input / output terminals (IO0 to IO31) included in each of the four nonvolatile memory devices 5.

  The nonvolatile memory controller 4 performs the same kind of data transfer control on the four nonvolatile memory devices 5 in parallel, and confirms that the data transfer control for the four nonvolatile memory devices 5 has been completed. Then, the next data transfer control is performed. For example, after confirming that all the data writes to the four nonvolatile memory devices 5 have been completed, data read to the four nonvolatile memory devices 5 is performed.

  The non-volatile memory device 5 includes a terminal that outputs a RY / BY signal and a terminal that receives a RY / BY signal output from the non-volatile memory device 5 disposed in the preceding stage. A terminal that receives the RY / BY signal output from the non-volatile memory device 5 in the previous stage is referred to as an RY / BY_In terminal. A terminal that outputs the RY / BY signal is referred to as an RY / BY_Out terminal.

  Furthermore, the RY / BY_In terminal and the RY / BY_Out terminal included in each nonvolatile memory device 5 are described in association with the reference numerals of the nonvolatile memory devices 5. For example, the RY / BY_In terminal included in the nonvolatile memory device 5-1 is expressed as RY / BY_In1, and the RY / BY_Out terminal is expressed as RY / BY_Out1.

  Furthermore, the RY / BY signal output from each nonvolatile memory device 5 is also described in association with the code of each nonvolatile memory device 5. For example, a signal output from the RY / BY_Out1 terminal of the nonvolatile memory device 5-1 is represented as an RY / BY1 signal.

  Referring to FIG. 2, it is understood that the RY / BY_In terminals and the RY / BY_Out terminals of the four nonvolatile memory devices 5 are connected in series, and a plurality of nonvolatile memory devices 5 are cascaded (so-called rosary connection). it can.

  As for the first-stage nonvolatile memory device 5-1, since there is no nonvolatile memory device arranged in the preceding stage, the RY / BY_In 1 terminal and the power supply VDD are connected. In addition, the RY / BY_Out4 terminal of the nonvolatile memory device 5-4 at the final stage is connected to the input terminal of the nonvolatile memory controller 4. The RY / BY4 signal output from the non-volatile memory device 5-4 at the final stage is set as the RY / BY_All signal.

  Next, the internal configuration of the nonvolatile memory device 5 will be described.

  FIG. 1 is a diagram illustrating an example of the internal configuration of the nonvolatile memory device 5.

  The nonvolatile memory device 5 includes a variable resistance element (resistance change element) as a memory cell. The nonvolatile memory device 5 includes a control signal input terminal, an input / output terminal, and a power supply terminal in addition to the RY / BY_In terminal and the RY / BY_Out terminal described above.

  The control signal input terminals include a chip enable signal input terminal CEB, a command latch enable signal input terminal CLE, an address latch enable signal input terminal ALE, a write enable signal input terminal WEB, a read enable signal input terminal REB, and a write protect signal input terminal WPB. Consists of various terminals.

  Input / output terminals IO0 to IO7 receive an address ADD and data for accessing a memory cell. Further, the signals received by the input / output terminals IO0 to IO7 include commands for the nonvolatile memory device 5. The nonvolatile memory device 5 is supplied with power from the outside via power supply terminals (VDD, VSS).

  The nonvolatile memory device 5 includes an internal power supply generation circuit 10, a control signal input circuit 11, an input / output control circuit 12, a control logic circuit 13, a command register 14, a status register 15, an address register 16, a row Address buffer 17, column address buffer 18, row decoder 19, column decoder 20, memory cell array 21, sense amplifier 22, write amplifier 23, verify determination circuit 24, data buffer 25, and array control circuit 26 and a logical product circuit 27.

  The internal power supply generation circuit 10 generates various power supplies used inside the nonvolatile memory device 5. The power generated by the internal power generation circuit 10 is supplied to a circuit group (not shown) in addition to the circuit group shown in FIG. Note that INT_Vref and INTV shown in FIG. 1 are generic names of reference voltages and power supplies used in various circuits.

  The control signal input circuit 11 receives a control signal output from the nonvolatile memory controller 4 connected to the nonvolatile memory device 5 via the control signal input terminal. The control signal input circuit 11 outputs the received control signal to the input / output control circuit 12 and the control logic circuit 13.

  The input / output control circuit 12 decodes a command COM input from a signal received via the input / output terminals IO0 to IO7 and a signal output from the control signal input circuit 11, and registers the decoded command in the command register 14. Further, by referring to the status register 15 in which the operation status of the control logic circuit 13 is stored, data transmission / reception via the input / output terminals IO0 to IO7 is realized. The input / output control circuit 12 decodes the address ADD from the signal received via the input / output terminals IO0 to IO7 and registers it in the address register 16. The input / output control circuit 12 stores write data in the data buffer 25 or reads data from the data buffer 25.

  The control logic circuit 13 outputs an internal command INT_com to the array control circuit 26 in accordance with a control signal obtained from the control signal input terminal and a command registered in the command register 14. The control logic circuit 13 causes the array control circuit 26 to access the memory cells included in the memory cell array 21 by outputting the internal command INT_com.

  The control logic circuit 13 receives the response signal RES_com from the array control circuit 26. The response signal RES_com includes the result of access control in the array control circuit 26 (whether or not the access is normally completed). The control logic circuit 13 responds to a command received from the outside in response to the response signal RES_com. Further, the control logic circuit 13 sets the RY / BY signal to be supplied to the AND circuit 27 to the L level when the access control to the memory cell array 21 is being executed (during the program operation, the erase operation, and the read operation). To do. That is, when the RY / BY signal is at L level, the nonvolatile memory device 5 is in the Busy state, and when the RY / BY signal is at H level, it is in the Ready state.

  The address ADD registered in the address register 16 is separated into a row address Radd and a column address Cadd, and stored in the row address buffer 17 and the column address buffer 18, respectively. The row address Radd fetched into the row address buffer 17 is supplied to the row decoder 19. The column address Cadd fetched into the column address buffer 18 is supplied to the column decoder 20.

  The memory cell array 21 includes a plurality of memory cells. Each memory cell includes a variable resistance element 30 and a selection transistor 31. One end of the variable resistance element 30 is connected to the source or drain of the selection transistor 31, and the other end is connected to the power source VEQ. The gate (control terminal) of the selection transistor 31 is connected to the word line WL, and the source or drain is connected to the bit line BL.

  The row decoder 19 selects the word line WL connected to the memory cell to be accessed from the word lines WL extending through the memory cell array 21 by decoding the row address Radd. Similarly, the column decoder 20 decodes the column address Cadd to select the bit line BL connected to the access target memory cell from the bit lines BL extending the memory cell array 21.

  The sense amplifier 22 reads a data stored in the memory cell by applying a predetermined voltage to the bit line BL for a predetermined time and reading a resistance change of the variable resistance element 30.

  The write amplifier 23 writes data to the memory cell by switching the power supply connected to the bit line BL.

  The verify determination circuit 24 is a circuit (data register) that compares data supplied from the outside (nonvolatile memory controller 4) with data read from the memory cell and determines whether they match or not.

  The data buffer 25 is a buffer prepared for transmitting / receiving data to / from the outside via the input / output terminals IO0 to IO7.

  The array control circuit 26 supplies control signals to the row decoder 19, the column decoder 20, the sense amplifier 22 and the write amplifier 23 in accordance with the internal command INT_com supplied from the control logic circuit 13, and the memory included in the memory cell array 21. Access the cell.

  The array control circuit 26 outputs a control signal Rcont to the row decoder 19 and outputs a control signal Ccont to the column decoder 20. The array control circuit 26 outputs the write enable signal WRen and the read enable signal RDen to circuits such as the sense amplifier 22 and the write amplifier 23. The array control circuit 26 receives the determination signal Judge from the verify determination circuit 24.

  The verify determination circuit 24 verifies the data read from the memory cell when the internal command INT_com indicates data programming, and outputs a determination signal Judge as a verification result. The array control circuit 26 ends the program operation when the determination signal Judge matches the data read from the memory cell with the data instructed to program the memory cell.

  Next, the operation of the information processing system including the nonvolatile memory device 5 according to this embodiment will be described.

  FIG. 3 is a timing chart showing an example of the operation of the information processing system according to the present embodiment. In the following description, the RY / BY signal generated inside the nonvolatile memory device 5 is referred to as an internal RY / BY signal, and is described in association with the code of each nonvolatile memory device 5. For example, an internal RY / BY signal generated inside the nonvolatile memory device 5-1 is expressed as RY / BY_I1. As described above, RY / BY1 to RY / BY4 are RY / BY signals output from the four nonvolatile memory devices 5, respectively.

  At time T <b> 01, the nonvolatile memory controller 4 starts control related to data writing with respect to the four nonvolatile memory devices 5. More specifically, the nonvolatile memory controller 4 sequentially inputs a write command and supplies write data using a control terminal and an IO bus connected to each of the four nonvolatile memory devices 5. The issue of the write command in the nonvolatile memory controller 4 is based on an instruction input from the host system via the host interface 1. The nonvolatile memory device 5 that has been supplied with a write command or the like starts a program operation.

  Since the operation state of the nonvolatile memory device 5 is during the program operation, the control logic circuit 13 included in each of the four nonvolatile memory devices 5 sets the internal RY / BY signal to the L level (from T02 to T03). period). When the internal RY / BY signal transitions to the L level, the output of the AND circuit 27 becomes the L level regardless of the RY / BY signal output from the non-volatile memory device 5 in the previous stage. Alternatively, the output of the AND circuit 27 becomes L level in response to the RY / BY signal output from the non-volatile memory device 5 in the previous stage being set to L level. Therefore, the RY / BY_All signal (RY / BY4 signal) transitions to the L level when at least one of the nonvolatile memory devices 5-1 to 5-4 sets the RY / BY signal to the L level (time T02). .

  Thereafter, the four nonvolatile memory devices 5 set the internal RY / BY signals to the H level in response to the end of the respective program operations (period T04 to T07). Here, when the internal RY / BY signal is set to H level and the RY / BY signal output from the nonvolatile memory device 5 in the previous stage is also at H level, the AND circuit 27 outputs the RY / BY signal at H level, Output from the RY / BY_Out terminal. For example, referring to FIG. 3, the internal RY / BY signal (RY / BY_I4) of the nonvolatile memory device 5-4 is changed to the H level at time T05, but the nonvolatile memory device 5-3 outputs the signal. Since the RY / BY3 signal is still at the L level, the RY / BY4 signal does not change from the L level.

  At time T07, in response to the RY / BY3 signal transitioning to the H level, the RY / BY4 signal (that is, the RY / BY_All signal) becomes the H level. The non-volatile memory controller 4 can perform control following the data write after confirming that the RY / BY_All signal is at the H level. That is, the nonvolatile memory controller 4 can perform the following control after confirming that all of the four nonvolatile memory devices 5 have transitioned to the Ready state.

  Note that the control related to the data read for the four nonvolatile memory devices 5 of the nonvolatile memory controller 4 can be performed in the same manner as the control related to the data write, and the description thereof will be omitted. More specifically, the nonvolatile memory controller 4 issues a read command instead of issuing a write command, and instead of supplying write data to the IO bus, each of the four nonvolatile memory devices 5 becomes an IO bus. Read the supplied data sequentially. Further, the control related to the RY / BY signal in the nonvolatile memory controller 4 is the same as the control at the time of data writing (after the H level of the RY / BY_All signal is confirmed, the following control is performed).

  In the present embodiment, the configuration in which all the nonvolatile memory devices 5 included in the information processing system are connected in cascade has been described. However, it is not necessary to connect all the non-volatile memory devices 5 in cascade, and a configuration in which the units controlled by the non-volatile memory controller 4 are grouped and the RY / BY signals are grouped may be adopted.

  FIG. 4 is a diagram illustrating another example of the information processing system including the semiconductor device according to the present embodiment. 4, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  Referring to FIG. 4, the nonvolatile memory controller 4a controls data transfer between a group including the nonvolatile memory devices 5-1 and 5-2 and a group including the nonvolatile memory devices 5-3 and 5-4, respectively. It is a unit concerning. The IO buses of the nonvolatile memory devices 5-1 and 5-2 and the IO buses of the nonvolatile memory devices 5-3 and 5-4 are controlled independently of each other. The non-volatile memory controller 4a is a non-volatile memory device 5 included in each group, and outputs RY / BY signals output from the non-volatile memory devices 5-2 and 5-4 located in the last stage to the RY, respectively. / BY_All_1 signal, RY / BY_All_2. The RY / BY_All_1 signal conveys information that summarizes the operation state of the nonvolatile memory devices 5-1 and 5-2, and the RY / BY_All_2 signal summarizes the operation state of the nonvolatile memory devices 5-3 and 5-4. Communicate information.

  As described above, the nonvolatile memory devices 5 included in the information processing system are divided into a plurality of groups including at least two or more nonvolatile memory devices 5, and the nonvolatile memory devices 5 are cascaded in the group. . Further, the non-volatile memory controller 4a is included in the grouped group, and among the non-volatile memory devices 5 connected in cascade, the non-volatile memory controller 4a is based on the RY / BY_All signal output from the non-volatile memory device 5 at the final stage. Data transfer to the nonvolatile memory devices 5 included in each group is controlled.

  Further, in the present embodiment, the description has been given assuming that the nonvolatile memory device 5 is in the Busy state when the RY / BY signal output from each nonvolatile memory device 5 is at the L level. However, this is not intended to limit the logic level of the RY / BY signal. Of course, when the RY / BY signal is at the H level, the nonvolatile memory device 5 can be in the Busy state. Alternatively, the logical level of the internal RY / BY signal generated inside the nonvolatile memory device 5 may be different from the logical level of the RY / BY signal output from the RY / BY_Out terminal. In such a case, the internal RY / BY signal output from the control logic circuit 13 may be inverted by an inverter circuit or the like and input to the logical product circuit 27.

  Further, an AND circuit 27 is used as a circuit for outputting the RY / BY signal based on the RY / BY signal output from the non-volatile memory device 5 in the previous stage and the internal RY / BY signal generated by the control logic circuit 13. However, this does not mean that the circuit for generating the RY / BY signal is limited to the logical product operation circuit. A circuit corresponding to the logical product circuit 27 may be realized by combining other logical operation circuits.

  As described above, the information processing system including the nonvolatile memory device 5 according to the present embodiment has a configuration in which a plurality of nonvolatile memory devices 5 are connected in cascade. Furthermore, the non-volatile memory controller 4 executes data transfer control for the non-volatile memory device 5 based on the RY / BY_All signal that reflects the information regarding the operation states of the four non-volatile memory devices 5 included in the information processing system. . As a result, the number of terminals necessary for the nonvolatile memory controller 4 to grasp the operating states of the four nonvolatile memory devices 5 can be set to 1, and the number of terminals necessary for the nonvolatile memory controller 4 can be reduced. Can be reduced.

  Further, as disclosed in Patent Documents 1 and 2, when each device included in the system is connected to a memory controller, the problem is that the bus area is compressed according to the increase in the number of chips mounted like an SSD. However, in the information processing system including the nonvolatile memory device 5 according to the present embodiment, such a problem does not occur.

  Here, if the purpose is simply to reduce the number of terminals in the non-volatile memory controller 4, it is conceivable to employ a configuration as shown in FIG. When the RY / BY signal shown in FIG. 5 is at the L level, it indicates that each nonvolatile memory device is in the Ready state. 5 is a wiring capacity of wiring that connects the nonvolatile memory devices 201 to 204 and the nonvolatile memory controller 300.

  The information processing system shown in FIG. 5 is configured to share the output terminals (output nodes) of the nonvolatile memory devices 201 to 204.

  In the system configuration as shown in FIG. 5, it is necessary to increase the resistance value of the resistor R01. This is because it is necessary to reduce the current flowing from the power supply VDD to the ground of the nonvolatile memory devices 201 to 204.

  However, when the resistance value is increased, there arises a problem that it takes a long time until information indicating that all the nonvolatile memory devices 201 to 204 have transitioned to the Ready state is transmitted to the host system. This is because the time from when the transistor T01 included in the nonvolatile memory devices 201 to 204 is turned off and the potential of the output terminal rises from the ground voltage VSS to the power supply voltage VDD depends on the resistance value of the resistor R01.

  Even if the rise time of the output terminal potential is somewhat longer, it may be allowed in a system using a NAND flash memory or the like, but in a system using a non-volatile memory that requires high-speed operation, There is a risk of speeding up. Examples of the memory that requires high-speed operation include a resistance change memory (ReRAM), a PRAM (Phase change RAM), and an STTRAM (Spin Torque Transfer RAM) according to the present embodiment. .

  On the other hand, in the information processing system including the nonvolatile memory device 5 according to the present embodiment, a configuration in which a plurality of nonvolatile memory devices 5 are cascade-connected is provided, so that the output terminals (RY / BY_Out) of the respective nonvolatile memory devices 5 are connected. Terminal) can be reduced, and wiring required between the nonvolatile memory controller 4 and the nonvolatile memory device 5 can be reduced.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) within the scope of the claims of the present invention, Selection is possible. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. In particular, with respect to the numerical ranges described in this document, any numerical value or small range included in the range should be construed as being specifically described even if there is no specific description.

1 Host interface 2 MPU (Micro Processing Unit)
3 RAM (Random Access Memory)
4, 4a, 300 Nonvolatile memory controller 5, 5-1 to 5-4, 201 to 204 Nonvolatile memory device 10 Internal power generation circuit 11 Control signal input circuit 12 Input / output control circuit 13 Control logic circuit 14 Command register 15 Status Register 16 Address register 17 Row address buffer 18 Column address buffer 19 Row decoder 20 Column decoder 21 Memory cell array 22 Sense amplifier 23 Write amplifier 24 Verify determination circuit 25 Data buffer 26 Array control circuit 27 AND circuit 30 Variable resistance element 31 Select transistor 100 System bus C01 Wiring capacitance R01 Resistance T01 Transistor

Claims (7)

  A semiconductor device characterized in that, based on a first signal indicating an operating state of another semiconductor device, a second signal indicating its own operating state is output to the outside.   When the first signal indicates the first operation state and the own operation state is the first state, the second signal is output and the operation state is the second state. In this case, the semiconductor device according to claim 1, wherein the second signal is not output regardless of the state indicated by the first signal.   3. The semiconductor device according to claim 2, wherein, when the first signal indicates the second operation state, the second signal is not output regardless of its operation state.   The signal obtained by performing a logical product operation on the first signal and a third signal that is generated internally and that indicates an operation state of the first signal is defined as the second signal. The semiconductor device according to any one of 1 to 3. A memory cell;
A control circuit for controlling access to the memory cell;
With
5. The semiconductor device according to claim 4, wherein the control circuit generates the third signal while executing any one of a program operation, an erase operation, and a read operation for the memory cell. An input terminal for receiving a first signal indicating an operating state of another semiconductor device;
Based on the first signal, a second signal indicating its own operating state is generated, and a circuit that outputs the second signal from an output terminal;
A plurality of semiconductor devices comprising:
By connecting the input terminal and the output terminal of each of the plurality of semiconductor devices in series, the plurality of semiconductor devices are connected in cascade, and the semiconductor device at the last stage among the plurality of semiconductor devices connected in cascade A controller for controlling data transfer to the plurality of semiconductor devices based on the second signal output by
An information processing system comprising: The plurality of semiconductor devices are divided into a plurality of groups including at least two or more semiconductor devices, and the plurality of semiconductor devices included in the divided groups are connected in cascade.
The controller outputs the second signal based on the second signal output from the last-stage semiconductor device among the cascaded semiconductor devices included in the divided group. The information processing system according to claim 6, wherein data transfer to a plurality of semiconductor devices included in the group is controlled.

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