JP2014126931A - Logic circuit device for data processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sorter for pull scheduling with a single comparator.SOLUTION: There is provided a device which has buffer queues of a plurality of stages and processes data by propagating the data from a lower stage to an upper stage while decreasing the data by 1/N (suitably, N: 2, where "m" is an integer equal to or larger than 2), the device including a single comparator which is arranged between buffer queues of adjacent stages and compares a pair of entries of a buffer queue and carries a value to a buffer of an upper stage according to a comparison result, and receiving specification of positions of a pair of entries of a buffer queue that each comparator should compare from an upper stage and then specifying them to a lower stage. A typical application example of this configuration is a sorter. Further, the device is provided with index queues of the plurality of stages which receive and store specification of positions of the pair of entries of buffer queues that each comparator should compare.

Description

  The present invention relates to a data processing logic circuit device that has a plurality of buffer queues and performs processing while sending data from a lower stage to an upper stage. One specific example is a sorter implemented by an FPGA or the like.

  A sorter having a plurality of buffer queues uses a comparator (comparator) for comparing data when data is sent from the lower stage to the upper stage. Such a sorter has a configuration in which data is compared at once by a plurality of comparators. However, if a plurality of comparators are provided, there is a problem that the hardware size increases.

  Therefore, a sorter with a single comparator configuration between the lower and upper stages, saving hardware size, was proposed by Kerming Fleming et al., "High-throughput Pinelined Mergesort", MIT-CSAIL, 2008, etc. . However, if there is a single comparator, scheduling in which order the comparators are applied is necessary.

  Scheduling includes push scheduling in which data is sent from the lower stage to the upper stage and pull scheduling in which the upper stage requests and pulls data from the lower stage.

  However, in order to realize push scheduling, there is still a problem that relatively large-scale hardware is required and latency is large.

  At this time, push size scheduling is pull scheduling, so that the hardware size can be further saved. A known algorithm is to process and move data when the inputs are complete and the output buffer is not full.

  As a conventional technique, Japanese Patent Application Laid-Open No. 5-151166 discloses that a comparison unit compares and determines whether or not the head data stored in the reception buffer is suitable for the sort order with respect to the memory data indicated by the index register of the data memory. If “appropriate”, the control unit inserts and registers the head data of the reception buffer before the memory data indicated by the index register, and if the sorting order is “no”, the index register indicates by the control unit. Disclosed is a sorter configured to update memory data to the next data position so that the above-described sorting order suitability determination process is always performed on the memory data after the latest sorting position.

  Japanese Patent Application Laid-Open No. 7-160475 creates auxiliary information list by acquiring auxiliary information including an identifier of a block and a representative key value of the block for each write block at the time of merge target list group generation processing of merge sort processing. Next, the auxiliary information list is sorted according to the representative key value, the sorted auxiliary information list is divided into sub auxiliary information lists, each is assigned to each processing device, and each processing device is assigned to the sub auxiliary information assigned to itself. A configuration is disclosed in which merge processing is performed in parallel according to an information list to complete sort processing.

Japanese Patent Application Laid-Open No. 10-336216 discloses that in order to sort data elements each including a sort key, the storage means can include each element, and n consecutive numbers numbered from 0 to n−1. Stage q is organized according to a binary tree having 2 ⁿ -1 nodes with nodes 2 ^q to 2 ^{q + 1} -1 and elements are included in node i Are distributed in the tree such that they have a sort key that is smaller than the sort keys of the elements contained in nodes 2i and 2i + 1, each having n-1 interface registers 26q between stages 20q or successive stages. By m consecutive controllers 21q combined with several consecutive stages of the tree (2 ≦ m ≦ n) It discloses a sorter tree is managed.

  However, these prior arts do not suggest a single comparator, pull scheduling sorter configuration that can save hardware size.

JP-A-5-151166 JP-A-7-160475 Japanese Patent Laid-Open No. 10-336216

Kerming Fleming et al., "High-throughput Pinelined Mergesort", MIT-CSAIL, 2008

  It is an object of the present invention to provide a pull scheduling sorter with a single comparator.

  Another object of the present invention is to provide a technique for avoiding deadlocks in a single comparator and pull scheduling sorter by ensuring that the output buffer is not always full during operation.

According to this invention, it has a multi-stage buffer queue, and processes data by propagating to the upper stage while decreasing by 1 / N (N is preferably 2 ^m , m is an integer of 1 or more) from the lower stage. A device having a single comparator that is arranged between adjacent stage buffer queues, compares the entries of a pair of buffer queues and raises the value of the upper stage buffer based on the comparison result; An apparatus is provided for receiving designations from the upper stage of the entry of the pair of buffer queues to be compared by each comparator and making designations to the lower stage. A typical application of this configuration is a sorter.

  According to one aspect of the present invention, a multi-stage index queue is provided that receives and stores designations of entry positions of buffer queue pairs to be compared by each comparator from the upper stage.

  According to another aspect of the invention, in response to neither of the pair of entries being empty and the lower level index queue being full, the comparator is operated to cause the contents of one of the pair of entries. Is a logic circuit that executes processing for sending the request for the index of the one entry to the lower stage and popping the first element of the index queue of the stage Is provided.

  According to yet another aspect of the invention, the logic circuit performs a function of sending a request for an index of an empty entry to the lower stage in response to either of the pair of entries being empty.

  According to still another aspect of the present invention, in order to avoid deadlock, when the buffer queue is full, an attempt to add more elements does not cause overflow. In addition, the buffer queue is designed to be full at the end of startup to achieve high performance. For this reason, the size of the buffer queue is made equal to the size of the index queue.

  According to still another aspect of the present invention, in order to achieve high performance, the buffer queue is never emptied in a steady state when the latency of receiving a request from the upper stage is L in cycle number. The size of the buffer queue is set to L + 1 or more.

  As described above, according to the present invention, it is possible to realize a sorter that operates efficiently with a small amount of hardware consumption when mounted in hardware by a configuration of pull scheduling with a single comparator.

It is a block diagram of the hardware constitutions of the apparatus of this invention. It is a block diagram of the hardware constitutions of the apparatus of this invention. It is a figure for demonstrating the function of the hardware constitutions of the apparatus of this invention. It is a block diagram of a function structure of the apparatus of this invention. It is a figure which shows the flowchart of a process of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the start-up cycle of the apparatus of this invention. It is a figure which shows operation | movement of the steady cycle of the apparatus of this invention. It is a figure which shows operation | movement of the steady cycle of the apparatus of this invention. It is a figure which shows operation | movement of the steady cycle of the apparatus of this invention. It is a figure which shows operation | movement of the steady cycle of the apparatus of this invention. It is a figure which shows operation | movement of the steady cycle of the apparatus of this invention. It is a figure which shows operation | movement of the steady cycle of the apparatus of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. It should be understood that these examples are for the purpose of illustrating preferred embodiments of the invention and are not intended to limit the scope of the invention to what is shown here. Further, throughout the following drawings, the same reference numerals denote the same objects unless otherwise specified.

  FIG. 1 is a block diagram of a hardware configuration of a sorter according to an embodiment of the present invention. This configuration is produced by an FPGA (Field Programmable Gate Array).

  A typical use of this sorter is an ETL (Extract / Transformation / Load) database product that receives database record columns from an ETL / database engine, sorts them by a specific key, and then returns them to the ETL / database engine. The usage is to return a sorted record sequence. However, the present invention is not limited to this, and any sorter can be used.

In this embodiment, it is implemented as a four-stage buffer queue array. However, the number of stages and the number of buffer queues in each buffer queue array are appropriately set according to the purpose of use, but as the process proceeds to the upper stage. From the lower stage, 1 / N (N is preferably 2 ^m , m is an integer of 1 or more) is set to decrease. In this embodiment, m = 1.

  The configuration of FIG. 1 has buffer queue arrays 102, 104, 106 and 108. For example, data is sent from the data input logic circuit 110 connected to the memory bus while being sorted in the order of the buffer queue arrays 102, 104, 106 and 108, and sorted to the data output logic circuit 112 connected to the memory bus, for example. The operation to output the recorded data is performed.

  The lowermost buffer queue array 102 has eight buffer queues 102a, 102b, 102c, 102d, 102e, 102f, 102g, and 102h, and the upper buffer queue array 104 has four buffer queues. 104a, 104b, 104c, and 104d, the upper buffer queue array 106 has two buffer queues 104a and 104b, and the uppermost buffer queue array 108 has a single 108a.

  Between the buffer queue array 102 and the buffer queue array 104, a single comparator 114 for comparing the values of the two buffer queues of the buffer queue array 102 and feeding them to the buffer queue array 104, and a scheduler A scheduler 116 that receives a request from 120 and designates the position of a buffer queue to which the comparator 114 performs a comparison operation is arranged.

  Between the buffer queue array 104 and the buffer queue array 106, a single comparator 118 for comparing the values of the two buffer queues of the buffer queue array 104 and feeding them to the buffer queue array 106, and a scheduler A scheduler 120 that receives a request from 124 and designates the position of a buffer queue to which the comparator 118 performs a comparison operation is arranged.

  Between the buffer queue array 106 and the buffer queue array 108, a single comparator 122 for comparing the values of the two buffer queues of the buffer queue array 106 and feeding them to the buffer queue array 108, and data A scheduler 124 that receives a request from the output logic circuit 112 and designates the position of the buffer queue where the comparator 122 performs the comparison operation is arranged.

  Each of the schedulers 116, 120, and 124 has an index queue for storing indexes from the upper buffer queue array, as shown in FIG. Hereinafter, the index queue of the scheduler 116 is indicated by a symbol 116a, and the index queue of the scheduler 120 is indicated by a symbol 120a. The data input logic circuit 110 also has a scheduler function for designating a position for sending data from the memory bus to the buffer queue array 102.

  FIG. 2 shows a part of a configuration logically equivalent to the configuration of FIG. That is, in the configuration of FIG. 1, the comparator and the scheduler are shown as separate components, but in FIG. 2, the comparator 122 is shown as including the function of the scheduler 124 shown in FIG. It should be understood that this is simply a matter of calling functional elements and not essential.

  FIG. 3 is a diagram schematically illustrating the functions of the comparator and the scheduler. That is, as shown in FIG. 3, the scheduler 120 in the upper stage (also referred to as a stage) sends a request as a 2-bit index to the scheduler 116 in the immediately lower stage.

The scheduler 116 processes this request and sends control signals to the following four locations.
(1) A signal for designating the write position of the buffer queue array 104. Each buffer queue array has a write index, as shown in FIG. 4 or FIG. That is, an instruction is given to write to the i-th buffer queue from the 0th.
(2) Reading position indication of the buffer queue array 102 lower than the buffer queue array 104. Each buffer queue array has a read index, as shown in FIG. 4 or FIG. That is, an instruction is given such that data is read from the i * 2 and i * 2 + 1th buffer queues using the read index, and compared by the comparator 114.
(3) Control signal for the comparator 114. That is, the processing of the comparator 114 is started. In addition, a control completion signal is received from the comparator 114.
(4) Requests for lower level schedulers. If the lower buffer queue array is at the bottom, the data input logic 110 acts as a scheduler.
Such a function is common to the schedulers 120 and 124.

  Next, the logical function of the sorter shown in FIG. 1 will be described with reference to FIG. First, as shown in FIG. 1, each buffer queue array has one or more buffer queues, but each buffer queue has a plurality of entries (elements) as shown in FIG. As also shown in FIG. 4, FIG. 6, etc., the index queue also has a plurality of entries. According to one aspect of the invention, to avoid deadlock, the size of the buffer queue entry and the size of the index queue are chosen subject to predetermined constraints. This restriction will be described later.

  Further, FIG. 4 shows that the comparator 114 compares even and odd numbered pairs of buffer queues in the buffer queue array 102. As shown in FIG. 4, each such buffer queue pair is numbered as a read index, 0,1,2,3, and an entry in the index queue 116a points to this read index. .

  Next, the function of the sorter in FIG. 1, particularly the processing of the scheduler, will be described with reference to the flowchart in FIG. FIG. 5 shows the process of the scheduler at each stage. Accordingly, each scheduler executes the processing shown in FIG.

  In step 502, the scheduler determines whether its index queue is empty, and if so, does nothing in step 524, and if there is a request from the above stage in step 526, the index queue. Is added to the end of, and the process ends.

  If the scheduler determines in step 502 that its index queue is not empty, it stores the first element of the index queue in a variable i in step 504, and the index queue in the lower stage is full in step 506. If so, do nothing at step 524, and add at the end of the index queue if there is a request from the upper stage at step 526, and terminate the process.

  If the lower stage index queue is not full, the scheduler determines in step 508 whether the lower stage buffer queue i * 2 is empty. If so, the scheduler sends a request (i * 2) to the lower stage at step 510, and adds a request from the upper stage to the end of the index queue at step 526 for processing. Exit.

  If the lower stage buffer queue i * 2 is not empty, the scheduler determines in step 512 whether the lower stage buffer queue i * 2 + 1 is empty. If so, the scheduler sends the request (i * 2 + 1) to the lower stage at step 514, and at step 526, if there is a request from the upper stage (stage), it is placed at the end of the index queue. Add and finish the process.

  If the scheduler determines that neither the input-side buffer queue i * 2 nor the lower-stage buffer queue i * 2 + 1 is empty, the scheduler, at step 516, a: = the first value of the lower-stage buffer queue i * 2 , B: = Store with the first value of the buffer queue i * 2 + 1 of the lower stage.

  In step 518, the comparator compares the values of a and b. If a> b, b is added to the output side, that is, the end of the buffer queue i of the upper buffer queue array in step 520, and the request (i * 2 + 1) is sent to the lower stage, the first value of the input buffer queue i * 2 + 1 is deleted, the first value (i) of the index queue is deleted, and in step 526, the upper stage (stage) is deleted. If there is a request, add it to the end of the index queue and finish the process.

  If the comparator determines in step 518 that a> b is not true, in step 522 a is added to the output side, that is, the end of buffer queue i of the upper buffer queue array, and request (i * 2) is added to the lower stage. , Delete the top value of the input buffer queue i * 2, delete the top value (i) of the index queue, and if there is a request from the upper stage in step 526, the index queue Is added to the end of, and the process ends.

  In the above processing, in steps 510, 514, 522, and 524, processing for sending a request to the lower stage is performed. In this configuration, at the time when the request is thrown, the following condition setting is performed. Guarantees that the output buffer queue will not fill up.

  That is, at startup, the size of the buffer queue is made equal to the size of the index queue so that the buffer queue is full and never overflows. The size of the index queue here is the size of the index queue immediately below the buffer queue.

  Further, when the latency for receiving a request from the upper stage is L in terms of the number of cycles, the size of the buffer queue is set to L + 1 or more so that the buffer queue never becomes empty in a steady state. In more detail, the latency is the latency from when a request from the stage immediately above the buffer queue is issued until the requested data is written to the buffer queue.

  By setting in this way, the process shown in the flowchart of FIG. 5 can avoid deadlock without particularly checking whether the output buffer queue is empty.

  Next, an example of the operation of the configuration of FIG. 1 will be described with reference to FIGS. In this embodiment, the size of the buffer queue of the lowermost buffer queue array 102 is 3, while the size of the buffer queues of the two buffer queue arrays 104 and 106 above it is 2. Thus, the buffer queue size does not need to be the same for each buffer queue array, and may be set to a different size. However, due to the above-mentioned restrictions, the size of the buffer queue and the size of the index queue immediately below it are made the same. In the example of FIG. 6, the index queue 116a is directly below the buffer queue array 104.

  The sorter operation consists of a start-up cycle and a steady cycle. FIG. 6 is a diagram showing the startup cycle 1. In FIG. 6, since the first entry of the buffer queue 104a and the buffer queue 104b of the buffer queue array 104 is empty, the scheduler 120 sends a request with index = 0 to the scheduler 116 of the lower buffer queue array 102.

  In the next start-up cycle 2 shown in FIG. 7, since the top entries of the buffer queue 104a and the buffer queue 104b of the buffer queue array 104 are still empty, the scheduler 120 sends the request with the index = 0 to the lower buffer queue. It is sent again to the scheduler 116 of the array 102. In this way, the scheduler 116 receives the request, but the scheduler 116 sends the request to the lower input logic circuit 110 because the top entries of the buffer queue 102a and the buffer queue 102b of the buffer queue array 102 are empty.

  In the next start-up cycle 3 shown in FIG. 8, the top entries of the buffer queue 104a and the buffer queue 104b of the buffer queue array 104 are still empty, but the scheduler queue 120 is full because the lower-level index queue 116a is full. do nothing. On the other hand, the scheduler 116 sends a request to the lower input logic circuit 110 because the first entry in the buffer queue 102a and the buffer queue 102b of the buffer queue array 102 is empty.

  In the next startup cycle 4 shown in FIG. 9, the first entry of the buffer queue 104a and the buffer queue 104b of the buffer queue array 104 is still empty, but the scheduler queue 120 is full because the lower-level index queue 116a is full. do nothing. On the other hand, the scheduler 116 waits for an entry to be stored at the head of both the buffer queue 102a and the buffer queue 102b of the buffer queue array 102.

  FIG. 10 is a diagram showing the startup cycle 7. Even at this stage, the top entries of the buffer queue 104a and the buffer queue 104b of the buffer queue array 104 are still empty, but the scheduler 120 does nothing because the lower-level index queue 116a is full. On the other hand, the scheduler 116 has an entry stored in the buffer queue 102a of the buffer queue array 102, but since the entry in the buffer queue 102b is still empty, it waits for the entry to be stored at the head of both.

  FIG. 11 is a diagram showing the startup cycle 8. The first entry of the buffer queue 104a and the buffer queue 104b of the buffer queue array 104 is still empty, but the scheduler 120 does nothing because the lower-level index queue 116a is full. On the other hand, the scheduler 116 starts to operate because the values are stored at the heads of both the buffer queue 102a and the buffer queue 102b of the buffer queue array 102, whereby the head entry of the buffer queue 102a becomes the buffer queue array. Popped to the buffer queue 104a of 104.

  In the startup cycle 9 of FIG. 12, since the buffer queue 104a is no longer empty, while the buffer queue 104b is still empty, the scheduler 120 sends a request with index = 1. On the other hand, in response to the entry in the index queue 116 a, the buffer queue 102 a and the buffer queue 102 b in the buffer queue array 102 are compared by the comparator 114, and the result is popped in the buffer queue 104 a in the buffer queue array 104.

  In the startup cycle 10 of FIG. 13, two entries are pushed into the buffer queue 104a of the buffer queue array 104 in correspondence with the two entries in the index queue.

  14 to 19 show the operation of a steady cycle. 14 to 19, the index queues 116a, 120a, and 124a are shown as a single element for convenience, but are actually two elements. In the steady cycle 1 of FIG. 14, the index queue 124a of the scheduler 124 points to the read index = 0 of the buffer queue array 106. As a result, the top entries of the buffer queue 106a and the buffer queue 106b are compared by the comparator 122. The top entry of the buffer queue 104a becomes the movement target in the upper stage. In addition, the write index of the buffer queue 104a to be moved is used in the next cycle.

  Further, in FIG. 14, the index queue 120a points to the read index = 1 of the buffer queue array 104. As a result, the top entries of the buffer queue 104c and the buffer queue 104d are compared by the comparator 118, and the head of the buffer queue 104c is compared. The entry is moved to the upper row. Further, the write index of the buffer queue 104c that is the movement target is used in the next cycle.

  Further, in FIG. 14, the index queue 116a points to the read index 1 of the buffer queue array 102. As a result, the top entries of the buffer queue 102c and the buffer queue 102d are compared by the comparator 114, and the top of the buffer queue 104c is compared. The entry becomes the movement target in the upper row.

  FIG. 15 shows the continuation of steady cycle 1. That is, in FIG. 15, the head entry of the buffer queue 106 a of the buffer queue array 106 is sent to the data output logic circuit 112, and the head entry of the buffer queue 104 c of the buffer queue array 104 is the buffer of the buffer queue array 106. The first entry of the buffer queue 102d of the buffer queue array 102 is sent to the buffer queue 104b of the buffer queue array 104.

  In steady cycle 2 of FIG. 16, the index queue 124a of the scheduler 124 points to the read index = 0 of the buffer queue array 106. As a result, the top entries of the buffer queue 106a and the buffer queue 106b are compared by the comparator 122. The top entry of the buffer queue 104a becomes the movement target in the upper stage. In addition, the write index of the buffer queue 104a to be moved is used in the next cycle.

  Further, in FIG. 16, the index queue 120a points to the read index = 0 of the buffer queue array 104. As a result, the top entries of the buffer queue 104a and the buffer queue 104b are compared by the comparator 118, and the head of the buffer queue 104a is compared. The entry is moved to the upper row. In addition, the write index of the buffer queue 104a to be moved is used in the next cycle.

  Further, in FIG. 16, the index queue 116a points to the read index = 2 of the buffer queue array 102. As a result, the top entries of the buffer queue 102e and the buffer queue 102f are compared by the comparator 114, and the head of the buffer queue 104f is compared. The entry is moved to the upper row.

  FIG. 17 shows the continuation of steady cycle 2. That is, in FIG. 17, the head entry of the buffer queue 106 a of the buffer queue array 106 is sent to the data output logic circuit 112, and the head entry of the buffer queue 104 a of the buffer queue array 104 is the buffer of the buffer queue array 106. The first entry in the buffer queue 102 f of the buffer queue array 102 is sent to the buffer queue 104 c of the buffer queue array 104.

  In steady cycle 3 of FIG. 18, the index queue 124a of the scheduler 124 points to the read index = 0 of the buffer queue array 106. As a result, the top entries of the buffer queue 106a and the buffer queue 106b are compared by the comparator 122. The top entry of the buffer queue 104b becomes the movement target in the upper stage. Further, the write index of the buffer queue 104b that is the movement target is used in the next cycle.

  Further, in FIG. 18, the index queue 120a points to the read index = 0 of the buffer queue array 104. As a result, the top entries of the buffer queue 104a and the buffer queue 104b are compared by the comparator 118, and the head of the buffer queue 104b is compared. The entry is moved to the upper row. Further, the write index of the buffer queue 104b that is the movement target is used in the next cycle.

  Further, in FIG. 18, the index queue 116a indicates the read index = 0 of the buffer queue array 102. As a result, the top entries of the buffer queue 102a and the buffer queue 102b are compared by the comparator 114, and the head of the buffer queue 104a is compared. The entry is moved to the upper row.

  FIG. 19 shows the continuation of steady cycle 2. That is, in FIG. 19, the head entry of the buffer queue 106 a of the buffer queue array 106 is sent to the data output logic circuit 112, and the head entry of the buffer queue 104 b of the buffer queue array 104 is the buffer of the buffer queue array 106. The first entry of the buffer queue 102 a of the buffer queue array 102 is sent to the buffer queue 104 a of the buffer queue array 104.

  As described above, the embodiments of the specific number of buffer queue arrays, the buffer queue size, and the index queue size (number of elements) have been described. Any number of buffer queue array stages, buffer queue sizes, and index queue numbers can be used.

  Further, the preferred implementation of the configuration of the present invention is hardware implementation using a rewritable logic element such as FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device). The logic circuit built on the silicon wafer may be used, or may be implemented by software. In the case of software implementation, the operation speed is generally lower than that of hardware implementation. However, when the functions of the present invention are coded, the code description can be rationalized by simplifying the functions.

102, 104, 106 ... Buffer queue array 114, 118, 122 ... Comparator 116, 120, 124 ... Scheduler 116a, 120a, 124a ... Index queue

Claims (10)

A device that has multiple stages of buffer queues and processes data by propagating to the upper stage while decreasing by 1 / N (N is an integer of 2 or more) from the lower stage,
A single comparator located between adjacent stage buffer queues that compares entries in a pair of buffer queues and increments the upper stage buffer based on the comparison results;
Each comparator receives the specification of the position of the entry of the buffer queue pair to be compared from the upper stage, and performs the specification to the lower stage.
apparatus.   The apparatus of claim 1, further comprising a multi-stage index queue that receives and stores designations of buffer queue pair entries to be compared by each comparator from the upper stage. In response to the fact that neither of the pair of entries is empty and the lower-level index queue is not full, the comparator is operated to send the contents of one of the pair of entries to the upper level, And a means for sending a request for the index of the one entry to the lower stage,
The apparatus of claim 2, further comprising means for popping the first element of the stage index queue.   The apparatus of claim 1, further comprising means for sending a request for an index of an empty entry to a lower stage in response to either of the paired entries being empty.   The apparatus according to claim 2, wherein a size of the buffer queue is equal to a size of the index queue immediately below the buffer queue.   The buffer queue size is set to L + 1 or more so that the buffer queue never becomes empty when the latency of receiving a request from an upper stage is L in terms of the number of cycles. Equipment.   The apparatus of claim 1, wherein N is 2 or 4.   The apparatus of claim 1, wherein the apparatus is a sorter.   The apparatus of claim 1, wherein the apparatus is implemented by hardware.   The apparatus of claim 9, wherein the apparatus is implemented by an FPGA.

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