JP2014124428A - Ultrasonic receiving circuit, ultrasonic measurement device, ultrasonic probe and ultrasonic diagnostic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ultrasonic receiving circuit, an ultrasonic measurement device, an ultrasonic probe, an ultrasonic diagnostic device and the like, capable of improving range resolution of an ultrasonic measurement result image.SOLUTION: An ultrasonic receiving circuit includes: first to M-th A/D converters ADC1-ADC8; a connection switching part for switching the connection between first to M-th receiving channels and the first to M-th A/D converters ADC1-ADC8; and a sampling clock generation circuit 140 for generating first and second sampling clocks CK1, CK2 having the same frequency and different in phase. The connection switching part 130 outputs a receive signal from the (2i-1)th receiving channel to the (2i-1)th A/D converter and the 2i-th A/D converter. The (2i-1)th A/D converter performs sampling for the (2i-1)th receive signal on the basis of the first sampling clock CK1. The 2i-th A/D converter performs sampling for the (2i-1)th receive signal on the basis of the second sampling clock CK2.

Description

  The present invention relates to an ultrasonic receiving circuit, an ultrasonic measuring device, an ultrasonic probe, an ultrasonic diagnostic device, and the like.

  As an apparatus that emits ultrasonic waves toward an object and receives reflected waves from an interface with different acoustic impedance inside the object, for example, an ultrasonic measurement apparatus for inspecting the inside of a human body that is a subject is known. ing. In this ultrasonic measurement apparatus, a reception circuit that receives a reception signal from each channel of the ultrasonic transducer device is provided. This ultrasonic reception circuit is provided with a circuit that performs A / D conversion, phasing processing, and the like of a reception signal from the reception channel. An ultrasonic receiving circuit is disclosed in, for example, Patent Document 1.

Japanese Patent Laid-Open No. 2004-216047

  In an ultrasonic measurement apparatus, how to increase the resolution of an ultrasonic measurement result image is a problem. The resolution is the minimum distance at which an echo between two points can be identified, and includes distance resolution, azimuth resolution, and the like. The distance resolution is an identification limit distance between echo sources in the ultrasonic beam direction, and the azimuth resolution is a limit distance at which an echo between two points existing in the ultrasonic scan direction can be identified. However, in the conventional techniques so far, for example, a technique for improving the distance resolution by the connection switching method of the A / D converter has not been disclosed.

  According to some aspects of the present invention, it is possible to provide an ultrasonic reception circuit, an ultrasonic measurement device, an ultrasonic probe, an ultrasonic diagnostic device, and the like that can improve the distance resolution of an ultrasonic measurement result image.

  One aspect of the present invention includes a first A / D converter to an Mth (M is an integer of 2 or more) A / D converter that performs A / D conversion of a reception signal of an ultrasonic transducer device; A connection switching unit that performs connection switching between a first reception channel to an Mth reception channel that is a reception channel of a reception signal, and the first A / D converter to the Mth A / D converter; A sampling clock generating circuit for generating a first sampling clock and a second sampling clock having the same frequency and different phases and outputting the first sampling clock and the second sampling clock to the M-th A / D converter The connection switching unit includes a second i-1 from the second i-1 (i is a natural number satisfying 2i ≦ M) of the first reception channel to the Mth reception channel. Received signal of the first A / D conversion To the 2i-1 A / D converter and the 2i A / D converter of the Mth A / D converters, and the 2i-1 A / D converter The 2i-1 received signal is sampled based on a first sampling clock to perform A / D conversion, and the second i A / D converter is configured to perform the A / D conversion based on the second sampling clock. The present invention relates to an ultrasonic receiving circuit that samples a 2i-1 received signal and performs A / D conversion.

  According to one aspect of the present invention, the sampling clock generation circuit generates first and second sampling clocks having the same frequency but different phases. The connection switching unit outputs the 2i-1 received signal from the 2i-1 receive channel to the 2i-1 and 2i A / D converters. The 2i-1 and 2i A / D converters respectively sample the 2i-1 received signal based on the first and second sampling clocks, and perform A / D conversion. In this way, for example, without changing the overall speed or data rate of the ultrasonic receiving circuit, the substantial sampling rate is doubled, for example, and the 2i-1 received signal is sampled. Conversion can be performed. Therefore, it is possible to realize an ultrasonic receiving circuit that can improve the distance resolution of the ultrasonic measurement result image.

  In the aspect of the invention, in the first period, the connection switching unit converts the second i-1 received signal from the second i-1 reception channel into the second i-1 A / D. Converter, the 2i A / D converter, the 2i-1 A / D converter, and the 2i A / D converter, respectively, the first sampling clock, the second i / D converter, The second i-1 received signal is sampled based on the second sampling clock, and in the second period, the connection switching unit selects the first of the first to Mth received channels. A 2i reception signal from a 2i reception channel is output to the 2i-1 A / D converter, the 2i A / D converter, and the 2i-1 A / D converter; The second i A / D converters each include the first sampler. Clock based on the second sampling clock may sample the received signal of the first 2i.

  In this way, in the first and second periods, the 2i-1 and 2i received signals are sampled by multiplying the substantial sample rate by, for example, twice, and A / D conversion is performed. Is possible. If a measurement result image is generated using these A / D conversion result data, the distance resolution of the measurement result image can be improved.

  In one embodiment of the present invention, a plurality of ultrasonic measurement result images are configured based on A / D conversion result data from the first A / D converter to the M-th A / D converter. A processing unit for obtaining each scan data of the scan data, wherein the processing unit includes a first A from the first A / D converter to the M-th A / D converter in the first period. Each scan data of the odd-numbered reception channel is obtained based on the / D conversion result data, and the second data from the first A / D converter to the Mth A / D converter in the second period. Each scan data of the even-numbered reception channel is obtained based on the A / D conversion result data, and the measurement result image is obtained based on each scan data of the odd-numbered reception channel and each scan data of the even-numbered reception channel. The plurality of scan devices constituting It may be obtained each scan data of the data.

  In this way, each scan data of the odd number receiving channel is obtained based on the first A / D conversion result data in the first period, and the second A / D conversion result data in the second period. Thus, it is possible to obtain each scan data of the even-numbered reception channel based on the above, and obtain each scan data of a plurality of channels constituting the ultrasonic measurement result image.

  In the aspect of the present invention, the first period is a first frame, the second period is a second frame, and the processing unit is configured to receive odd-numbered reception channels in the first frame. A plurality of scan data of the even-numbered reception channel, a plurality of scan data of the odd-numbered reception channel, a plurality of scan data of the even-numbered reception channel in the second frame, The plurality of scan data constituting the measurement result image may be obtained based on the above.

  In this way, it is possible to obtain a plurality of scan data constituting an ultrasonic measurement result image by switching between the odd-numbered reception channel and the even-numbered reception channel for each frame.

  In the aspect of the invention, the first period is an odd-numbered scan period in which an odd-numbered reception channel is selected, and the second period is an even-numbered scan period in which an even-numbered reception channel is selected. The processing unit obtains each scan data of the odd-numbered reception channel in the odd-numbered scan period, obtains each scan data of the even-numbered reception channel in the even-numbered scan period, and obtains each scan data of the odd-numbered reception channel. Each scan data of the plurality of scan data constituting the measurement result image may be obtained based on the scan data and each scan data of the even-numbered reception channel.

  In this way, it is possible to obtain a plurality of scan data constituting an ultrasonic measurement result image by switching between the odd-numbered reception channel and the even-numbered reception channel for each scan.

  In the aspect of the invention, the connection switching unit may perform scanning from the first channel to the Nth channel (N is an integer of 2 or more) of the ultrasonic transducer device. Reception channel to M-th reception channel, the selected first reception channel to M-th reception channel, and the first A / D converter to M-th A / D converter May be switched.

  If it does in this way, connection switching between the 1st-Nth channel and the 1st-Mth receiving channel of an ultrasonic transducer device, the 1st-Mth receiving channel, and the 1st-Mth receiving channel While switching the connection with the A / D converter, the received signal is input to each A / D converter, and a process of sampling the received signal at a high sampling rate can be realized.

In the aspect of the invention, the sampling clock generation circuit may use the first sampling clock and the second sampling clock as clocks having the same frequency but different phases by 360 degrees / 2 ^L (L is a natural number). May be generated as

  In one embodiment of the present invention, the sampling clock generation circuit generates a first sampling clock, a second sampling clock, a third sampling clock, and a fourth sampling clock having the same frequency and different phases. Output from the first A / D converter to the M-th A / D converter, and the connection switching unit outputs the fourth j-3 of the first reception channel to the M-th reception channel. The fourth j-3 received signal from the receiving channel (j is a natural number satisfying 4j ≦ M) is the fourth j-3 of the first A / D converter to the Mth A / D converter. A / D converter, 4j-2 A / D converter, 4j-1 A / D converter, 4j A / D converter, and 4j-3 A / D converter Converter, the 4j-2 A / D converter, the 4j-1 The A / D converter and the 4j A / D converter are respectively based on the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock. The 4j-3 received signal may be sampled and A / D converted.

  In this way, it is possible to perform the A / D conversion by sampling the 4j-3 received signal by increasing the effective sampling rate by, for example, four times.

  In the aspect of the invention, in the first period, the connection switching unit converts the 4j-3 reception signal from the 4j-3 reception channel into the 4j-3 A / D. Output to the converter, the 4j-2 A / D converter, the 4j-1 A / D converter, the 4j A / D converter, and the 4j-3 A / D conversion , The 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, the first sampling clock, the second The 4j-3 received signal is sampled based on the sampling clock, the third sampling clock, and the fourth sampling, and in the second period, the connection switching unit is configured to transmit the first reception channel. The reception of the fourth j-2 of the Mth reception channels. The 4j-2 received signal from the channel is converted into the 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, Output to the 4j A / D converter, the 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, the 4j The A / D converters respectively sample the fourth j-2 received signal based on the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling. In the third period, the connection switching unit receives the 4j-1 received signal from the 4j-1 received channel among the first received channel to the Mth received channel, The 4j-3 A / D converter, the 4j-2 A A D converter, a 4j-1 A / D converter, a 4j A / D converter, a 4j-3 A / D converter, and a 4j-2 A / D The converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, the first sampling clock, the second sampling clock, the third sampling clock, Based on the fourth sampling, the 4j-1 received signal is sampled, and in the fourth period, the connection switching unit is configured to select the one of the first reception channel to the Mth reception channel. A 4j-3 received signal from a 4jth receiving channel, the 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, Output to the 4jth A / D converter, and the 4j-3th A / D The converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, the first sampling clock, the second The 4jth received signal may be sampled based on the sampling clock, the third sampling clock, and the fourth sampling.

  In this way, in the first, second, third, and fourth periods, the received signals of the 4j-3, 4j-2, 4j-1, 4j are set to a substantial sampling rate of, for example, 4 It becomes possible to perform A / D conversion by sampling by doubling.

  Another aspect of the present invention relates to an ultrasonic measurement apparatus including the ultrasonic receiving circuit according to any one of the above.

  Moreover, the other aspect of this invention is related with the ultrasonic probe containing the ultrasonic measuring apparatus as described above.

  Another aspect of the present invention relates to an ultrasonic diagnostic apparatus including the ultrasonic measurement apparatus described above and a display unit that displays an image.

1 is a configuration example of an ultrasonic receiving circuit according to the present embodiment. 1 is a configuration example of an ultrasonic measurement apparatus according to the present embodiment. 3A to 3C are explanatory diagrams of the linear scan mode and the sector scan mode. 4A and 4B are detailed explanatory diagrams of the configuration and operation of this embodiment. FIG. 5A and FIG. 5B are also detailed explanatory diagrams of the configuration and operation of this embodiment. FIGS. 6A and 6B are also detailed explanatory views of the configuration and operation of this embodiment. 7A and 7B are explanatory diagrams of the normal mode. Explanatory drawing of the production | generation method of the frame image in normal mode. Explanatory drawing of the 1st production | generation method of the frame image of this embodiment. Explanatory drawing of the 2nd production | generation method of the frame image of this embodiment. FIG. 11A and FIG. 11B are explanatory diagrams of the configuration and operation of a modified example of this embodiment. FIGS. 12A to 12C are configuration examples of ultrasonic transducer elements. The structural example of an ultrasonic transducer device. FIGS. 14A and 14B are configuration examples of an ultrasonic transducer element group provided corresponding to each channel. FIG. 15A to FIG. 15C are examples of specific device configurations of the ultrasonic measurement apparatus.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Ultrasonic Receiver Circuit, Ultrasonic Measuring Device FIG. 1 shows a configuration example of the ultrasonic receiver circuit of this embodiment. The ultrasonic reception circuit includes A / D converters ADC1 to ADC8, a connection switching unit 130, and a sampling clock generation circuit 140. Further, the memories 161 to 168 and the processing unit 170 can be included. The ultrasonic receiving circuit of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components, replacing them with other components, and adding other components. Implementation is possible.

  The A / D converters ADC1 to ADC8 (first to Mth A / D converters in a broad sense; M is an integer of 2 or more) perform A / D conversion of the received signal of the ultrasonic transducer device 100. Specifically, the first and second sampling clocks CK1 and CK2 from the sampling clock generation circuit 140 are used to sample the reception signals from the reception channels RCH1 to RCH8 and perform A / D conversion. As the A / D converters ADC1 to ADC8, various types of A / D converters such as a successive approximation type and a delta-sigma type can be used.

  The memories 161 to 168 (first to Mth memories) store A / D conversion result data of the A / D converters ADC1 to ADC8. The memories 161 to 168 can be realized by a RAM or the like.

  The processing unit 170 performs various processes based on the A / D conversion result data stored in the memories 161 to 168. For example, the processing unit 170 performs a phasing addition process (reception beamformer process) for adding the phases of the A / D conversion result data of each reception channel together, a detection process, a logarithmic conversion process, and the like.

  The ultrasonic transducer device 100 includes a plurality of ultrasonic transducer elements (ultrasonic element array) and a substrate on which a plurality of openings are arranged in an array. Each ultrasonic transducer element of the plurality of ultrasonic transducer elements includes a vibration film that closes each opening of the plurality of openings, and a piezoelectric element portion that includes a lower electrode, an upper electrode, and a piezoelectric film provided on the vibration film. And have. Details of the ultrasonic transducer device 100 will be described later. As the ultrasonic transducer device 100, a type of transducer using a piezoelectric element (thin film piezoelectric element) as described later can be adopted, but the present embodiment is not limited to this. For example, a transducer using a capacitive element such as c-MUT (Capacitive Micro-machined Ultrasonic Transducers) may be used.

  The connection switching unit 130 includes reception channels RCH1 to RCH8 (first to Mth reception channels in a broad sense) that are reception channels of ultrasonic reception signals, and A / D converters ADC1 to ADC8 (first to Mth reception channels). Switching of the A / D converter). This connection switching is performed by the ADC connection switching unit 134 included in the connection switching unit 130. The ADC connection switching unit 134 is provided between the nodes of the reception channels RCH1 to RCH8 and the input nodes NI1 to NI8 of the A / D converters ADC1 to ADC8.

  In addition, the connection switching unit 130 receives the reception channels RCH1 to RCH1 to be scanned from the channels CH1 to CH64 (first to Nth channels in a broad sense, where N is an integer of 2 or more) of the ultrasonic transducer device 100. Connection switching for selecting the RCH 8 can also be performed. This connection switching is performed by the multiplexer 132 included in the connection switching unit 130. That is, the multiplexer 132 performs connection switching between the channels CH1 to CH64 of the ultrasonic transducer device 100 and the reception channels RCH1 to RCH8, and the ADC connection switching unit 134 performs A / D conversion with the reception channels RCH1 to RCH8. The connection between the devices ADC1 to ADC8 is switched. The output signal from the multiplexer 132 is amplified by an amplification circuit (LNA) (not shown) included in the ADC connection switching unit 134, for example.

  The connection switching unit 130 includes a plurality of switch elements. Each switch element can be composed of, for example, a CMOS transistor. For example, each switch element can be constituted by a CMOS transfer gate or the like.

  The sampling clock generation circuit 140 generates first and second sampling clocks CK1 and CK2 and outputs them to the A / D converters ADC1 to ADC8. The first and second sampling clocks CK1 and CK2 are clocks having the same frequency but different phases. Specifically, the first sampling clock CK1 (0 degrees) and the second sampling clock CK2 (180 degrees) have a phase difference of 180 degrees. Such clocks having the same frequency but different phases can be generated by a PLL (Phase Locked Loop) circuit 142 included in the sampling clock generation circuit 140.

  In the following description, the case where the number of channels of the ultrasonic transducer device 100 is 64 (N = 64) and the number of reception channels is 8 (M = 8) will be described as an example. However, the present embodiment is not limited thereto. Not. The number of channels may be less than 64 or may be greater, and the number of reception channels may be less than 8 or greater. The channel corresponds to a terminal or a signal line of the ultrasonic transducer device 100 to which an ultrasonic reception signal is output or an ultrasonic transmission signal is input. The reception channel is a channel selected as a reception target (scan target) from the channels of the ultrasonic transducer device 100, and N ≧ M, where N is the number of channels and M is the number of reception channels.

  In the present embodiment, the connection switching unit 130 receives the second i-th channel from the second i−1 (i is a natural number satisfying 2i ≦ M) of the first to Mth reception channels (RCH1 to RCH8). 1 received signal is output to the 2i-1 and 2i A / D converters of the 1st to Mth A / D converters (ADC1 to ADC8).

  For example, in the first period (first frame, odd number scan period), the 2i-1 A / D converters (ADC1, ADC3, ADC5, ADC7) are based on the first sampling clock CK1. The 2i-1 received signals (received signals of RCH1, RCH3, RCH5, and RCH7) are sampled and A / D converted. The 2i A / D converters (ADC2, ADC4, ADC6, ADC8) sample the 2i-1 received signal based on the second sampling clock CK2, and perform A / D conversion.

  On the other hand, for example, in the second period (second frame, even-numbered scan period), the connection switching unit 130 receives the second i reception signals (RCH2, RCH4, RCH6, RCH8 reception signals) from the second i reception channel. Are output to the 2i-1 and 2i A / D converters.

  The 2i-1 A / D converter samples the 2i received signal based on the first sampling clock CK1, and performs A / D conversion. The 2i A / D converter samples the second received signal based on the second sampling clock CK2, and performs A / D conversion.

  The connection switching process and the A / D conversion sampling process will be described later in detail with reference to FIGS. 4A to 7B.

  FIG. 2 is a configuration example of an ultrasonic measurement apparatus having the ultrasonic reception circuit of the present embodiment. The ultrasonic measurement apparatus includes an ultrasonic transducer device 100, a transmission circuit 120, a connection switching unit 130, a sampling clock generation circuit 140, an A / D conversion unit 150, a memory unit 160, a processing unit 170, and an image generation unit 180. For example, when the ultrasonic measurement apparatus is used as an ultrasonic diagnostic apparatus, the ultrasonic diagnostic apparatus can include a display unit 190. The ultrasonic receiving circuit according to the present embodiment is realized by the connection switching unit 130, the sampling clock generation circuit 140, the A / D conversion unit 150, and the like. Note that the ultrasonic measurement apparatus according to the present embodiment is not limited to the configuration shown in FIG. 2, and various components such as omitting some of the components, replacing them with other components, and adding other components. Variations are possible.

  The transmission circuit 120 is a circuit that outputs a transmission signal to the channels CH <b> 1 to CH <b> 64 of the ultrasonic transducer device 100. The transmission circuit 120 includes a pulsar or the like. During the transmission period, the transmission signal from the transmission circuit 120 is output to the ultrasonic transducer device 100 via the multiplexer 132. Specifically, the transmission signal from the transmission circuit 120 is output to the channel selected by the multiplexer 132 from the channels CH1 to CH64.

  The A / D converter 150 includes the A / D converters ADC1 to ADC8 in FIG. The memory unit 160 includes the memories 161 to 168 shown in FIG. 1 and a frame memory for storing frame images.

  The processing unit 170 performs various processes such as a phasing process, and can be realized by a processor such as a microcomputer or a dedicated circuit (ASIC) such as a gate array.

  The image generation unit 180 generates an ultrasonic measurement result image and generates, for example, a B-mode image. The display unit 190 displays the measurement result image generated by the image generation unit 180. The display unit 190 can be realized by various displays such as an LCD.

  FIG. 3A is a diagram illustrating a linear scan mode that is a scan mode of the ultrasonic measurement apparatus.

  In the linear scan mode of FIG. 3A, the multiplexer 132 performs an operation of sequentially selecting channels to be subjected to linear scanning from the channels CH1 to CH64 of the ultrasonic transducer device 100.

  For example, first, channels CH1 to CH8 are selected as targets for linear scanning, and a transmission signal (transmission pulse) from the transmission circuit 120 is output to the channels CH1 to CH8 of the ultrasonic transducer device 100 via the multiplexer 132. The Thereby, for example, the ultrasonic beam BM1 of FIG. Then, the received signals from the channels CH1 to CH8 are input to the A / D conversion unit 150 via the multiplexer 132 and the ADC connection switching unit 134. That is, in this case, the channels CH1 to CH8 are selected as the reception channels RCH1 to RCH8. The A / D conversion unit 150 performs A / D conversion of the reception signals from the reception channels RCH1 to RCH8, and the processing unit 170 performs various processes such as phasing addition processing on the A / D conversion result data. Do.

  Next, channels CH2 to CH9 are selected as targets for linear scanning, and a transmission signal from the transmission circuit 120 is output to channels CH2 to CH9. Thereby, for example, the ultrasonic beam BM2 of FIG. Then, the received signals from the channels CH <b> 2 to CH <b> 9 are input to the A / D conversion unit 150 via the multiplexer 132 and the ADC connection switching unit 134. That is, in this case, the channels CH2 to CH9 are selected as the reception channels RCH1 to RCH8.

  In this way, channel selection by linear scanning is sequentially performed, and finally channels CH57 to CH64 are selected as reception channels RCH1 to RCH8.

  Note that the scan mode of the ultrasonic measurement apparatus is not limited to the linear scan mode of FIG. 3A, and may be the sector scan mode of FIG. In the sector scan mode, a transmission signal from the transmission circuit 210 is output to the channels CH1 to CH64 of the ultrasonic transducer device 100. Thereby, the ultrasonic beams BM1 to BMj in FIG. 3B are transmitted. In this case, in the sector scan mode, by performing delay control on the transmission start timing of the transmission signal of the transmission circuit 120, the ultrasonic beams BM1 to BMj are transmitted in the direction shown in FIG. . For example, the transmission of the ultrasonic beam BM1 in FIG. 3B is realized by delaying the transmission start timing of the left ultrasonic transducer element and increasing the transmission start timing of the right ultrasonic transducer element on the paper surface. The On the other hand, the transmission of the ultrasonic beam BMj is realized by increasing the transmission start timing of the left ultrasonic transducer element and delaying the transmission start timing of the right ultrasonic transducer element on the paper surface.

  In the linear scan mode of FIG. 3A, an ultrasonic beam having an emission width WS corresponding to the width of the selected channel (for example, channels CH1 to CH8) is emitted from the ultrasonic transducer device 100. In the sector scan mode of FIG. 3B, an ultrasonic beam having an emission width WS that extends over the entire device width in a line shape (or the width of a target channel for sector scan) is emitted from the ultrasonic transducer device 100. Then, as shown in FIG. 3C, the transmission focus control of the ultrasonic beam is performed so that the width in the scanning direction is converged at the focus point FP by delay control of the transmission signal, an acoustic lens, or the like.

2. Details of Configuration and Operation Next, details of the configuration and operation of the present embodiment will be described. In FIG. 4A, selectors SL1 and SL2 are provided in the ADC connection switching unit 134 of FIG. 1, and are configured by switch elements such as CMOS transistors.

In FIG. 4A, the received signal from the receiving channel RCH1 (in a broad sense, the 2i-1th receiving channel RCH2i _-1 , i is a natural number satisfying 2i ≦ M) is the first input of the selectors SL1 and SL2. Input to terminals I11 and I21. Received signal from the reception channel RCH2 (receive channel _{RCH 2i} of the 2i in a broad sense) is input to a second input terminal I12, I22 selector SL1, SL2.

The output signal from the output terminal Q1 of the selector SL1 is A / D converters ADC1 (in a broad sense the 2i-1 of the A / D converter _{ADC 2i-1)} is input to. An output signal from the output terminal Q2 of the selector SL2 is input to the A / D converter ADC2 (2i A / D converter ADC _{2i in a} broad sense).

In the first period (first frame, odd-numbered scan period), as shown in FIG. 4A, the selectors SL1 and SL2 select the reception signal of the reception channel RCH1. As a result, the reception signal from the reception channel RCH1 is input to the A / D converters ADC1 and ADC2. That is, in the first period, the connection switching unit 130 of FIG. 1, a reception signal from the receiving channel _{RCH1 (RCH 2i-1),} A / D converter _ADC1, the _{ADC2 (ADC 2i-1, ADC} 2i) Output.

  The sampling clock generation circuit 140 generates sampling clocks CK1 and CK2 as clocks for sampling the received signal, and outputs them to the A / D converters ADC1 and ADC2 and the memories 161 and 162. As shown in FIG. 4B, the sampling clocks CK1 and CK2 are clocks having the same frequency but different phases. Specifically, there is a phase difference of 180 degrees between the sampling clocks CK1 and CK2.

Then, as indicated by A1 in FIG. 4B, in the first period, the A / D converter ADC1 (ADC _2i-1 ) starts from the reception channel RCH1 (RCH _2i-1 ) based on the sampling clock CK1. The received signal is sampled and A / D conversion is performed. Further, as shown in A2 of FIG. 4 (B), in the first period, A / D converter ADC2 _{(ADC 2i)} on the basis of the sampling clock CK2, received from the receiving channel RCH1 _{(RCH 2i-1)} The signal is sampled and A / D conversion is performed. That is, the A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal from the reception channel RCH1 at the sampling interval TS while changing the phase of the sampling clock by 180 degrees. Then, the A / D conversion result data from these A / D converters ADC1 and ADC2 is transferred to the subsequent processing unit 170 via the memories 161 and 162 as A / D conversion result data of the received signal of RCH1. .

  In this way, as shown by A3 in FIG. 4B, the substantial sampling interval is TS / 2, which is ½ times the sampling interval TS in the case of A1 and A2. That is, it is equivalent to sampling at twice the sampling rate. Therefore, the sampling rate of each reception channel can be increased without changing the operation speed and data rate of the entire reception circuit. Then, the A / D conversion result data from the A / D converters ADC1 and ADC2 is used as the A / D conversion result data of the received signal of RCH1, for example, ultrasonic measurement as described later with reference to FIGS. Generate a result image. In this way, it is possible to improve the distance resolution of the measurement result image without changing the operation speed and data rate of the entire receiving circuit.

In FIG. 4A, since the reception signal of the reception channel RCH2 is not sampled, as shown in FIG. 5A, the selector SL1 is used in the second period (second frame, even-numbered scan period). , SL2 selects the reception signal of the reception channel RCH2. As a result, the reception signal from the reception channel RCH2 is input to the A / D converters ADC1 and ADC2. That is, in the second period, the connection switching unit 130 of FIG. 1 outputs the received signal from the receiving channel _{RCH2 (RCH 2i), A /} D converter _ADC1, the _{ADC2 (ADC 2i-1, ADC} 2i) .

Then, as indicated by B1 in FIG. 5B, in the second period, the A / D converter ADC1 (ADC _2i-1 ) receives from the reception channel RCH2 (RCH _2i ) based on the sampling clock CK1. The signal is sampled and A / D conversion is performed. Further, as indicated by B2 in FIG. 5B, in the second period, the A / D converter ADC2 (ADC _2i ) receives the reception signal from the reception channel RCH2 (RCH _2i ) based on the sampling clock CK2. Sampling and A / D conversion are performed. That is, the A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal from the reception channel RCH2 at the sampling interval TS while changing the phase by 180 degrees. Then, the A / D conversion result data from these A / D converters ADC1 and ADC2 is transferred as the A / D conversion result data of the received signal of RCH2 to the downstream processing unit 170 via the memories 161 and 162. .

  In this way, as shown in B3 of FIG. 5B, the substantial sampling interval is TS / 2, which is ½ times the sampling interval TS of B1 and B2, so that it is twice as long. Equivalent to sampling at the sampling rate.

  As described above, in the first period, the reception signal of the reception channel RCH1 is sampled. In the second period, the reception signal of the reception channel RCH2 is sampled, and the A / D conversion of the reception signals of the RCH1 and RCH2 is performed. Do. For example, when the first period is the first frame (odd frame) as shown in FIG. 9 described later and the second period is the second frame (even frame), A / D for two frames. Using the conversion result data, a one-frame measurement result image (B-mode image or the like) is generated. In this way, it is possible to improve the distance resolution of the measurement result image although the frame rate is lowered. Therefore, for example, a measurement result image suitable for a case where the movement of the subject is not so large can be generated.

  4A to 5B, the sampling operation of the reception channels RCH1 and RCH2 and the operation of the A / D converters ADC1 and ADC2 have been described as examples. However, the sampling of the other reception channels RCH3 to RCH8 is described. The operations and the operations of the other A / D converters ADC3 to ADC8 are the same.

  For example, FIGS. 6A and 6B are diagrams for explaining the sampling operation of the reception channels RCH3 and RCH4 and the operation of the A / D converters ADC3 and ADC4.

In FIG. 6A, the reception signal from the reception channel RCH3 (RCH _2i-1 ) is input to the first input terminals I31 and I41 of the selectors SL3 and SL4. Received signal from the reception channel RCH4 _{(RCH 2i)} is input to a second input terminal I32, I42 selector SL3, SL4.

An output signal from the output terminal Q3 of the selector SL3 is input to the A / D converter ADC3 (ADC _2i-1 ). An output signal from the output terminal Q4 of the selector SL4 is input to the A / D converter ADC4 (ADC _2i ).

  In the first period, as shown in FIG. 6A, the selectors SL3 and SL4 select the reception signal of the reception channel RCH3. As a result, the reception signal from the reception channel RCH3 is input to the A / D converters ADC3 and ADC4.

Then, as indicated by C1 in FIG. 6B, in the first period, the A / D converter ADC3 (ADC _2i-1 ) starts from the reception channel RCH3 (RCH _2i-1 ) based on the sampling clock CK1. The received signal is sampled and A / D conversion is performed. Further, as indicated by C2 in FIG. 5B, in the first period, the A / D converter ADC4 (ADC _2i ) receives from the reception channel RCH3 (RCH _2i-1 ) based on the sampling clock CK2. The signal is sampled and A / D conversion is performed. Then, the A / D conversion result data from these A / D converters ADC3 and ADC4 is transferred as the A / D conversion result data of the RCH3 received signal to the subsequent processing unit 170 via the memories 163 and 164. .

  The operation in the second period is similar to that in FIGS. 5A and 5B. That is, in the second period, the selectors SL3 and SL4 select a reception signal from the reception channel RCH4 and output it to the A / D converters ADC3 and ADC4. The A / D converters ADC3 and ADC4 sample the reception signal from the reception channel RCH4 based on the sampling clocks CK1 and CK2, respectively, and perform A / D conversion. Then, the A / D conversion result data from the A / D converters ADC3 and ADC4 is transferred to the subsequent processing unit 170 via the memories 163 and 164 as the A / D conversion result data of the RCH4 received signal. . Since the sampling operations of the other receiving channels RCH5 to RCH8 and the operations of the other A / D converters ADC5 to ADC8 are the same, detailed description is omitted.

  In the present embodiment, apart from the above-described mode in which the substantial sampling rate is doubled (L times in a broad sense), an operation in the normal mode in which the sampling rate is not doubled is also possible.

That is, in the normal mode, as shown in FIG. 7A, the selector SL1 selects the reception signal from the reception channel RCH1 (RCH2i _-1 ) and sends it to the A / D converter ADC1 (ADC2i _-1 ). Output. The selector SL2 selects a received signal from the receiving channel RCH2 _{(RCH 2i),} and outputs it to the A / D converter ADC2 (ADC2 _i). Then, as indicated by E1 in FIG. 7B, the A / D converter ADC1 samples the received signal from the reception channel RCH1 at the sampling interval TS based on the sampling clock CK1, for example, and performs A / D conversion. I do. Further, the A / D converter ADC2 samples the reception signal from the reception channel RCH2 at the sampling interval TS as shown by E2 based on the sampling clock CK1, and performs A / D conversion. As described above, each A / D converter samples the reception signal of each reception channel at a normal sampling rate, so that the operation in the normal mode can be realized. Therefore, for example, in the case of generating a measurement result image in which the subject motion is small but the distance resolution is prioritized, the sampling rate is set to a mode that doubles the sampling rate as shown in FIGS. Set. On the other hand, the normal mode is set for a measurement result image with a large subject movement or the like. By so doing, it becomes possible to generate a suitable measurement result image according to the application.

3. Generation of Frame Image Next, a specific method for generating a frame image that is a measurement result image will be described in detail.

3.1 Generation Method in Normal Mode FIG. 8 is an explanatory diagram of the frame image generation method in the normal mode described with reference to FIGS. 7 (A) and 7 (B). In the normal mode, for example, 57 scans are performed per frame. For example, in the linear scan mode of FIG. 3A, the channels CH1 to CH8 of the ultrasonic transducer device 100 are selected in the first scan. In the second scan, channels CH2 to CH9, in the third scan, channels CH3 to CH10,... Are selected as channel CH57 to CH64 in the 57th scan, and a total of 57 scans are performed.

  For example, in FIG. 8, in the first scan (scan number = 1) of frame 1 (frame number = 1), channels CH1 to CH8 are selected as reception channels RCH1 to RCH8. Then, the A / D converters ADC1 to ADC8 perform A / D conversion on the reception signals of the reception channels RCH1 to RCH8. Next, the processing unit 170 performs phasing addition processing of the A / D conversion result data of the A / D converters ADC1 to ADC8, and generates scan data 1. The phasing addition process is a process for adding the data of each reception channel in phase, and is a process for reception focusing. The processing unit 170 performs processing such as detection processing and logarithmic conversion processing on the scan data 1. Then, the processed scan data 1 is written at a line position corresponding to the first scan of the frame memory included in the memory unit 160 of FIG. As a result, the first line of the image of frame 1 is formed. The detection process is a so-called envelope detection process, and the logarithmic conversion process is a process performed as a pre-process of the process of converting the amplitude value of the scan data into a luminance value. In the frame memory, data (B mode data) after being converted into luminance values is written.

  Next, in the second scan of frame 1, channels CH2 to CH9 are selected as reception channels RCH1 to RCH8. Then, the A / D converters ADC1 to ADC8 perform A / D conversion of the received signals of RCH1 to RCH8, and scan data 2 is generated by phasing addition processing. Scan data 2 after processing such as detection processing is written at a line position corresponding to the second scan of the frame memory. As a result, the second line of the image of frame 1 is formed.

  The above processing is repeated, and at the end of the frame 1, scan data 57 is generated by the 57th scan, and the scan data 57 after the processing such as the detection processing is a line corresponding to the 57th scan of the frame memory. Written to location. Thereby, all the lines of the image of frame 1 are formed, and the generated image of frame 1 is output and displayed on the display unit 190 of FIG.

  Similar processing is performed in frame 2 as well. Then, scan data 57 by the 57th scan is generated at the end of the frame 2, and the scan data 57 after processing such as detection processing is written in the frame memory. As a result, an image of frame 2 is generated and output to the display unit 190 for display.

3.2 First Generation Method FIG. 9 is an explanatory diagram of a first generation method of a frame image according to the present embodiment. The first generation method is a method of switching between the odd-numbered reception channel and the even-numbered reception channel for each frame.

  In FIG. 9, in the first scan of frame 1 (first period in a broad sense), channels CH1 to CH8 are selected as reception channels RCH1 to RCH8. As described with reference to FIG. 4A, the A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal of the odd-numbered reception channel RCH1. As described with reference to FIG. 6A, the A / D converters ADC3 and ADC4 perform A / D conversion by sampling the reception signal of the odd-numbered reception channel RCH3. Similarly, the A / D converters ADC5 and ADC6, ADC7 and ADC8 respectively sample the reception signals of the odd-numbered reception channels RCH5 and RCH7 and perform A / D conversion. In this case, the A / D converters ADC1, ADC3, ADC5, and ADC7 sample the received signal based on the sampling clock CK1 (0 degree), and the A / D converters ADC2, ADC4, ADC6, and ADC8 use the sampling clock CK2. The received signal is sampled based on (180 degrees).

  Then, the processing unit 170 performs phasing addition processing based on the A / D conversion result data from the A / D converters ADC1 to ADC8, and generates scan data 1 of the odd-numbered reception channel. The scan data 1 of the odd-numbered reception channel is data generated by A / D conversion result data whose sampling rate is substantially twice that in the normal mode of FIG.

  Next, the processing unit 170 performs processing such as detection processing and logarithmic conversion processing on the generated scan data 1 of the odd-numbered reception channel. Then, the processed scan data 1 of the odd-numbered reception channel is written as intermediate scan data 1 at the line position corresponding to the first scan of the frame memory. Intermediate scan data 1 is intermediate scan data before completion.

  Next, in the second scan of frame 1, channels CH2 to CH9 are selected as reception channels RCH1 to RCH8. The A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal of the odd number receiving channel RCH1. Here, the reception signal of the reception channel RCH1 is a reception signal from the channel CH2. The A / D converters ADC3 and ADC4 perform A / D conversion by sampling the reception signal of the odd number receiving channel RCH3. Here, the reception signal of the reception channel RCH3 is a reception signal from the channel CH4. Similarly, the A / D converters ADC5 and ADC6, ADC7 and ADC8 respectively sample the reception signals of the odd-numbered reception channels RCH5 and RCH7 and perform A / D conversion. Here, the reception signals of the reception channels RCH5 and RCH7 are reception signals from the channels CH6 and CH8.

  Next, the phasing addition process is performed based on the A / D conversion result data from the A / D converters ADC1 to ADC8, and the scan data 2 of the odd-numbered reception channel is generated. Then, processing such as detection processing is performed on the generated scan data 2 of the odd-numbered reception channel, and the scan data 2 of the odd-numbered reception channel after processing corresponds to the second scan of the frame memory. The intermediate scan data 2 is written at the line position.

  The above processing is repeated, and at the end of frame 1, scan data 57 of the odd-numbered reception channel is generated by the 57th scan. Then, the scan data 57 of the odd-numbered reception channel after processing such as detection processing is written as intermediate scan data 57 at the line position corresponding to the 57th scan of the frame memory.

  In the normal mode of FIG. 8, the frame image is output and displayed on the display unit 190 at this time. On the other hand, in the first generation method of FIG. 9, the frame image is not completed at this time, and an intermediate (provisional) frame image is generated and stored in the frame memory.

  Next, in the first scan of frame 2 (second period in a broad sense), channels CH1 to CH8 are selected as reception channels RCH1 to RCH8. As described with reference to FIG. 5A, the A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal of the even-numbered reception channel RCH2. Similarly, the A / D converters ADC3 and ADC4, ADC5 and ADC6, ADC7 and ADC8 respectively sample the reception signals of the even-numbered reception channels RCH4, RCH6 and RCH8 and perform A / D conversion.

  Next, phasing addition processing is performed based on the A / D conversion result data from the A / D converters ADC1 to ADC8, and the scan data 1 of the even-numbered reception channel is generated. Then, processing such as detection processing is performed on the generated scan data 1 of the even-numbered reception channel. Then, the scan data 1 is generated based on the scan data 1 of the even-numbered reception channel after processing and the scan data 1 of the odd-numbered reception channel that is the intermediate scan data 1 already stored in the frame memory. Then, the generated scan data 1 is written at the line position corresponding to the first scan of the frame memory. As a result, the first line of the frame image is formed.

  Next, in the second scan of frame 2, channels CH2 to CH9 are selected as reception channels RCH1 to RCH8. The A / D converters ADC1 and ADC2, ADC3 and ADC4, ADC5 and ADC6, ADC7 and ADC8 respectively sample the reception signals of the even-numbered reception channels RCH2, RCH4, RCH6 and RCH8 and perform A / D conversion.

  Next, phasing addition processing is performed based on the A / D conversion result data from the A / D converters ADC1 to ADC8, and the scan data 2 of the even-numbered reception channel is generated. Then, processing such as detection processing is performed on the generated scan data 2 of the even-numbered reception channel. Then, the scan data 2 is generated based on the scan data 2 of the even-numbered reception channel after processing and the scan data 2 of the odd-numbered reception channel that is the intermediate scan data 2 already stored in the frame memory. Then, the generated scan data 2 is written at a line position corresponding to the second scan of the frame memory. As a result, the second line of the frame image is formed.

  The above processing is repeated, and at the end of frame 2, scan data 57 of the even-numbered reception channel is generated by the 57th scan. Then, based on the scan data 57 of the even-numbered reception channel after the processing such as the detection process and the scan data 57 of the odd-numbered reception channel which is the intermediate scan data 57 already stored in the frame memory, the scan data 57 is Generated. Then, the generated scan data 57 is written at a line position corresponding to the 57th scan of the frame memory. Thereby, all the lines of the frame image are formed, and the generated frame image is output to the display unit 190 and displayed. As described above, in FIG. 9, since one frame image is generated by two frames, the frame rate is lowered. However, as described with reference to FIGS. 4A to 6B, the distance resolution of the frame image is described. Can improve.

  As described above, in the present embodiment, the processing unit 170 performs ultrasonic wave generation based on the A / D conversion result data from the A / D converters ADC1 to ADC8 (first to Mth A / D converters). Each scan data of a plurality of scan data constituting the measurement result image is obtained. That is, each scan data stored in the frame memory is obtained as shown in FIG. Specifically, the processing unit 170 obtains each scan data of the odd number reception channel based on the first A / D conversion result data from the A / D converters ADC1 to ADC8 in the first period. Further, each scan data of the even-numbered reception channel is obtained based on the second A / D conversion result data from the A / D converters ADC1 to ADC8 in the second period. For example, by performing the phasing addition processing as shown in FIG. 9, each scan data of the odd numbered reception channel and the even numbered reception channel is obtained. Then, based on each scan data of the odd numbered reception channel and each scan data of the even numbered reception channel, each scan data of the plurality of scan data constituting the ultrasonic measurement result image is obtained.

  For example, in the first generation method shown in FIG. 9, the first period is the first frame, and the second period is the second frame.

  Then, as illustrated in FIG. 9, the processing unit 170 obtains a plurality of scan data 1 to 57 of the odd-numbered reception channel in the first frame. Further, the processing unit 170 obtains a plurality of scan data 1 to 57 of the even-numbered reception channel in the second frame.

  The processing unit 170 obtains a plurality of scan data constituting an ultrasonic measurement result image based on the plurality of scan data of the odd-numbered reception channels and the plurality of scan data of the even-numbered reception channels. Taking FIG. 9 as an example, a plurality of scan data 1 to 57 is obtained based on a plurality of scan data 1 to 57 of odd numbered reception channels and a plurality of scan data 1 to 57 of even numbered reception channels. A frame image (B-mode image or the like) composed of the plurality of scan data 1 to 57 is displayed on the display unit 190 as an ultrasonic measurement result image.

  As described above, in the first generation technique, each scan data is generated by switching between the odd-numbered reception channel and the even-numbered reception channel for each frame, and one frame image is generated with two frames. Accordingly, it is possible to generate a frame image with a high distance resolution although the frame rate is reduced.

3.3 Second Generation Method FIG. 10 is an explanatory diagram of a second generation method of a frame image according to this embodiment. The second generation method is a method of switching between the odd-numbered reception channel and the even-numbered reception channel for each scan.

  First, in FIG. 10, in the first scan of frame 1, channels CH1 to CH8 are selected as reception channels RCH1 to RCH8. In the first scan, the same element group is scanned twice. That is, two scans are performed with the channels CH1 to CH8 of the ultrasonic transducer device 100 as the reception channels RCH1 to RCH8. The first scan period (1-1 in FIG. 10) is an odd number scan period (first period in a broad sense), and the second scan period (1-2 in FIG. 10) is an even number scan period (in a broad sense). Is the second period). Note that the first scan period may be an even-numbered scan period, and the second scan may be an odd-numbered scan period.

  In the odd-numbered scan period (1-1), as described in FIG. 4A, the A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal of the odd-numbered reception channel RCH1. . Similarly, the A / D converters ADC3 and ADC4, ADC5 and ADC6, ADC7 and ADC8 respectively sample the reception signals of the odd-numbered reception channels RCH3, RCH5 and RCH7 and perform A / D conversion.

  Next, phasing addition processing is performed based on the A / D conversion result data from the A / D converters ADC1 to ADC8, and the scan data 1 of the odd-numbered reception channel is generated. Then, processing such as detection processing is performed on the generated scan data 1 of the odd-numbered reception channel, and the scan data 1 of the odd-numbered reception channel after processing is a line corresponding to the first scan of the frame memory. The intermediate scan data 1 is written at the position.

  In the even-numbered scan period (1-2), as described with reference to FIG. 5A, the A / D converters ADC1 and ADC2 perform A / D conversion by sampling the reception signal of the even-numbered reception channel RCH2. . Similarly, the A / D converters ADC3 and ADC4, ADC5 and ADC6, ADC7 and ADC8 respectively sample the reception signals of the even-numbered reception channels RCH4, RCH6 and RCH8 and perform A / D conversion.

  Next, phasing addition processing is performed based on the A / D conversion result data from the A / D converters ADC1 to ADC8, and the scan data 1 of the even-numbered reception channel is generated. Then, processing such as detection processing is performed on the generated scan data 1 of the even-numbered reception channel. Then, the scan data 1 is generated based on the scan data 1 of the even-numbered reception channel after processing and the scan data 1 of the odd-numbered reception channel that is the intermediate scan data 1 already stored in the frame memory. Then, the generated scan data 1 is written at the line position corresponding to the first scan of the frame memory. As a result, the first line of the frame image is formed.

  In the second scan of frame 1, channels CH2 to CH9 are selected as receiving channels RCH1 to RCH8. In the second scan, the same element group is scanned twice.

  Even in the odd-numbered scan period (2-1) and even-numbered scan period (2-2) in the second scan, the odd-numbered scan period (1-1) and even-numbered scan period (in the first scan) The same processing as in 1-2) is performed to generate scan data 2 for odd-numbered reception channels and scan data 2 for even-numbered reception channels. The scan data 2 is generated based on the scan data 2 of the odd-numbered reception channel and the scan data 2 of the even-numbered reception channel, and the generated scan data 2 is written into the frame memory.

  The above processing is repeated, and the scan data 57 of the odd-numbered reception channel is generated in the odd-numbered scan period of the 57th scan at the end of the frame 1, and the scan data of the even-numbered reception channel is generated in the even-numbered scan period. 57 is generated. Scan data 57 is generated based on the scan data 57 of the odd-numbered reception channel and the scan data 57 of the even-numbered reception channel, and the generated scan data 57 is written into the frame memory. Thereby, all the lines of the frame image are formed, and the generated frame image is output to the display unit 190 and displayed.

  As described above, in the second generation method of FIG. 10, the first period is an odd-numbered scan period in which odd-numbered reception channels are selected, and the second period is an even-numbered in which even-numbered reception channels are selected. The second scan period.

  Then, the processing unit 170 obtains each scan data of the odd-numbered reception channel in the odd-numbered scan period, and obtains each scan data of the even-numbered reception channel in the even-numbered scan period. Taking FIG. 10 as an example, each scan data 1, 2... 57 of the odd numbered reception channel is obtained, and each scan data 1, 2,. Then, the processing unit 170 obtains each scan data of a plurality of scan data constituting the ultrasonic measurement result image based on each scan data of the odd numbered reception channel and each scan data of the even numbered reception channel. Taking FIG. 10 as an example, based on the scan data 1, 2,... 57 of the odd-numbered reception channel and the scan data 1, 2,. 2 ... 57 is obtained. A frame image composed of these scan data 1 to 57 is displayed on the display unit 190 as an ultrasonic measurement result image.

  As described above, in the second generation method, each scan data is generated by switching between the odd-numbered reception channel and the even-numbered reception channel for each scan. Then, based on each scan data of the odd number receiving channel and each scan data of the even number receiving channel, each scan data constituting the frame image is obtained, and one frame image is generated. Therefore, it is possible to generate a frame image with a high distance resolution although the frame rate is reduced.

4). In the above description, the method of sampling each of the reception signals of the odd-numbered reception channel and the even-numbered reception channel using the two first and second sampling clocks that are out of phase has been described. This is not a limitation. For example, various modifications such as using four sampling clocks out of phase or using eight or more sampling clocks are possible.

That is, the sampling clock generation circuit 140 may be any circuit that can generate sampling clocks whose phases are different by 360 degrees / 2 ^L (L is a natural number). For example, when two sampling clocks are used, L = 1, and the sampling clock generation circuit 140 uses the first and second clocks whose phases are different from each other by 360 degrees / 2 ^L = 360 degrees / 2 = 180 degrees. Generated as a sampling clock. When four sampling clocks are used, L = 2, and clocks whose phases are different from each other by 360 degrees / 2 ^L = 360 degrees / 4 = 90 degrees are generated as the first to fourth sampling clocks. When eight sampling clocks are used, L = 3, and clocks whose phases are different from each other by 360 degrees / 2 ^L = 360 degrees / 8 = 45 degrees are generated as the first to eighth sampling clocks.

  FIG. 11A and FIG. 11B are diagrams for explaining the detailed configuration and operation of this embodiment in the case of using four first to fourth sampling clocks CK1, CK2, CK3, and CK4.

In FIG. 11A, selectors SL <b> 1 to SL <b> 4 are provided as the ADC connection switching unit 134. The first input terminals I11, I21, I31, and I41 of the selectors SL1, SL2, SL3, and SL4 have a reception channel RCH1 (fourth j _-3 reception channel RCH4j _-3 , j in a broad sense, 4j ≦ M). Received signal from a natural number is input. A second input terminal I12, I22, I32, the I42 is the received signal from the reception channel RCH2 (receive channel _{RCH 4j-2} in a broad sense the 4j-2) are inputted. A third input terminal I13, I23, I33, the I43 is the received signal from the reception channel RCH3 (receive channel _{RCH 4j-1} of in a broad sense the 4j-1) is input. The fourth input terminal I14, I24, I34, I44, received signals from the reception channels RCH4 (receive channel _{RCH 4j} of in a broad sense the 4j) is input.

The output signals from the output terminals Q1, Q2, Q3, Q4 of the selectors SL1, SL2, SL3, SL4 are A / D converters ADC1, ADC2, ADC3, ADC4 (4j-3, 4j-2, 4th, 4j-1, 4j A / D converters ADC _4j-3 , ADC _4j-2 , ADC _4j-1 , ADC _4j ).

  The sampling clock generation circuit 140 outputs first, second, third, and fourth sampling clocks CK1, CK2, CK3, and CK4 having the same frequency and different phases to the A / D converters ADC1 to ADC4. As shown in FIG. 11B, the sampling clocks CK1, CK2, CK3, and CK4 are clocks whose phases are different from each other by 90 degrees.

In the first period (first frame), the selectors SL1 to SL4 (connection switching unit 130) receive the reception signal (the fourth j _-3 reception signal) from the reception channel RCH1 (RCH _4j-3 ). It outputs to A / D converter ADC1, ADC2, ADC3, ADC4 (ADC _4j-3 , ADC _4j-2 , ADC _4j-1 , ADC _4j ). Then, as indicated by F1, F2, F3, and F4 in FIG. 11B, the A / D converters ADC1, ADC2, ADC3, and ADC4 are received channels based on the sampling clocks CK1, CK2, CK3, and CK4, respectively. The received signal from RCH1 (RCH _4j-3 ) is sampled.

In the second period (second frame), the selectors SL1 to SL4 convert the reception signal (fourth j _-2 reception signal) from the reception channel RCH2 (RCH _4j-2 ) into the A / D converters ADC1 to ADC1. Output to ADC4. The A / D converters ADC1 to ADC4 sample the reception signal from the reception channel RCH2 (RCH4j _-2 ) based on the sampling clocks CK1 to CK4.

In the third period (third frame), the selectors SL1 to SL4 convert the reception signal (fourth j _-1 reception signal) from the reception channel RCH3 (RCH4j _-1 ) to the A / D converters ADC1 to ADC1. Output to ADC4. The A / D converters ADC1 to ADC4 sample the reception signals from the reception channel RCH3 (RCH4j _-1 ) based on the sampling clocks CK1 to CK4, respectively.

In the fourth period (fourth frame), the selector SL1~SL4 the received signal from the reception channel RCH4 _{(RCH 4j)} (reception signal of the 4j), and outputs it to the A / D converter ADC1~ADC4 . The A / D converter ADC1~ADC4 are each based on the sampling clock CK1 to CK4, samples the received signal from the receiving channel RCH4 _{(RCH 4j).}

  In this way, as shown at F5 in FIG. 11B, the substantial sampling interval is TS / 4, and the length is 1/4 of the sampling interval TS in the case of F1 to F4. That is, it is equivalent to sampling at a four times higher sampling rate. Therefore, the sampling rate of each reception channel can be increased without changing the operation speed and data rate of the entire reception circuit, and the distance resolution of the measurement result image can be further improved.

5. Ultrasonic Transducer Element FIGS. 12A to 12C show a configuration example of the ultrasonic transducer element 10 of the ultrasonic transducer device 100. FIG. The ultrasonic transducer element 10 includes a vibration film (membrane, support member) 50 and a piezoelectric element part. The piezoelectric element section includes a first electrode layer (lower electrode) 21, a piezoelectric layer (piezoelectric film) 30, and a second electrode layer (upper electrode) 22.

  FIG. 12A is a plan view of the ultrasonic transducer element 10 formed on the substrate (silicon substrate) 60 as seen from a direction perpendicular to the substrate 60 on the element forming surface side. FIG. 12B is a cross-sectional view showing a cross section along A-A ′ of FIG. FIG. 12C is a cross-sectional view showing a cross section along B-B ′ of FIG.

  The first electrode layer 21 is formed on the vibration film 50 as a metal thin film, for example. The first electrode layer 21 may be a wiring that extends to the outside of the element formation region and is connected to the adjacent ultrasonic transducer element 10 as shown in FIG.

The piezoelectric layer 30 is formed of, for example, a PZT (lead zirconate titanate) thin film, and is provided so as to cover at least a part of the first electrode layer 21. The material of the piezoelectric layer 30 is not limited to PZT. For example, lead titanate (PbTiO ₃ ), lead zirconate (PbZrO ₃ ), lead lanthanum titanate ((Pb, La) TiO ₃ ), etc. May be used.

  The second electrode layer 22 is formed of a metal thin film, for example, and is provided so as to cover at least a part of the piezoelectric layer 30. The second electrode layer 22 may be a wiring that extends to the outside of the element formation region and is connected to the adjacent ultrasonic transducer element 10 as shown in FIG.

The vibration film (membrane) 50 is provided so as to close the opening 40 by a two-layer structure of, for example, a SiO ₂ thin film and a ZrO ₂ thin film. The vibration film 50 supports the piezoelectric layer 30 and the first and second electrode layers 21 and 22 and can vibrate according to the expansion and contraction of the piezoelectric layer 30 to generate ultrasonic waves.

  The openings (cavity regions) 40 are arranged in an array on the substrate 60. The opening 40 is formed by etching by reactive ion etching (RIE) or the like from the back surface (surface on which no element is formed) side of the substrate 60 (silicon substrate). The resonance frequency of the ultrasonic wave is determined by the size of the vibrating membrane 50 that can be vibrated by the formation of the opening 40, and the ultrasonic wave is radiated to the piezoelectric layer 30 side (from the back to the front in FIG. 12A). Is done.

  The lower electrode (first electrode) of the ultrasonic transducer element 10 is formed by the first electrode layer 21, and the upper electrode (second electrode) is formed by the second electrode layer 22. Specifically, a portion of the first electrode layer 21 covered with the piezoelectric layer 30 forms a lower electrode, and a portion of the second electrode layer 22 covering the piezoelectric layer 30 forms an upper electrode. . That is, the piezoelectric layer 30 is provided between the lower electrode and the upper electrode.

  The piezoelectric layer 30 expands and contracts in the in-plane direction when a voltage is applied between the lower electrode and the upper electrode, that is, between the first electrode layer 21 and the second electrode layer 22. The ultrasonic transducer element 10 uses a monomorph (unimorph) structure in which a thin piezoelectric element (piezoelectric layer 30) and a metal plate (vibrating film 50) are bonded together, and the piezoelectric layer 30 expands and contracts in the plane. Then, warping occurs because the size of the bonded diaphragm 50 remains the same. By applying an AC voltage to the piezoelectric layer 30, the vibration film 50 vibrates in the film thickness direction, and ultrasonic waves are emitted by the vibration of the vibration film 50.

  The voltage applied to the piezoelectric layer 30 is, for example, 10 to 30 V, and the frequency is, for example, 1 to 10 MHz. That is, it can be driven at a lower voltage than when a bulk piezoelectric element is used, and the driving IC can be manufactured by a semiconductor process with a low breakdown voltage. This makes it possible to reduce the size of the ultrasonic measurement apparatus and increase the number of channels.

  The ultrasonic transducer element 10 also operates as a receiving element that receives an ultrasonic echo that is returned when the emitted ultrasonic wave is reflected by an object. The vibration film 50 is vibrated by the ultrasonic echo, and stress is applied to the piezoelectric layer 30 by this vibration, and a voltage is generated between the lower electrode and the upper electrode. This voltage can be taken out as a received signal.

6). Ultrasonic Transducer Device FIG. 13 shows a configuration example of the ultrasonic transducer device 100 (element chip). The ultrasonic transducer device 100 of this configuration example includes a plurality of ultrasonic transducer element groups UG1 to UG64, drive electrode lines DL1 to DL64 (first to nth drive electrode lines in a broad sense. N is an integer of 2 or more) ), Common electrode lines CL1 to CL8 (first to mth common electrode lines in a broad sense, where m is an integer of 2 or more). The number of drive electrode lines (n) and the number of common electrode lines (m) are not limited to the numbers shown in FIG.

  The plurality of ultrasonic transducer element groups UG1 to UG64 are arranged in 64 rows along the second direction D2 (scanning direction). Each of the ultrasonic transducer element groups UG1 to UG64 has a plurality of ultrasonic transducer elements arranged along the first direction D1 (slice direction).

  FIG. 14A shows an example of the ultrasonic transducer element group UG (UG1 to UG64). In FIG. 14A, the ultrasonic transducer element group UG is composed of first to fourth element arrays. The first element row is configured by ultrasonic transducer elements UE11 to UE18 arranged along the first direction D1, and the second element row is an ultrasonic wave arranged along the first direction D1. It is constituted by transducer elements UE21 to UE28. The same applies to the third element row (UE31 to UE38) and the fourth element row (UE41 to UE48). Drive electrode lines DL (DL1 to DL64) are commonly connected to these first to fourth element rows. Further, common electrode lines CL1 to CL8 are connected to the ultrasonic transducer elements of the first to fourth element rows.

  Then, the ultrasonic transducer element group UG in FIG. 14A constitutes one channel of the ultrasonic transducer device. That is, the drive electrode line DL corresponds to a 1-channel drive electrode line, and a 1-channel transmission signal from the transmission circuit is input to the drive electrode line DL. In addition, a one-channel reception signal from the drive electrode line DL is output from the drive electrode line DL. Note that the number of element rows constituting one channel is not limited to four rows as shown in FIG. 14A, and may be less than four rows or more than four rows. For example, as shown in FIG. 14B, the number of element rows may be one.

  As shown in FIG. 13, the drive electrode lines DL1 to DL64 (first to nth drive electrode lines) are wired along the first direction D1. Of the drive electrode lines DL1 to DL64, the jth drive electrode line DLj (jth channel) where j is an integer satisfying 1 ≦ j ≦ n is an ultrasonic transformer of the jth ultrasonic transducer element group UGj. It is connected to a first electrode (for example, a lower electrode) of the reducer element.

  In a transmission period in which ultrasonic waves are emitted, transmission signals VT1 to VT64 are supplied to the ultrasonic transducer elements via the drive electrode lines DL1 to DL64. In the reception period for receiving the ultrasonic echo signal, the reception signals VR1 to VR64 from the ultrasonic transducer elements are output via the drive electrode lines DL1 to DL64.

  The common electrode lines CL1 to CL8 (first to mth common electrode lines) are wired along the second direction D2. The second electrode of the ultrasonic transducer element is connected to any one of the common electrode lines CL1 to CL8. Specifically, for example, as shown in FIG. 13, the i-th common electrode line CLi (i is an integer satisfying 1 ≦ i ≦ m) among the common electrode lines CL1 to CL8 is arranged in the i-th row. The ultrasonic transducer element is connected to a second electrode (for example, an upper electrode).

  A common voltage VCOM is supplied to the common electrode lines CL1 to CL8. The common voltage VCOM may be a constant DC voltage and may not be 0 V, that is, the ground potential (ground potential).

  In the transmission period, a voltage difference between the transmission signal voltage and the common voltage is applied to the ultrasonic transducer element, and ultrasonic waves having a predetermined frequency are emitted.

  The arrangement of the ultrasonic transducer elements is not limited to the matrix arrangement shown in FIG. 13, but may be a so-called staggered arrangement.

  12A to 14B show the case where one ultrasonic transducer element is used as both a transmitting element and a receiving element, the present embodiment is not limited to this. For example, ultrasonic transducer elements for transmitting elements and ultrasonic transducer elements for receiving elements may be provided separately and arranged in an array.

  FIG. 15A to FIG. 15C show examples of specific device configurations of the ultrasonic measurement device (electronic device in a broad sense) of this embodiment. FIG. 15A shows an example of a handy type ultrasonic measuring apparatus 400, and FIG. 15B shows an example of a stationary type ultrasonic measuring apparatus 400. FIG. 15C shows an example of an integrated ultrasonic measurement apparatus 400 in which the ultrasonic probe 300 is built in the main body.

  15A and 15B includes an ultrasonic probe 300 and an ultrasonic measurement device main body 401 (electronic device main body in a broad sense), and the ultrasonic probe 300 and the ultrasonic measurement device. The main body 401 is connected by a cable 312. A probe head 320 is provided at the tip of the ultrasonic probe 300, and a display unit 440 for displaying an image is provided in the ultrasonic measurement apparatus main body 401. In FIG. 15C, an ultrasonic probe 300 is built in an ultrasonic measurement apparatus 400 having a display portion 440. In the case of FIG. 15C, the ultrasonic measurement apparatus 400 can be realized by a general-purpose portable information terminal such as a smartphone.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, at least once, together with different terms having a broader meaning or the same meaning (first to Mth A / D converters, first to Mth reception channels, first to Nth channels, etc.) The described terms (A / D converters ADC1 to ADC8, reception channels RCH1 to RCH8, channels CH1 to CH64, etc.) can be replaced with the different terms in any part of the specification or the drawings. Also, the configuration and operation of the ultrasonic receiving circuit, ultrasonic measuring device, ultrasonic probe, ultrasonic transducer device, ultrasonic transducer element, etc. are not limited to those described in this embodiment, and various modifications can be made. It is.

CH1 to CH64 channel, RCH1 to RCH8 reception channel,
ADC1 to ADC8 A / D converter, CK1 to CK4 sampling clock,
SL1-SL4 selector, NI1-NI8 input node,
DL1-DL64 drive electrode line, CL1-CL8 common electrode line, VBS bias voltage,
VT1 to VT64 transmission signal, VR1 to VR64 reception signal, VCOM common voltage,
10 ultrasonic transducer elements, 21 first electrode layer, 22 second electrode layer,
30 piezoelectric layer, 40 openings, 45 openings, 50 vibration film, 60 substrate,
100 ultrasonic transducer device, 120 transmission circuit,
130 connection switching unit, 132 multiplexer, 134 ADC connection switching unit,
140 sampling clock generation circuit, 142 PLL circuit, 150 A / D converter,
160 memory unit, 161-168 memory, 170 processing unit, 180 image generation unit,
190 display unit, 300 ultrasonic probe, 312 cable, 320 probe head,
400 ultrasonic measurement device, 401 ultrasonic measurement device main body, 440 display unit

Claims (12)

A first A / D converter to M-th (M is an integer of 2 or more) A / D converters that perform A / D conversion of a received signal of an ultrasonic transducer device;
Connection switching unit for switching connection between the first reception channel to the Mth reception channel, which are reception channels of the reception signal, and the first A / D converter to the Mth A / D converter When,
A sampling clock generation circuit that generates a first sampling clock and a second sampling clock having the same frequency but different phases, and outputs the first sampling clock and the second sampling clock to the M-th A / D converter; ,
Including
The connection switching unit
The 2i-1 received signals from the 2i-1 (i is a natural number satisfying 2i ≦ M) of the first to Mth received channels are used as the first A / Output from the D converter to the 2i-1 A / D converter, the 2i A / D converter among the Mth A / D converters,
The second i-1 A / D converter is:
Sampling the second i-1 received signal based on the first sampling clock, and performing A / D conversion;
The second i A / D converter includes:
An ultrasonic receiving circuit that performs A / D conversion by sampling the 2i-1 received signal based on the second sampling clock. In claim 1,
In the first period,
The connection switching unit outputs the 2i-1 received signal from the 2i-1 reception channel to the 2i-1 A / D converter and the 2i A / D converter. ,
The 2i-1 A / D converter and the 2i A / D converter respectively receive the second i-1 received signal based on the first sampling clock and the second sampling clock. Sample
In the second period,
The connection switching unit converts a 2i received signal from a 2i received channel among the 1st received channel to the Mth received channel, the 2i-1 A / D converter, Output to 2i A / D converter
The 2i-1 A / D converter and the 2i A / D converter respectively sample the second i received signal based on the first sampling clock and the second sampling clock. An ultrasonic receiving circuit. In claim 2,
Based on A / D conversion result data from the first A / D converter to the M-th A / D converter, each scan data of a plurality of scan data constituting an ultrasonic measurement result image is obtained. Including a processing unit,
The processor is
Based on the first A / D conversion result data from the first A / D converter to the M-th A / D converter in the first period, each scan data of the odd-numbered reception channel is obtained. Seeking
Based on the second A / D conversion result data from the first A / D converter to the M-th A / D converter in the second period, each scan data of the even-numbered reception channel is obtained. Seeking
The ultrasonic reception characterized in that each scan data of the plurality of scan data constituting the measurement result image is obtained based on each scan data of the odd number reception channel and each scan data of the even number reception channel. circuit. In claim 3,
The first period is a first frame, the second period is a second frame;
The processor is
In the first frame, a plurality of scan data of odd number receiving channels is obtained,
In the second frame, a plurality of scan data of even-numbered reception channels are obtained,
An ultrasonic receiving circuit that obtains the plurality of scan data constituting the measurement result image based on a plurality of scan data of the odd numbered reception channel and a plurality of scan data of the even numbered reception channel . In claim 3,
The first period is an odd number scan period in which an odd number reception channel is selected, and the second period is an even number scan period in which an even number reception channel is selected,
The processor is
In the odd number scan period, each scan data of the odd number reception channel is obtained,
In the even-numbered scan period, each scan data of the even-numbered reception channel is obtained,
An ultrasonic wave characterized in that each scan data of the plurality of scan data constituting the measurement result image is obtained based on each scan data of the odd numbered reception channel and each scan data of the even numbered reception channel. Receiver circuit. In any one of Claims 1 thru | or 5,
The connection switching unit
From the first channel to Nth channel (N is an integer of 2 or more) of the ultrasonic transducer device, the first reception channel to the Mth reception channel to be scanned are selected,
A connection switching between the selected first reception channel to the Mth reception channel and the first A / D converter to the Mth A / D converter is performed. Sound wave receiving circuit. In any one of Claims 1 thru | or 6.
The sampling clock generation circuit includes:
An ultrasonic receiving circuit, wherein clocks having the same frequency and different phases by 360 degrees / 2 ^L (L is a natural number) are generated as the first sampling clock and the second sampling clock. In any one of Claims 1 thru | or 7,
The sampling clock generation circuit includes:
A first sampling clock, a second sampling clock, a third sampling clock, and a fourth sampling clock having the same frequency and different phases are generated, and the first A / D converter to the M-th sampling clock are generated. Output to the A / D converter,
The connection switching unit
The 4j-3 received signals from the 4j-3 (j is a natural number satisfying 4j ≦ M) of the first to Mth received channels are used as the first A / Among the D converter to the Mth A / D converter, the 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, Output to 4j A / D converter,
The 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, Sampling the 4j-3 received signal based on the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock to perform A / D conversion An ultrasonic receiving circuit. In claim 8,
In the first period,
The connection switching unit converts the 4j-3 received signal from the 4j-3 reception channel into the 4j-3 A / D converter, the 4j-2 A / D converter, Output to the 4j-1 A / D converter and the 4j A / D converter;
The 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, Sampling the fourth j-3 received signal based on the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling;
In the second period,
The connection switching unit converts a 4j-2 received signal from the 4j-2 receive channel from the first receive channel to the Mth receive channel into the 4j-3 A / D. Output to the converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter,
The 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, Sampling the fourth j-2 received signal based on the first sampling clock, the second sampling clock, the third sampling clock, the fourth sampling;
In the third period,
The connection switching unit converts a 4j−1 received signal from the 4j−1 received channel from the first received channel to the Mth received channel into the 4j−3 A / D. Output to the converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter,
The 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, Sampling the 4j-1 received signal based on the first sampling clock, the second sampling clock, the third sampling clock, the fourth sampling;
In the fourth period,
The connection switching unit converts a 4j received signal from the 4j receive channel of the 1st receive channel to the Mth receive channel, the 4j-3 A / D converter, Output to the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter,
The 4j-3 A / D converter, the 4j-2 A / D converter, the 4j-1 A / D converter, and the 4j A / D converter, respectively, An ultrasonic receiving circuit, wherein the 4j received signal is sampled based on a first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling.   An ultrasonic measuring apparatus comprising the ultrasonic receiving circuit according to claim 1.   An ultrasonic probe comprising the ultrasonic measurement device according to claim 10. The ultrasonic measurement apparatus according to claim 10;
An ultrasonic diagnostic apparatus comprising: a display unit that displays an image.

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