JP2014120901A - Time-to-digital conversion circuit and time-to-digital conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time-to-digital conversion circuit that has a reduced circuit scale.SOLUTION: The time-to-digital conversion circuit includes a first delay line 1010, a second delay line 1040, a determination circuit 1055 and a control circuit 1015. The first delay line 1010 includes n delay elements 1011 connected in series, and captures a reference clock and inputs an operational result of an output of the nth stage delay element 1011 and the reference clock into the first stage delay element 1011. The second delay line 1040 includes n delay elements 1041 connected in series and captures a signal to be measured. The determination circuit 1055 outputs one series of outputs of the delay elements 1011 and the delay elements 1041 latched on the other on the basis of the number of stages of propagation of the reference clock at the capture of the signal to be measured. The control circuit 1015 outputs a phase of the signal to be measured relative to the reference clock on the basis of the number of times when the reference clock has reached the nth stage delay element 1011, the number of stages of propagation and the outputs of the determination circuit 1055.

Description

  The present invention relates to a time digital conversion circuit, and is suitably used for a circuit that converts a phase difference or time difference into a digital signal, for example.

  A time-to-digital-converter (TDC) that detects the phase of a signal under measurement with respect to a reference clock is known. For example, Japanese Patent No. 4444316 (corresponding US Patent: US7884871 (B2)) discloses a time digital conversion circuit. This time digital conversion circuit detects the phase of the signal under measurement with respect to the reference clock. The time digital conversion circuit includes a first delay line, a second delay line group, a plurality of determination circuits, and an arithmetic circuit. The first delay line connects a plurality of first delay elements that delay an input signal by a first delay amount in series, and the reference clock is input to the first delay element in the first stage. The second delay line group is connected to a connection node of the plurality of first delay elements of the first delay line or to an input node of the first delay element in the first stage, and an input signal is different from the first delay amount. At least one second delay element that is delayed by a delay amount is connected in series. The plurality of determination circuits have the reference clock output from the plurality of first delay elements of the first delay line and the plurality of second delay elements of the second delay line group when the change edge of the signal under measurement is changed. It is determined whether the signal is advanced or delayed with respect to the changed edge of the delayed signal. The arithmetic circuit calculates the phase of the change edge of the signal under measurement with respect to the reference clock from the determination results of the plurality of determination circuits. A difference between the first delay amount and the second delay amount is smaller than the first delay amount and the second delay amount.

  Each of the first delay element and the second delay element outputs a delay clock obtained by delaying the reference clock by the total delay amount of the path from the first delay element in the first stage. Therefore, various combinations of the first delay amount τ1 and the second delay amount τ2, for example, delay clocks with delay amounts such as 2 · τ1, τ1 + τ2, 2 · τ1 + τ2, 2 · τ1 + 2 · τ2,. For example, 2 · τ1 and τ1 · τ2 are different delay clocks by τ1-τ2. The first delay element and the second delay element can output delay clocks having different delay amounts by τ1-τ2. For example, when the time resolution is 10 ps and a phase difference up to 200 ps is detected, the TDC is as follows. In this TDC, the difference amount τ1−τ2 (10 ps) between the first delay amount τ1 (30 ps) and the second delay amount τ2 (20 ps) is used as a unit delay amount, and the delay amount up to 200 ps is an integral multiple of the unit delay amount (10 ps). Delay clocks are generated. However, a delay clock having a delay amount of 10 ps cannot be generated. In other words, a delay clock is generated every 10 ps from 20 ps to 200 ps.

  As a related technique, Japanese Patent Laid-Open No. 2010-130699 (corresponding US Patent: US7953578 (B2)) discloses a time / digital converter and a digital phase lock loop. The time / digital converter includes a converter, a phase frequency detector, and a frequency detector. The converter receives the first signal and the second signal, delays the second signal in stages using a plurality of delay elements connected in series, and converts the delayed second signal and the first signal. In comparison, a phase error of the second signal with respect to the first signal is output. The phase frequency detector receives a third signal from one of the nodes of the first signal and the plurality of delay elements, and outputs a phase difference with respect to the first signal and the third signal. The frequency detector outputs a frequency error of the second signal with respect to the first signal to a digital code using the output signal of the phase frequency detector and the second signal.

  Japanese Patent Application Laid-Open No. 2009-246590 discloses an A / D conversion circuit. The A / D conversion circuit includes a pulse traveling unit, a decoding unit, a calculation unit, and a setting unit. The pulse traveling unit is connected to a plurality of delay elements that give a delay amount corresponding to the magnitude of the analog input signal to the traveling pulse. The decoding unit decodes the traveling position of the pulse according to the input sampling clock and outputs a decoded value. The arithmetic unit outputs a difference between the decoded value at the previous sampling clock and the decoded value at the current sampling clock as a digital conversion value of the analog input signal. The setting unit sets the number of bits that can be decoded by the decoding unit according to the number of bits of the digital conversion value.

  Japanese Patent No. 4626581 (corresponding US patent: US7450049 (B2)) discloses a numerical device. The digitizing apparatus includes a pulse delay circuit, a higher-order encoding circuit, an inversion timing extraction circuit, a first delay line, a second delay line, and a lower-order encoding circuit. The pulse delay circuit is formed by connecting a plurality of pulse delay units that delay a pulse signal with a delay time corresponding to the voltage level of the analog input signal in series or in a ring shape, and sequentially transferring the pulse signal according to the delay time of each delay unit. Transmit with delay. When the measurement signal indicating the measurement timing is input, the high-order encoding circuit generates numerical data corresponding to the number of stages of the pulse delay unit through which the pulse signal has passed in the pulse delay circuit. The inversion timing extraction circuit extracts the output of the pulse delay unit that is inverted first after the measurement timing as an inversion timing signal. The first delay line is formed by connecting a plurality of first delay units for delaying a signal by a preset first delay time in series or in a ring shape, and the inversion timing signal extracted by the inversion timing extraction circuit. Are transmitted while being sequentially delayed. The second delay line delays the signal by a second delay time larger than the first delay time by a delay time difference set to 1 / M (M is an integer of 2 or more) of the delay time of the pulse delay unit. A plurality of second delay units are connected in series or in a ring shape. The measurement signals are transmitted while being sequentially delayed. The low-order encoding circuit is configured so that the number of stages of the first delay unit through which the delay signal on the first delay line has passed exceeds the number of stages of the second delay unit through which the delay signal on the second delay line has passed. Based on the required number of stages of the first or second delay unit, the following is executed. That is, numerical data corresponding to the time difference between the measurement timing and the inversion timing of the output of the pulse delay unit is generated. Output data having numerical data generated by the upper encoding circuit as upper bits and numerical data generated by the lower encoding circuit as lower bits is generated.

  Japanese Patent Laid-Open No. 2003-273735 (corresponding US Patent: US6801150 (B2)) discloses an A / D conversion method and apparatus. In this A / D conversion method, an analog signal is A / D converted at a predetermined timing using a plurality of A / D conversion means for converting an analog voltage into an m-bit digital value. Then, by adding or averaging the digital values obtained by each A / D conversion means, an n-bit digital value having a larger number of bits than the digital value obtained by each A / D conversion means is calculated.

  Japanese Patent No. 3372860 (corresponding US Patent: US Pat. No. 5,128,624 (A)) discloses a signal phase difference detection circuit and a signal phase difference detection method. The signal phase difference detection circuit includes a delay signal generation means (1), a position detection means (3), a count means (2), and a circulation number determination means (27). In the delay signal generating means (1), a plurality of signal delay circuits are connected in a ring shape, and the first signal input at an arbitrary timing is circulated in the connected signal delay circuits. The position detection means (3) receives the second signal having an arbitrary phase difference from the first signal, and the first signal in the plurality of signal delay circuits when the second signal is input. Detect the round position of the signal. The counting means (2) has a plurality of number of laps in which the first signal circulates in the plurality of signal delay circuits from when the first signal is input to when the second signal is input. Count at different timings. The number-of-turns determination means (27) determines a desired number of turns from the plurality of turns counted by the counting means. Based on the desired number of laps from the lap number determination means (27) and the lap position of the first signal detected by the position detection means (3), the first signal and the second The phase difference between the two signals is output.

  Japanese Patent No. 3438342 discloses a pulse phase difference encoding circuit. The pulse phase difference encoding circuit includes a pulse circulation circuit, a counter, a circulation position detection unit, and a data output line. In the pulse circuit, a plurality of inverting circuits that invert and output an input signal are connected in a ring shape, and one of the inverting circuits can control the inverting operation by a first control signal from the outside. Configured as a circuit. Then, the pulse signal circulates with the start of the inverting operation of the start-up inverting circuit by the input of the first control signal. The counter counts the number of circulations of the pulse signal in the pulse circulation circuit, and outputs the count result as binary digital data. When the second control signal having an arbitrary phase difference with respect to the first control signal is input from the outside, the circulating position detecting means outputs the output of each inverting circuit of the pulse circulating circuit according to the operating voltage. Then, the data is binarized using a predetermined threshold value determined in this manner. Then, based on the output of each inverting circuit that has been binarized, the circulating position of the pulse signal in the pulse circulating circuit is detected, and a binary digital signal corresponding to the circulating position is output. The data output line has a plurality of binary digital data, the first digital control data and the second digital data, the binary digital data from the rotation position detecting means being the lower bits and the binary digital data from the counter being the upper bits. Output as data representing the phase difference of the control signal. In the pulse phase difference encoding circuit, voltage adjusting means for adjusting the operating voltage of the circulating position detecting means is provided. The threshold value of the circuit position detecting means is obtained by adjusting the operating voltage by the voltage adjusting means, and by adjusting the operating voltage, the output value of each of the inverting circuits taken by the circuit position detecting means is binarized. The phase difference of the output of the inverting circuit is adjusted so as to be constant.

No. 2868266 (corresponding US patent: US Pat. No. 5,128,624 (A)) discloses a signal phase difference detection circuit and a signal phase difference detection method. The signal phase difference detection circuit includes a ring delay pulse generation circuit (1), counters (2, 21, 22), a pulse selector (3), and an encoder (4). The ring delay pulse generation circuit (1) is connected so that the final output stage is returned to the first signal delay circuit in a number of signal delay circuits. Then, to orbit while delayed by the delay time of the signal delay circuit of one pulse P _A inputted at arbitrary timing by said signal delay circuit. Furthermore, repeatedly generates a plurality of delayed pulses the pulse P _A is delayed in sequence by a delay time of the signal delay circuit passing through. Counter (2,21,22), the ring delay pulse generating circuit (1) the pulse _{P A} within counts the the number of cycles to orbit. The pulse selector (3) has a plurality of input lines to which the delay pulse of the ring delay pulse generation circuit (1) is input and a plurality of output lines corresponding to the delay pulse. Then, the input timing of the pulse P _B having an arbitrary phase difference with respect to the pulse P _A, depending on the state of the delay pulse from the ring delay pulse generating circuit in a specific temporal relationship (1) , Change the state of the output line. The encoder (4) receives the output from the output line of the pulse selector (3) as an input, and outputs a digital signal corresponding to the state of the output line of the pulse selector (3). The pulse P _A and the pulse P _B are determined by the number of laps in the ring delay pulse generation circuit (1) of the pulse P _A when the pulse P _{B is} input and the digital signal output from the encoder (4). A phase difference signal representing the phase difference is obtained.

Japanese Patent No. 4443616 JP 2010-130699 A JP 2009-246590 A Japanese Patent No. 4626581 JP 2003-273735 A Japanese Patent No. 3372860 Japanese Patent No. 3438342 No. 2868266

  In the time digital conversion circuit of the above-mentioned Japanese Patent No. 4443616, there is a problem that it is necessary to increase the circuit scale in order to perform measurement with a wide measurement range with high resolution. The reason is as follows. For example, when measuring a 24-bit measurement range with a resolution of 10 ps, that is, when detecting with a resolution of 10 ps from 20 ps to 167 μs, the number of flip-flops becomes enormous. Specifically, in order to set the maximum measurement time to 167 μs, the number of delay elements constituting the first delay line and the second delay line group and the number of flip-flops are required to be 167 μs / 10 ps = 16.7 million, respectively. Become. A technique that can keep the circuit scale small regardless of the measurement range is desired.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A time digital conversion circuit according to an embodiment is a time digital conversion circuit that detects a phase of a signal under measurement with respect to a reference clock, and a first delay line that receives the reference clock and a second delay that inputs the signal under measurement. A delay line, a determination circuit, and a control circuit are provided. The determination circuit is provided corresponding to the n first delay elements of the first delay line. The reference clock is input to the first delay element at the first stage, and when it reaches the first delay element at the nth stage, it is inverted and returned to the first delay element at the first stage. That is, the same first delay line is repeatedly used. Accordingly, the same inverting circuit is repeatedly used. The control circuit counts the number of times that the reference clock reaches the nth first delay element.

  According to the one embodiment, the circuit scale can be kept small regardless of the measurement range.

FIG. 1 is a block diagram showing the configuration of the time digital conversion circuit according to the first embodiment. FIG. 2 is a block diagram illustrating a configuration example of the time digital conversion circuit according to the first embodiment. FIG. 3 is a timing chart showing an example of the operation of the time digital conversion circuit according to the first embodiment. FIG. 4 is a timing chart showing another example of the operation of the time digital conversion circuit according to the first embodiment. FIG. 5 is a table showing various specifications of the time digital conversion circuit according to the first embodiment. FIG. 6 is a block diagram showing a configuration of the time digital conversion circuit according to the second embodiment. FIG. 7 is a block diagram illustrating a configuration example of an ultrasonic flowmeter to which the time digital conversion circuit according to the third embodiment is applied. FIG. 8 is a timing chart showing an example of the operation of the ultrasonic flowmeter to which the time digital conversion circuit according to the third embodiment is applied. FIG. 9 is a block diagram illustrating a configuration example of an ADC to which the time digital conversion circuit according to the fourth embodiment is applied. FIG. 10 is a diagram illustrating a configuration example of the first delay element in the ADC to which the time digital conversion circuit according to the fourth embodiment is applied. FIG. 11 is a timing chart showing an example of the operation of the ADC to which the time digital conversion circuit according to the fourth embodiment is applied. FIG. 12 is a block diagram illustrating a configuration example of an ADPLL to which the time digital conversion circuit according to the fifth embodiment is applied.

  The time digital conversion circuit and the time digital conversion method according to the embodiment will be described below.

(First embodiment)
The configuration of the time digital conversion circuit according to the first embodiment will be described. FIG. 1 is a block diagram showing the configuration of the time digital conversion circuit according to the first embodiment. The time digital conversion circuit 1000 detects the phase (OUT) of the signal under measurement SC with respect to the reference clock CLK. The time digital conversion circuit 1000 includes a first delay line 1010, a second delay line 1040, a determination circuit 1055, and a control circuit 1015. The first delay line 1010 includes n first delay elements 1011 connected in series, receives a reference clock CLK, and outputs an operation result of the output Dn of the n-th first delay element 1011 and the reference clock CLK. Input to the first delay element 1011 at the first stage. The second delay line 1040 includes n second delay elements 1041 connected in series, and receives the signal under measurement SC as an input. The determination circuit 1055 executes the following based on the number of propagation stages (SEL) indicating how many first delay elements 1011 the reference clock CLK has propagated in the first delay line 1010 when the signal under measurement SC is input. . First delay outputs D1 to Dn from the first delay elements 1011 at each stage in the first delay line 1010 and second delay outputs C1 to Cn from the second delay elements 1041 at each stage in the second delay line 1040 One of them is latched and output at the other timing (P1, P2,...). Alternatively, the other is latched and output at one timing (M1, M2,...). The control circuit 1015 includes the number of times the reference clock CLK has reached the n-th first delay element 1011 (COUNT), the number of propagation stages (SEL; FEOUT), and the output of the determination circuit 1055 (P1,..., M1,...; SEOUT). Based on the above, the phase (OUT) is output.

  In this time digital conversion circuit 1000, the reference clock CLK is input to the first delay element 1011 at the first stage, and when it reaches the first delay element 1011 at the nth stage, it is inverted and the first delay element at the first stage is inverted. The process of returning to 1011 is repeated. That is, the same first delay line 1010 is repeatedly used, and the same determination circuit 1055 is repeatedly used. The control circuit 1015 counts the number of repetitions (COUT). Therefore, if the measurement range is to be widened without changing the resolution, it is only necessary to increase the repetition of the reference clock CLK. In this case, it is not necessary to increase the first delay line 1010 and the determination circuit 1055. That is, even if the resolution is not changed and the measurement range is widened, the circuit scale can be kept small. Hereinafter, the time digital conversion circuit 1000 will be further described. This time digital conversion circuit 1000 may be mixedly mounted on one semiconductor chip together with other circuits.

  FIG. 2 is a block diagram illustrating a configuration example of the time digital conversion circuit according to the first embodiment. Note that n in the sentence represents a natural number. The time digital conversion circuit 1000 receives the reference clock CLK and the signal under measurement SC and outputs a time digital conversion output OUT. The time digital conversion output OUT indicates the phase of the signal under measurement SC with respect to the reference clock CLK. The time digital conversion circuit 1000 includes a first delay line 1010, a second delay line 1040, a determination circuit 1055, and a control circuit 1015.

  The first delay line 1010 includes a NAND circuit 1012 and a first delay element 1011 at the first stage and a first delay element 1011 at the nth stage. The first delay element 1011 at the first stage and the first delay element 1011 at the nth stage are connected in series in this order. The delay time of each first delay element is t1. The NAND circuit 1012 supplies a negative logical product of the reference clock CLK and the output Dn of the n-th first delay element 1011 as the NAND output Di to the first delay element 1011 in the first stage. The first delay element 1011 at the first stage and the first delay element 1011 at the nth stage output n delay element outputs from the output D1 to the output Dn, respectively.

  The second delay line 1040 includes a second delay element 1041 in the first stage and a second delay element 1041 in the nth stage. The second delay element 1041 at the first stage to the second delay element 1041 at the nth stage are connected in series in this order. The delay time of each second delay element is t2. The second delay element 1041 at the first stage to the second delay element 1041 at the nth stage output n delay element outputs from the output C1 to the output Cn, respectively.

  The determination circuit 1055 corresponds to the n first delay elements 1011 of the first delay line 1010, and includes a first determination circuit 1060, a second determination circuit 1080,..., An (n−1) th determination circuit 1100. , And an nth determination circuit 1120 (n in total). The determination circuit 1055 further includes a first inversion determination circuit 1070, a second inversion determination circuit 1090,... (N−1) th corresponding to the n second delay elements 1041 of the second delay line 1040. An inversion determination circuit 1110 and an nth inversion determination circuit 1130 are included (n in total).

  The first determination circuit 1060 receives the output D1 of the first delay element 1011 at the first stage and the output C1 of the second delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. The output P1 is output as the determination circuit output. The second determination circuit 1080 receives the output D2 of the first delay element 1011 at the second stage and the output Cn of the second delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. The output P2 is output as the determination circuit output. Similarly, the (n−1) th determination circuit 1100 includes the output Dn−1 of the (n−1) th first delay element 1011 and the output C1 to the nth stage of the first delay element 1041 of the first stage. The output Cn of the second delay element 1041 is input, and the output Pn−1 is output as the determination circuit output. The nth determination circuit 1120 receives the output Dn of the first delay element 1011 at the nth stage and the output Cn of the first delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. The output Pn is output as the determination circuit output.

  The first inversion determination circuit 1070 receives the output D1 of the first delay element 1011 at the first stage and the output Cn of the second delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. Then, the output M1 is output as the inversion determination circuit output. The second inversion determination circuit 1090 inputs the output D2 of the first delay element 1011 at the second stage and the output Cn of the second delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. Then, the output M2 is output as the inversion determination circuit output. Similarly, the (n−1) th inversion determination circuit 1110 outputs the output Dn−1 of the (n−1) th stage first delay element 1011 and the output C1 to the nth stage of the first stage second delay element 1041. The output Cn of the second delay element 1041 is input, and the output Mn-1 is output as the inversion determination circuit output. The n-th inversion determination circuit 1130 receives the output Dn of the n-th stage first delay element 1011 and the output Cn of the first-stage second delay element 1041 to the output Cn of the n-th stage second delay element 1041. Then, the output Mn is output as the inversion determination circuit output.

The control circuit 1015 includes a counter 1020, a first encoder 1030, and a second encoder 1050.
The counter 1020 receives the output Dn of the nth first delay element 1011 and the signal under measurement SC. The counter 1020 counts up at the rising timing or falling timing of the output Dn while the signal under measurement SC is “Low” with respect to the initial value 0. The result is output as the counter output COUT at the rising timing of the signal under measurement SC. The counter output COUT indicates the number of times that the reference clock CLK has reached the first delay element 1011 in the nth stage until the signal under measurement SC is input. Therefore, the detection time of the signal SC under measurement is the time calculated by (the period at which the reference clock CLK reaches the first delay element 1011 at the nth stage) × (counter output COUT) (hereinafter also referred to as the first time). That's it.

  The first encoder 1030 receives n delay element outputs from the output D1 of the first delay element 1011 at the first stage to the output Dn of the first delay element 1011 at the nth stage, and the signal to be measured SC. . The first encoder 1030 outputs a select signal SEL based on the output D1 to the output Dn and the signal under measurement SC. The select signal SEL indicates how many stages of the first delay element 1011 in the first delay line 1010 have propagated (the number of propagation stages) when the signal under measurement SC is input. The first encoder 1030 further encodes the output D1 to the output Dn and the signal under measurement SC, and outputs a first encoder output FEOUT. The first encoder output FEOUT indicates a value corresponding to the select signal SEL (the number of propagation stages). Therefore, the detection time of the signal SC under measurement is the time obtained by adding the first time to the time calculated by (delay time of the first delay element 1011) × (number of propagation stages) (hereinafter also referred to as second time). That's it.

  The second encoder 1050 includes n determination circuit outputs from the output P1 of the first determination circuit 1060 to the output Pn of the nth determination circuit 1120, and the output M1 of the first inversion determination circuit 1070 to the nth inversion determination circuit 1130. The n inversion determination circuit outputs up to the output Mn are input. The second encoder 1050 further receives a counter output COUT, a select signal SEL, and an output Cn. When the output Cn is input, the second encoder 1050 encodes the output P1 to the output Pn, the outputs M1 to Mn, the counter output COUT, and the select signal SEL, and outputs the second encoder output SEOUT. The second encoder output SEOUT is a relationship between the phase of the signal under measurement SC propagating through the second delay line 1040 and the phase of the reference clock CLK propagating through the first delay line 1010 (one period within the first delay line 1010). Per phase). In other words, the signal under measurement SC propagating through the second delay element 1041 having a small delay time can be considered to have a higher propagation speed than the reference clock CLK propagating through the first delay element 1011 having a large delay time. Therefore, the second encoder output SEOUT indicates at which stage of the first delay element 1011 in the first delay line 1010 the signal under measurement SC has caught up with the reference clock CLK. Therefore, the detection time of the signal under test SC is calculated by (the difference between the delay time of the first delay element 1011 and the delay time of the second delay element 1041) × (the number of catching up stages) (hereinafter referred to as the third time). It is a time obtained by adding the first time and the second time to the above.

  The control circuit 1015 bundles the counter output COUT, which is a signal having a bit width, the first encoder output FEOUT, and the second encoder output SEOUT, and outputs it as a time digital conversion output OUT.

  The first determination circuit (non-inversion determination circuit) 1060 includes n flip-flops 1061 and a multiplexer 1062. Each flip-flop 1061 latches the output D1 at the rising edge of n delay element outputs from the output C1 to the output Cn. The latched result is output to the multiplexer 1062. The multiplexer 1062 selects the latch result of each flip-flop 1061 by the select signal SEL and outputs it as the output P1 of the first determination circuit. The second determination circuit 1080 has n flip-flops 1081 and a multiplexer 1082. Each flip-flop 1081 latches the output D2 at the rising edge of n delay element outputs from the output C1 to the output Cn. The latched result is output to the multiplexer 1082. The multiplexer 1082 selects the latch result of each flip-flop 1081 with the select signal SEL and outputs it as the output P2 of the second determination circuit. Similarly, the (n−1) th determination circuit 1100 includes n flip-flops 1101 and a multiplexer 1102. Each flip-flop 1101 latches the output Dn−1 at the rising edge of n delay element outputs from the output C1 to the output Cn. The latched result is output to the multiplexer 1102. The multiplexer 1102 selects the latch result of each flip-flop 1101 by the select signal SEL and outputs it as the output Pn−1 of the first determination circuit. The nth determination circuit 1120 includes n flip-flops 1121 and a multiplexer 1122. Each flip-flop 1121 latches the output Dn at the rising edge of n delay element outputs from the output C1 to the output Cn. The latched result is output to the multiplexer 1122. The multiplexer 1122 selects the latch result of each flip-flop 1121 with the select signal SEL and outputs it as the output Pn of the nth determination circuit.

  The first inversion determination circuit 1070 has n flip-flops 1071 and a multiplexer 1072. Each flip-flop 1071 latches n delay element outputs from the output C1 to the output Cn at the falling edge of the output D1. The latched result is output to the multiplexer 1072. The multiplexer 1072 selects the latch result of each flip-flop 1071 by the select signal SEL and outputs it as the output M1 of the first inversion determination circuit. The second inversion determination circuit 1090 has n flip-flops 1091 and a multiplexer 1092. Each flip-flop 1091 latches n delay element outputs from the output C1 to the output Cn at the falling edge of the output D2. The latched result is output to the multiplexer 1092. The multiplexer 1092 selects the latch result of each flip-flop 1091 with the select signal SEL and outputs it as the output M2 of the second inversion determination circuit. Similarly, the (n−1) th inversion determination circuit 1110 has n flip-flops 1111 and a multiplexer 1112. Each flip-flop 1111 latches n delay element outputs from the output C1 to the output Cn at the falling edge of the output Dn-1. The latched result is output to the multiplexer 1112. The multiplexer 1112 selects the latch result of each flip-flop 1111 by the select signal SEL and outputs it as the output Mn−1 of the n−1th inversion determination circuit. The n-th inversion determination circuit 1130 includes n flip-flops 1131 and a multiplexer 1132. Each flip-flop 1131 latches n delay element outputs from the output C1 to the output Cn at the falling edge of the output Dn. The latched result is output to the multiplexer 1132. The multiplexer 1132 selects the latch result of each flip-flop 1131 by the select signal SEL and outputs it as the output Mn of the nth inversion determination circuit.

  The delay time t1, the delay time t2, the number of bits of the second encoder 1050, the number of bits of the first encoder 1030, and the number of bits of the counter 1020 in the time digital conversion circuit according to the present embodiment are expressed by the following equation (1 ) To Equation (5).

The bit width of the measurement range required for the time digital conversion circuit is rng, and the measurement resolution is res. The number of first delay elements 1011 in the first delay line 1010 is n. The number of second delay elements 1041 in the second delay line 1040 is n.
The delay time t1 of the first delay element 1011 is expressed by Expression (1).
t1 = res × n Expression (1)
A relational expression between the delay time t1 of the first delay element 1011 and the delay time t2 of the second delay element 1041 is expressed by Expression (2).
res = t1-t2 (2)
The number of bits Be2 of the second encoder 1050 is expressed by Expression (3).
Be2 = Log2 (n) (3)
The number of bits Be1 of the first encoder 1030 is expressed by Expression (4).
Be1 = Log2 (n) (4)
The bit number Bc of the counter 1020 is expressed by Expression (5).
Bc = rng− (Be1 + Be2) (5)
The count-up cycle Ct of the counter 1020 is expressed by equation (6).
Ct = t1 × n (6)
However, the number n is determined in consideration of the count-up cycle of the counter 1020 determined by Expression (6). That is, if n is small, the count-up cycle of the counter 1020 becomes small, and the power consumption of the counter 1020 increases. Therefore, n is determined in consideration of the power consumption of the counter 1020.

  Next, the operation (time digital conversion method) of the time digital conversion circuit according to the present embodiment will be described. In this example, the measurement period from the rising timing of the reference clock CLK to the rising timing of the signal SC to be measured is measured in a 24-bit measurement range (rng = 24 bits) with a resolution of 10 ps (res = 10 ps). explain.

  In that case, n = 16 is set so that the count-up cycle Ct of the counter 1020 is 2.56 ns from Equation (6). That is, each of the first delay line 1010 and the second delay line 1040 is constituted by 16 stages (16 pieces) of delay elements. At that time, the delay time t1 is 160 ps from the equation (1), and the delay time t2 is 150 ps from the equation (2). Further, the second encoder output SEOUT is composed of 4 bits from equation (3), the first encoder output FEOUT is composed of 4 bits from equation (4), and the counter 1020 is composed of 16 bits from equation (5). The reference clock CLK sets a period that is sufficiently longer than the count-up period Ct. It is assumed that the signal under measurement SC rises after an equivalent measurement period TW1 elapses every time the reference clock CLK rises.

  Next, an example of the operation (time digital conversion method) of the time digital conversion circuit according to the first embodiment will be described. The time digital conversion method is a method of detecting the phase (OUT) of the signal under measurement SC with respect to the reference clock CLK. The time digital conversion method includes the following steps. In the first step, a reference clock CLK is input to a first delay line 1010 including n first delay elements 1011 connected in series, and the output Dn of the n-th first delay element 1011 and the reference clock CLK Is input to the first delay element 1011 at the first stage. The second step is a step of inputting the signal under measurement SC to a second delay line 1040 including n second delay elements 1041 connected in series. The third step is based on the number of propagation stages (SEL) that the determination circuit 1055 indicates how many first delay elements 1011 the reference clock CLK has propagated in the first delay line 1010 when the signal under measurement SC is input. This is the step of executing the following process. First delay outputs D1 to Dn from the first delay elements 1011 at each stage in the first delay line 1010 and second delay outputs C1 to Cn from the second delay elements 1041 at each stage in the second delay line 1040 One of them is latched and output at the other timing (P1,..., Pn). Alternatively, the other is latched and output at one timing (M1,..., Mn). In the fourth step, the control circuit 1015 counts the number of times the reference clock CLK reaches the first delay element 1011 in the nth stage, the number of propagation stages (SEL; FEOUT), and the output (P1,..., M1,. ...; SEOUT), and outputting the phase (OUT).

  In this time digital conversion method, the reference clock CLK is input to the first delay element 1011 at the first stage, and when it reaches the first delay element 1011 at the nth stage, it is inverted and the first delay element 1011 at the first stage is inverted. Repeat that. That is, the same first delay line 1010 is repeatedly used, and the same determination circuit 1055 is repeatedly used. The control circuit 1015 counts the number of repetitions (COUT). Therefore, if the measurement range is to be widened without changing the resolution, it is only necessary to increase the repetition of the reference clock CLK. In this case, it is not necessary to increase the first delay line 1010 and the determination circuit 1055. That is, even if the resolution is not changed and the measurement range is widened, the circuit scale can be kept small. Hereinafter, the time digital conversion method will be further described.

  FIG. 3 is a timing chart showing an example of the operation of the time digital conversion circuit according to the first embodiment. However, (a) shows the reference clock CLK, and (b) shows the signal under measurement SC. (C) is the output D1 from the first delay element 1011 at the first stage, (d) is the output C15 from the second delay element 1041 at the fifteenth stage, and (e) is from the first delay element 1011 at the second stage. , Outputs D2 and (f) respectively indicate the output C16 from the 16th stage second delay element 1041. (G) is the output D3 from the first delay element 1011 at the third stage, (h) is the output C1 from the second delay element 1041 at the first stage, and (i) is from the first delay element 1011 at the fourth stage. , Outputs D4 and (j) indicate the output C2 from the second delay element 1041 in the second stage. (K) is the output D5 from the first delay element 1011 at the fifth stage, (l) is the output C3 from the second delay element 1041 at the third stage, and (m) is from the first delay element 1011 at the fifteenth stage. The outputs D15 and (n) respectively indicate the outputs C13 from the 13th stage second delay element 1041. (O) is the output D16 from the first delay element 1011 at the 16th stage, (p) is the output C14 from the second delay element 1041 at the 14th stage, (q) is the select signal SEL from the first encoder 1030, (R) shows the counter output COUT from the counter 1020, respectively. (S) is the first encoder output FEOUT from the first encoder 1030, (t) is the second encoder output SEOUT from the second encoder 1050, and (u) is the output OUT of the control circuit 1015 (time digital conversion circuit). Show. In the following description, α and β represent natural numbers equal to or less than n, and 0x0000 notation represents a hexadecimal number.

  When the reference clock CLK rises (timing T1), the reference clock CLK propagates to the first delay line 1010, and the output D1 of the first delay element 1011 at the first stage rises. Hereinafter, the reference clock CLK propagates through the first delay elements 1011 of the first delay line 1010 in order.

  After the measurement period TW1 elapses from the timing T1, the signal under measurement is measured, and the signal under measurement SC rises. The signal under measurement SC propagates through the second delay line 1040. The first encoder 1030 is configured such that the output D1 to the output D3 of the first to third delay elements 1011 of the first delay line 1010 are “Hi” at the rising timing of the signal SC to be measured, and the first first of the fourth stage. It is determined that the output D4 of the delay element 1011 is “Low”. Based on the result, the first encoder 1030 holds and outputs “0x0008” in which the third bit is set to “Hi” as the select signal SEL. In addition, as the first encoder output FEOUT, “0x3” which is the bit number of “Hi” is held and outputted by the select signal SEL. The counter 1020 outputs the count value “0x0000” at the rising timing of the signal under measurement SC to the counter output COUT (timing T2).

  After timing T2, the first determination circuit 1060 to the sixteenth determination circuit 1120 and the first inversion determination circuit 1070 to the sixteenth inversion determination circuit 1130 start output in response to the select signal SEL.

The β-th determining circuit is latched at the rising edge of the output Cα of the second delay element 1041 of the α-th stage of the second delay line 1040 by the select signal SEL, and the first delay element 1011 of the β-th stage of the first delay line 1010 is latched. The output Dβ is output. The β-th inversion determination circuit receives the second delay of the α-th stage of the second delay line 1040 latched at the falling edge of the output Dβ of the first delay element 1011 of the β-th stage of the first delay line 1010 by the select signal SEL. The output Cα of the element 1041 is output. The second encoder 1050 selects a combination of the output Dβ from the βth determination circuit and the output Cα from the βth inversion determination circuit. The combination is expressed by equation (7).
x = α + (the bit number of “Hi” in the select signal SEL) −1 (1)
However, when x ≦ n: β = x;
When x> n: β = x−n
It is. Hereinafter, description will be made in order from the case of α = 1.

(1) α = 1
From the result of the select signal SEL = “0x0008”, x = 3 (≦ 16) and β = 3 from Expression (7). Therefore, the third determination circuit (not shown) of the first delay element 1011 of the third stage of the first delay line 1010 is the rising edge of the output C1 of the second delay element 1041 of the first stage of the second delay line 1040. Latch the output D3. The latch result is output to the second encoder 1050 as the output P3 of the third determination circuit (timing T3). In the example of this figure, the output P3 is “Hi”.

(2) α = 2
From the result of the select signal SEL = “0x0008”, x = 4 (≦ 16) and β = 4 from Expression (7). Accordingly, the fourth determination circuit (not shown) of the first delay element 1011 in the fourth stage of the first delay line 1010 is triggered by the rise of the output C2 of the second delay element 1041 in the second stage of the second delay line 1040. Latch the output D4. The latch result is output to the second encoder 1050 as the output P4 of the fourth determination circuit (timing T4). In the example of this figure, the output P4 is “Hi”.

(3) α = 3
From the result of the select signal SEL = “0x0008”, from equation (7), x = 5 (≦ 16) and β = 5. Therefore, the fifth determination circuit (not shown) outputs the output D5 of the first delay element 1011 at the fifth stage of the first delay line at the rising edge of the output C3 of the second delay element 1041 at the third stage of the second delay line. Latch. The latch result is output to the second encoder 1050 as the output P5 of the fifth determination circuit (timing T5). In the example of this figure, the output P5 is “Hi”. The same applies hereinafter.

(4) α = 13
From the result of the select signal SEL = “0x0008”, x = 15 (≦ 16th) and β = 15 from Expression (7). Accordingly, the fifteenth determination circuit 1100 latches the output D15 of the first delay element 1011 at the fifteenth stage of the first delay line 1010 at the rising edge of the output C13 of the second delay element 1041 at the thirteenth stage of the second delay line 1040. To do. The latch result is output to the second encoder 1050 as the output P15 of the fifteenth determination circuit 1100 (timing T6). In the example of this figure, the output P15 is “Low”. Although not shown, the outputs P6 to P14 are “Low”.

(5) α = 14
From the result of the select signal SEL = “0x0008”, from equation (7), x = 16 (≦ 16) and β = 16. Accordingly, the sixteenth determination circuit 1120 latches the output D16 of the sixteenth stage first delay element 1011 of the first delay line 1010 at the rising edge of the output C14 of the fourteenth stage second delay element 1041 of the second delay line 1040. To do. The latch result is output to the second encoder 1050 as the output P16 of the sixteenth determination circuit 1120 (timing T7). In the example of this figure, the output P16 is “Low”.

  The reference clock CLK propagates through the first delay element 1011 in the first delay line 1010 in 16 stages (16 pieces), and is then input to the NAND circuit 1012 as the output D16 of the 16th stage first delay element 1011. Then, it is inverted by the NAND circuit 1012 and output as the NAND output Di and propagates through the first delay line 1010.

(6) α = 15
From the result of the select signal SEL = “0x0008”, from equation (7), x = 17 (> 16) and β = 17−16 = 1. Accordingly, the first inversion determination circuit 1070 outputs the output C15 of the second delay element 1041 of the 15th stage of the second delay line 1040 at the falling edge of the output D1 of the first delay element 1011 of the first stage of the first delay line 1010. Latch. The latch result is output to the second encoder 1050 as the output M1 of the first inversion determination circuit 1070 (timing T8). In the example of this figure, the output M1 is “Hi”. However, it is inverted by the second encoder 1050 and determined to be “Low”.

(7) α = 16
From the result of the select signal SEL = “0x0008”, from equation (7), x = 18 (> 16) and β = 18−16 = 2. Accordingly, the second inversion determination circuit 1090 outputs the output C16 of the second delay element 1041 of the 16th stage of the second delay line 1040 at the falling edge of the output D2 of the first delay element 1011 of the second stage of the first delay line 1010. Latch. The latch result is output to the second encoder 1050 as the output M2 of the second inversion determination circuit 1090 (timing T9). In the example of this figure, the output M2 is “Hi”. However, it is inverted by the second encoder 1050 and determined to be “Low”.

  The second encoder 1050 outputs the result from the output P3 of the third determination circuit (not shown) to the output P16 of the sixteenth determination circuit 1120, and the output M1 of the first inversion determination circuit 1070 to the output of the second inversion determination circuit 1090. Encode the result up to M2. The encoding result is output as the second encoder output SEOUT (timing T9).

  Here, in the second encoder 1050, the counter output COUT value output by the counter 1020 at the rising timing of the signal under test SC is 0 (or even) (“0x0000”) and the result of the select signal SEL (“0x0008”). ) And encoding.

  The value of the counter output COUT being 0 is before the output D16 of the 16th first delay element 1011 of the first delay line 1010 rises. Further, the value of the counter output COUT being an even number is after counting up at the rising edge of the output D16 of the 16th stage first delay element 1011 and further counting up at the falling edge. That is, the value of the counter output COUT being 0 or an even number means that the NAND output Di rises from the “Low” level and the “Hi” level after the rise propagates from the output D1 to the output D16. It can be judged that.

  The selection signal SEL = "0x0008" indicates that the output ("Low") obtained by inverting the output D16 of the first delay line 1010 by the NAND circuit 1012 is the output D1 of the first delay line 1010 as the first and second determinations. This indicates that the signal is input to the circuit or the first and second inversion determination circuits. At this time, when the first and second determination circuits 1060 and 1080 are used at the timings T8 and T9, similarly to the timings T3 to T7, the following occurs. At timing T8, the first determination circuit 1060 latches the output D1 at the rising edge of the output C15 of the second delay line 1040. Thereafter, at timing T9, the second determination circuit 1080 latches the output D2 of the first delay line 1010 at the rising edge of the output C16 of the second delay line 1040. The latch results at the timings T8 and T9 pass through the multiplexers 1062 and 82, respectively, and become the outputs P1 and P2 of the first and second determination circuits 1060 and 1080, respectively. The outputs P1 and P2 are output to the second encoder 1050. The second encoder 1050 inverts and encodes in order to maintain the continuity of the bit data with the latch result from timing T3 to timing T7.

  However, at timing T8, the time from the rise of the output C15 of the second delay line 1040 to the fall of the output D1 of the first delay line 1010 is considered to be 10 ps or less of the measurement resolution depending on the measurement period TW1. It is done. In that case, a flip-flop hold time violation may occur, and the flip-flop may not latch the output D1 correctly. Therefore, the first inversion determination circuit 1070 is used to prevent a situation in which the hold time violation occurs and the output D1 cannot be latched correctly. The first inversion determination circuit 1070 latches the output C15 at the falling edge of the output D1. The latch result at timing T8 passes through the multiplexer 1072 and becomes the output M1 of the first inversion determination circuit 1070. The output M1 is output to the second encoder 1050. The second encoder 1050 inverts and encodes the output M1. Thereby, the continuity of the bit data with the result latched from timing T3 to timing T7 can be maintained.

  Also at the timing T9, the second inversion determination circuit 1090 is used similarly to the timing T8. The second inversion determination circuit 1090 latches the output C16 of the second delay line at the falling edge of the output D2 of the first delay line. The latch result at timing T9 passes through the multiplexer 1092 and becomes the output M2 of the second inversion determination circuit 1090. The output M2 is output to the second encoder 1050. The second encoder 1050 inverts and encodes the output M2. Thereby, the continuity of the bit data with the result latched from timing T3 to timing T8 can be maintained.

The second encoder 1050 performs encoding using 16-bit data from the most significant bit to the least significant bit, and outputs a 4-bit encoded result to the second encoder output SEOUT.
For example, in the example of FIG. First, the most significant bit of the 16-bit data is the result (“Low”) of inverting the output M2 (“Hi”) of the second inversion determination circuit 1090. The fifteenth bit is a result (“Low”) of inverting the output M1 (“Hi”) of the first inversion determination circuit 1070. The 14th bit is the output P16 (“Low”) of the 16th determination circuit 1120. The thirteenth bit is the output P15 (“Low”) of the fifteenth determination circuit 1100. The twelfth bit is an output P14 (“Low”) of a fourteenth determination circuit (not shown). The eleventh bit is an output P13 ("Low") of a thirteenth determination circuit (not shown). The tenth bit is an output P12 (“Low”) of a twelfth determination circuit (not shown). The ninth bit is an output P11 ("Low") of an eleventh determination circuit (not shown). The eighth bit is an output P10 (“Low”) of a tenth determination circuit (not shown). The seventh bit is an output P9 (“Low”) of a ninth determination circuit (not shown). The sixth bit is an output P8 (“Low”) of an eighth determination circuit (not shown). The fifth bit is an output P7 (“Low”) of a seventh determination circuit (not shown). The fourth bit is an output P6 (“Low”) of a sixth determination circuit (not shown). The third bit is an output P5 (“Hi”) of a fifth determination circuit (not shown). The second bit is an output P4 (“Hi”) of a fourth determination circuit (not shown). The least significant bit is an output P3 (“Hi”) of a third determination circuit (not shown). That is, the second encoder 1050 determines the output of the determination circuit 1055 as “0000, 0000, 0000, 0111” as 16-bit data.
Subsequently, the second encoder 1050 determines how many bits (output corresponding to the second delay element 1041 of the second delay line 1040) is “1”, and outputs the second encoder. Output as SEOUT. In the example of FIG. 2, since the first bit up to the third bit (the output corresponding to the second delay element 1041 at the third stage of the second delay line) is “1”, “0x3” is output as the second encoder output SEOUT. .

  The time digital conversion circuit 1000 outputs a time digital conversion output OUT having the counter output COUT as upper 16 bits, the first encoder output FEOUT as middle 4 bits, and the second encoder output SEOUT as lower 4 bits. In the example of FIG. 2, the time digital conversion output OUT = “0x000003” is output based on the counter output COUT = “0x0000”, the first encoder output FEOUT = “0x3”, and the second encoder output SEOUT = “0x3” ( Timing T9).

  Next, another example of the operation of the time digital conversion circuit according to the first embodiment will be described. FIG. 4 is a timing chart showing another example of the operation of the time digital conversion circuit according to the first embodiment. However, (a) to (u), α, β, and 0x0000 are the same as those in FIG.

  When the reference clock CLK rises (timing T11), the reference clock CLK propagates to the first delay line 1010, and the output D1 of the first delay element 1011 at the first stage rises. Hereinafter, the reference clock CLK propagates through the first delay elements 1011 of the first delay line 1010 in order.

  When the reference clock CLK propagates to the output D16 of the 16th delay element 1011 of the first delay line 1010 and the output D16 rises, the counter 1020 counts up and outputs “0x0001” to the counter output COUT (timing T12). ).

  After the measurement period TW11 elapses from the timing T11, the signal under measurement is measured, and the signal under measurement SC rises. The signal under measurement SC propagates through the second delay line 1040. In the first encoder 1030, the counter output COUT is “0x0001” at the rise timing of the signal under measurement SC, and the outputs D1 to D3 of the first to third delay elements 1011 of the first delay line 1010 are “Low”. The output D4 of the first delay element 1011 at the fourth stage is determined as “Hi. Based on the result, the first encoder 1030 sets“ 0x0008 ”with the third bit“ Hi ”as the select signal SEL. In addition, as the first encoder output FEOUT, “0x3” which is the bit number of “Hi” is held and outputted as the select signal SEL (timing T13).

  After timing T13, the first determination circuit 1060 to the sixteenth determination circuit 1120 and the first inversion determination circuit 1070 to the sixteenth inversion determination circuit 1130 start outputting in response to the select signal SEL.

  The β determination circuit uses the select signal SEL to obtain the output Dβ of the delay element 1011 in the β stage of the first delay line latched at the rising edge of the output Cα of the second delay element 1041 in the α stage of the second delay line. Output. The β inversion determination circuit outputs the output of the second delay element 1041 of the second delay α stage latched at the falling edge of the output Dβ of the first delay element 1011 of the β stage of the first delay line by the select signal SEL. Cα is output. The second encoder 1050 selects a combination of the output Dβ from the βth determination circuit and the output Cα from the βth inversion determination circuit. The combination is represented by the above formula (7). Hereinafter, description will be made in order from the case of α = 1.

(1) α = 1
From the result of the select signal SEL = “0x0008”, x = 3 (≦ 16) and β = 3 from Expression (7). Accordingly, the third inversion determination circuit (not shown) has the second delay element of the first stage of the second delay line 1040 at the falling edge of the output D3 of the first delay element 1011 of the third stage of the first delay line 1010. The output C1 of 1041 is latched. The latch result is output to the second encoder 1050 as the output M3 of the third inversion determination circuit (timing T13). In the example of this figure, the output M3 is “Low”. However, it is inverted by the second encoder 1050 and determined as “Hi”. Unlike the example of FIG. 3, the inversion determination circuit is selected (in the second encoder 1050) because the counter output COUT is an odd number.

(2) α = 2
From the result of the select signal SEL = “0x0008”, x = 4 (≦ 16) and β = 4 from Expression (7). Therefore, the fourth inversion determination circuit (not shown) has the second delay element of the second stage of the second delay line 1040 at the falling edge of the output D4 of the first delay element 1011 of the fourth stage of the first delay line 1010. The output C2 of 1041 is latched. The latch result is output to the second encoder 1050 as the output M4 of the fourth inversion determination circuit (timing T14). In the example of this figure, the output M4 is “Low”. However, it is inverted by the second encoder 1050 and determined as “Hi”.

(3) α = 3
From the result of the select signal SEL = “0x0008”, from equation (7), x = 5 (≦ 16) and β = 5. Accordingly, the fifth inversion determination circuit (not shown) has the third delay element of the third stage of the second delay line 1040 at the falling edge of the output D5 of the first delay element 1011 of the fifth stage of the first delay line 1010. The output C3 of 1041 is latched. The latch result is output to the second encoder 1050 as the output M5 of the fifth inversion determination circuit (timing T15). In the example of this figure, the output M5 is “Hi”. However, it is inverted by the second encoder 1050 and determined to be “Low”. The same applies hereinafter.

(4) α = 13
From the result of the select signal SEL = “0x0008”, x = 15 (≦ 16th) and β = 15 from Expression (7). Therefore, the fifteenth inversion determination circuit 1110 outputs the output C13 of the thirteenth stage second delay element 1041 of the second delay line 1040 at the falling edge of the output D15 of the fifteenth stage first delay element 1011 of the first delay line 1010. Latch. The latch result is output to the second encoder 1050 as the output M15 of the fifteenth inversion determination circuit 1110 (timing T16). In the example of this figure, the output M15 is “Hi”. However, it is inverted by the second encoder 1050 and determined to be “Low”.

(5) α = 14
From the result of the select signal SEL = “0x0008”, from equation (7), x = 16 (≦ 16) and β = 16. Accordingly, the sixteenth inversion determination circuit 1130 outputs the output C14 of the 14th stage second delay element 1041 of the second delay line 1040 at the falling edge of the output D16 of the 16th stage first delay element 1011 of the first delay line 1010. Latch. The latch result is output to the second encoder 1050 as the output M16 of the sixteenth inversion determination circuit 1130 (timing T17). In the example of this figure, the output M16 is “Hi”. However, it is inverted by the second encoder 1050 and determined to be “Low”.

  The reference clock CLK propagates through the first delay element 1011 in the first delay line 1010 in 16 stages (16 pieces), and then the output D16 of the 16th stage first delay element 1011 is input to the NAND circuit 1012. Then, it is inverted by the NAND circuit 1012 and output as the NAND output Di and propagates through the first delay line 1010.

(6) α = 15
From the result of the select signal SEL = “0x0008”, from equation (7), x = 17 (> 16) and β = 17−16 = 1. Therefore, the first determination circuit 1060 latches the output D1 of the first delay element 1011 of the first stage of the first delay line 1010 at the rising edge of the output C15 of the second delay element 1041 of the 15th stage of the second delay line 1040. To do. The latch result is output to the second encoder 1050 as the output P1 of the first determination circuit 1060 (timing T18). In the example of this figure, the output P1 is “Low”.

(7) α = 16
From the result of the select signal SEL = “0x0008”, from equation (7), x = 18 (> 16) and β = 18−16 = 2. Therefore, the second determination circuit 1080 latches the output D2 of the first delay element 1011 of the second stage of the first delay line 1010 at the rising edge of the output C16 of the second delay element 1041 of the 16th stage of the second delay line 1040. To do. The latch result is output to the second encoder 1050 as the output P2 of the second determination circuit 1080 (timing T19). In the example of this figure, the output P2 is “Low”.

  The second encoder 1050 outputs the results from the output M3 of the third inversion determination circuit to the output M16 of the sixteenth inversion determination circuit 1130 and the results from the output P1 of the first determination circuit 1060 to the output P2 of the second determination circuit 1080. Encode. The encoding result is output as the second encoder output SEOUT (timing T19).

  Here, the second encoder 1050 is based on the result (“0x0001”) of the counter output COUT value output by the counter 1020 at the rising timing of the signal under measurement SC and the result of the select signal SEL (“0x0008”). Encode.

  The value of the counter output COUT is an odd number after it is counted up at the rise of the output D16 of the 16th first delay element 1011 of the first delay line 1010. That is, the value of the counter output COUT being an odd number means that the NAND output Di falls from the “Hi” level, and the “Low” level after the fall propagates from the output D1 to the output D16. It can be judged that.

  The selection signal SEL = “0x0008” means that the output D16 of the first delay line 1010 is inverted by the NAND circuit 1012 (“Hi”) as the output D1 of the first delay line 1010. This indicates that the input is made to the determination circuit. That is, the output D1 is latched at the rising edge of the output C15 of the 15th second delay element 1041 of the second delay line 1040, and the output D2 is output from the 16th second delay element 1041 of the second delay line 1040 to the output C16. Latching at the rising edge.

  At timing T13, the time from the fall of the output D3 of the first delay line 1010 to the rise of the output C1 of the second delay line 1040 may be 10 ps or less of the measurement resolution depending on the measurement period TW11. In that case, a flip-flop hold time violation may occur and the flip-flop may not latch the output C1 correctly. Therefore, a third inversion determination circuit (not shown) is used to prevent a situation in which the hold time violation occurs and the output C1 cannot be latched correctly. The third inversion determination circuit latches the output C1 at the falling edge of the output D3. The latch result at timing T13 passes through a multiplexer (not shown) and becomes the output M3 (not shown) of the third inversion determination circuit. The output M3 is output to the second encoder 1050. The second encoder 1050 inverts and encodes the output M3. Thereby, the continuity of the bit data with the result latched from timing T18 to timing T19 can be maintained.

  Also at timing T14 to timing T17, the fourth inversion determination circuit (not shown) to the sixteenth inversion determination circuit 1130 are used similarly to the timing T13. A fourth inversion determination circuit (not shown) to a sixteenth inversion determination circuit 1130 latch the outputs C2 to C14 of the second delay line 1040 at the falling edge of the outputs D4 to D16 of the first delay line 1010, respectively. The latch results from timing T14 to timing T17 pass through the multiplexer (not shown) of the fourth inversion determination circuit to the multiplexer 1032 and become the outputs M4 to M16 of the fourth inversion determination circuit to the sixteenth inversion determination circuit 1130. These outputs M4 to M16 are output to the second encoder 1050. The second encoder 1050 inverts and encodes these outputs M4 to M16. Thereby, the continuity of the bit data with the result latched from timing T18 to timing T19 can be maintained.

  Accordingly, from timing T13 to timing T17, the results from the output M3 of the third inversion determination circuit to the output M16 of the sixteenth inversion determination circuit 1130 are input to the second encoder 1050, and the second encoder 1050 inverts these results. And encode. On the other hand, at timing T18 and timing T19, the output P1 of the first determination circuit 1060 and the output P2 of the second determination circuit 1080 are input to the second encoder 1050, and the second encoder 1050 encodes the results as they are.

The second encoder 1050 performs encoding using 16-bit data from the most significant bit to the least significant bit, and outputs a 4-bit encoded result to the second encoder output SEOUT.
For example, in the example of FIG. First, the most significant bit of the 16-bit data is the output P2 (“Low”) of the second determination circuit 1080. The fifteenth bit is the output P1 (“Low”) of the first determination circuit 1060. The fourteenth bit is a result (“Low”) of inverting the output M16 (“Hi”) of the sixteenth inversion determination circuit 1130. The thirteenth bit is a result (“Low”) of inverting the output M15 (“Hi”) of the fifteenth inversion determination circuit 1110. The twelfth bit is a result (“Low”) of inverting the output M14 (“Hi”) of the fourteenth inversion determination circuit (not shown). The eleventh bit is the result (“Low”) of inverting the output M13 (“Hi”) of the thirteenth inversion determination circuit (not shown). The tenth bit is a result (“Low”) of inverting the output M12 (“Hi”) of the twelfth inversion determination circuit (not shown). The ninth bit is a result (“Low”) of inverting the output M11 (“Hi”) of the eleventh inversion determination circuit (not shown). The eighth bit is a result (“Low”) of inverting the output M10 (“Hi”) of the tenth inversion determination circuit (not shown). The seventh bit is a result (“Low”) of inverting the output M9 (“Hi”) of the ninth inversion determination circuit (not shown). The sixth bit is a result (“Low”) of inverting the output M8 (“Hi”) of the eighth inversion determination circuit (not shown). The fifth bit is the result (“Low”) of inverting the output M7 (“Hi”) of the seventh inversion determination circuit (not shown). The fourth bit is the result (“Low”) of inverting the output M6 (“Hi”) of the sixth inversion determination circuit (not shown). The third bit is a result (“Low”) of inverting the output M5 (“Hi”) of the fifth inversion determination circuit (not shown). The second bit is the result (“Hi”) of inverting the output M4 (“Low”) of the fourth inversion determination circuit (not shown). The least significant bit is the result of inverting the output M3 ("Low") of a third inversion determination circuit (not shown) ("Hi")
). That is, the second encoder 1050 determines that the output of the determination circuit 1055 is “0000, 0000, 0000, 0011” as 16-bit data.
Subsequently, the second encoder 1050 determines how many bits (output corresponding to the second delay element 1041 of the second delay line 1040) is “1”, and outputs the second encoder. Output as SEOUT. In the example of FIG. 4, since the first bit (the output corresponding to the second delay element 1041 at the second stage of the second delay line) is “1”, “0x2” is output as the second encoder output SEOUT. .

  The time digital conversion circuit 1000 outputs a time digital conversion output OUT having the counter output COUT as upper 16 bits, the first encoder output FEOUT as middle 4 bits, and the second encoder output SEOUT as lower 4 bits. In the example of FIG. 4, the time digital conversion output OUT = “0x000132” is output based on the counter output COUT = “0x0001”, the first encoder output FEOUT = “0x3”, and the second encoder output SEOUT = “0x2” ( Timing T19).

  The time digital conversion circuit 1000 according to the present embodiment can reduce the circuit scale even when the maximum measurement range is large and measurement is performed with high resolution. The reason is as follows.

  In the operation of the present embodiment (FIGS. 3 and 4), the first delay line 1010 is composed of 16 stages of first delay elements 1011 (n = 16), and the second delay line 1040 is made of 16 stages of second delay. An element 1041 is used (n = 16). However, the delay time t1 of the first delay element 1011 is 160 ps, and the delay time t2 of the second delay element 1041 is 150 ps. In this case, the output D16 of the 16th first delay element 1011 of the first delay line 1010 is inverted at a cycle of 160 ps × 16 stages = 2.56 ns. Therefore, the counter 1020 outputs the counter output COUT with a resolution of every 2.56 ns.

  The time difference between the output Dm (m = 1 to n−1, natural number) of the first delay element 1011 in the first delay line 1010 and the output m + 1 is 160 ps. Therefore, the first encoder 1030 outputs the first encoder output FEOUT with a resolution of 160 ps.

  Further, the outputs P1, M1,..., P16, M16 of the first determination circuit 1060, the first inversion determination circuit 1070,..., The sixteenth determination circuit 1120, and the sixteenth inversion determination circuit 1130 are the delay time t1 of the first delay element 1011. And a resolution for each difference between the delay time t2 of the second delay element 1041 and the second delay element 1041. That is, the outputs P1, M1,..., P16, M16 are output with a resolution of every difference t1-t2 = 160 ps-150 ps = 10 ps. Accordingly, the second encoder 1050 outputs the second encoder output SEOUT with a resolution of 10 ps.

  At this time, the measurement time is calculated by counter output COUT × 2.56 ns + first encoder output FEOUT × 160 ps + second encoder output SEOUT × 10 ps. In other words, in the measurement time, the counter output COUT corresponds to the upper digit, the first encoder output FEOUT corresponds to the middle digit, and the second encoder output SEOUT corresponds to the lower digit.

  As described above, the time digital conversion circuit 1000 according to the present embodiment can measure with a resolution of every 10 ps by the second encoder output SEOUT. Here, since the second encoder output SEOUT and the first encoder output FEOUT are 16-stage encode outputs, each is a 4-bit output. By configuring the counter 1020 with 16 bits, a 24-bit output time digital conversion circuit output OUT can be generated.

  In this case, the time digital conversion circuit 1000 includes 16 first delay elements 1011 and 2nd delay elements 1041, 1 16-bit counter 1020, and 4 4-bit first and second encoders 1030 and 1050 in total. , And 512 flip-flops. However, there are 512 flip-flops of 16 stages × 16 stages × 2. With such a configuration, the time digital conversion circuit 1000 can measure a 24-bit measurement range with a resolution of 10 ps. As described above, the time-digital conversion circuit 1000 according to the present embodiment can reduce the circuit scale as compared with the conventional technique that requires 16.7 million delay elements and flip-flops. That is, the circuit scale can be kept small regardless of the measurement range.

  In the time digital conversion circuit 1000 of the above embodiment, the measurement range is 24 bits and the measurement resolution is 10 ps. The delay time of the first delay element 1011 of the first delay line 1010 is 160 ps, the delay time of the second delay element 1041 of the second delay line 1040 is 150 ps, and the number of both delay elements is 16 (16 stages). is there. Further, the first encoder 1030 has 4 bits, the second encoder 1050 has 4 bits, the counter 1020 has 16 bits, and the counter 1020 has an operation period of 2.56 ns (390 MHz). However, the present embodiment is not limited to this example. The time digital conversion circuit 1000 can appropriately change the performance (specification) according to the device to which it is applied.

  FIG. 5 is a table showing various specifications of the time digital conversion circuit according to the present embodiment. The measurement range (rng) and measurement resolution (res) are determined by the required specifications. When the delay time t1 of the first delay element 1011 is set, the delay time t2 of the second delay element 1041 is set by t1-res. The number n of both delay elements is set at t1 / res. The number of bits Be1 of the first encoder 1030 and the number of bits Be2 of the second encoder 1050 are both set to lon2 (n). The bit number Bc of the counter 1020 is set by rng− (Be1 + Be2). The operation cycle (count-up cycle) Ct of the counter 1020 is set by t1 · n.

  Therefore, for example, when the measurement range rng is decreased (or increased), the bit number Bc of the counter 1020 is decreased (or increased). For example, when the measurement range rng is reduced to 18 bits, the bit number Bc of the counter 1020 is set to 10 bits. At that time, the measurement resolution is set to 10 ps, and the delay time t1 is set to 160 ps. In this case, the delay time t2 is 150 ps, and the number n of both delay elements is 16 (16 stages). The bit number Be1 of the first encoder 1030 is 4 bits, the bit number Be2 of the second encoder 1050 is 4 bits, and the operation cycle (count-up cycle) Ct of the counter 1020 is 2.56 ns (390 MHz).

  For example, when the measurement resolution res is reduced (or increased), the delay time t2 of the second delay element 1041 is decreased (or increased). For example, when the measurement resolution res is reduced to 20 ps, the delay time t2 of the second delay element 1041 is reduced to 140 ps. At that time, the measurement range rng is set to 24 bits, and the delay time t1 is set to 160 ps. In this case, the number n of both delay elements is 8 (8 stages). The bit number Be1 of the first encoder 1030 is 3 bits, the bit number Be2 of the second encoder 1050 is 3 bits, the bit number n of the counter 1020 is 18 bits, and the operation cycle (count-up cycle) Ct of the counter 1020 is 1.28 ns ( 780 MHz).

  For example, when the operation cycle Ct of the counter 1020 is delayed (or accelerated), the delay times t1 and t2 are increased (or decreased) according to the required measurement resolution res and / or the number n of both delay elements. Increase (or decrease). For example, when the operation cycle Ct of the counter 1020 is delayed to 40.96 ns (24.4 MHz), if the required measurement resolution res is 10 ps, the delay time t1 is set to 640 ps and the delay time t2 is set to 640 ps. In this case, the number n of both delay elements is 64 (64 stages). The bit number Be1 of the first encoder 1030 is 6 bits, the bit number Be2 of the second encoder 1050 is 6 bits, the bit number n of the counter 1020 is 12 bits, and the operation cycle (count-up cycle) Ct of the counter 1020 is 40.96 ns ( 24.4 MHz).

  As described above, the performance (specification) of the time digital conversion circuit 1000 according to the present embodiment can be changed as appropriate according to the device to which it is applied.

(Second Embodiment)
A time digital conversion circuit 2000 according to the second embodiment will be described. The time digital conversion circuit 2000 according to the present embodiment is different from the first embodiment in the configuration and operation of the determination circuit 1055. Below, the difference is mainly demonstrated.

  The configuration of the time digital conversion circuit according to the second embodiment will be described. FIG. 6 is a block diagram showing a configuration of the time digital conversion circuit according to the second embodiment. This time digital conversion circuit 2000 may be mixedly mounted on one semiconductor chip together with other circuits.

  The determination circuit 1055 of the time digital conversion circuit 2000 corresponds to the n first delay elements 1011 of the first delay line 1010, and includes a first determination circuit 2060, a second determination circuit 2080,. 1) It has a determination circuit 2100 and an nth determination circuit 2120 (n in total). The determination circuit 1055 further includes a first inversion determination circuit 2070, a second inversion determination circuit 2090,... (N−1) th corresponding to the n second delay elements 1041 of the second delay line 1040. An inversion determination circuit 2110 and an nth inversion determination circuit 2130 are provided (n in total).

  The first determination circuit (non-inversion determination circuit) 2060 includes the output D1 of the first delay element 1011 at the first stage and the outputs C1 to C1 of the second delay element 1041 at the first stage and the second delay elements 1041 at the nth stage. The output Cn is input, and the output QP1 is output as the determination circuit output. The second determination circuit 2080 receives the output D2 of the first delay element 1011 at the second stage and the output Cn of the second delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. The output QP2 is output as the determination circuit output. Similarly, the (n−1) th determination circuit 2100 includes the output Dn−1 of the (n−1) th first delay element 1011 and the output C1 to the nth stage of the first delay element 1041 of the first stage. The output Cn of the second delay element 1041 is input, and the output QPn−1 is output as the determination circuit output. The nth determination circuit 2120 receives the output Dn of the first delay element 1011 at the nth stage and the output Cn of the first delay element 1041 at the first stage and the output Cn of the second delay element 1041 at the nth stage. The output QPn is output as the determination circuit output.

  The first inversion determination circuit 2070 receives the output D1 of the first delay element 1011 at the first stage and the output Dn of the first delay element 1011 at the nth stage and the output C1 of the second delay element 1041 at the first stage. Then, the output QM1 is output as the inversion determination circuit output. The second inversion determination circuit 2090 receives the output D1 of the first delay element 1011 at the first stage and the output Dn of the first delay element 1011 at the nth stage and the output C2 of the second delay element 1041 at the second stage. Then, the output QM2 is output as the inversion determination circuit output. Similarly, the (n−1) th inversion determination circuit 2110 outputs the output D1 of the first delay element 1011 at the first stage to the output Dn of the first delay element 1011 at the nth stage and the (n−1) th stage. The output Cn-1 of the 2-delay element 1041 is input, and an output QMn-1 is output as an inversion determination circuit output. The nth inversion determination circuit 2130 receives the output D1 of the first delay element 1011 at the first stage, the output Dn of the second delay element 1041 at the nth stage, and the output Cn of the second delay element 1041 at the nth stage. Then, the output QMn is output as the inversion determination circuit output.

  The first determination circuit 2060 includes a multiplexer 2061 and a flip-flop 2062. The multiplexer 2061 selects n delay element outputs from the output C1 to the output Cn by the select signal SEL, and outputs the selected output to the flip-flop 2062. The flip-flop 2062 latches the output D1 at the rising edge of the output of the multiplexer 2061 and outputs it as the first determination circuit output QP1. The second determination circuit 2080 includes a multiplexer 2081 and a flip-flop 2082. The multiplexer 2081 selects n delay element outputs from the output C1 to the output Cn by the select signal SEL and outputs the selected delay element outputs to the flip-flop 2082. The flip-flop 2082 latches the output D2 at the rising edge of the output of the multiplexer 2081 and outputs it as the first determination circuit output QP2. Similarly, the (n−1) th determination circuit 2100 includes a multiplexer 2101 and a flip-flop 2102. The multiplexer 2101 selects n delay element outputs from the output C <b> 1 to the output Cn by the select signal SEL and outputs it to the flip-flop 2102. The flip-flop 2102 latches the output Dn−1 at the rise of the output of the multiplexer 2101 and outputs it as the (n−1) th determination circuit output QPn−1. The nth determination circuit 2120 includes a multiplexer 2121 and a flip-flop 2122. The multiplexer 2121 selects n delay element outputs from the output C <b> 1 to the output Cn by the select signal SEL and outputs it to the flip-flop 2122. The flip-flop 2122 latches the output Dn at the rise of the output of the multiplexer 2101 and outputs it as the nth determination circuit output QPn.

  The first inversion determination circuit 2070 has a multiplexer 2071 and a flip-flop 2072. The multiplexer 2071 selects n delay element outputs from the output D1 to the output Dn by the select signal SEL and outputs the selected signal to the flip-flop 2072. The flip-flop 2072 latches the output C1 at the falling edge of the output of the multiplexer 2071 and outputs it as the first inversion determination circuit output QM1. The second inversion determination circuit 2090 has a multiplexer 2091 and a flip-flop 2092. The multiplexer 2091 selects n delay element outputs from the output D1 to the output Dn by the select signal SEL and outputs the selected signal to the flip-flop 2092. The flip-flop 2092 latches the output C2 at the falling edge of the output of the multiplexer 2091 and outputs it as the second inversion determination circuit output QM2. The (n−1) th inversion determination circuit 2110 has a multiplexer 2111 and a flip-flop 2112. The multiplexer 2111 selects n delay element outputs from the output D1 to the output Dn by the select signal SEL and outputs the selected signal to the flip-flop 2112. The flip-flop 2112 latches the output Cn−1 at the falling edge of the output of the multiplexer 2111, and outputs it as the (n−1) th inversion determination circuit output QMn−1. The n-th inversion determination circuit 2130 includes a multiplexer 2131 and a flip-flop 2132. The multiplexer 2131 selects n delay element outputs from the output D1 to the output Dn with the select signal SEL and outputs the selected signal to the flip-flop 2132. The flip-flop 2132 latches the output Cn at the falling edge of the output of the multiplexer 2131 and outputs it as the nth inversion determination circuit output QMn.

  Next, the operation (time digital conversion method) of the time digital conversion circuit according to the present embodiment will be described.

  In the first embodiment, in the first determination circuit 1060 to the nth determination circuit 1120 and the first inversion determination circuit 1070 to the nth inversion determination circuit 1130, the results of latching by the flip-flops 1061 to 1131 are multiplexers 1062 to 1132. Select with. On the other hand, in this embodiment, in the first determination circuit 2060 to the nth determination circuit 2120 and the first inversion determination circuit 2070 to the nth inversion determination circuit 2130, the clocks latched by the flip-flops 2062 to 2132 are multiplexed by the multiplexers 2061 to 2131. Select by.

  That is, the first determination circuit 1060 of the first embodiment has n flip-flops 1061. Each flip-flop 1061 latches the output D1 at the rising edge of n delay element outputs from the output C1 to the output Cn. The multiplexer 1062 selects the latched result with the select signal SEL and outputs it to the first determination circuit output P1. On the other hand, in the first determination circuit 2060 of the present embodiment, first, the multiplexer 2061 selects n delay element outputs from the output C1 to the output Cn by the select signal SEL. Then, the flip-flop 2062 latches the output D1 at the rising edge of the result selected by the multiplexer 2061, and outputs it to the second encoder 1050 as the first determination circuit output QP1.

  The first inversion determination circuit 1070 of the first embodiment has n flip-flops 1071. Each flip-flop 1071 latches n delay element outputs from the output C1 to the output Cn at the falling edge of the output D1. The multiplexer 1072 selects the latched result with the select signal SEL and outputs it to the first inversion determination circuit output M1. On the other hand, in the first inversion determination circuit 2070 of this embodiment, first, the multiplexer 2071 selects n delay element outputs from the output D1 to the output Dn by the select signal SEL. The flip-flop 2072 latches the output C1 and outputs it as the first inversion determination circuit output QM1 at the falling edge of the result selected by the multiplexer 2071.

  Thereafter, similarly to the first determination circuit 2060 and the first inversion determination circuit 2070, the second determination circuit 2080 to the nth determination circuit 2120 and the second inversion determination circuit 2090 to the nth inversion determination circuit 2130 operate. The other operations of the determination circuit 1055 are the same as those in the first embodiment (FIGS. 3 and 4).

Also in this embodiment, the same effect as that of the first embodiment can be obtained.
Further, in the present embodiment, the time digital conversion circuit 2000 can further reduce the circuit scale as compared with the first embodiment when measuring with a wide maximum measurement range and high resolution. . The reason is that the number of flip-flops required for the time-to-digital conversion circuit is selected in the first to n-th determination circuit and the first to n-th inversion determination circuits by preselecting a signal to be latched by the flip-flop with a multiplexer. This is because 1 / n in the case of the first embodiment can be achieved.

(Third embodiment)
A time digital conversion circuit according to a third embodiment will be described. In this embodiment, a case where the time digital conversion circuit according to the first to second embodiments is applied to an ultrasonic flow meter will be described.

First, a configuration example of the ultrasonic flowmeter will be described.
FIG. 7 is a block diagram showing a configuration example of an ultrasonic flowmeter to which the time digital conversion circuit according to the present embodiment is applied. The ultrasonic flowmeter includes an ultrasonic transducer 2, an ultrasonic transducer 3, and a control circuit 4. The ultrasonic transducer 2 is installed upstream of the flow path 1 through which the flow rate measurement target flows, is supplied with a drive signal DRVA indicating the start of driving, transmits ultrasonic waves to the measurement target, and transmits the transmitted ultrasonic waves or received ultrasonic waves. A sound wave is output as a vibration signal USNDA. The ultrasonic transducer 3 is installed downstream of the flow path 1 and is supplied with a drive signal DRVB indicating the start of driving, transmits an ultrasonic wave to a measurement object, and transmits the transmitted ultrasonic wave or the received ultrasonic wave as a vibration signal USNDB. Output as. The control circuit 4 outputs a drive signal DRVA and a drive signal DRVB that control the ultrasonic transducers 2 and 3, receives the vibration signal USNDA and the vibration signal USNDB, and calculates a flow rate.

  The control circuit 4 includes a transmission / reception switching circuit 9, a transmission detection circuit 10, a reception detection circuit 6, a time digital conversion circuit 1000, a calculation unit 8, a control unit 7, and a drive circuit 5. The transmission / reception switching circuit 9 is supplied with the vibration signal USNDA, the vibration signal USNDB, the control signal CNT, and the drive notification signal DRV, and outputs the drive signal DRVA, the drive signal DRVB, the transmission detection signal SEN, and the reception detection signal REC. The transmission detection circuit 10 is supplied with a transmission detection signal SEN and outputs a reference clock CLK. The reception detection circuit 6 is supplied with the reception detection signal REC and outputs the signal under measurement SC. The time digital conversion circuit 1000 is supplied with the reference clock CLK and the signal under measurement SC and outputs a time digital conversion output OUT. The time digital conversion circuit 1000 is exemplified in the configuration of FIG. 2, but may be the time digital conversion circuit 2000 exemplified in the configuration of FIG. 6. The calculation unit 8 is supplied with the time digital conversion output OUT and outputs a calculation result RES. The control unit 7 is supplied with the calculation result RES and outputs a control signal CNT and a measurement start signal STR. The drive circuit 5 is supplied with the measurement start signal STR and outputs a drive notification signal DRV. However, the transmission / reception switching circuit 9, the transmission detection circuit 10, the reception detection circuit 6, the arithmetic unit 8, the control unit 7, and the drive circuit 5 can be regarded as one internal control circuit. The control circuit 4 including the time digital conversion circuit 1000 may be mixedly mounted on one semiconductor chip.

Next, the operation of the ultrasonic flow meter will be described.
FIG. 8 is a timing chart showing an example of the operation of the ultrasonic flowmeter to which the time digital conversion circuit according to the present embodiment is applied. However, (a) shows the control signal CNT. (B) shows the measurement start signal STR. (C) shows the drive notification signal DRV. (D) shows the drive signal DRVA. (E) The drive signal DRVB is shown. (F) shows the vibration signal USNDA. (G) shows the transmission detection signal SEN. (H) shows the reference clock CLK. (I) shows the vibration signal USNDB. (J) shows the reception detection signal REC. (K) shows the signal under measurement SC. (L) shows the time digital conversion output OUT. (M) indicates the calculation result RES.

  The control unit 7 outputs “Hi” as the control signal CNT to the transmission / reception switching circuit 9 in order to measure the flow rate from upstream to downstream of the flow path 1. The transmission / reception switching circuit 9 is set to measure the flow rate from upstream to downstream by the control signal CNT (timing T101). The control unit 7 outputs a measurement start signal STR indicating the start of measurement to the drive circuit 5 (timing T102). In response to the measurement start signal STR, the drive circuit 5 outputs a drive notification signal DRV indicating drive start to the transmission / reception switching circuit 9. In response to the drive notification signal DRV, the transmission / reception switching circuit 9 outputs the drive signal DRVA to the ultrasonic transducer 2 in order to drive the ultrasonic transducer 2 installed upstream of the flow path 1 (timing T103). . The ultrasonic transducer 2 starts oscillating ultrasonic waves and outputs a vibration signal USNDA that is the transmitted ultrasonic waves to the transmission / reception switching circuit 9. The transmission / reception switching circuit 9 outputs the vibration signal USNDA as the transmission detection signal SEN to the transmission detection circuit 10 (timing T104). The transmission detection circuit 10 detects the transmission detection signal SEN and outputs the reference clock CLK to the time digital conversion circuit 1000 (timing T105). The ultrasonic transducer 3 installed downstream of the flow path 1 receives the vibration signal USNDA that is an ultrasonic wave transmitted from the ultrasonic transducer 2 and outputs the vibration signal USNDA to the transmission / reception switching circuit 9 as the vibration signal USNDB. The transmission / reception switching circuit 9 outputs the vibration signal USNDB to the reception detection circuit 6 as the reception detection signal REC (timing T106). The reception detection circuit 6 detects the reception detection signal REC and outputs the signal under measurement SC to the time digital conversion circuit 1000 (timing T107). The time digital conversion circuit 1000 measures the time from the input of the reference clock CLK to the input of the signal to be measured SC, and outputs the time digital conversion output OUT to the arithmetic unit 8 as the measurement result (timing T108). The calculation unit 8 determines the measurement result based on the time digital conversion output OUT and outputs the calculation result RES to the control unit 7.

  Next, the control unit 7 outputs “Low” as the control signal CNT to the transmission / reception switching circuit 9 in order to measure the flow rate from the downstream side to the upstream side of the flow path 1. The transmission / reception switching circuit 9 is set to measure the flow rate from downstream to upstream by the control signal CNT. The transmission detection circuit 10 and the reception detection circuit 6 clear the reference clock CLK and the signal under measurement SC via the transmission / reception switching circuit 9 (timing T109). The control unit 7 outputs a measurement start signal STR indicating the start of measurement to the drive circuit 5 (timing T110). In response to the measurement start signal STR, the drive circuit 5 outputs a drive notification signal DRV indicating drive start to the transmission / reception switching circuit 9. In response to the drive notification signal DRV, the transmission / reception switching circuit 9 outputs the drive signal DRVB to the ultrasonic transducer 3 in order to drive the ultrasonic transducer 3 installed downstream of the flow path 1 (timing T111). . The ultrasonic transducer 3 starts oscillating ultrasonic waves and outputs a vibration signal USNDB which is the transmitted ultrasonic waves to the transmission / reception switching circuit 9. The transmission / reception switching circuit 9 outputs the vibration signal USNDB as the transmission detection signal SEN to the transmission detection circuit 10 (timing T112). The transmission detection circuit 10 detects the transmission detection signal SEN and outputs the reference clock CLK to the time digital conversion circuit 1000 (timing T113). The ultrasonic transducer 2 installed upstream of the flow path 1 receives the vibration signal USNDB which is an ultrasonic wave transmitted from the ultrasonic transducer 3, and outputs the vibration signal USNDB to the transmission / reception switching circuit 9 as the vibration signal USNDA. The transmission / reception switching circuit 9 outputs the vibration signal USNDA as the reception detection signal REC to the reception detection circuit 6 (timing T114). The reception detection circuit 6 detects the reception detection signal REC and outputs the signal under measurement SC to the time digital conversion circuit 1000 (timing T115). The time digital conversion circuit 1000 measures the time from the input of the reference clock CLK to the input of the signal under measurement SC, and outputs the time digital conversion output OUT to the arithmetic unit 8 as the measurement result (timing T116).

  With the above operation, ultrasonic waves are transmitted and received between the ultrasonic transducers (ultrasonic transducers 2 and 3 in the present embodiment) arranged opposite to the upstream and downstream of the flow path 1, and each transmission / reception arrives. The flow rate can be obtained from the time difference. That is, the apparatus shown in FIG. 7 can operate as an ultrasonic flowmeter to which a time digital conversion circuit is applied.

  In the present embodiment, the configuration of the ultrasonic flowmeter shown in FIG. 7 generates a reference clock (CLK) indicating the start of measurement using the vibration start (USNDA, USDB) of the ultrasonic transducers (2, 3) as a trigger. To do. Thereby, measurement excluding the operation delay time of the drive circuit (5) and the ultrasonic transducers (2, 3) becomes possible. That is, the ultrasonic flowmeter according to the present embodiment can effectively utilize the above-described operations and effects of the time digital conversion circuit (1000, 2000) that can be measured with high resolution.

  In the present embodiment, the time digital conversion circuits 1000 and 2000 are applied to an ultrasonic flowmeter. However, in addition to this application example, the time digital conversion circuits 1000 and 2000 also apply to all sensors (example: other measurement devices such as flowmeters and autofocus devices) that perform measurement using a time difference between two signals. Applicable.

(Fourth embodiment)
A time digital conversion circuit according to a fourth embodiment will be described. In the present embodiment, a case where the time digital conversion circuit according to the first to second embodiments is applied to an ADC (Analog-Digital Converter) will be described.

First, a configuration example of the ADC will be described.
FIG. 9 is a block diagram showing a configuration example of an ADC to which the time digital conversion circuit according to the present embodiment is applied. The ADC includes a delay circuit 110, a reset generation circuit 120, a time digital conversion circuit 1000, and an output circuit 130. The delay circuit 110 delays the reference clock CLK by a predetermined time and outputs it as the signal under measurement SC. The reset generation circuit 120 detects the timing (eg, falling timing) of the reference clock CLK, and outputs a reset signal for resetting each output in the time digital conversion circuit 1000. However, each output in the time digital conversion circuit 1000 includes a counter output COUT, a first encoder output FEOUT, a second encoder output SEOUT, first to nth determination circuit outputs P1 to Pn, and first to nth inversion determination circuit outputs. M1 to Mn. The time digital conversion circuit 1000 is supplied with the reference clock CLK and the signal under measurement SC, is further supplied with an analog signal input VIN, and outputs a time digital conversion output OUT. The time digital conversion circuit 1000 is further supplied with a reset signal, and each output is reset. The time digital conversion circuit 1000 is exemplified in the configuration of FIG. 2, but may be the time digital conversion circuit 2000 exemplified in the configuration of FIG. 6. The output circuit 130 outputs the time digital conversion output OUT at the timing of the reference clock CLK (example: falling timing).

  In the time digital conversion circuit 1000, an analog signal input VIN that is an AD conversion target is a first delay element 1011 at each stage in the first delay line 1010 and a second delay element 1041 at each stage in the second delay line 1040. Is input as the power supply voltage. The reset signal of the reset generation circuit 120 is input to the counter 1020, the first encoder 1030, the second encoder 1050, the first determination circuit 1060 to the nth determination circuit 1120, and the first inversion determination circuit 1070 to the nth inversion determination circuit 1130. The This ADC may be mixedly mounted on one semiconductor chip including the time digital conversion circuit 1000.

  FIG. 10 is a diagram illustrating a configuration example of the first delay element 1011 at each stage in the first delay line 1010 in the ADC to which the time digital conversion circuit according to the present embodiment is applied. An analog signal input VIN that is an object of AD conversion is supplied to the power supply voltage of the first delay element 1011. When the voltage of the analog signal input VIN increases, the delay time of the first delay element 1011 decreases. On the other hand, when the voltage of the analog signal input VIN decreases, the delay time of the first delay element 1011 decreases. That is, the delay time varies depending on the voltage of the analog signal input VIN. The configuration example of the second delay element 1041 at each stage in the second delay line 1040 is the same as that in FIG. That is, the analog signal input VIN that is the object of AD conversion is input to the power supply voltage of the second delay element 1041, and the same operation as in FIG.

Next, the operation of the ADC will be described.
FIG. 11 is a timing chart showing an example of the operation of the ADC to which the time digital conversion circuit according to this embodiment is applied. However, (a) shows an analog signal input VIN to be AD converted, (b) shows a reference clock CLK, and (c) shows a signal under measurement SC. (D) to (h) are outputs D1 to D5 from the first delay element 1011 of the first stage to the fifth stage, and (i) to (m) are the first delay elements 1011 of the 12th to 16th stages. Outputs D12 to D16 are respectively shown. (N) to (r) are outputs C1 to C5 from the second delay element 1041 of the first stage to the fifth stage, and (s) to (w) are the second delays of the twelfth stage to the sixteenth stage. Outputs C12 to C16 from the element 1041 are shown, respectively. (X) shows the counter output COUT from the counter 1020, (y) the first encoder output FEOUT from the first encoder 1030, and (z) shows the second encoder output SEOUT from the second encoder 1050, respectively. (A) shows the output OUT of the control circuit 1015 (time digital conversion circuit), and (B) shows the output ADOUT of the ADC.

  In the ADC time digital conversion circuit 1000, the first delay line 1010 and the second delay line 1040 operate with a delay time corresponding to the voltage of the analog signal input VIN to be AD converted. At this time, the duty of the reference clock CLK (the period of “Hi” output and the period of “Low” output) is a count-up cycle Ct (a cycle in which the delay propagation of the first delay line 1010 makes one round) represented by Expression (6). It is assumed that the input is made at a period of twice or more.

  In this ADC, after the reference clock CLK rises, the delay circuit 110 outputs the signal under measurement SC obtained by delaying the reference clock CLK for a predetermined time (the signal under measurement SC rises). The time digital conversion circuit 1000 starts, for example, the time digital conversion operation described in the first embodiment at the rising timing of the signal under measurement SC, and starts the A / D conversion operation of the analog signal input VIN (timing). T11). Subsequently, the time digital conversion circuit 1000 outputs a time digital conversion output OUT by a time digital conversion operation (timing T12). Thereafter, the output circuit 130 outputs the time digital conversion output OUT as the A / D conversion output ADOUT at the falling timing of the reference clock CLK (timing T13).

  At the same time, the reset generation circuit 120 outputs a reset signal to the time digital conversion circuit 1000 in response to the falling timing of the reference clock CLK. In response to the reset signal, the time digital conversion circuit 1000 includes a counter output COUT, a first encoder output FEOUT, a second encoder output SEOUT, first to nth determination circuit outputs P1 to Pn, and first to nth inversion determination circuits. The outputs M1 to Mn are reset (cleared to 0). “Low” starts to propagate through the first delay line 1010 (timing T13). Further, after the reference clock CLK falls, the delay circuit 110 outputs the signal under measurement SC obtained by delaying the reference clock CLK for a certain time (the signal under measurement SC falls). After the signal under test SC falls, “Low” starts to propagate through the second delay line 1040. The signals propagated to the first delay line 1010 and the second delay line 1040 are cleared to 0 (timing T14).

  Thereafter, the operations at timings T11 to T14 are repeated for each cycle of the reference clock CLK. As a result, the analog value of the analog signal input VIN at the timing of the signal under measurement SC delayed by a certain time from the rising timing of the reference clock CLK is A / D converted, and A / D converted at the falling timing of the reference clock CLK. Output as a digital value of the output ADOUT. At this time, when the voltage of the analog signal input VIN increases, the delay time of the first delay line 1010 and the second delay line 1040 decreases, and the value of the A / D conversion output ADOUT obtained by the A / D conversion operation increases. . On the other hand, when the voltage of the analog signal input VIN decreases, the delay time of the first delay line 1010 and the second delay line 1040 increases, and the value of the A / D conversion output ADOUT obtained by the A / D conversion operation increases.

  With the above operation, the analog signal input VIN can be converted from analog to digital with multi-bit high resolution.

  The ADC according to the present embodiment can effectively utilize the above-described operation and effect of the time digital conversion circuit (1000, 2000) that can be measured with high resolution by the configuration shown in FIGS.

(Fifth embodiment)
A time digital conversion circuit according to a fifth embodiment will be described. In the present embodiment, a case will be described in which the time digital conversion circuit according to the first to second embodiments is applied to an ADPLL (All Digital Phase-Locked Loop).

First, a configuration example of ADPLL will be described.
FIG. 12 is a block diagram showing a configuration example of an ADPLL to which the time digital conversion circuit according to this embodiment is applied. The ADPLL includes a cumulative adder 901, a phase comparator 902, a loop filter 903, a DCO (Digitally Controlled-Oscillator) gain normalization circuit 904, and a DCO 905. The ADPLL further includes a cumulative adder 906, a sampling circuit 907, a DCO cycle normalization circuit 908, a retiming circuit 909, and a time digital conversion circuit 1000. The ADPLL may be mixedly mounted on one semiconductor chip including the time digital conversion circuit 1000.

  The retiming circuit 909 receives the reference clock signal FREF at the data terminal and the output signal CKV of the DCO 905 at the clock terminal. The retiming circuit 909 samples the reference clock signal FREF in response to the rising edge of the output signal CKV, and outputs it to the cumulative adder 901 and the sampling circuit 907 as the clock signal CKR adjusted in timing.

  The cumulative adder 906 cumulatively adds the number of edges of the output signal CKV. The sampling circuit 907 outputs the cumulative added value of the cumulative adder 906 to the phase comparator 902 for each edge timing (example: rising edge timing) of the clock signal CKR. The cumulative adder 906 and the sampling circuit 907 measure how many times the frequency of the output signal CKV is an integer value of the frequency of the reference clock signal FREF. The cumulative adder 906 and the sampling circuit 907 may be integrated.

  In the time digital conversion circuit 1000, the reference clock signal FREF is input as the signal under measurement SC, and the output signal CKV is input as the reference clock CLK. Accordingly, the time digital conversion circuit 1000 outputs a difference between the phase of the reference clock signal FREF and the phase of the output signal CKV as a time digital conversion output OUT that is digital data. The time digital conversion output OUT is output to the DCO cycle normalization circuit 908. The DCO cycle normalization circuit 908 normalizes the phase difference (time digital conversion output OUT) with respect to the delay time measured by the time digital conversion circuit 1000 to a ratio with respect to one cycle of the output signal CKV, and outputs it to the phase comparator 902. To do. When the time digital conversion circuit 1000 and the DCO cycle normalization circuit 908 measure how many times the frequency of the output signal CKV is about the frequency of the reference clock signal FREF, the decimal part excluding the integer value is measured.

  The cumulative adder 901 performs cumulative addition of the frequency setting data FCW every time an edge of the clock signal CKR is input, and outputs the result to the phase comparator 902.

  The phase comparator 902 calculates phase error data based on the cumulative addition value from the cumulative adder 901, the cumulative addition value from the cumulative adder 906, and the phase difference from the DCO cycle normalization circuit 908, and loops Output to the filter 903. The loop filter 903 smoothes the phase error data and outputs it to the DCO gain normalization circuit 904. The DCO gain normalization circuit 904 normalizes the DCO gain based on the smoothed phase error data, and supplies the digital signal to the DCO 905 at the timing of the clock signal CKR so that the phase error data becomes zero. To do. The DCO 905 generates and outputs an output signal CKV based on the digital signal.

  With the above configuration and operation, the ADPLL can operate by adjusting the oscillation frequency of the DCO 905 so that the phase error data output from the phase comparator 902 becomes zero. As described above, the ADPLL according to the present embodiment can effectively utilize the above-described operations and effects of the time digital conversion circuit (1000, 2000) that can be measured with high resolution by the configuration shown in FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. The technology of each embodiment can be applied to other embodiments as long as no contradiction occurs.

DESCRIPTION OF SYMBOLS 1: Flow path 2: Ultrasonic transducer 3: Ultrasonic transducer 4: Control circuit 5: Drive circuit 6: Reception detection circuit 7: Control part 8: Calculation part 9: Transmission / reception switching circuit 10: Transmission detection circuit 110: Delay Circuit 120: Reset generation circuit 130: Output circuit 901: Cumulative adder 902: Phase comparator 903: Loop filter 904: Gain normalization circuit 906: Cumulative adder 907: Sampling circuit 908: DCO cycle normalization circuit 909: Retiming Circuit 1000: Time digital conversion circuit 1010: Delay line 1011: Delay element 1012: NAND circuit 1015: Control circuit 1020: Counter 1030: First encoder 1040: Delay line 1041: Delay element 1050: Second encoder 1055: Determination circuit 1060: Judgment circuit 1061: Flip Flop 1062: Multiplexer 1070: First inversion determination circuit 1071: Flip flop 1072: Multiplexer 1080: Second determination circuit 1081: Flip flop 1082: Multiplexer 1090: Second inversion determination circuit 1091: Flip flop 1092: Multiplexer 1100: (N-1) decision circuit 1101: Flip flop 1102: Multiplexer 1110: (n-1) inversion decision circuit 1111: Flip flop 1112: Multiplexer 1120: Nth decision circuit 1121: Flip flop 1122: Multiplexer 1130 : N-th inversion judgment circuit 1131: flip-flop 1132: multiplexer 2000: time digital conversion circuit 2060: first judgment circuit 2061: round Plexer 2062: Flip flop 2070: First inversion determination circuit 2071: Multiplexer 2072: Flip flop 2080: Second determination circuit 2081: Multiplexer 2082: Flip flop 2090: Second inversion determination circuit 2091: Multiplexer 2092: Flip flop 2100: (n-1) decision circuit 2101: multiplexer 2102: flip-flop 2110: (n-1) inversion decision circuit 2111: multiplexer 2112: flip-flop 2120: nth decision circuit 2121: multiplexer 2122: flip-flop Flop 2130: nth inversion determination circuit 2131: Multiplexer 2132: Flip flop

Claims (10)

A time digital conversion circuit for detecting a phase of a signal under measurement with respect to a reference clock,
N first delay elements connected in series are provided, the reference clock is input, and an operation result of the output of the nth first delay element and the reference clock is input to the first delay element of the first stage. A first delay line that
A second delay line comprising n second delay elements connected in series and receiving the signal under measurement;
The first delay of each stage in the first delay line is based on the number of propagation stages indicating how many first delay elements the reference clock has propagated in the first delay line when the signal under measurement is input. One of the first delay output from the element and the second delay output from the second delay element of each stage in the second delay line is latched at the other timing, or the other at the one timing. A determination circuit that latches and outputs, and
A time digital conversion circuit comprising: a control circuit that outputs the phase based on the number of times the reference clock reaches the n-th first delay element, the number of propagation stages, and the output of the determination circuit. The time digital conversion circuit according to claim 1,
The determination circuit includes:
Based on the number of propagation stages, the first delay output from the first delay element of each stage in the first delay line is used as the timing of the second delay output from the second delay element of each stage in the second delay line. A plurality of non-inversion determination circuits latched at
Based on the number of propagation stages, the second delay output from the second delay element in each stage in the second delay line is used as the timing of the first delay output from the first delay element in each stage in the first delay line. And a plurality of inversion determination circuits latched at
The control circuit selects an output of the determination circuit from a plurality of first outputs of the plurality of non-inversion determination circuits and a plurality of second outputs of the plurality of inversion determination circuits based on the number of times and the number of propagation stages. To time digital conversion circuit. In the time digital conversion circuit according to claim 2,
The control circuit includes:
A counter that outputs a counter value indicating the number of times;
A first encoder for outputting the number of propagation stages and a first encoded value indicating the number of propagation stages based on the signal under measurement and the first delay output of each stage of the first delay line;
Based on the counter value and the number of propagation stages, an output of the determination circuit is selected from the plurality of first outputs and the plurality of second outputs, and the reference clock and the target in the first delay line are selected. A time digital conversion circuit comprising: a second encoder that outputs a phase difference from a measurement signal. In the time digital conversion circuit according to claim 3,
The time digital conversion circuit, wherein the control circuit outputs the phase with the counter value as an upper digit, the first encoded value as a middle digit, and the second encoded value as a lower digit. In the time digital conversion circuit according to claim 2,
Each of the plurality of non-inversion determination circuits includes:
A plurality of first delay outputs latched at the timing of the second delay output from the second delay element of each stage in the second delay line with the first delay output from the i-th first delay element in the first delay line. 1 flip-flop circuit,
A first multiplex circuit that selects one of a plurality of outputs from the plurality of first flip-flop circuits based on the number of propagation stages; and
Each of the plurality of inversion determination circuits includes:
A plurality of second delay outputs latched at the timing of the first delay output from the first delay element of each stage in the first delay line with the second delay output from the jth second delay element in the second delay line. 2 flip-flop circuits,
And a second multiplex circuit that selects one of a plurality of outputs from the plurality of second flip-flop circuits based on the number of propagation stages. In the time digital conversion circuit according to claim 2,
Each of the plurality of non-inversion determination circuits includes:
A first multiplex circuit that selects one second delay output from the second delay outputs from the second delay elements of each stage in the second delay line based on the number of propagation stages;
The first delay output from the i-th (i = 1 to n) first delay element in the first delay line is latched at the timing of the second delay output selected by the first multiplex circuit. Including flip-flop circuit and
Each of the plurality of inversion determination circuits includes:
A second multiplex circuit that selects one first delay output from the first delay outputs from the first delay elements of each stage in the first delay line based on the number of propagation stages;
A second latch that latches the second delay output from the second delay element of the jth stage (j = 1 to n) in the second delay line at the timing of the first delay output selected by the third multiplex circuit. Flip-flop circuit and time digital conversion circuit. A first supersonic wave is installed in the flow path through which the flow rate measurement target flows, is supplied with a first drive signal indicating the start of driving, transmits an ultrasonic wave to the flow rate measurement target, and outputs the transmitted ultrasonic wave as a first vibration signal. A sound wave vibration unit;
A second ultrasonic vibration unit installed in the flow path, supplied with a second drive signal indicating drive start, and outputting the received ultrasonic wave as a second vibration signal;
A control circuit that outputs the first drive signal and the second drive signal, receives the first vibration signal and the second vibration signal, and calculates a flow rate of the flow rate measurement target;
The control circuit includes:
An internal control circuit that generates and outputs a reference clock in response to the first vibration signal, and generates and outputs a signal under measurement in response to the second vibration signal;
The time digital conversion circuit according to claim 1, wherein a time from the input of the reference clock to the input of the signal under measurement is measured and output as a time digital conversion output.
The internal control circuit is an ultrasonic flowmeter that calculates the flow rate based on the time digital conversion output. A delay circuit that delays the reference clock for a predetermined time and outputs it as a signal under measurement;
The time digital conversion circuit according to claim 1, wherein the time clock conversion circuit is supplied with the reference clock, the signal under measurement, and an analog signal input, and outputs a time digital conversion output.
An output circuit for outputting the time digital conversion output at the timing of the reference clock,
The analog signal input VIN is input as a power supply voltage of the first delay element at each stage in the first delay line and the second delay element at each stage in the second delay line of the time digital conversion circuit. . DCO (Digitally-Controlled-Oscillator) that outputs an output signal;
A retiming circuit that samples a reference clock signal at the timing of the output signal, and outputs the sampled clock signal as a timing-adjusted clock signal;
A first cumulative addition circuit that outputs a first cumulative addition value obtained by cumulatively adding the number of edges of the output signal based on an input of the clock signal;
A time digital conversion circuit that uses the reference clock signal as a signal under measurement, the output signal is input as a reference clock, and is output as a time digital conversion output that is a phase difference between the two signals;
A DCO cycle normalization circuit that normalizes and outputs the time digital conversion output to a ratio of one cycle of the output signal;
A second cumulative addition unit that outputs a second cumulative addition value obtained by cumulatively adding the frequency setting data based on the input of the clock signal;
A phase comparator that calculates and outputs phase error data based on the first cumulative addition value, the second cumulative addition value, and the normalized time digital conversion output;
A loop filter for smoothing and outputting the phase error data;
A DCO gain normalization circuit that normalizes the gain of the DCO based on the smoothed phase error data and supplies a digital signal at the timing of the clock signal so that the phase error data becomes zero; Equipped,
The DCO is a complete digital phase synchronization circuit that generates the output signal CKV based on the digital signal. A time digital conversion method for detecting a phase of a signal under measurement with respect to a reference clock,
The reference clock is input to a first delay line including n first delay elements connected in series, and an operation result of the output of the nth first delay element and the reference clock is calculated as the first delay line. Inputting to one delay element;
Inputting the signal under measurement to a second delay line comprising n second delay elements connected in series;
Each stage in the first delay line has a decision circuit based on the number of propagation stages indicating the number of first delay elements propagated in the first delay line when the signal under measurement is input. One of the first delay output from the first delay element and the second delay output from the second delay element of each stage in the second delay line is latched at the other timing, or the other is Latching and outputting at one timing;
A control circuit comprising: a step of outputting the phase based on the number of times the reference clock reaches the n-th first delay element, the number of propagation stages, and the output of the determination circuit; .

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