JP2014119953A - Computer and interrupt service routine execution method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable execution of coded interrupt service routines on a computer.SOLUTION: In one embodiment, a computer (1) is configured to respond to occurrence of a first interrupt by having a control unit (14) send an interrupt pseudo instruction (IPI) for branching to a first interrupt service routine to an instruction processing unit (11). The interrupt pseudo instruction (IPI) is associated with a first decoding key identifier corresponding to the first interrupt. The computer (1) is also configured to set a decoding key corresponding to the first decoding key identifier in a decoding circuit (50) in association with execution of the interrupt pseudo instruction (IPI) by the instruction processing unit (11), and have the decoding circuit (50) decode the first coded interrupt service routine.

Description

  The present invention relates to a computer and can be suitably used for, for example, a computer that decrypts and executes an encrypted program code.

  Patent Documents 1 to 3 disclose a computer that decrypts and executes an encrypted program code (instruction routine). For example, the computer disclosed in Patent Document 1 reads the encrypted program code from the external memory, decrypts the encrypted program code using the decryption key corresponding to the key identifier specified by the processor, The decrypted program code is stored in the cache memory. Then, the processor reads the decrypted program code from the cache memory and executes it.

  Further, in Patent Document 1, the program code includes an explicit instruction for shifting from the non-tamper resistant state to the tamper resistant state. The computer shifts from the non-tamper resistant state to the tamper resistant state by executing the instruction. This instruction designates the start address of the memory block storing the encrypted program code and the address of the decryption key.

  Furthermore, it is described that the computer disclosed in Patent Document 1 shifts from a tamper resistant state to a non-tamper resistant state when a hardware interrupt occurs. That is, the computer disclosed in Patent Document 1 executes an interrupt service routine (interrupt handler) in a non-tamper resistant state.

JP 2003-51819 A JP 2009-301565 A JP 2009-278491 A

  The computer of Patent Literature 1 executes an interrupt service routine (interrupt handler) in a non-tamper resistant state when a hardware interrupt occurs. Therefore, interrupt service routines stored in non-volatile memory (eg, mask ROM (Read Only Memory), programmable ROM, flash memory, or hard disk drive) for supply to a computer are not encrypted. However, assuming various computer usage scenarios, it is preferable to be able to use an encrypted interrupt service routine. The computers disclosed in Patent Documents 1 to 3 have a problem that the encrypted interrupt service routine cannot be executed on the computer. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In one embodiment, the computer is configured to inject an interrupt pseudo-instruction for branching to the first interrupt service routine from the control unit to the instruction processing unit in response to the occurrence of the first interrupt. The interrupt pseudo instruction is associated with a first decryption key identifier corresponding to the first interrupt. Further, the computer sets a decryption key corresponding to the first decryption key identifier in the decryption circuit based on execution of the interrupt pseudo-instruction in the instruction processing unit, and an encrypted first interrupt service routine Is decoded by the decoding circuit.

  The above-described embodiments can execute an encrypted interrupt service routine in a computer.

It is a block diagram which shows the 1st structural example of the computer which concerns on 1st Embodiment. FIG. 2 is a block diagram illustrating a configuration example of an interrupt vector table illustrated in FIG. 1. It is a flowchart which shows an example of the execution method of the interruption service routine which concerns on 1st Embodiment. It is a block diagram which shows the 2nd structural example of the computer which concerns on 1st Embodiment. FIG. 5 is a block diagram illustrating a configuration example of an interrupt controller illustrated in FIG. 4. It is a block diagram which shows the structural example of the computer which concerns on 2nd Embodiment. It is a flowchart which shows an example of the output control method of the trace data which concerns on 2nd Embodiment.

  Hereinafter, specific embodiments will be described in detail with reference to the drawings. In each drawing, the same or corresponding elements are denoted by the same reference numerals, and redundant description is omitted as necessary for clarification of the description.

<First Embodiment>
The computer 1 according to the present embodiment controls an interrupt pseudo instruction (IPI) for branching to a first interrupt service routine (ISR) in response to the occurrence of the first interrupt. The logic 14 is configured to be input to the instruction processing unit 11. In one example, the IPI is associated with a first decryption key identifier (eg, key number KN) corresponding to the first interrupt. In other words, the IPI includes an instruction that causes the decryption circuit 50 to set the decryption key corresponding to the first decryption key identifier. The decryption circuit 50 sets a decryption key corresponding to the first decryption key identifier based on the execution of IPI in the instruction processing unit 11. Thereby, the instruction processing unit 11 branched to the first ISR can execute the ISR. That is, the computer 1 can be executed after decrypting the encrypted ISR.

  A CPU (Central Processing Unit) 10 executes a plurality of ISRs in order to handle a plurality of interrupt factors (for example, a plurality of interrupts from a plurality of peripheral devices). In one example, the plurality of ISRs are encrypted with different encryption keys and require decryption with different decryption keys. Therefore, the control logic 14 may specify a decryption key (decryption key identifier) corresponding to the interrupt factor (or interrupt vector). Specifically, the computer 1 may have a registry that defines a plurality of decryption key identifiers corresponding to a plurality of interrupt factors (or interrupt vectors). The registry may be arranged in the CPU 10, the interrupt vector table 21, or the interrupt controller 20. The control logic 14 may specify a decryption key (decryption key identifier) corresponding to the generated interrupt based on the registry. According to such an architecture, a plurality of ISRs that require different decryption keys can be executed in the computer 1.

  The computer 1 according to the present embodiment is, for example, a microprocessor, a microcomputer, a microcontroller, or an SoC (System on Chip). The computer 1 may be composed of only one IC chip or may be composed of a plurality of IC chips. Below, the specific example of a structure and operation | movement of the computer 1 which concerns on this embodiment is demonstrated.

  FIG. 1 is a block diagram illustrating a first configuration example of the computer 1. The CPU 10 includes an instruction processing unit 11. The instruction processing unit 11 fetches instructions, decodes instructions, and executes the instructions. The instruction processing unit 11 is typically an instruction pipeline. In the configuration example of FIG. 1, the instruction processing unit 11 includes an instruction fetch unit 110, an instruction decode unit 111, an instruction execution unit 112, and a write back unit 113.

  The instruction fetch unit 110 fetches the program code stored in the memory 40 via the cache memory 30 and the bus controller 13. The instruction decode unit 111 decodes the fetched instruction, determines an operation type (for example, addition / subtraction, multiplication, division, or logical operation) to be executed, and generates a necessary control signal. The instruction execution unit 112 changes the internal state of the CPU 10 according to the decoded instruction. That is, the instruction execution unit 112 has a plurality of execution units (for example, an ALU (Arithmetic Logic Unit), a multiplier, a barrel shifter, and a load / store unit), and executes an operation according to the decoded instruction. The write back unit 113 writes the output data of the instruction execution unit 112 to a general purpose register (GPR: General Purpose Register) of the register file 12.

  Further, the CPU 10 includes a control logic 14 and a save register 15. The control logic 14 detects a hardware interrupt and controls execution of an interrupt service routine (interrupt handler) by the instruction processing unit 11. The save register 15 holds values of control registers including a program counter (PC) 160, a program status word (PSW) register 161, and a key number (KN) register 162 that are saved when branching to an interrupt service routine. The key number (KN) register 162 indicates a decryption key number applied to the program code executed in the CPU 10.

  The interrupt controller 20 receives a plurality of interrupts (INT1, INT2,...) From one or a plurality of peripheral devices. When a plurality of interrupts are simultaneously generated, the interrupt controller 20 determines the priority order of the interrupts and requests an interrupt. A signal (INTR) and an interrupt factor number (INTNO) are output. INTR indicates the occurrence of an interrupt. The interrupt factor number (INTNO) is a number indicating the interrupt factor selected based on the priority order. In the example of FIG. 1, an interrupt request signal (INTR) is sent to the control logic 14 of the CPU 10, and an interrupt factor number (INTNO) is sent to an interrupt vector table (IVT: Interrupt Vector Table) 21.

  The interrupt vector table 21 shown in FIG. 1 defines a plurality of decryption key identifiers corresponding to a plurality of interrupt vectors. The interrupt vector table 21 receives the interrupt number signal (INTNO) from the interrupt controller 20, and receives the interrupt vector (INTV) and the decryption key number (KN) associated with the interrupt number indicated by the interrupt number signal (INTNO). Send to control logic 14. Here, the interrupt vector (INTV) may indicate a vector address, for example. The vector address is an ISR start address or an address where a branch instruction to the ISR is placed. The interrupt vector (INTV) may indicate an offset for obtaining a vector address or a vector number for obtaining a vector address. The key number (KN) is only an example of a key identifier for specifying a decryption key. That is, the interrupt vector table 21 may store another code different from the key number (KN) as the key identifier.

When receiving the interrupt request signal (INTR), the control logic 14 of the CPU 10 sends an interrupt acknowledge signal (INTA) to the interrupt controller 20. The control logic 14 receives the interrupt vector (INTV) and the decryption key number (KN) from the interrupt vector table 21, and generates an interrupt pseudo instruction (IPI). Then, the control logic 14 inputs the IPI to the instruction processing unit 11 (specifically, the instruction execution unit 112). The IPI is associated with an interrupt vector and a decryption key number. The IPI may include an immediate value indicating an interrupt vector and a decryption key number, or may indicate a register in which the interrupt vector and the decryption key number are stored. The IPI may include a plurality of instructions. For example, the IPI may include the following instructions:
-Rewrite instruction of save register 15;
An instruction that causes the decryption key 50 to be set in the decryption circuit 50 corresponding to the first decryption key identifier; and Instruction to cause.

  When the instruction execution unit 112 receives the IPI, the instruction execution unit 112 suspends the instruction being executed, and controls the control registers including the program counter (PC) 160, the program status word (PSW) register 161, and the key number (KN) register 162. The value is saved in the save register 15. Then, the instruction execution unit 112 sends the key setting request signal (KNREQ) and the key number (KN) indicated by the IPI to the decryption circuit 50. Further, the instruction execution unit 112 generates a fetch target address (FADS) from the interrupt vector indicated by the IPI. This address (FADS) indicates the start address of the ISR or the address where the branch instruction to the ISR is placed. The instruction execution unit 112 sets the generated address (FADS) in the PC 160 and sends the address (FADS) and the fetch request (FREQ) to the instruction fetch unit 110. The instruction fetch unit 110 sends a fetch request to the cache memory 30. As a result, the instruction processing unit 11 branches to the ISR and executes the ISR.

  The cache memory 30 reads an instruction from the memory 40 in line units (for example, 16 bytes or 32 bytes), and temporarily stores the read instruction. The cache memory 30 may cache data read from the memory 40. The cache memory 30 is, for example, an SRAM (Static Random Access Memory). The memory 40 is, for example, an SRAM (that is, a secondary cache), a DRAM (Dynamic Random Access Memory), a mask ROM, a programmable ROM, or a flash memory.

  In the present embodiment, at least a part (including one or a plurality of ISRs) of a plurality of program codes (instruction routines) executed in the instruction processing unit 11 is stored in the memory 40 in an encrypted state. Therefore, the configuration example of FIG. The decryption circuit 50 decrypts the encrypted program code read from the memory 40 and stores it in the cache memory 30. The decryption key used for decrypting the program code in the decryption circuit 50 is designated by the CPU 10. Specifically, the decryption circuit 50 includes a decoder 51 and a key storage unit 52. The key storage unit 52 stores a plurality of decryption keys (for example, KEY1, KEY2,...) Associated with different decryption key numbers (for example, KN1, KN2,...). The key storage unit 52 receives the key setting request signal (KNREQ) and the decryption key number (KN) from the CPU 10 (command processing unit 11), and sends the decryption key corresponding to the decryption key number designated by the CPU 10 to the decoder 51. Set.

  FIG. 2 shows a configuration example of the interrupt vector table 21. In the example of FIG. 2, an interrupt factor number (INTNO), an interrupt vector (INTV), and a decryption key number (KN) are stored in association with each other. The interrupt vector (INTV) in FIG. 2 indicates a vector number. For example, INTTV = 64 and KN = 1 are associated with the interrupt factor of INTNO = 0. INTTV = 65 and KN = 3 are associated with the interrupt factor of INTNO = 1. Further, INTTV = 66 and KN = 10 are associated with the interrupt factor of INTNO = 2.

  FIG. 3 is a flowchart showing an example of an execution method of the interrupt service routine in the CPU 10. In step S <b> 11, the control logic 14 receives an interrupt request signal (INTQ) from the interrupt controller 20. In step S12, the control logic 14 acquires the interrupt vector (INTV) and the decryption key number (KN) from the interrupt vector table 21 in response to the reception of the interrupt request signal (INTQ). As already described, this decryption key number (KN) specifies the decryption key to be used for decryption of the ISR specified by the interrupt vector (INTV). In step S13, the control logic 14 generates an interrupt pseudo instruction (IPI). The IPI is associated with an interrupt vector (INTV) and a decryption key number (KN). In step S14, the control logic 14 inputs the generated IPI into the instruction processing unit 11 (instruction execution unit 112).

  In step S15, the instruction execution unit 112 that has received the IPI interrupts the instruction being executed, and saves the context (PC160, PSW161, KN162) relating to the interrupted instruction in the save register 15. In step S <b> 16, the instruction execution unit 112 sets a decryption key applied to the decryption of the ISR in the decryption circuit 50. Specifically, as already described, the instruction execution unit 112 sends the key number (KN) and key setting request signal (KNREQ) indicated by the IPI to the decryption circuit 50.

  In step S17, the instruction processing unit 11 branches to the ISR and executes the ISR. The ISR instruction fetched from the cache memory 30 by the instruction fetch unit 110 is decoded by the decoding circuit 50. Therefore, the CPU 10 can execute the ISR stored in the memory 40 in an encrypted state.

  When the ISR process is completed, the CPU 10 returns to the interrupted instruction. In the configuration example of FIG. 1, the decryption key number applied to the interrupted instruction (interrupted program code) is saved in the save register 15 in addition to the PC and PSW of the interrupted instruction. Therefore, the CPU 10 returns the context including the decryption key number to the PC 160, the PSW register 161, and the KN register 162, and returns to the interrupted instruction. Thereby, the computer 1 can restart decoding of the interrupted program code in the decoding circuit 50, and can continue execution of the interrupted program code in the CPU 10.

  Subsequently, another configuration example of the computer 1 will be described below. FIG. 4 is a block diagram illustrating a second configuration example of the computer 1. In the configuration example of FIG. 4, the interrupt controller 200 manages a plurality of decryption key numbers corresponding to a plurality of interrupt factors (or a plurality of ISRs). Then, the interrupt controller 200 supplies an interrupt request (INTR) and a decryption key number (KN) to the control logic 14 when an interrupt occurs. For example, the interrupt controller 200 may include one or a plurality of registers that define a plurality of decryption key numbers corresponding to a plurality of interrupt factors. The interrupt vector table 210 shown in FIG. 4 may hold the interrupt number (INTNO) and the interrupt vector (INTV) in association with each other.

  FIG. 5 shows a configuration example of the interrupt controller 200. The interrupt controller 200 has a plurality of interrupt factor registers 201. Each interrupt factor register 201 stores the presence / absence of a corresponding interrupt (INT0, INT1, etc.), an interrupt priority (PRI), and a key number (KN). That is, in the configuration example of FIG. 5, each interrupt factor register 201 holds a set value of a key number corresponding to each interrupt factor. The factor selection circuit 202 detects an interrupt that has occurred with reference to the flag, and selects an interrupt factor to be notified to the CPU 10 based on the priority (PRI). Then, the factor selection circuit 202 outputs an interrupt request signal (INTR), an interrupt number (INTNO) and a key number (KN) corresponding to the selected interrupt factor.

<Second Embodiment>
In the present embodiment, a modification of the computer 1 according to the first embodiment will be described. FIG. 6 is a block diagram illustrating a configuration example of the computer 2 according to the present embodiment. The computer 2 according to the present embodiment has a comparison circuit 61 and a trace output circuit 62. The comparison circuit 61 is configured to compare the decryption key number applied to the decryption circuit 50 (decoder 51) for decryption of the encrypted program code with the decryption key number associated with the trace target program code. Has been. The trace output circuit 62 is configured to output trace data indicating the instruction execution status of the instruction processing unit 11 on condition that the two key numbers match in the comparison circuit 61. The decryption key number associated with the trace target program code is set in the trace key number register 60.

  The key number can be written to the register 60 from, for example, a debug tool (not shown). The debug tool may authenticate the user and set the decryption key number associated with the user in the trace key number register 60 on condition that the user has been successfully authenticated.

  FIG. 7 is a flowchart showing an example of a trace data output control method according to the present embodiment. In step S <b> 21, the computer 1 sets the authenticated decryption key number in the trace key number register 60. In steps S22 and S23, the comparison circuit 61 uses the key number (that is, the value of the KN register 162) of the decryption key used for decrypting the program code being executed as the authenticated key number (that is, for tracing It is determined whether or not these two key numbers match each other. If the two key numbers match (YES in step S23), the CPU 10 permits output of trace data from the trace output circuit 62 (step S24). On the other hand, if the two key numbers do not match (NO in step S23), the CPU 10 prohibits the output of trace data (step S25).

  A general CPU has a debugging function, and is configured to output trace data indicating instruction execution status and access data. If anyone can trace the execution status of the program code (for example, user program, interrupt service routine) stored in the memory 40 in an encrypted state, the tamper resistance of these program codes can be reduced. descend. The computer 2 of the present embodiment, on condition that the decryption key identifier (key number) applied to the program code being executed matches the decryption key identifier (key number) associated with the trace target program code, Allows output of trace data. Therefore, it is possible to prevent the tamper resistance of the program code stored in the memory 40 from being encrypted.

  In the present embodiment, the comparison circuit 61 may be configured not to compare the decryption key identifier (for example, key number) but to compare the decryption keys themselves. That is, the comparison circuit 61 may compare the decryption key applied to the decryption circuit 50 (decoder 51) with the decryption key used for decrypting the program code to be traced. The trace output circuit 62 may output trace data indicating the instruction execution status of the instruction processing unit 11 on condition that the two decryption keys match in the comparison circuit 61.

<Other embodiments>
The configuration examples of the computers 1 and 2 shown in FIGS. 1, 4, and 6 are merely examples. For example, in some architectures, control logic 14 that generates interrupt pseudo-instructions may be located in interrupt controller 20.

  In other architectures, the control logic 14 or the interrupt controller 20 (200) may include a logic circuit that generates an interrupt vector based on an interrupt signal. That is, the interrupt vector table 21 (210) may not explicitly exist. In this case, the CPU 10 or the interrupt controller 20 (200) only needs to have a registry (for example, a register or a table on the ROM) that defines a plurality of decryption key identifiers corresponding to a plurality of interrupt factors.

  Furthermore, the above-described embodiment is merely an example relating to application of the technical idea obtained by the present inventors. That is, the technical idea is not limited to the above-described embodiment, and various changes can be made.

  For example, the technical idea obtained by the present inventors includes Embodiments A1 to A7 and B1 to B7 described below.

(Embodiment A1)
CPU (Central Processing Unit) that decodes and executes instructions,
An interrupt controller that supplies a first decryption key identifier to the CPU in response to the occurrence of a first interrupt; and an encrypted first interrupt service that receives the first decryption key identifier from the CPU and is encrypted A decryption circuit for decrypting a routine using a decryption key corresponding to the first decryption key identifier;
A computer comprising:
(Embodiment A2)
The computer according to embodiment A1, wherein the interrupt controller includes one or more registers that define a plurality of decryption key identifiers corresponding to a plurality of interrupt factors.
(Embodiment A3)
The CPU
An instruction processing unit for decoding and executing instructions;
A control unit for controlling the instruction processing unit to branch to the first interrupt service routine in response to an interrupt request from the interrupt controller based on the first interrupt;
A computer as described in embodiment A1 or A2.
(Embodiment A4)
The computer of embodiment A3, wherein the control of the instruction processing unit by the control unit includes throwing an interrupt pseudo-instruction to branch to the first interrupt service routine to the instruction processing unit.
(Embodiment A5)
The computer of embodiment A4, wherein the interrupt pseudo-instruction is associated with the first decryption key identifier.
(Embodiment A6)
In the embodiment A4, the instruction processing unit supplies the signal indicating the first decryption key identifier to the decryption circuit by executing the interrupt pseudo-instruction, and branches to the first interrupt service routine. The listed computer.
(Embodiment A7)
The computer according to embodiment A1 or A2, wherein the instruction processing unit executes the first interrupt service routine decoded by the decoding circuit.

(Embodiment B1)
CPU (Central Processing Unit) that decodes and executes instructions,
Defining a plurality of decryption key identifiers corresponding to a plurality of interrupt factors, and supplying a first decryption key identifier corresponding to the first interrupt to the CPU when a first interrupt occurs; and A decryption circuit for receiving a first decryption key identifier and decrypting the encrypted first interrupt service routine using a decryption key corresponding to the first decryption key identifier;
A computer comprising:
(Embodiment B2)
The computer of embodiment B2 wherein the registry is an interrupt vector table.
(Embodiment B3)
The CPU
An instruction processing unit for decoding and executing instructions;
A control unit that controls the instruction processing unit to branch to the first interrupt service routine when the first interrupt occurs;
A computer as described in embodiment B1 or B2.
(Embodiment B4)
The computer of embodiment B3, wherein the control of the instruction processing unit by the control unit includes pitching an interrupt pseudo-instruction for branching to the first interrupt service routine to the instruction processing unit.
(Embodiment B5)
The computer of embodiment B4, wherein the interrupt pseudo-instruction is associated with the first decryption key identifier.
(Embodiment B6)
The instruction processing unit supplies the signal indicating the first decryption key identifier to the decryption circuit by executing the interrupt pseudo-instruction, and branches to the first interrupt service routine. Embodiment B4 The listed computer.
(Embodiment B7)
The computer according to embodiment B1 or B2, wherein the instruction processing unit executes the first interrupt service routine decoded by the decoding circuit.

1, 2 Computer 10 CPU (Central Processing Unit)
11 Instruction processing unit 20, 200 Interrupt controller 21, 210 Interrupt vector table 30 Cache memory 40 Memory 50 Decoding circuit 60 Trace key number register 61 Comparison circuit 62 Trace output circuit 201 Interrupt factor register ISR Interrupt service routine IPI Interrupt pseudo instruction KN key number

Claims (20)

An instruction processing unit for decoding and executing instructions;
In response to the occurrence of the first interrupt, a control unit that inputs an interrupt pseudo-instruction for branching to the first interrupt service routine to the instruction processing unit, and the interrupt pseudo-instruction corresponds to the first interrupt corresponding to the first interrupt. A decryption key that is associated with the first decryption key identifier and that corresponds to the first decryption key identifier based on execution of the interrupt pseudo-instruction in the instruction processing unit; A decryption circuit for decrypting an interrupt service routine using the decryption key;
A computer comprising:   The instruction processing unit supplies the signal indicating the first decryption key identifier to the decryption circuit by executing the interrupt pseudo-instruction, and branches to the first interrupt service routine. The listed computer. A registry that defines a plurality of decryption key identifiers corresponding to a plurality of interrupt factors;
The control unit obtains the first decryption key identifier corresponding to the first interrupt from the registry;
The computer according to claim 1 or 2. An interrupt vector table that defines a plurality of decryption key identifiers corresponding to a plurality of interrupt vectors;
The interrupt vector table supplies a first interrupt vector corresponding to the first interrupt and the first decryption key identifier to the control unit when the first interrupt occurs.
The computer according to claim 1 or 2. The first interrupt vector indicates a vector address, an offset for obtaining the vector address, or a vector number for obtaining the vector address,
The computer according to claim 4, wherein the vector address is a start address of the first interrupt service routine or an address of a branch instruction to the first interrupt service routine.   The computer according to claim 1, further comprising an interrupt controller that supplies an interrupt request and the first decryption key identifier to the control unit when the first interrupt occurs.   The computer according to claim 6, wherein the interrupt controller includes one or more registers that define a plurality of decryption key identifiers corresponding to a plurality of interrupt factors.   The computer according to claim 1, wherein the interrupt pseudo-instruction is further associated with a first interrupt vector corresponding to the first interrupt.   The computer according to claim 1, wherein the interrupt pseudo-instruction includes an instruction that causes a decryption key corresponding to the first decryption key identifier to be set in the decryption circuit.   The computer according to claim 1, wherein the interrupt pseudo instruction includes an instruction that causes a jump to a start address of the first interrupt service routine or an address of a branch instruction to the first interrupt service routine. The instruction processing unit is configured to save a context relating to a program code executed by the instruction processing unit in response to the occurrence of the first interrupt,
The computer according to claim 1, wherein the context includes a second decryption key identifier applied to decrypt the program code. A third decryption key identifier applied to the decryption circuit for decrypting the encrypted program code or a decryption key corresponding to the third decryption key identifier is associated with the program code to be traced. A comparison circuit for comparing with a decryption key identifier of 4 or a decryption key corresponding to the fourth decryption key identifier;
The instruction process on condition that the third decryption key identifier and the fourth decryption key identifier match or the decryption keys associated with the third and fourth decryption key identifiers match. An output circuit that outputs trace data indicating the instruction execution status of the unit;
Further comprising
The computer according to claim 1 or 2.   The computer according to claim 1, wherein the decryption circuit includes a key storage unit that stores a plurality of decryption keys associated with different decryption key identifiers.   The cache memory according to claim 1, further comprising a cache memory that temporarily stores the first interrupt service routine decoded by the decoding circuit and supplies the first interrupt service routine to the instruction processing unit. Computer. A method of executing an interrupt service routine in a computer,
In response to the occurrence of the first interrupt, an interrupt pseudo instruction for branching to the first interrupt service routine is input from the control unit to the instruction processing unit,
The interrupt pseudo-instruction includes an instruction that causes the decryption key corresponding to the first decryption key identifier to be set in the decryption circuit.
Method.   The method according to claim 1 or 2, wherein the interrupt pseudo-instruction includes an instruction that causes a jump to a start address of the first interrupt service routine or an address of a branch instruction to the first interrupt service routine.   16. The method according to claim 15, further comprising: supplying a first interrupt vector corresponding to the first interrupt and the first decryption key identifier from the interrupt vector table to the control unit when the first interrupt occurs. 16. The method according to 16.   The method according to claim 15 or 16, further comprising supplying an interrupt request and the first decryption key identifier from an interrupt controller to the control unit when the first interrupt occurs. Evacuating a context related to the program code executed by the instruction processing unit in response to the occurrence of the first interrupt;
The context includes a second decryption key identifier applied to decrypt the program code,
The method according to claim 15 or 16. Setting a decryption key corresponding to the first decryption key identifier in a decryption circuit based on execution of the interrupt pseudo-instruction in the instruction processing unit;
Branching to the first interrupt service routine based on execution of the interrupt pseudo-instruction in the instruction processing unit;
Decrypting the encrypted first interrupt service routine in the decryption circuit using the decryption key; and executing the first interrupt service routine in the instruction processing unit;
The method according to claim 15 or 16, further comprising:

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