JP2014119779A - Semiconductor device and debugging control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restore a debugging invalid mode after the end of debugging only by removing a debugging device in a semiconductor device that has an on-chip debugging function.SOLUTION: An MCU 100 includes: a debugging terminal 102 that is connected with an external debugging device 300; and a terminal monitor unit 110 that monitors a change of a signal level in the debugging terminal 102 during the execution of debugging by the debugging device 300. If the signal level has not changed for a predetermined period of time, the MCU causes transition from a first mode for executing debugging to a second mode for performing a normal operation.

Description

  The present invention relates to a semiconductor device and a debug control method thereof, for example, a semiconductor device having an on-chip debug function and a debug control method thereof.

  2. Description of the Related Art In recent years, microcomputers that are a type of semiconductor device have an on-chip debug function that has a built-in debug function in the microcomputer due to the complexity of functions and improvement in performance. For this reason, many microcomputers having a built-in debugging function are also used in microcomputers having a small scale and few pins. For example, there is a microcomputer that employs a one-wire debugging protocol. In particular, after a microcomputer is mounted on a system, a debugging apparatus (such as an emulator) is connected for system maintenance, field test, etc., and the debugging and testing are increasing.

  Here, in-vehicle devices are evaluated and adjusted in a state of being mounted on an ECU (Electronic Control Unit) installed in a narrow space. Therefore, there is an increasing demand for connection to a microcomputer with a small number of interface signals. In addition, some of the circuits and functions designed by customers operate separately from the CPU. Therefore, it is required to realize the operation after power-on when the debugging device is removed after debugging.

  Patent Document 1 discloses a technique related to a debug mode determination method for determining a debug mode using a power-on reset. As the debug mode, a debug valid mode that allows MCU debugging and a debug invalid mode that does not allow debugging are used. The power-on reset circuit in the MCU according to Patent Document 1 outputs a reset signal (hereinafter referred to as a “power-on reset signal”) when the power is turned on and / or when it is detected that the power supply voltage has dropped below an allowable value. To do. The MCU according to Patent Document 1 latches the input signal level of the debug terminal during the period when the power-on reset signal is generated, and determines the mode selected based on the latched signal level. After the mode is determined, in the debug invalid mode, the user program is executed after resetting the MCU. On the other hand, in the debug valid mode, the debug dedicated program (or monitor program) is executed after resetting the MCU.

JP 2009-99054 A

  However, the technique according to Patent Document 1 has a problem that it is difficult to return to the debug invalid mode after the end of debugging simply by removing the debugging device. The reason is that the technology according to Patent Document 1 can determine the connection state of the external debug device when the power is turned on, but even if the external debug device is removed after the debugging is finished, the debug terminal is low level or high impedance (disconnected). This is because it is not possible to detect that it is not connected.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device is configured to execute debugging when there is no change in signal level at the debug terminal during a debug execution by an external debug device connected to the debug terminal. A transition is made from the first mode to the second mode for normal operation.

  According to the embodiment, in a semiconductor device having an on-chip debugging function, debugging can be realized with a simple operation.

1 is a block diagram showing a configuration of a microcomputer according to a first embodiment. It is a block diagram which shows the structure of the terminal monitor part concerning this Embodiment 1. FIG. FIG. 3 is a block diagram showing a configuration of a reset mask control unit according to the first embodiment. 3 is a flowchart showing a flow of operations of the microcomputer according to the first embodiment. 3 is a flowchart showing a flow of debug control according to the first embodiment. 6 is a timing chart in debug control according to the first embodiment. It is a block diagram which shows the structure of the microcomputer concerning this Embodiment 2. It is a block diagram which shows the structure of the reset mask control part concerning this Embodiment 2. FIG.

  Hereinafter, specific embodiments to which means for solving the above-described problems are applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
First, the above-described problems will be described in detail. In the debug mode determination method according to Patent Literature 1, the debug mode is determined by determining the connection state of the external debug device immediately after the MCU power is turned on. During debugging, reset to the CPU is masked so as not to affect the debugging environment. Further, the software reset in Patent Document 1 cannot perform terminal reset. Therefore, a separate terminal reset is required to return to the debug invalid mode. If the debug valid mode is not canceled by setting the reset state in this way, the CPU may run away. Also, in-vehicle devices and the like, it is often not recommended to provide a debug-dedicated reset terminal because it may become a noise source. Therefore, in such an environment, a power-on reset by power OFF / ON must be performed.

  Therefore, in order to debug an MCU mounted on an in-vehicle device or the like and then return to the debug invalid mode, the following operation is required in Patent Document 1. First, an external debugging device is connected to the MCU while the MCU is turned off. Next, the MCU is powered on. At this point, since the external debug device is connected, the MCU transits to the debug valid mode. Subsequently, debugging is executed by the external debugging device on the MCU.

  Then, after the execution of debugging is finished, the external debugging device is removed. However, at this time, the MCU cannot determine whether or not the external debug device is connected. The reason is that the MCU and the external debugging device are connected by one line (one-wire debugging protocol), so the debugging terminal becomes low level or high impedance (disconnected state), and it cannot be detected that it is not connected. Because. Therefore, the power is turned OFF / ON by removing the MCU battery. As a result, when the MCU is subsequently activated, it is determined that the external debug device is not connected, and a transition to the debug invalid mode can be made.

  Here, an MCU mounted on an ECU such as an in-vehicle device cannot easily perform an operation such as removing a battery. For this reason, it is not possible to perform simple debugging such as connecting an external debugging device for MCU inspection or the like and switching to the debug invalid mode by removing it after debugging. For this reason, it is difficult to apply an MCU that does not have a debug-dedicated reset terminal in an environment where power supply OF / ON cannot be easily performed.

  Therefore, the semiconductor device according to the first embodiment includes a debug terminal connected to an external debug device, a terminal monitor unit that monitors a change in signal level at the debug terminal during debug execution by the debug device, Is provided. The semiconductor device transitions from the first mode for executing debugging to the second mode for performing normal operation when the signal level does not change for a predetermined time or more. Thus, the absence of a change in the signal level at the debug terminal for a predetermined time or more means that debugging is not being executed or the debug device is not connected. Therefore, it can be detected that the debugging device has been removed, and debugging can be realized with a simple operation in a semiconductor device having an on-chip debugging function.

  The debug terminal is preferably connected to the debug device by at least one signal group. In this case, the terminal monitor unit measures a signal maintenance time which is a time during which at least a part of the signal level in the signal group is maintained at a specific level, and whether or not the signal maintenance time is equal to or longer than a predetermined time. Determine whether. Then, when it is determined that the signal maintenance time is equal to or longer than the predetermined time, the semiconductor device does not change the signal level for the predetermined time or longer. In this way, by measuring the signal level maintaining time with the debug device, it is possible to measure the equivalent of the access time, and more reliably detect the removal of the debug device.

  Further, the semiconductor device causes a transition to the first mode when the signal level at the debug terminal changes from the specific level to a level other than the specific level in the second mode, and a reset signal input from the outside Mask. The terminal monitor unit starts monitoring a change in signal level at the debug terminal after the debug execution by the debug device is started. Thereafter, when the terminal monitoring unit determines that the signal maintenance time is equal to or longer than a predetermined time, the semiconductor device cancels the masking of the reset signal and makes a transition to the second mode. Thereby, the reset timing can be controlled flexibly.

  In addition, the terminal monitor unit measures a level detection circuit that detects that at least a part of signal levels in the signal group is the specific level, and measures the signal maintenance time, and the signal maintenance time is equal to or longer than a predetermined time. It is desirable to provide a timer unit for determining whether or not. In this case, the timer unit includes setting means for setting the predetermined time, a measuring instrument for measuring a maintenance time of the signal level detected by the level detection circuit, the measured maintenance time, and the set predetermined time. A comparator that compares the time and outputs a comparison result. Thereby, it is possible to more appropriately monitor the access state.

  Further, the semiconductor device shifts to the first mode when the debug device is connected, masks a reset signal input from the outside, and resets the signal when the signal level does not change for a predetermined time or more. It can be said that the signal mask is canceled and the mode is changed to the second mode. Thereby, the reset timing can be controlled flexibly.

  Here, the semiconductor device according to the first embodiment can also be expressed as follows. That is, the semiconductor device according to the first embodiment is a debug terminal connected to an external debug device, and a time during which a specific signal level at the debug terminal is maintained during debug execution by the debug device. A terminal monitor unit for measuring a signal maintenance time, and a mode control for transitioning from a first mode for executing debugging to a second mode for performing normal operation when the signal maintenance time is maintained for a predetermined time or more. A section. Thus, maintaining the signal maintenance time for a predetermined time or more means that debugging is not being executed or the debugging device is not connected. Therefore, it can be detected that the debugging device has been removed, and debugging can be realized with a simple operation in a semiconductor device having an on-chip debugging function.

  The mode control unit masks a reset signal input from the outside in the first mode, and cancels the masking of the reset signal when the signal maintaining time is maintained for a predetermined time or more. It is desirable to do. This eliminates an external reset request during debugging and enables stable debugging.

  Further, the mode control unit enables a reset mask signal for masking the reset signal in the first mode, and outputs the reset mask signal when the signal maintaining time is maintained for a predetermined time or more. A reset mask control unit to be invalidated, and a reset control unit that inputs the reset signal and the reset mask signal and outputs a reset signal after masking may be provided. Thereby, the external reset signal can be easily controlled by the reset mask signal.

  Furthermore, the terminal monitor unit may determine whether or not the signal maintenance time is maintained for a predetermined time or more, and output a terminal monitor signal to the reset mask control unit according to the determination result. The reset mask control unit may invalidate the reset mask signal when the terminal monitor signal indicates that the signal maintenance time is maintained for a predetermined time or more. Thus, the reset mask signal can be controlled more appropriately by the terminal monitor signal.

  Further, the reset mask control unit inputs a signal from the debug terminal and a power-on reset signal, and outputs a high level signal when the signal from the debug terminal changes after debug execution, And a logical product circuit that outputs a logical product of the terminal monitor signal and the output signal from the latch circuit as the reset mask signal to the reset control unit. As a result, the reset mask signal can be controlled more appropriately.

  In addition, the debug terminal is connected to the debug device by at least one signal group, and the terminal monitor unit is a time during which at least a part of the signal level in the signal group is maintained at a specific level. It is desirable to measure a signal maintenance time, determine whether the signal maintenance time is equal to or longer than a predetermined time, and output a terminal monitor signal to the mode control unit according to the determination result. In this way, by measuring the signal level maintaining time with the debug device, it is possible to measure the equivalent of the access time, and more reliably detect the removal of the debug device.

  The semiconductor device debug control method according to the first embodiment can be expressed as follows. That is, this is a debug control method for a semiconductor device having a debug terminal connected to an external debug device. At this time, the semiconductor device monitors a change in the signal level at the debug terminal during debugging by the debug device, and executes a debug when the change in the signal level does not exceed a predetermined time. Transition from the mode to the second mode for normal operation is performed. Thus, the absence of a change in the signal level at the debug terminal for a predetermined time or more means that debugging is not being executed or the debug device is not connected. Therefore, it can be detected that the debugging device has been removed, and debugging can be realized with a simple operation in a semiconductor device having an on-chip debugging function.

  The debug terminal is connected to the debug device by at least one signal group, and the semiconductor device is a signal at which at least a part of the signal level in the signal group is maintained at a specific level. When the maintenance time is measured, it is determined whether or not the signal maintenance time is equal to or longer than a predetermined time, and when it is determined that the signal maintenance time is equal to or longer than the predetermined time, the change in the signal level does not exceed the predetermined time Is desirable. In this way, by measuring the signal level maintaining time with the debug device, it is possible to measure the equivalent of the access time, and more reliably detect the removal of the debug device.

  Furthermore, when the signal level at the debug terminal changes from the specific level to a level other than the specific level in the second mode, the semiconductor device makes a transition to the first mode and is input from the outside. After the start of debug execution by the debug device, the monitoring of the signal level change at the debug terminal is started, and when the signal maintenance time is determined to be a predetermined time or more, the reset signal mask is released. And it is good to make a transition to the second mode. Thereby, the reset timing can be controlled flexibly.

  Hereinafter, a microcomputer (MCU) with an on-chip debug function which is an example of the semiconductor device according to the first embodiment will be described. FIG. 1 is a block diagram showing a configuration of the MCU 100 according to the first embodiment.

  First, as a premise, a debugging system for a single-chip MCU targeted in the present embodiment includes an MCU 100, an external debugging device 300, and debugger software (not shown) that operates on a host computer (not shown). Shall be. The MCU 100 is mounted on a substrate of a semiconductor integrated circuit. Further, an external reset control circuit 200 is mounted on the substrate depending on the system configuration. The MCU 100 is connected to the external reset control circuit 200 via the reset terminal 101. The MCU 100 is connected to the external debug device 300 via the debug terminal 102. Therefore, the MCU 100 is connected to the host computer via the external debug device 300.

  The external debug device 300 connects a pull-up circuit 301 to the debug terminal 102 of the MCU 100 mounted on the board. The external debug device 300 performs various debugging processes on the MCU 100 by executing a debug program or the like outside the MCU 100. The external reset control circuit 200 is connected to the reset terminal 101 of the MCU 100 mounted on the substrate. The external reset control circuit 200 corresponds to, for example, a reset IC outside the MCU 100 or another ECU.

  The MCU 100 includes a reset terminal 101, a debug terminal 102, a terminal monitor unit 110, a mode control unit 120, a CPU 130, a power-on reset unit 140, and an N-channel open drain buffer 150. The reset terminal 101 is connected to the external reset control circuit 200. The debug terminal 102 is connected to the external debug device 300. The debug terminal 102 is connected to the debug device by at least one signal group.

  The terminal monitor unit 110 inputs the debug signal 205 from the external debug device 300 via the debug terminal 102 and outputs the terminal monitor signal 206 to the debug control unit 122. In addition, the terminal monitor unit 110 monitors the debug terminal 102. Specifically, the terminal monitor unit 110 monitors a change in signal level at the debug terminal 102 during execution of debugging by the external debug device 300. More specifically, the terminal monitor unit 110 measures a signal maintenance time that is a time during which a specific signal level at the debug terminal 102 is maintained during execution of debugging by the external debug device 300. Then, the terminal monitor unit 110 determines whether or not the signal maintenance time is equal to or longer than a predetermined time. That is, the terminal monitor unit 110 detects that the signal level has not changed for a predetermined time. Alternatively, the terminal monitor unit 110 detects that the signal maintenance time is a predetermined time or more. Here, if the terminal monitoring unit 110 determines that the signal maintenance time is equal to or longer than the predetermined time, it can be said that the signal level does not change more than the predetermined time. The terminal monitor unit 110 outputs a terminal monitor signal 206 to the reset mask control unit 123 described later according to the determination result.

  Further, the terminal monitor unit 110 has at least a timer unit 111. The timer unit 111 measures the high level period of the debug terminal 102. That is, the timer unit 111 measures a signal maintenance time that is a time during which a specific signal level is maintained, and determines whether or not the signal maintenance time is equal to or longer than a predetermined time.

  Here, the debug mode control function of the mode control unit 120 determines a mode that permits debugging of the MCU 1 (debug enabled mode) or a mode that does not allow debugging (debug disabled mode), and causes the MCU 100 to transition to the determined mode. Here, the debug valid mode is an example of a first mode for executing debugging, and the debug invalid mode is an example of a second mode for performing normal operation.

  The mode control unit 120 changes the mode of the MCU 100 from the first mode to the second mode when there is no change in the signal level for a predetermined time or more. That is, the mode control unit 120 changes the mode of the MCU 100 from the first mode to the second mode when the signal maintenance time is maintained for a predetermined time or more.

  The mode control unit 120 includes at least a reset mask circuit 121 and a debug control unit 122. The debug control unit 122 validates the reset mask signal 202 for masking the reset signal 201 in the first mode, and invalidates the reset mask signal 202 when the signal maintenance time is maintained for a predetermined time or more. . The reset mask circuit 121 is an example of a reset control unit that inputs the reset signal 201 and the reset mask signal 202 and outputs the reset signal 203 after the reset mask. The reset mask circuit 121 can be realized by an OR circuit, for example.

  Here, the debug control unit 122 monitors and controls various operations and states of the CPU 130 during debugging. The debug control unit 122 is connected to the debug terminal 102 via the N channel open drain buffer 150. The debug control unit 122 includes at least a reset mask control unit 123. The reset mask control unit 123 receives the terminal monitor signal 206 from the terminal monitor unit 110, and outputs a reset mask signal 202 to the reset mask circuit 121 based on the terminal monitor signal 206. Specifically, the reset mask control unit 123 invalidates the reset mask signal 202 when the terminal monitor signal 206 indicates that the signal maintenance time is maintained for a predetermined time or more.

  The reset mask circuit 121 masks the reset signal 201 during debugging. That is, the reset mask circuit 121 receives the reset signal 201 from the reset terminal 101 and the reset mask signal 202 from the debug control unit 122, and outputs the logical sum result as the reset signal 203 after the reset mask.

  The CPU 130 controls the MCU 100. The CPU 130 inputs the power-on reset signal 204 from the power-on reset unit 140 and the reset signal 203 after reset mask from the reset mask circuit 121, respectively. The power-on reset unit 140 detects the state when the power of the MCU 100 is turned on or the source voltage falls below an allowable value, and resets the MCU 100. The power-on reset unit 140 receives the power supply voltage VDD and outputs a power-on reset signal 204 to the CPU 130 and the debug control unit 122.

  The N-channel open drain buffer 150 sets the debug terminal 102 to high impedance when a high level is output from the debug control unit 122. The N-channel open drain buffer 150 receives a high-level or low-level debug signal 207 from the debug control unit 122 and sets the debug terminal 102 to high impedance, or outputs the low-level debug signal 205 to the external debug device 300. Further, the N-channel open drain buffer 150 receives a debug signal 205 of high impedance or low level from the debug terminal 102 and outputs the debug signal 207 to the debug control unit 122.

  When the signal level at the debug terminal 102 changes from the high level to the low level in the second mode, the mode control unit 120 shifts to the first mode and masks the reset signal 201 input from the outside. Then, the terminal monitor unit 110 starts monitoring the change in the signal level at the debug terminal 102 after the debug execution by the external reset control circuit 200 is started. Thereafter, when the terminal monitoring unit 110 determines that the signal maintenance time is equal to or longer than the predetermined time, the mode control unit 120 cancels the masking of the reset signal 201 and makes a transition to the second mode.

  Alternatively, the mode control unit 120 shifts to the first mode when the external debug device 300 is connected, masks the reset signal 201 input from the outside, and resets when the signal level does not change for a predetermined time or more. It can be said that the mask of the signal 201 is canceled and the mode is changed to the second mode.

  FIG. 2 is a block diagram illustrating a configuration of the terminal monitor unit 110 according to the first embodiment. The terminal monitor unit 110 includes a level detection circuit 112 and a timer unit 111. The level detection circuit 112 detects that at least a part of signal levels in the signal group is a specific level. That is, the level detection circuit 112 receives the debug signal 205 from the debug terminal 102, detects the signal level, and outputs the signal level to the measuring instrument 114 that measures the high level period of the debug terminal 102. The timer unit 111 measures the signal maintenance time and determines whether or not the signal maintenance time is equal to or longer than a predetermined time. The timer unit 111 includes a register 113, a measuring instrument 114, and a comparator 115. Here, it can be said that the timer unit 111 includes a function of a setting unit that sets a predetermined time, which is a threshold value of the measured signal maintenance time, in the register 113. Therefore, an arbitrary release time of the reset mask signal 202 is set in the register 113. The measuring instrument 114 measures the signal maintenance time of the signal level detected by the level detection circuit 112. That is, the measuring instrument 114 receives the level detection signal from the level detection circuit 112 and outputs the measurement result to the comparator 115. The comparator 115 compares the measured maintenance time with the set predetermined time and outputs the comparison result as a terminal monitor signal 206. That is, the comparator 115 inputs the reset mask signal 202 release time and the time measured by the measuring instrument 114 from the register 113, and outputs the comparison result to the reset mask control unit 123.

  FIG. 3 is a block diagram illustrating a configuration of the reset mask control unit 123 according to the first embodiment. The reset mask control unit 123 includes a latch circuit 124 and an AND circuit 125. The latch circuit 124 receives the debug signal 207 and the power-on reset signal 204 from the debug terminal 102, and outputs a high level signal when the debug signal 207 from the debug terminal 102 changes after execution of debugging. Here, when the debug signal 207 changes to the low level even once after the start of debugging, the latch circuit 124 outputs a high level signal until the power-on reset signal 204 is turned on. The logical product circuit 125 outputs the logical product of the terminal monitor signal 206 and the output signal from the latch circuit 124 as a reset mask signal 202 to the reset mask circuit 121 which is a reset control unit. Here, the terminal monitor signal 206 is at a low level when the signal maintenance time is maintained for a predetermined time or more. The reset mask signal 202 is made valid when the reset signal 201 is at a high level, and is unmasked when the reset signal is at a low level.

  FIG. 4 is a flowchart showing an operation flow of the MCU 100 according to the first embodiment. First, the system to be debugged including the MCU 100 is turned on (step S101). Next, in the MCU 100, after the power is turned on, the reset terminal 101 becomes low level (step S102). Thereby, MCU100 will be in a reset state. Subsequently, in the MCU 100, the reset terminal 101 becomes high level (step S103). Thereby, the MCU 100 is released from the reset state and transitions to the debug invalid mode.

  Here, the MCU 100 determines whether or not the external debugging device 300 is connected (step S104). At this time, the terminal monitor unit 110 may determine whether or not the external debug device 300 is connected based on the level of the debug signal 205 from the debug terminal 102. If the external debug device 300 is connected, the process proceeds to step S105. If the external debug device 300 is not connected, the process proceeds to step S107.

  In step S104, when the external debug device 300 is not connected, the debug signal 205 is at a high level (step S107). At this time, the MCU 100 continues the debug invalid mode. Then, the CPU 130 executes the user program in the debug invalid mode (step S108). Thereafter, the CPU 130 determines whether or not a reset by the reset signal 203 after the reset mask has occurred (step S109). If a reset has occurred, the process proceeds to step S104.

  In step S104, when the external debug device 300 is connected, the debug signal 205 is at a low level (step S105). At this time, the MCU 100 transitions to the debug valid mode. Then, the MCU 100 executes a debug control process (step S106).

  FIG. 5 is a flowchart showing a flow of debug control according to the first embodiment. First, the terminal monitor unit 110 sets the reset mask signal release time TW2 in the register 113 (step S201). The reset mask signal release time TW2 is a threshold for determining that the communication with the external debug device 300 has ended, and is an arbitrary time.

  Next, the MCU 100 masks the reset signal 201 that is an input to the reset terminal 101 in the debug valid mode. That is, the debug control unit 122 sets, that is, validates the reset mask signal 202 (step S202). Then, the CPU 130 executes a debug dedicated program (monitor program) executed in the debug control unit 122 in the debug valid mode (step S203).

  Here, the timer unit 111 starts a timer (step S204). Then, the terminal monitor unit 110 monitors the debug terminal 102 (step S205). That is, the level detection circuit 112 outputs a signal indicating whether or not the signal level of the debug signal 205 from the debug terminal 102 is high to the measuring instrument 114. The measuring instrument 114 measures the signal maintaining time TW1 while the signal level of the debug signal 205 is high. When the level of the debug signal 205 changes from the high level to the low level, the measuring instrument 114 ends the measurement of the signal maintaining time TW1. Then, the comparator 115 determines whether or not the measured signal maintenance time TW1 is equal to or longer than the reset mask signal release time TW2 set in the register 113 (step S206). That is, it is determined whether or not the signal maintenance time TW1, which is the time elapsed from when the debug signal 205 changes to high level until it changes to low level, is equal to or longer than the reset mask signal release time TW2.

  Here, when the timer has elapsed from the start time to the reset mask signal release time TW2, the timer stops measurement by the measuring instrument 114 and causes the comparator 115 to perform comparison. Therefore, if the signal maintaining time TW1 is equal to or longer than the reset mask signal canceling time TW2, before the measuring instrument 114 finishes measuring the signal maintaining time TW1, the comparator 115 causes the signal maintaining time TW1 to be equal to or longer than the reset mask signal canceling time TW2. It is determined that That is, the terminal monitor unit 110 determines that the communication with the external debug device 300 is completed when the high level signal continues from the external debug device 300 to the MCU 100 for the reset mask signal release time TW2 (step S206). YES)

  In other words, the terminal monitor unit 110 determines whether or not a low level has been detected before the signal maintenance time TW1, which is the high level period of the debug terminal 102, has passed the reset mask signal release time TW2. If it is determined that the signal maintenance time TW1 is equal to or longer than the reset mask signal release time TW2 (TW1> = TW2), the process proceeds to step S208. On the other hand, when it is determined that the signal maintenance time TW1 is less than the reset mask signal release time TW2 (TW1 <TW2), the process proceeds to step S207.

  Here, if it is determined that the signal maintenance time TW1 is less than the reset mask signal release time TW2 (TW1 <TW2), the terminal monitoring unit 110 determines that debugging is being executed, and clears the signal maintenance time TW1 and the timer. (Step S207). Then, the process proceeds to step S204.

  Since the debug terminal 102 is used by connecting the N-channel open drain buffer 150 and the pull-up circuit 301, the debug terminal 102 continues to be in a high level state when communication with the external debug device 300 is completed. In this case, it is determined that the signal maintenance time TW1 is equal to or longer than the reset mask signal release time TW2 (TW1> = TW2). Then, the timer unit 111 stops the timer (step S208). Subsequently, the debug control unit 122 cancels the reset mask signal 211 based on the terminal monitor signal 206 (step S209), and outputs the reset signal 201 from the reset terminal 101 as it is to the CPU 130 as it is. That is, thereafter, when a valid reset signal 201 is input from the external reset control circuit 200, the MCU 100 can reset the inside.

  Thereafter, the CPU 130 determines whether or not a reset by the reset signal 203 after the reset mask has occurred (step S109). If a reset has occurred, the process proceeds to step S104.

  FIG. 6 is a timing chart in debug control according to the first embodiment. At time T0, the MCU 100 is powered on (step S101). In the period from time T0 to T1, the input of the reset terminal 101 of the MCU 100 is at a low level, and the MCU 100 is in a reset state (step S102). At time T1, the input to the reset terminal 101 of the MCU 100 changes from low level to high level (step S103). Accordingly, the reset is released, and the MCU 100 shifts to the debug invalid mode. And MCU100 continues debug invalid mode in the area of time T1-T2.

  It is assumed that the external debug device 300 is connected to the debug terminal 102 at time T2. At this time, the debug terminal 102 becomes low level (step S105), and the MCU 100 shifts to the debug valid mode. When the external debug device 300 is not connected, the debug terminal 102 is at the high level, and the debug invalid mode of the MCU 100 continues.

  In the section from time T2 to T5, the MCU 100 continues the debug valid mode. In the period from time T2 to T3, the terminal monitor unit 110 sets the reset mask signal release time TW2 in the register 113 (step S201). Then, the reset mask control unit 123 changes the reset mask signal 202 from low level to high level (step S202). Along with this, the reset signal 203 after reset masking in which the reset signal 201 from the reset terminal 101 is masked is output, and the subsequent reset to the CPU 130 is masked. That is, since the reset mask signal 202 is at a high level, even if a low level is input to the reset terminal 101, the reset mask circuit 121 always outputs the reset signal 203 after the reset mask as a high level, and the MCU 100 does not enter a reset state. .

  Here, the CPU 130 executes a debug-dedicated program (step S203). Thereafter, the debug terminal 102 repeats the change between the low level and the high level due to the access to the MCU 100 by the debug dedicated program. Meanwhile, the timer is started (step S204), the debug terminal 102 is monitored (step S205), and the signal maintenance time TW1 and the reset mask signal release time TW2 are determined to be large or small (step S206).

  That is, the terminal monitor unit 110 monitors the change of the debug terminal 102 to a high level or a low level. When the debug terminal 102 changes from the low level to the high level, the terminal monitor unit 110 starts measurement by the measuring instrument 114 for the signal maintenance time TW1 that is the high level period of the debug terminal 102 (step S205). If the terminal monitoring unit 110 determines that the signal maintenance time TW1 of the debug terminal 102 is less than the reset mask signal release time TW2 (TW1 <TW2), the terminal 100 determines that the MCU 100 is debugging (NO in step S206). In FIG. 6, since the signal maintaining times TW1a, TW1b, TW1c, and TW1d are smaller than the reset mask signal release time TW2, the timer is cleared (step S207), and steps S204 to S207 are repeated.

  Thereafter, at time T <b> 3, the terminal monitor unit 110 starts measuring the signal maintaining time TW <b> 1 e of the debug terminal 102 with the measuring instrument 114 of the timer unit 111. (Steps S204 and S205).

  It is assumed that the external debug device 300 is removed from the debug terminal 102 at time T4. At this time, since the debug terminal 102 becomes high impedance (disconnected state), the signal level is maintained at the high level from time T3. And the terminal monitor part 110 continues measuring signal maintenance time TW1e.

  It is assumed that the reset mask signal release time TW2 has elapsed by the timer of the timer unit 111 at time T5. Therefore, the comparator 115 compares the signal maintenance time TW1e at this time with the reset mask signal release time TW2. Here, it is determined that TW1e and TW2 are equal (YES in step S206), the timer is stopped (step S208), and the reset mask signal 202 is released, that is, changes to the low level (step S209).

  Therefore, at time T6, when the reset terminal 101 changes from the high level to the low level, the reset mask circuit 121 sets the reset signal 203 after the reset mask to the low level and outputs it to the CPU 130. Thereby, CPU130 will be in a reset state.

  As described above, in the first embodiment, the transition from the debug valid mode to the debug invalid mode is enabled by the control of the reset terminal 101 instead of the control of the power-on reset of the MCU 100. Therefore, there is an effect that even if the external debug device 300 is not connected to the debug terminal 102 after debugging, the debug valid mode can be returned to the debug invalid mode. Further, by detecting that the debugging has been completed or the external debugging device 300 has been removed that the signal level signal maintaining time TW1 of the debugging terminal 102 is equal to or longer than the reset mask signal releasing time TW2, the external debugging device 300 is detected. The debugged MCU 100 can be shifted to a state in which the user program can be executed without separately performing a battery removal operation or the like other than the removal of the user program.

<Embodiment 2>
The second embodiment is a modification of the first embodiment described above. In the semiconductor device according to the second embodiment, when the terminal monitoring unit determines that the signal maintenance time is equal to or longer than a predetermined time, the semiconductor device is shifted to the second mode after resetting the inside of the semiconductor device. is there. Alternatively, the semiconductor device according to the second embodiment makes a transition to the first mode when a debug device is connected, and resets the inside of the semiconductor device when the signal level has not changed for a predetermined time or more. It can also be said that the mode is changed to the second mode later. Furthermore, when the semiconductor device determines that the signal maintenance time is equal to or longer than a predetermined time, the semiconductor device can be shifted to the second mode after resetting the inside of the semiconductor device. Thus, since the mode is forcibly shifted to the second mode, the execution of the user program can be started immediately after the end of the execution of debugging.

  In addition, the mode control unit according to the second embodiment disables the reset signal when transitioning to the first mode, and enables the reset signal when the signal maintaining time is maintained for a predetermined time or more. And a reset control unit for outputting. That is, when the execution of debugging or the removal of the debugging device is detected by monitoring the signal maintaining time, a reset signal for resetting the semiconductor device is directly output. Thereby, the execution of the user program in the second mode can be started with the end of debugging.

  Further, the terminal monitor unit determines whether or not the signal maintenance time is maintained for a predetermined time or more, and outputs a terminal monitor signal to the reset control unit according to the determination result, the reset control unit, In the case where the terminal monitor signal indicates that the signal maintenance time is maintained for a predetermined time or more, it is desirable that the reset signal is enabled and output. Thus, the reset signal can be controlled more appropriately by the terminal monitor signal.

  FIG. 7 is a block diagram showing a configuration of the MCU 100a according to the second embodiment. The MCU 100a differs from the MCU 100 of FIG. 1 described above in that the mode control unit 120 is replaced with a mode control unit 120a. The reset signal 208 output from the mode control unit 120a is a reset signal for not only the CPU but also various components in the MCU 100a. Therefore, the CPU is omitted in FIG.

  The mode control unit 120a includes a reset control circuit 121a and a debug control unit 122a. The debug control unit 122a includes a reset mask control unit 123a. The debug control unit 122a does not accept the terminal monitor signal 206a from the terminal monitor unit 110, and outputs a reset mask signal 202a.

  FIG. 8 is a block diagram showing a configuration of the reset mask control unit 123a according to the second embodiment. The reset mask control unit 123a is obtained by removing the AND circuit 125 from the reset mask control unit 123 of FIG. The latch circuit 124 of the reset mask controller 123a outputs a high level signal until the power-on reset signal 204 is turned on when the debug signal 207 changes to the low level even once after the start of debugging. Then, the reset mask control unit 123a outputs the output signal from the latch circuit 124 as the reset mask signal 202a to the reset control circuit 121a. When the reset mask signal 202a is at a high level, the mask of the reset signal 201 is valid, and when the reset mask signal 202a is at a low level, the mask of the reset signal 201 is cancelled.

  Returning to FIG. The reset control circuit 121 a receives the reset signal 201 from the external reset control circuit 200 via the reset terminal 101. Further, the reset control circuit 121a receives the terminal monitor signal 206a from the terminal monitor unit 110, the reset mask signal 202a from the reset mask control unit 123a, and the power-on reset signal 204 from the power-on reset unit 140. The reset control circuit 121a controls which domain or component in the MCU 100a issues a reset signal based on a signal input based on the above-described factors. At this time, the reset control circuit 121 a issues a reset signal having the same level as the reset signal 201 from the reset terminal 101. The reset signal issued by the reset control circuit 121a includes, for example, reset of the debug control unit 122a itself and reset of the IO unit.

  As described above, in the second embodiment, as in the first embodiment described above, the terminal monitor unit 110 detects that there is no change in the signal level at the debug terminal 102 for a predetermined time or more. In this case, the terminal monitor unit 110 outputs the fact as a terminal monitor signal 206a to the reset control circuit 121a. Then, the reset control circuit 121a outputs a reset signal 208 for enabling reset based on the terminal monitor signal 206a. Thereby, the MCU 100a can be reset when the end of the execution of the debug or the removal of the external debug device 300 is detected. Therefore, after the external debugging device 300 is removed, a user program or the like can be executed immediately without separately issuing a reset from the outside.

<Other embodiments>
The first and second embodiments described above relate to a microcomputer with an on-chip debug function and a control method therefor, and particularly to a microcomputer that has few interface signal lines and a debug-dedicated reset terminal. Applicable.

  The first embodiment can also be expressed as follows. That is, a semiconductor integrated circuit including a debug control unit that performs control for program debugging in the semiconductor integrated circuit, for example, a microcomputer with an on-chip debug function. The semiconductor integrated circuit is connected by one or more signal groups to an arbitrary debug device connected to the outside, and when the signal level of the signal group or is physically separated, the semiconductor integrated circuit passes through a specific terminal from the outside of the semiconductor integrated circuit. The terminal monitor unit that can measure the signal level of the signal input at any time, and the reset signal input from the semiconductor integrated circuit is masked during debugging by the monitor signal output from the terminal monitor unit in the debug control unit A reset mask controller. Then, the terminal monitor unit monitors the connection status with the debug device, and the debug control unit cancels the mask state of the reset mask control unit when there is no access from the debug device for an arbitrarily set period or longer. Then, the semiconductor integrated circuit is reset from the debug control state, and the semiconductor integrated circuit transits from the debug enabled state (debug effective mode) to the normal program execution state (user mode). Thereby, there exists an effect which can perform the power-on reset by power supply OFF, without removing a battery with systems, such as vehicle-mounted ECU.

  Further, in the terminal monitor unit, a means for setting an arbitrary reset mask signal release time and one or more signal groups connected to the debug device are input via an arbitrary terminal to detect the level of the signal. A level detection circuit, a measuring device for outputting a level detection signal output as a result of the detection to a comparator, a comparator for comparing the measured result with an arbitrarily set reset mask signal release time, and the comparison result It is good to have a timer part which outputs to a debugging control part for every fixed time.

  Alternatively, a semiconductor integrated circuit control method including a debug control unit that performs control for program debugging in the semiconductor integrated circuit, for example, a microcomputer control method with an on-chip debug function. In this control method, when one or more signal groups are connected to an arbitrary debug device connected to the outside, and the signal level of the signal group or physically separated, the debug device is connected and the debug valid mode A step of setting an arbitrary reset mask signal release time at the time and determining whether an arbitrary signal level continues within the set time; and a reset signal for reset mask signal and reset mask circuit to mask the reset terminal A step of resetting the CPU unit by a reset signal after masking with a reset mask and a step of monitoring a terminal state by measuring a signal level with a level detection circuit and a measuring instrument with respect to an arbitrary terminal state connected to the debugging device; The reset mask is compared with the measured result and the reset mask signal release time set arbitrarily. If it is less than the signal release time, initialize the time measurement instrument and repeat the monitoring of the terminal status again.If it is the same or larger, stop measuring the signal level and send the reset mask signal of the reset terminal to the terminal monitor signal. And enabling the reset signal from the reset terminal to the CPU unit.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

100 MCU
100a MCU
DESCRIPTION OF SYMBOLS 101 Reset terminal 102 Debug terminal 110 Terminal monitor part 111 Timer part 112 Level detection circuit 113 Register 114 Measuring instrument 115 Comparator 120 Mode control part 120a Mode control part 121 Reset mask circuit 121a Reset control circuit 122 Debug control part 122a Debug control part 123 Reset mask control unit 123a Reset mask control unit 124 Latch circuit 125 AND circuit 130 CPU
140 Power-on reset unit 150 N-channel open drain buffer 200 External reset control circuit 201 Reset signal 202 Reset mask signal 202a Reset mask signal 203 Reset signal after reset mask 204 Power-on reset signal 205 Debug signal 206 Terminal monitor signal 206a Terminal monitor signal 207 Debug signal 208 Reset signal 300 External debug device 301 Pull-up circuit VDD Power supply voltage T0 Time T1 Time T2 Time T3 Time T4 Time T5 Time T6 Time TW1 Signal maintenance time TW1a Signal maintenance time TW1b Signal maintenance time TW1c Signal maintenance time T1 Time TW2 Reset mask signal release time

Claims (19)

A debug terminal connected to an external debug device;
A terminal monitor unit that monitors a change in signal level at the debug terminal during debugging by the debug device, and
A semiconductor device that transitions from a first mode for performing debugging to a second mode for performing normal operation when the signal level does not change for a predetermined time or more. The debug terminal is connected to the debug device by at least one signal group,
The terminal monitor unit is
Measuring a signal maintenance time, which is a time during which at least a part of the signal level in the signal group is maintained at a specific level;
Determining whether the signal maintenance time is a predetermined time or more;
When it is determined that the signal maintenance time is equal to or longer than a predetermined time, the change in the signal level is not longer than the predetermined time.
The semiconductor device according to claim 1. In the second mode, when the signal level at the debug terminal changes from the specific level to a level other than the specific level, the mode is changed to the first mode, and a reset signal input from the outside is masked.
The terminal monitor unit starts monitoring a change in signal level at the debug terminal after the start of debug execution by the debug device;
3. The semiconductor device according to claim 2, wherein when the terminal monitoring unit determines that the signal maintenance time is equal to or longer than a predetermined time, the mask of the reset signal is canceled and the mode is changed to the second mode. 4. The semiconductor device according to claim 3, wherein the terminal monitor unit makes a transition to the second mode after resetting the inside of the semiconductor device when it is determined that the signal maintenance time is a predetermined time or more. 5. The terminal monitor unit is
A level detection circuit for detecting that at least a part of signal levels in the signal group is the specific level;
A timer unit for measuring the signal maintenance time and determining whether the signal maintenance time is a predetermined time or more,
The timer unit is
Setting means for setting the predetermined time;
A measuring instrument for measuring the maintenance time of the signal level detected by the level detection circuit;
A comparator that compares the measured maintenance time with the set predetermined time and outputs a comparison result;
The semiconductor device according to claim 3 or 4. Transition to the first mode when the debug device is connected, masking a reset signal input from the outside,
2. The semiconductor device according to claim 1, wherein when the change in the signal level does not exceed a predetermined time, the mask of the reset signal is released and the mode is changed to the second mode. Transition to the first mode when the debug device is connected;
2. The semiconductor device according to claim 1, wherein when the signal level does not change for a predetermined time or more, the semiconductor device is reset to the second mode after the inside of the semiconductor device is reset. A debug terminal connected to an external debug device;
A terminal monitor unit for measuring a signal maintenance time, which is a time during which a specific signal level at the debug terminal is maintained during debugging by the debugging device;
A mode control unit that transitions from a first mode for performing debugging to a second mode for performing normal operation when the signal maintenance time is maintained for a predetermined time or more;
A semiconductor device comprising: The mode control unit
When in the first mode, mask the reset signal input from the outside,
The semiconductor device according to claim 8, wherein when the signal maintenance time is maintained for a predetermined time or more, the mask of the reset signal is released. The mode control unit
A reset mask control unit that enables a reset mask signal for masking the reset signal in the first mode, and disables the reset mask signal when the signal maintaining time is maintained for a predetermined time or more; ,
The semiconductor device according to claim 9, further comprising: a reset control unit that inputs the reset signal and the reset mask signal and outputs a reset signal after masking. The terminal monitor unit is
Determining whether the signal maintenance time is maintained for a predetermined time or more;
According to the determination result, a terminal monitor signal is output to the reset mask control unit,
The reset mask controller is
The semiconductor device according to claim 10, wherein the reset mask signal is invalidated when the terminal monitor signal indicates that the signal maintenance time is maintained for a predetermined time or more. The reset mask controller is
A latch circuit that inputs a signal from the debug terminal and a power-on reset signal, and outputs a high-level signal when the signal from the debug terminal changes after debug execution;
A logical product circuit that outputs a logical product of the terminal monitor signal and an output signal from the latch circuit to the reset control unit as the reset mask signal;
The semiconductor device according to claim 11, comprising: The mode control unit
A reset control unit that disables the reset signal when transitioning to the first mode, and enables and outputs the reset signal when the signal maintaining time is maintained for a predetermined time or longer. The semiconductor device described. The terminal monitor unit is
Determining whether the signal maintenance time is maintained for a predetermined time or more;
According to the determination result, a terminal monitor signal is output to the reset control unit,
The reset control unit
The semiconductor device according to claim 13, wherein the reset signal is validated and output when the terminal monitor signal indicates that the signal maintenance time is maintained for a predetermined time or more. The debug terminal is connected to the debug device by at least one signal group,
The terminal monitor unit is
Measuring a signal maintenance time, which is a time during which at least a part of the signal level in the signal group is maintained at a specific level;
Determining whether the signal maintenance time is a predetermined time or more;
The semiconductor device according to claim 8, wherein a terminal monitor signal is output to the mode control unit according to the determination result. A debug control method for a semiconductor device having a debug terminal connected to an external debug device,
The semiconductor device is
During debug execution by the debug device, the signal level change at the debug terminal is monitored,
A method for controlling the debugging of a semiconductor device, wherein a transition from a first mode for performing debugging to a second mode for performing normal operation is performed when the signal level does not change for a predetermined time or more. The debug terminal is connected to the debug device by at least one signal group,
The semiconductor device is
Measuring a signal maintenance time, which is a time during which at least a part of the signal level in the signal group is maintained at a specific level;
Determining whether the signal maintenance time is a predetermined time or more;
When it is determined that the signal maintenance time is equal to or longer than a predetermined time, the change in the signal level is not longer than the predetermined time.
The debug control method according to claim 16. The semiconductor device is
In the second mode, when the signal level at the debug terminal changes from the specific level to a level other than the specific level, the mode is changed to the first mode, and a reset signal input from the outside is masked.
After starting debug execution by the debug device, start monitoring signal level change at the debug terminal,
The debug control method according to claim 17, wherein when it is determined that the signal maintenance time is equal to or longer than a predetermined time, the mask of the reset signal is canceled and the mode is changed to the second mode. The semiconductor device is
The debug control method according to claim 18, wherein when it is determined that the signal maintenance time is equal to or longer than a predetermined time, the semiconductor device is reset to the second mode after being reset.

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