JP2014116894A - Data transmission device, data reception device and bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mechanism for easily assembling an existing module whose high reliability is not required in a highly reliable bus system without alteration.SOLUTION: In a data transmission device to be used in a bus system having a transmission part including: a transmission data creation part: an ECC(Error Correcting Code) generation part for generating the ECC of transmission data to be output from the transmission data creation part; and a data output part for transmitting the transmission data and the ECC, the data output part comprises: a rise ECC transmission part for transmitting the ECC synchronously with the rise of a bus clock; and a fall data transmission part for transmitting the transmission data synchronously with the fall of the bus block.

Description

  The present invention relates to a data transmission device, a data reception device, and a bus system.

  In industrial control systems such as plants, railways, and aircraft that require extremely high reliability to ensure the safety of human lives and the environment, even if a failure or abnormality occurs in the system, the system should not be stopped as much as possible. Increased availability is required. In such a system, a controller that controls the system is often used, and it is important to increase the reliability and availability of the controller.

  In the controller, a plurality of modules constituting the controller are connected and communicated to perform control. In particular, in order to increase the availability of communication in the bus system, for example, error correction code called ECC (Error Correcting Code) is used. It is conceivable to add a code. In ECC, by adding several ECC bits to the data body portion, in addition to correcting a 1-bit error, a 2-bit error can be efficiently detected.

  Here, when an ECC is added with high reliability of an existing bus system, it is necessary to add several bits for the ECC bit to the bus bits. This may require significant changes to the hardware in some cases and can hinder the development of a reliable system in a short period of time. Therefore, it is conceivable to realize communication with ECC added without adding hardware for ECC bits.

  FIG. 13 is a diagram illustrating an example of a conventional bus system in which high reliability is not performed. In the following bus systems, description will be made assuming that all data transfers operate in synchronization with the bus clock. Transmission data created by the transmission data creation unit 104 in the transmission unit 101 is received from the data output unit 106 through the bus 103 by the data input unit 109 in the reception unit 102 and used as data in the reception unit 102. Is done.

  FIG. 14 shows an example of a timing chart in the case of performing transfer in the bus system shown in FIG. The transmission data D1 is transmitted from the data output unit 106 at the rising edge C0 of the bus clock shown in FIG. 14, and the data input unit 109 receives it at the next rising edge C2. Similarly, data D2, D3, and D4 are transmitted and received. Here, FIG. 15 shows an example of a bus system in a case where ECC is added to transmission data of the bus system and transfer is performed without increasing the bus width.

  For the transmission data created by the transmission data creation unit 204 in the transmission unit 206 shown in FIG. 15, an ECC corresponding to the data is generated by the ECC generation unit 205 and sent to the data output unit 206. The data output unit 206 includes an output timing control unit 211 that adjusts the timing of transmitting ECC and data. The data input unit 209 in the receiving unit 202 includes an input timing control unit 212 that adjusts the timing of receiving the ECC and data, and transmits the received data to the ECC correction unit 213. The ECC correction unit 213 receives the received data and the ECC bit. To correct the error. FIG. 16 shows an example of a timing chart in the case of performing transfer by the bus system shown in FIG.

  At the rising edge C0 shown in FIG. 16, the data output unit 206 transmits ECC1 for the data D1, and at the next rising edge C2, the data input unit 209 receives ECC1. The data output unit 206 transmits the data D1 body at the same rising edge C2, and the data input unit 209 receives the data D1 at the next rising edge C4. The same applies to transmission and reception of ECC2 and data2. Here, since the bus 203 has only the bit width of the data portion, it is necessary to design the output timing control unit 211 and the input timing control unit 212 to adjust the timing of the ECC and the data body. Patent Document 1 describes an example of performing highly reliable data transfer without increasing the bus width in data transfer with ECC added.

JP 2005-354310 A

  By the way, as a result of the study of the highly reliable bus system that performs transfer by adding ECC to the conventional bus system, the following has been clarified.

  In order to modify the bus system so as not to increase the bit width for ECC bits, it is also necessary to transfer ECC on the data transmission bus. However, in order to adjust the timing of the ECC and the data body, output timing control is performed. And the input timing control unit need to be newly designed. For this reason, even when communicating with existing modules that are required during development but not required during actual operation of the system, such as debugging applications and error injection applications for high-reliability function confirmation, even when communicating with existing modules that do not require high reliability. There was a problem that the data reception part of the module had to be modified.

  Further, in order to transfer without increasing the bit width for ECC bits, as shown in FIG. 16, it is necessary to provide a cycle for transferring ECC separately from the cycle for transferring data. There was a problem that became larger.

  Furthermore, Patent Document 1 describes a mechanism for transferring highly reliable data without increasing the bit width for ECC bits. However, a cycle for transferring ECC is newly provided on the transmission side and the reception side. Therefore, there is a problem that the existing modules that do not require high reliability also need to be modified.

  Therefore, the present invention is a bus system used for a controller such as an industrial control system, and only a module that requires a new high reliability without changing the bus specification of an already designed module that does not require a high reliability. Is designed so that, for example, a data transmitter, a data receiver, and a bus system used in a controller having a bus system and an industrial control system using the controller can be easily constructed.

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The subject includes a plurality of means for solving the above-described problem. To give an example, a transmission data creation unit, an ECC generation unit that generates an ECC of transmission data output from the transmission data creation unit, A data transmission device used in a bus system including a transmission unit including transmission data and a data output unit that transmits the ECC, wherein the data output unit transmits the ECC in synchronization with a rising edge of a bus clock. And a falling data transmitter that transmits the transmission data in synchronization with a falling edge of the bus clock.

  A data receiving device used in a bus system including a data input unit that receives ECC and transmission data, and an ECC correction unit that performs ECC correction from the ECC and the transmission data. The data input unit includes a falling ECC receiving unit that receives the ECC in synchronization with the falling edge of the bus clock, and a rising data receiving unit that receives the transmission data in synchronization with the rising edge of the bus clock. It is characterized by that.

  A data transmission apparatus comprising: a transmission data creation unit; an ECC generation unit that generates an ECC of transmission data output from the transmission data creation unit; and a data output unit that transmits the transmission data and the ECC. A data receiving device comprising: a data input unit that receives the ECC and the transmission data; and an ECC correction unit that performs ECC correction from the ECC and the transmission data. The data output unit of the apparatus includes a rising ECC transmission unit that transmits the ECC in synchronization with a rising edge of a bus clock, and a falling data transmission unit that transmits the transmission data in synchronization with a falling edge of the bus clock. The data input unit of the data receiving device includes the EC in synchronization with a fall of the bus clock. Characterized in that it comprises a fall ECC receiving unit receives a, and a rising data receiving unit that receives the transmission data in synchronization with the rising edge of the bus clock.

  According to the present invention, it is possible to provide a mechanism that can be easily incorporated into a highly reliable bus system without remodeling an existing module that does not require high reliability to a bus system to which ECC is added. It becomes possible to design a data transmission device, a data reception device, and a bus system used in an industrial control system using a simpler in a short period of time.

  Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

It is an example of the reliable transmission part in the bus system of this invention. It is an example of the highly reliable receiving part in the bus system of this invention. It is the example which connected the reliable transmission part and the reliable receiving part in Example 1. FIG. FIG. 4 is an example of a timing chart for performing transmission and reception of ECC and data in one bus clock cycle by the transmission unit and the reception unit illustrated in FIG. 3. FIG. 4 is an example of a timing chart in which the transmission unit and the reception unit illustrated in FIG. 3 transmit and receive ECC and data in two bus clock cycles. It is the example which connected the highly reliable transmission part and the receiving part which is the existing module which does not require high reliability in Example 2. FIG. 7 is an example of a timing chart for performing transmission and reception of ECC and data between the transmission unit and the reception unit illustrated in FIG. 6. FIG. 12 is an example of a block diagram in which data is transmitted and received by the highly reliable module A and the highly reliable module B in the third embodiment. FIG. 10 is an example of a block diagram in which data is transmitted and received between a highly reliable module A and an existing module C that does not require high reliability in the third embodiment. FIG. 11 is an example of a block diagram in which data is transmitted and received by a highly reliable module A, a highly reliable module B, and an existing module C that does not require high reliability in the third embodiment. This is an example of including information other than ECC at the time of ECC transfer in the fourth embodiment. It is an example of the controller in Example 5, and an industrial control system using the same (industrial control system). It is an example of the controller in Example 5, and an industrial control system using the same (information processing system). It is an example of the transmission part and receiving part in the conventional bus system. 14 is an example of a timing chart for transmitting and receiving data between the transmission unit and the reception unit illustrated in FIG. 13. It is an example of the reliable transmission part and the reliable receiving part in the conventional bus system. FIG. 16 is an example of a timing chart for performing transmission and reception of ECC and data between the transmission unit and the reception unit illustrated in FIG.

  Exemplary embodiments of a data transmission device, a data reception device, and a bus system according to the present invention will be described below in detail with reference to the accompanying drawings. In the following bus systems, description will be made assuming that all data transfers operate in synchronization with the bus clock.

  FIG. 1 is a diagram illustrating an example of a transmission unit in the bus system in the present embodiment, and FIG. 2 is a diagram illustrating an example of a reception unit in the bus system in the present embodiment. Since the example shown by connecting the transmission unit shown in FIG. 1 and the reception unit shown in FIG. 2 is FIG. 3, the bus system in the present embodiment will be described with reference to FIG. The bus system shown in FIG. 3 transmits data from the transmission unit 1 to the reception unit 2 via the bus 3. It is assumed that the availability of the bus system is enhanced by adding ECC capable of 1-bit error correction and 2-bit error detection to the transmitted data.

  Data to be transmitted is created from the transmission data creation unit 4 in the transmission unit 1 and transmitted to the ECC generation unit 5 and the data output unit 6. The ECC generation unit 5 generates an ECC corresponding to the data to be transmitted and transmits it to the data output unit 6.

  The data output unit 6 includes a rising ECC transmission unit 7 and a falling data transmission unit 8. The rising ECC transmission unit 7 transmits the data ECC in synchronization with the rising of the bus clock. The falling data transmitting unit 8 transmits the data body in synchronization with the falling of the bus clock. The ECC and data output from the data output unit 6 are received by the data input unit 9 in the receiving unit 2 via the bus 3.

  The data input unit 9 includes a falling ECC receiving unit 10 and a rising data receiving unit 11. The falling ECC receiving unit 10 receives the ECC of data in synchronization with the falling of the bus clock. The rising data receiving unit 11 receives the data body in synchronization with the rising edge of the bus clock. The ECC and data received by the data input unit 9 are received by the ECC correction unit 12 and become error-corrected data, which are used in the reception unit 2 or in the system ahead thereof.

  FIG. 4 shows an example of a timing chart when data transfer is performed in the bus system shown in FIG. FIG. 4 shows an example in which data transfer between the transmission unit 1 and the reception unit 2 is performed in one cycle in synchronization with the bus clock. At the rising edge C0 of the bus clock, the rising ECC transmitting unit 7 in the data output unit 6 of the transmitting unit 1 transmits ECC1 corresponding to the data D1 first, and at the falling edge C1, the falling data transmitting unit 8 To transmit data D1. On the other hand, at the falling edge C1 of the bus clock, the receiving unit 2 first receives ECC1 at the falling ECC receiving unit 10 in the data input unit 9, and at the rising edge C2, the data D1 is received at the rising data receiving unit 11. Receive. The ECC correction unit 12 in the reception unit 2 performs error correction of the data D1 using this ECC1.

  Similarly, the transmission unit 1 transmits ECC2 at the rising edge C2 of the bus clock, the reception unit 2 receives ECC2 at the falling edge C3, the transmission unit 1 transmits data D2 at the falling edge C3, and the rising edge. In C4, the receiving unit 2 receives the data D2. The ECC correction unit 12 in the reception unit 2 performs error correction of the data D2 using this ECC2. The same applies to the subsequent ECC3 and data D3, and ECC4 and data D4.

  FIG. 5 shows an example in which data transfer between the transmission unit 1 and the reception unit 2 of the bus system shown in FIG. 3 is performed in two cycles in synchronization with the bus clock. In FIG. 5, ECC1 transmitted by the transmitting unit 1 at the rising edge C0 of the bus clock is received by the receiving unit 2 at the falling edge C3 of the bus clock, and the data transmitted by the transmitting unit 1 at the falling edge C1 of the bus clock. D1 is received by the receiver 2 at the rising edge C4 of the bus clock.

  As described above, in the bus system according to the present embodiment, the transmission side transmits ECC in synchronization with the rising edge of the bus clock, the reception side receives ECC in synchronization with the falling edge of the bus clock, and the transmission side. Thus, data is transmitted in synchronization with the falling edge of the bus clock, and data is received on the receiving side in synchronization with the rising edge of the bus clock.

  As a result, it is not necessary to provide a new ECC bit bus width for an existing bus system that is not highly reliable. In addition, since the ECC is transferred in synchronization with the falling edge, it is possible to realize a highly reliable bus system without increasing the cycle overhead for data transmission / reception synchronized with the conventional rising edge. Thus, it becomes possible to quickly develop a controller using this bus system and an industrial control system using the controller.

  FIG. 6 shows an example in which a highly reliable transmitting unit and an existing module that does not require high reliability are connected as a receiving unit in the bus system according to the present embodiment. The transmitting unit 1 has the same configuration as that of the first embodiment, and thus detailed description thereof is omitted. The receiving unit 21 illustrated in FIG. 6 is an existing module that does not require high reliability, and does not include a circuit corresponding to ECC at the time of bus transfer. The data input unit 22 in the reception unit 21 is a circuit that receives data in synchronization with the rising edge of the bus clock, and is connected to the transmission unit 1 via the bus 3.

  FIG. 7 shows an example of a timing chart when data transfer is performed in the bus system shown in FIG. Since the transmission unit 1 is a highly reliable module that supports ECC, the rising ECC transmission unit 7 in the data output unit 6 transmits ECC1 corresponding to the data D1 at the rising edge C0 of the bus clock. Further, the falling data transmitting unit 8 transmits the data D1 at the falling edge C1 of the bus clock.

  On the other hand, the receiving unit 21 is an existing module that does not support ECC, and the data input unit 22 has only a function of receiving data in synchronization with the rise of the bus clock. Therefore, the ECC1 transmitted from the transmission unit 1 is ignored, and only the transmitted data D1 is received at the rising edge C2 of the bus clock, and used in the reception unit 22 and the subsequent modules. The same applies to the subsequent ECC2 and data D2, ECC3 and data D3, ECC4 and data D4, and ECC and data transmitted thereafter.

  As a result, it is not necessary to provide a new ECC bit bus width for an existing bus system that is not highly reliable. The highly reliable transmitting side transfers the ECC in synchronization with the falling edge of the bus clock and transmits data to the rising edge, so that the non-reliable receiving side has the rising edge of the bus clock as before. Therefore, it is possible to incorporate an existing module that does not require high reliability into a high-reliability bus system without modification.

  FIG. 8 shows an example of a bus system that performs bidirectional transmission and reception of highly reliable data in the bus system according to this embodiment. The module A (41) has a transmission data creation unit 4, an ECC generation unit 5, and a data output unit 6 as data transmission parts, as in the function of the transmission unit shown in FIG. The output unit 6 includes a rising ECC transmission unit 7 and a falling data transmission unit 8. The data output from the data output unit 6 is connected to the module B (42) via the bus 3.

  The module B (42) has a data input unit 9 and an ECC correction unit 12 as a part for receiving data, similarly to the function of the receiving unit shown in FIG. There is a falling ECC receiving unit 10 and a rising data receiving unit 11. On the other hand, the module B (42) has a transmission data creation unit 54, an ECC generation unit 55, and a data output unit 56 as a part for performing data transmission, similarly to the function of the transmission unit shown in FIG. The data output unit 56 includes a rising ECC transmission unit 57 and a falling data transmission unit 58. The data output from the data output unit 56 is connected to the module A (41) via the bus 53.

  On the other hand, the module A (41) has a data input unit 59 and an ECC correction unit 62 as a part for receiving data, similarly to the function of the receiving unit shown in FIG. 59 includes a falling ECC receiving unit 60 and a rising data receiving unit 61. Each functional block in the module A (41) and the module B (42) operates as described in the above embodiments, and the bus 3 and the bus 53 between the module A (41) and the module B (42) are operated. As shown in the timing charts shown in FIG. 4 and FIG. 5, the data transfer at the transmitting side transmits ECC at the rising edge of the bus clock and transmits data at the falling edge of the bus clock. On the receiving side, ECC is received at the falling edge of the bus clock, and data is received at the rising edge of the bus clock.

  FIG. 9 is an example of a bus system in which data is transmitted and received bidirectionally between a highly reliable module compatible with ECC and an existing module that does not require high reliability in the bus system of the present embodiment. The module A (41) has the same configuration as that shown in FIG. Module C (43) is an existing module that does not require high reliability and does not require ECC-compatible modification. The data input unit 22 in the module C (43) is a circuit that receives data in synchronization with the rising edge of the bus clock, and the data output unit 23 that transmits data from the transmission data creating unit 54 has a rising edge of the bus clock. Is a circuit for transmitting data in synchronization with the.

  Data is transmitted from the module A (41) to the module C (43) via the bus 3, and conversely, data is transmitted from the module C (43) to the module A (41) via the bus 53. As shown in FIG. 7, the timing chart of data transmitted from the module A (41) to the module C (43) is a module that transmits ECC and data from the highly reliable module A (41) and does not require high reliability. Only data is received in C (43).

  On the other hand, the data transmitted from the highly reliable module C (43) to the highly reliable module A (41) is not added with ECC, and is only the data body. In this case, in the data input unit 59, the falling ECC receiving unit 60 recognizes and receives the data as ECC, but on the system, this is ignored as don't care, and the ECC correcting unit 62 Do not use. The data received by the rising data receiving unit 61 is used as it is in the module A (41) and the subsequent module via the data line 71 as it is.

  FIG. 10 shows the high reliability module A (41) and the high reliability module B (42) shown in FIG. 8 and the existing module C (43) that does not require high reliability shown in FIG. It is an example of a bus system in the case of connecting a module B (42) and a module C (43). Since module A (41) is a highly reliable module, ECC and data are transmitted to and received from module B (42). On the other hand, since module C (43) is an existing module that does not require high reliability, even if ECC and data are transmitted from module A (41), only data is received at the rising edge of the bus clock, and module A (41). ), Only the data is transmitted, and the part corresponding to the ECC in the module A (41) is ignored.

  In this way, by increasing the number of buses between modules, data transfer can be performed bidirectionally and at high speed between highly reliable modules compatible with ECC. Further, even when one of the communicating modules is an existing module that does not require high reliability, the existing module can be incorporated without modification.

  FIG. 11 shows an example of a data transfer format in the bus systems shown in the first to fourth embodiments. Data transfer in the highly reliable bus system corresponding to ECC in the present embodiment is executed as in the timing charts shown in FIGS. 4 and 5, for example.

  In general, when ECC bits for error correction are added to transfer data, for example, 7 bits are added to 32-bit data and 8 bits are added to 64-bit data. It has been known. Thus, the bit width of the ECC bits is very small with respect to the bit width of the data body. That is, in the timing charts shown in FIGS. 4 and 5, in the bus cycle indicating the ECC transfer, only a part of the number of bits that can be transferred with respect to the bus width is used. Therefore, it is possible to transmit information including information other than ECC bits in the ECC transfer cycle.

  FIG. 11A shows an example in which the ECC bits are arranged at the least significant bit and the module identifier 31 is arranged in the high bit part. This system can also be applied to a device or system in a master-slave relationship in which one device controls one or more other devices unilaterally. In the bus system that transmits and receives data with a plurality of slaves, a unique module identifier is transmitted from the slave to the master simultaneously with the ECC. The received master can confirm which slave has transmitted the data, and can perform more reliable and fine-tuned control.

  FIG. 11B shows an example in which the ECC bits are arranged at the least significant bit and the sequence number 32 is arranged in the high bit part. For example, in a bus system, when the order of data to be transmitted is not determined and the order is switched and transmitted, the sequence number of the transfer data is transmitted simultaneously with the ECC. On the receiving side, it is possible to perform more efficient control such as checking the sequence number and rearranging the data in order.

  FIG. 11C shows an example in which the ECC bits are arranged at the least significant bit and the time stamp 33 is arranged in the high bit portion. For example, in the bus system, when it is desired to keep a log of the time of transferred data, the time stamp of the transferred data is transmitted simultaneously with the ECC. Realization of a system that can analyze, for example, at which time abnormal data transmission was performed by checking the time stamp on the receiving side and storing the data and time stamp data in association with each other. It becomes possible.

  Although FIG. 11 shows an example in which the ECC bits are arranged at the lowest order, they may be arranged in any vacant part. In addition, when the number of bits of information to include other than ECC is small, as shown in FIG. 11D, a format in which a plurality of pieces of information such as a module identifier 31, a sequence number 32, and a time stamp 33 are transmitted at a time is used. Good.

  In addition, as information to be transmitted simultaneously with the ECC bits, there are various kinds of information such as a parity bit for detecting an error of 1 bit, a cyclic redundancy code, a Reed-Solomon code, etc. It can be applied to transmitting various information. As a result, it is possible to increase the reliability of the bus system and perform finer control by simultaneously transmitting various information other than the ECC bits.

  FIG. 12A shows an example of an industrial control system using a controller having the bus system shown in the first to fourth embodiments.

  The industrial control system shown in FIG. 12A controls the power plant 305. An instruction from the control terminal 301 is transmitted from the bus 312 to the controller 303, and the instruction is transmitted from the I / O control 307 via the I / O device 304 to control the power plant. If the instruction from the control terminal 301 is mistakenly transmitted to the power plant 305, the power plant may not operate normally, and serious damage may occur. Therefore, the bus 311 connecting the control terminal 301 and the controller 303 The bus 312 performs highly reliable communication using ECC.

  Here, the debugging terminal 302 is a debugging terminal for investigating an I / O control malfunction of the controller 303. Although the debugging terminal 302 is connected to the debug control 308, it is used for analyzing data from the I / O control 307, and does not directly control the power plant 305. For this reason, even if the CPU module 306 of the controller 303 transmits ECC for high-reliability communication together with data via the bus 313, the debugging terminal does not make high-reliability and only buses conventional data. The specifications output from 314 may remain as they are.

  By applying the bus system shown in the first to fourth embodiments described above, in an industrial control system using a controller, it is divided into a highly reliable part and a part that does not require high reliability. It is possible to develop the system at an early stage because the existing design assets can be used as they are for parts that do not require high reliability.

  The bus systems shown in the first to fourth embodiments can be similarly widely applied to information processing systems other than the industrial control system using the above-described controller. For example, in a time stamp system that is required to measure an accurate time, even if a failure or abnormality occurs in the system, it is necessary to accurately measure the time, and thus it is required to increase availability. Therefore, it is important to increase the reliability and availability of the controller as in the industrial control system described above.

  FIG. 12B shows an example of an information processing system using a controller having the bus system shown in the first to fourth embodiments.

  The information processing system illustrated in FIG. 12B controls the time audit server 3051. An instruction from the client control terminal 3011 is transmitted from the bus 312 to the time stamp apparatus 3031. The instruction is transmitted from the I / O control 3071 via the communication apparatus 3041, and the time audit server is controlled. If the instruction from the client control terminal 301 is erroneously transmitted to the time audit server 3051, there is a risk that accurate time measurement or auditing may not be performed. Therefore, a bus connecting the client control terminal 3011 and the time stamp device 3031 The 311 and the bus 312 perform highly reliable communication using ECC.

  Here, the development terminal 3021 is a debugging / development terminal for investigating I / O control of the time stamp apparatus 3031 and malfunctions in the apparatus or developing a new system. The development terminal 3021 is connected to the development test control 3081, but is used for analyzing data from the I / O control 3071, and does not directly control the time audit server 3051. For this reason, even if the CPU module 3061 of the time stamp device 3031 transmits ECC for high-reliability communication together with data via the bus 313, the debugging terminal does not make high-reliability, but only conventional data. May be output from the bus 314.

  By applying the bus systems shown in the first to fourth embodiments described above, in this information processing system, as in the case of the industrial control system described above, a highly reliable portion and a high reliability are provided. Can be divided into parts that do not need to be designed, and parts that do not require high reliability can utilize the existing design assets as they are, so that the system can be developed at an early stage.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

DESCRIPTION OF SYMBOLS 1 Transmission part 2, 21 Reception part 3, 53 Bus | bath 4, 54 Transmission data creation part 5, 55 ECC production | generation part 6, 23, 56 Data output part 7, 57 Rising ECC transmission part 8, 58 Falling data transmission part 9, 22, 59 Data input unit 10, 60 Falling ECC receiving unit 11, 61 Rising data receiving unit 12, 62 ECC correction unit 31 Module identifier 32 Sequence number 33 Time stamp 41 Module A
42 Module B
43 Module C
71 Data lines 301, 302 Control terminal 303 Controller 304 I / O device 305 Power plant 3011 Client control terminal 3021 Development terminal 3031 Time stamp device 3041 Communication device 3051 Time audit server.

Claims (7)

A transmission comprising: a transmission data generation unit; an ECC generation unit that generates an ECC (Error Correcting Code) of transmission data output from the transmission data generation unit; and a data output unit that transmits the transmission data and the ECC A data transmission device used in a bus system having a unit,
The data output unit includes:
A rising ECC transmitter that transmits the ECC in synchronization with the rising edge of the bus clock;
A falling data transmitter for transmitting the transmission data in synchronization with a falling edge of the bus clock;
A data transmission device comprising: A data receiving device used in a bus system including a data input unit that receives ECC and transmission data, and an ECC correction unit that performs ECC correction from the ECC and the transmission data,
The data input unit includes:
A falling ECC receiver for receiving the ECC in synchronization with a falling edge of the bus clock;
A rising data receiving unit that receives the transmission data in synchronization with a rising edge of the bus clock;
A data receiving apparatus comprising: A data transmission apparatus comprising: a transmission data creation unit; an ECC generation unit that generates an ECC of transmission data output from the transmission data creation unit; and a data output unit that transmits the transmission data and the ECC; A data receiving unit comprising an ECC and a data input unit that receives the transmission data, and an ECC correction unit that performs ECC correction from the ECC and the transmission data, and a bus system comprising:
The data output unit included in the data transmission device includes:
A rising ECC transmitter that transmits the ECC in synchronization with the rising edge of the bus clock;
A falling data transmitter that transmits the transmission data in synchronization with a falling edge of the bus clock,
The data input unit of the data receiving device is:
A falling ECC receiver for receiving the ECC in synchronization with a falling edge of the bus clock;
A rising data receiving unit that receives the transmission data in synchronization with a rising edge of the bus clock;
A bus system comprising: The data transmitting device operates as a master module, the data receiving device operates as a slave module, and the data communication device and the data receiving device are connected to each other by a bus.
The bus system according to claim 3. The data transmission device includes:
The data output unit transmits a module identifier for identifying the module together with the ECC transmission timing in a cycle in which the ECC is transmitted;
The data receiving device is:
The data input unit identifies the module based on the received module identifier;
The bus system according to claim 4. The data transmission device includes:
In the cycle in which the data output unit transmits the ECC, the sequence number indicating the order of the transmission data is transmitted together with the transmission timing of the ECC,
The data receiving device is:
The data input unit rearranges the transmission data in the order of the transmission data based on the sequence number.
6. The bus system according to any one of claims 3 to 5, wherein: The data transmission device includes:
In the cycle in which the data output unit transmits the ECC, the time stamp of the transmission data is transmitted together with the transmission timing of the ECC,
The data input device includes:
The data input unit stores the time stamp and the transmission data in association with each other;
The bus system according to any one of claims 3 to 6, characterized in that:

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