JP2014093863A - Power supply device and method for controlling power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply device capable of improving the voltage accuracy of an output voltage while being kept operating stably in a CCM region.SOLUTION: A DC-DC converter 1 has a coil L, a switch SW11 for storing energy in the coil L, and switch circuits 21, 22, 23 connected in cascade between the coil L and output terminals Po1-Po4. The DC-DC converter 1 has a first control unit 30 for controlling on/off of the switch 11 on the basis of the result of all output voltages Vo1-Vo4 being synthesized, so that the result is brought closer to a first target value. The DC-DC converter 1 has second to fourth control units 40, 50, 60 for controlling on/off of the switch circuit 21 on the basis of the result of output voltages Vo2-Vo4 being synthesized, controlling on/off of the switch circuit 22 on the basis of the result of output voltages Vo3 and Vo4 being synthesized, and controlling on/off of the switch circuit 23 on the basis of only the output voltage Vo4.

Description

  The present invention relates to a power supply apparatus and a power supply control method.

  Electronic devices such as personal computers and mobile phones have a built-in switching power supply circuit (DC-DC converter) that supplies a drive voltage to an internal circuit that performs signal processing. The switching power supply circuit converts a DC voltage supplied from, for example, an AC adapter or a battery into a driving voltage suitable for the operation of the internal circuit. For example, the switching power supply circuit controls on / off of the main switch to boost and step down the DC input voltage to generate a DC output voltage, and feed back the DC output voltage supplied to the load to a constant target voltage. Control is in progress.

  Incidentally, in recent years, with the widespread use of portable electronic devices such as notebook personal computers and mobile phones, there is an increasing demand for miniaturization of the switching power supply circuit. Therefore, in order to meet such a demand, a single inductor multiple output (SIMO) DC-DC converter capable of obtaining a plurality of outputs with one inductor (coil) has been proposed. In this type of DC-DC converter, since a single inductor is shared by a plurality of outputs, an increase in the number of components and an increase in circuit area due to an increase in the number of outputs can be suppressed.

  In the multi-output type DC-DC converter, a switching cycle is assigned in advance for each output (load), and necessary power is supplied to each load within each switching cycle. For example, when there are two loads, switching periods are alternately assigned to the two loads. In each switching cycle, the time (duty ratio) for turning on the main switch for causing the current corresponding to the input voltage to flow through the single inductor is adjusted according to the weight of the corresponding load. For this reason, in order to stably operate such a DC-DC converter, it is necessary to make the coil current flowing through the inductor zero before the end of each switching cycle. That is, in order to stably operate the DC-DC converter, it is necessary to operate in a discontinuous conduction mode (DCM) in which the change of the coil current IL is discontinuous in each switching period. This is because, when operated in a continuous current mode (CCM) in which the coil current IL continuously changes in each switching cycle, the energy remaining in the inductor is transferred to another load in the next switching cycle. This is because the output voltage becomes unstable. However, when the DC-DC converter is operated with DCM, there is a problem that the efficiency is lower than when the DC-DC converter is operated with CCM.

  Therefore, single inductor multi-output DC-DC converters that can operate with CCM have been proposed (see, for example, Patent Documents 1 to 3 and Non-Patent Document 1). FIG. 16 shows an example of this type of DC-DC converter. The DC-DC converter 7 shown in FIG. 16 is a synchronous rectification step-down DC-DC converter that generates two output voltages Vo21 and Vo22 lower than the input voltage Vi based on the input voltage Vi.

  As shown in FIG. 16, the DC-DC converter 7 includes a main-side switch SW61 to which an input voltage Vi is supplied, a synchronization-side switch SW62, and an inductor connected to a connection point between the switches SW61 and SW62 ( Coil) L11. The DC-DC converter 7 includes output-side switches SW63 and SW64 connected in common to the coil L11, and capacitors C21 and C22 connected to the switches SW63 and SW64, respectively. In addition, the DC-DC converter 7 generates a feedback voltage VFB21 corresponding to a voltage obtained by adding two output voltages Vo21 and Vo22, and an error signal S11 obtained by amplifying a difference voltage between the feedback voltage VFB21 and the reference voltage Vr1. And an error amplifying circuit 112 for generating. The DC-DC converter 7 includes a PWM (Pulse Width Modulation) control circuit 113 that performs on / off control of the main switch SW61 and the synchronization switch SW62 in a complementary manner based on the error signal S11. Further, the DC-DC converter 7 includes an error amplifying circuit 115, a circuit 114 that generates a signal S12 corresponding to a difference voltage between the two output voltages Vo21 and Vo22, and an output-side switch SW63 based on the signal S12. And a PWM control circuit 116 for performing on / off control of the SW 64 in a complementary manner.

  As described above, in the DC-DC converter 7, the switches SW61 and SW62 on the input side are controlled based on the sum of the two output voltages Vo21 and Vo22, and the switches SW63 and SW64 on the output side are controlled by the two output voltages Vo21 and Vo22. Control is based on the difference voltage.

US Pat. No. 7,538,527 US Pat. No. 7,312,538 US Patent Application Publication No. 2008/0130331

D. Trevisan et al ,: Digital Control of Single-Inductor Multiple-Output Step-Down DC-DC Converters in CCM, IEEE TRANSACTIONS ON INDUSTRAIL ELECTRONICS, VOL.55, NO.9, SEPTEMBER 2008, 3746-3483.

  However, the DC-DC converter 7 has a problem that the voltage accuracy of the output voltages Vo21 and Vo22 is poor. That is, the output voltages Vo21 and Vo22 are affected by the relative variation of all the resistances and the offset variation of all the error amplification circuits 112 and 115 existing in the two feedback loops. For this reason, the voltage accuracy of the two output voltages Vo21 and Vo22 is poor.

  According to one aspect of the present invention, a coil, a first switch circuit connected to the first terminal of the coil and storing energy in the coil, and a second terminal of the coil and N (N is 3 or more) Based on a first synthesized voltage obtained by synthesizing N output voltages respectively generated at the N first output terminals, and a second switch circuit provided between the first output terminals and a natural number of the first output terminals. A first control unit that generates a first control signal for controlling on / off of the first switch circuit so that the first composite voltage approaches a first target value; and one of the N output voltages. Based on the remaining (N−1) second output voltages excluding the first output voltage, the same as the first control signal so that each of the second output voltages approaches the corresponding second target value. A plurality of second switches that turn on / off the second switch circuit in a cycle. A second control unit for generating a control signal, wherein the second switch circuit is connected in cascade between a second terminal of the coil and N first output terminals, and the plurality The first output terminal of any one of the N first output terminals is selectively connected to the second terminal of the coil according to the combination of the signal levels of the second control signals. The third switch circuit, each of the third switch circuits has two switch elements, and the second switch circuit has the second switch circuit of the (N−1) third switch circuits. The two switch elements are connected in common to the second terminal of the coil, and the two switch elements included in the second and subsequent third switch circuits among the (N-1) third switch circuits are the previous ones. Of the two switch elements of the third switch circuit. They are connected in common to the output terminal of the square of the switching element.

  According to one aspect of the present invention, it is possible to improve the voltage accuracy of the output voltage while stably operating in the CCM region.

The block circuit diagram which shows the DC-DC converter of 1st Embodiment. The block circuit diagram which shows the internal structural example of a PWM control circuit. (A), (b) is explanatory drawing which shows operation | movement of the DC-DC converter of 1st Embodiment. (A)-(c) is explanatory drawing which shows operation | movement of the DC-DC converter of 1st Embodiment. The timing chart which shows operation | movement of the DC-DC converter of 1st Embodiment. The block circuit diagram which shows the example of application of the DC-DC converter of 1st Embodiment. The circuit diagram which shows the internal structural example of a general purpose control circuit. The block circuit diagram which shows the conventional DC-DC converter. The block circuit diagram which shows the DC-DC converter of a modification. The timing chart which shows the operation | movement of the DC-DC converter of a modification. The block circuit diagram which shows the DC-DC converter of 2nd Embodiment. The timing chart which shows the operation | movement of the DC-DC converter of 2nd Embodiment. (A)-(c) is explanatory drawing which shows operation | movement of the DC-DC converter of 2nd Embodiment. (A), (b) is explanatory drawing which shows operation | movement of the DC-DC converter of 2nd Embodiment. The block circuit diagram which shows the application example of the DC-DC converter of 2nd Embodiment. The block circuit diagram which shows the conventional DC-DC converter.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the DC-DC converter 1 is a single inductor multi-output type that generates N (here, four) output voltages Vo1, Vo2, Vo3, and Vo4 with one inductor (coil) L. It is a DC-DC converter. The DC-DC converter 1 is a synchronous rectification step-down DC-DC converter that generates four output voltages Vo1 to Vo4 lower than the input voltage Vin based on the input voltage Vin supplied to the input terminal Pi. It is. The output voltage Vo1 is supplied to the load 2 connected to the output terminal Po1, and the output voltage Vo2 is supplied to the load 3 connected to the output terminal Po2. The output voltage Vo3 is supplied to the load 4 connected to the output terminal Po3, and the output voltage Vo4 is supplied to the load 5 connected to the output terminal Po4. Here, as examples of the loads 2, 3, 4, and 5, an internal circuit of a portable electronic device (a personal computer, a mobile phone, a game device, a digital camera, etc.) and other electronic devices, or a notebook personal computer Examples include a built-in rechargeable battery such as a lithium battery.

  The DC-DC converter 1 includes a converter unit 10, an output-side switch circuit 20, capacitors C1, C2, C3, and C4, a first control unit 30, and a second control unit that controls on / off of the switch circuit 20. 40, the third control unit 50, the fourth control unit 60, and an oscillator 70.

  In the converter unit 10, a switch SW11 and a switch SW12 are connected in series between an input terminal Pi to which the input voltage Vin is supplied and a power supply line (here, ground) having a potential lower than the input voltage Vin. Yes. These switches SW11 and SW12 are, for example, N-channel MOS transistors.

  The first terminal of the switch SW11 is connected to the input terminal Pi, and the second terminal of the switch SW11 is connected to the first terminal of the switch SW12. The second terminal of the switch SW12 is connected to the ground.

  The control signal VH1 is supplied from the first control unit 30 to the control terminal of the switch SW11, and the control signal VL1 is supplied from the first control unit 30 to the control terminal of the switch SW12. These input-side switches SW11 and SW12 are complementarily turned on and off in response to the control signals VH1 and VL1.

A connection point between the switches SW11 and SW12 is connected to the first terminal LX of the coil L. The switch circuit 20 is connected to the second terminal LY of the coil L.
The switch circuit 20 includes (N−1) (three in this case) switch circuits 21, 22, and 23 connected in cascade between the second terminal LY of the coil L and the output terminals Po1 to Po4. doing.

  The switch circuit 21 includes a switch SW21 and a switch SW22 that are commonly connected to the second terminal LY of the coil L. These switches SW21 and SW22 are, for example, N-channel MOS transistors.

  The first terminal of the switch SW21 is connected to the second terminal LY of the coil L, and the second terminal (output terminal) of the switch SW21 is connected to the first terminal of the capacitor C1 and the output terminal Po1. The second terminal of the capacitor C1 is connected to the ground. Then, an output voltage Vo1 that is a voltage across the capacitor C1 is supplied to the load 2 from the output terminal Po1. The capacitor C1 is included in a smoothing circuit that smoothes the output voltage Vo1. On the other hand, the first terminal of the switch SW22 is connected to the second terminal LY of the coil L, and the second terminal (output terminal) of the switch SW22 is connected to the switch circuit 22.

  The control signal VH2 is supplied from the second control unit 40 to the control terminal of the switch SW21, and the control signal VL2 is supplied from the second control unit 40 to the control terminal of the switch SW22. These switches SW21 and SW22 are turned on / off complementarily in response to the control signals VH2 and VL2.

  The switch circuit 22 includes a switch SW31 and a switch SW32 that are commonly connected to the second terminal of the switch SW22. The switches SW31 and SW32 are connected in series with the switch SW22. These switches SW31 and SW32 are, for example, N-channel MOS transistors.

  The first terminal of the switch SW31 is connected to the second terminal of the switch SW22, and the second terminal (output terminal) of the switch SW31 is connected to the first terminal of the capacitor C2 and the output terminal Po2. That is, the second terminal LY of the coil L is connected to the output terminal Po2 via the switch SW31 and the switch SW22 connected in series (cascade). The second terminal of the capacitor C2 is connected to the ground. Then, an output voltage Vo2 that is a voltage across the capacitor C2 is supplied to the load 3 from the output terminal Po2. The capacitor C2 is included in a smoothing circuit that smoothes the output voltage Vo2. On the other hand, the first terminal of the switch SW32 is connected to the second terminal of the switch SW22, and the second terminal (output terminal) of the switch SW32 is connected to the switch circuit 23.

  The control signal VH3 is supplied from the third control unit 50 to the control terminal of the switch SW31, and the control signal VL3 is supplied from the third control unit 50 to the control terminal of the switch SW32. These switches SW31 and SW32 are turned on / off complementarily in response to the control signals VH3 and VL3.

  The switch circuit 23 includes a switch SW41 and a switch SW42 that are commonly connected to the second terminal of the switch SW32. The switches SW41 and SW42 are connected in series with the switch SW32. These switches SW41 and SW42 are, for example, N-channel MOS transistors.

  The first terminal of the switch SW41 is connected to the second terminal of the switch SW32, and the second terminal (output terminal) of the switch SW41 is connected to the first terminal of the capacitor C3 and the output terminal Po3. That is, the second terminal LY of the coil L is connected to the output terminal Po3 via the switch SW41, the switch SW32, and the switch SW22 that are connected in series (cascade). The second terminal of the capacitor C3 is connected to the ground. Then, an output voltage Vo3 that is a voltage across the capacitor C3 is supplied to the load 4 from the output terminal Po3. The capacitor C3 is included in a smoothing circuit that smoothes the output voltage Vo3.

  On the other hand, the first terminal of the switch SW42 is connected to the second terminal of the switch SW32, and the second terminal (output terminal) of the switch SW42 is connected to the first terminal of the capacitor C4 and the output terminal Po4. That is, the second terminal LY of the coil L is connected to the output terminal Po4 via the switch SW42, the switch SW32, and the switch SW22 that are connected in series (cascade). The second terminal of the capacitor C4 is connected to the ground. Then, an output voltage Vo4 that is a voltage across the capacitor C4 is supplied to the load 5 from the output terminal Po4. The capacitor C4 is included in a smoothing circuit that smoothes the output voltage Vo4.

  The control signal VH4 is supplied from the fourth control unit 60 to the control terminal of the switch SW41, and the control signal VL4 is supplied from the fourth control unit 60 to the control terminal of the switch SW42. These switches SW41 and SW42 are complementarily turned on / off in response to control signals VH4 and VL4.

  All four output terminals Po1 to Po4 are connected to the first control unit 30, and all four output voltages Vo1 to Vo4 are fed back. The first control unit 30 combines the output voltage Vo1, the output voltage Vo2, the output voltage Vo3, and the output voltage Vo4 based on the result (synthetic voltage Vout1), and uses the combined voltage Vout1 as a target voltage (first target value). The switches SW11 and SW12 are turned on / off so as to be close to each other. In other words, the first control unit 30 adjusts the ON time of the switch SW11 based on the combined voltage Vout1 so that desired power is supplied to the loads 2, 3, 4, and 5. Specifically, the first control unit 30 switches the control signals VH1 and VL1 whose frequency (period) is constant and whose pulse width varies according to the power supplied to the loads 2, 3, 4 and 5 to the switches SW11 and SW12. To supply.

The first control unit 30 includes a first feedback voltage generation circuit 31, an error amplification circuit 32, and a PWM control circuit 33.
The first feedback voltage generation circuit 31 generates a first feedback voltage VFB1 corresponding to a combined voltage Vout1 obtained by adding all four output voltages of the output voltage Vo1, the output voltage Vo2, the output voltage Vo3, and the output voltage Vo4. . The first feedback voltage generation circuit 31 includes resistors R1, R2, R3, and R4 connected to output terminals Po1, Po2, Po3, and Po4, and resistors commonly connected to the resistors R1, R2, R3, and R4, respectively. R5. Specifically, the output terminal Po1 is connected to the first terminal of the resistor R1, and the second terminal of the resistor R1 is connected to the first terminal of the resistor R5. The output terminal Po2 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected to the first terminal of the resistor R5. The output terminal Po3 is connected to the first terminal of the resistor R3, and the second terminal of the resistor R3 is connected to the first terminal of the resistor R5. The output terminal Po4 is connected to the first terminal of the resistor R4, and the second terminal of the resistor R4 is connected to the first terminal of the resistor R5. The second terminal of the resistor R5 is connected to the ground. A node N1 between the resistors R1, R2, R3, R4 and the resistor R5 is connected to the inverting input terminal of the error amplifier circuit 32.

  In such a first feedback voltage generation circuit 31, the resistors R1 and R5 generate a divided voltage obtained by dividing the output voltage Vo1 according to the respective resistance values, and the resistors R2 and R5 have respective resistance values. Accordingly, a divided voltage obtained by dividing the output voltage Vo2 is generated. The resistors R3 and R5 generate a divided voltage obtained by dividing the output voltage Vo3 according to the respective resistance values, and the resistors R4 and R5 divide the output voltage Vo4 according to the respective resistance values. The divided voltage is generated. Then, a first feedback voltage VFB1 obtained by adding the divided voltage of the output voltage Vo1, the divided voltage of the output voltage Vo2, the divided voltage of the output voltage Vo3, and the divided voltage of the output voltage Vo4 is generated at the node N1. Will be. Here, the value of the divided voltage of the output voltage Vo1 corresponds to the ratio of the resistance values of the resistors R1 and R5 and the potential difference between the output voltage Vo1 and the ground, and the value of the divided voltage of the output voltage Vo2 is This corresponds to the ratio of the resistance values of the resistors R2 and R5 and the potential difference between the output voltage Vo2 and the ground. The value of the divided voltage of the output voltage Vo3 corresponds to the ratio of the resistance values of the resistors R3 and R5 and the potential difference between the output voltage Vo3 and the ground, and the value of the divided voltage of the output voltage Vo4 is the resistance value. This corresponds to the ratio of the resistance values of R4 and R5 and the potential difference between the output voltage Vo4 and the ground. Therefore, the first feedback voltage generation circuit 31 (resistors R1 to R5) generates the first feedback voltage VFB1 proportional to the combined voltage Vout1 obtained by adding the output voltage Vo1, the output voltage Vo2, the output voltage Vo3, and the output voltage Vo4. Will be generated. The first feedback voltage VFB1 is supplied to the inverting input terminal of the error amplifier circuit 32.

  The reference voltage Vr generated by the reference power supply E1 is supplied to the non-inverting input terminal of the error amplifier circuit 32. Here, the reference voltage Vr is a voltage that matches the first feedback voltage VFB1 when the combined voltage Vout1 reaches a target voltage (standard value).

The error amplifier circuit 32 compares the first feedback voltage VFB1 with the reference voltage Vr, and outputs an error signal S1 obtained by amplifying the difference voltage between the two voltages to the PWM control circuit 33.
The PWM control circuit 33 is supplied with a periodic signal CK having a predetermined period T (see FIG. 5) from the oscillator 70. The periodic signal CK is, for example, a sawtooth wave signal (a sawtooth waveform signal that rises from a reference value with a predetermined rising characteristic and rapidly drops to a reference value upon reset). The PWM control circuit 33 generates control signals VH1 and VL1 for performing on / off control of the switches SW11 and SW12 in a complementary manner according to the comparison result between the error signal S1 and the periodic signal CK. For example, the PWM control circuit 33 generates an H level control signal VH1 and an L level control signal VL1 when the periodic signal CK is lower than the error signal S1, and when the periodic signal CK is higher than the error signal S1. , An L level control signal VH1 and an H level control signal VL1 are generated. The switch SW11 is turned on in response to the H level control signal VH1, and is turned off in response to the L level control signal VH1. The switch SW12 is turned on in response to the H level control signal VL1, and turned off in response to the L level control signal VL1.

Next, an example of the internal configuration of the PWM control circuit 33 will be described.
As shown in FIG. 2, the PWM control circuit 33 includes a PWM comparison circuit 34, an anti-shoot-through circuit (AST) 35, and driver circuits 36 and 37.

  The error signal S <b> 1 is supplied from the error amplifier circuit 32 to the non-inverting input terminal of the PWM comparison circuit 34. A periodic signal CK is supplied from the oscillator 70 to the inverting input terminal of the PWM comparison circuit 34.

  The PWM comparison circuit 34 compares the error signal S1 with the periodic signal CK. The PWM comparison circuit 34 generates an L-level PWM signal SG1 when the level of the periodic signal CK is higher than the error signal S1, and the H-level PWM when the level of the periodic signal CK is lower than the error signal S1. A signal SG1 is generated. The PWM signal SG1 has the same cycle as the cycle T. The PWM signal SG1 is supplied to the AST 35.

  The AST 35 generates the control signals SH1 and SL1 based on the PWM signal SG1 so that the switches SW11 and SW12 of the converter unit 10 are turned on and off in a complementary manner and the switches SW11 and SW12 are not turned on at the same time. . For example, the AST 35 generates an L level control signal SH1 and an H level control signal SL1 based on the L level PWM signal SG1. The AST 35 generates an H level control signal SH1 and an L level control signal SL1 based on the H level PWM signal SG1.

  A control signal SH <b> 1 is supplied from the AST 35 to the driver circuit 36. The driver circuit 36 supplies the control signal VH1 having a signal level corresponding to the control signal SH1 to the control terminal of the switch SW11 (see FIG. 1). For example, the driver circuit 36 outputs the H level control signal VH1 to the switch SW11 in response to the H level control signal SH1, while the driver circuit 36 outputs the L level control signal VH1 to the switch SW11 in response to the L level control signal SH1. Output to.

  The driver circuit 37 is supplied with a control signal SL1 from the AST 35. The driver circuit 37 supplies the control signal VL1 having a signal level corresponding to the control signal SL1 to the control terminal of the switch SW12 (see FIG. 1). For example, the driver circuit 37 outputs the H level control signal VL1 to the switch SW12 in response to the H level control signal SL1, while the driver circuit 37 outputs the L level control signal VL1 to the switch SW12 in response to the L level control signal SL1. Output to.

These control signals VH1 and VL1 have the same cycle as the cycle T, similarly to the PWM signal SG1.
In the first controller 30 shown in FIGS. 1 and 2, the switches SW11 and SW12 are complementarily turned on / off so that the first feedback voltage VFB1 corresponding to the combined voltage Vout1 approaches the reference voltage Vr. Control signals VH1 and VL1 to be generated are generated. Accordingly, the combined voltage Vout1 of the output voltages Vo1, Vo2, Vo3, and Vo4 is controlled so as to approach the target voltage based on the reference voltage Vr and the resistance values of the resistors R1 to R5.

  As shown in FIG. 1, three output terminals Po2 to Po4 except for the output terminal Po1 among the four output terminals Po1 to Po4 are connected to the second control unit 40, and the four output voltages Vo1 to Vo4 are connected. The remaining output voltages Vo2 to Vo4 (second output voltage) excluding one output voltage Vo1 (first output voltage) are supplied. Specifically, the second control unit 40 is connected to output terminals Po2, Po3, and Po4 that are electrically connected to the output terminal of the switch SW22 included in the first-stage switch circuit 21 in the switch circuit 20. The output voltages Vo2, Vo3, and Vo4 generated at the output terminals Po2, Po3, and Po4, respectively, are supplied. Based on the result of combining the input output voltages Vo2, Vo3, and Vo4 (the combined voltage Vout2), the second control unit 40 is configured so that the combined voltage Vout2 approaches the target voltage (third target value). The switches SW21 and SW22 of the switch circuit 21 at the stage are turned on / off. In other words, the second control unit 40 adjusts the ON time of the switch SW22 so that desired power is supplied to the loads 3, 4, and 5 based on the combined voltage Vout2. Specifically, the second control unit 40 supplies the control signals VH2 and VL2 whose frequency (cycle) is constant and whose pulse width varies according to the power supplied to the loads 3, 4 and 5 to the switches SW21 and SW22. To do.

The second control unit 40 includes a second feedback voltage generation circuit 41, an error amplification circuit 42, and a PWM control circuit 43.
The second feedback voltage generation circuit 41 generates a second feedback voltage VFB2 corresponding to the combined voltage Vout2 obtained by adding the output voltage Vo2, the output voltage Vo3, and the output voltage Vo4. The second feedback voltage generation circuit 41 includes resistors R6, R7, R8 connected to the output terminals Po2, Po3, Po4, respectively, and a resistor R9 connected in common with the resistors R6, R7, R8. Yes. Specifically, the output terminal Po2 is connected to the first terminal of the resistor R6, and the second terminal of the resistor R6 is connected to the first terminal of the resistor R9. The output terminal Po3 is connected to the first terminal of the resistor R7, and the second terminal of the resistor R7 is connected to the first terminal of the resistor R9. The output terminal Po4 is connected to the first terminal of the resistor R8, and the second terminal of the resistor R8 is connected to the first terminal of the resistor R9. The second terminal of the resistor R9 is connected to the ground. A node N2 between the resistors R6, R7, R8 and the resistor R9 is connected to the inverting input terminal of the error amplifier circuit.

  In such a second feedback voltage generation circuit 41, the resistors R6 and R9 generate divided voltages obtained by dividing the output voltage Vo2 according to the respective resistance values, and the resistors R7 and R9 have respective resistance values. Accordingly, a divided voltage obtained by dividing the output voltage Vo3 is generated, and the resistors R8 and R9 generate divided voltages obtained by dividing the output voltage Vo4 according to the respective resistance values. Then, a second feedback voltage VFB2 obtained by adding the divided voltage of the output voltage Vo2, the divided voltage of the output voltage Vo3, and the divided voltage of the output voltage Vo4 is generated at the node N2. Here, the value of the divided voltage of the output voltage Vo2 corresponds to the ratio of the resistance values of the resistors R6 and R9 and the potential difference between the output voltage Vo2 and the ground, and the value of the divided voltage of the output voltage Vo3 is This corresponds to the ratio of the resistance values of the resistors R7 and R9 and the potential difference between the output voltage Vo3 and the ground. The value of the divided voltage of the output voltage Vo4 corresponds to the ratio of the resistance values of the resistors R8 and R9 and the potential difference between the output voltage Vo4 and the ground. Therefore, the second feedback voltage generation circuit 41 (resistors R6 to R9) generates the second feedback voltage VFB2 that is proportional to the combined voltage Vout2 obtained by adding the output voltage Vo2, the output voltage Vo3, and the output voltage Vo4. . The second feedback voltage VFB2 is supplied to the inverting input terminal of the error amplifier circuit 42.

  A reference voltage Vr generated by the reference power supply E1 is supplied to the non-inverting input terminal of the error amplifier circuit. Here, the reference voltage Vr is a voltage that matches the second feedback voltage VFB2 when the combined voltage Vout2 reaches a target voltage (standard value).

The error amplifier circuit 42 compares the second feedback voltage VFB2 with the reference voltage Vr, and outputs an error signal S2 obtained by amplifying the difference voltage between the two voltages to the PWM control circuit 43.
A periodic signal CK is supplied from the oscillator 70 to the PWM control circuit 43. Since the PWM control circuit 43 has substantially the same configuration as that of the PWM control circuit 33 shown in FIG. 2, illustration and detailed description thereof are omitted here. The PWM control circuit 43 generates control signals VH2 and VL2 for performing on / off control of the switches SW21 and SW22 in a complementary manner according to the comparison result between the error signal S2 and the periodic signal CK. For example, the PWM control circuit 43 generates an H level control signal VH2 and an L level control signal VL2 when the periodic signal CK is lower than the error signal S2, and when the periodic signal CK is higher than the error signal S2. , L level control signal VH2 and H level control signal VL2 are generated. These control signals VH2 and VL2 have the same period as the period T of the periodic signal CK. The switch SW21 is turned on in response to the H level control signal VH2, and is turned off in response to the L level control signal VH2. The switch SW22 is turned on in response to the H level control signal VL2, and is turned off in response to the L level control signal VL2.

  In such a second control unit 40, control signals VH2 and VL2 for complementary on / off control of the switches SW21 and SW22 are generated so that the second feedback voltage VFB2 corresponding to the combined voltage Vout2 approaches the reference voltage Vr. Is done. As a result, the combined voltage Vout2 of the output voltages Vo2, Vo3, and Vo4 is controlled so as to approach the target voltage based on the reference voltage Vr and the resistance values of the resistors R6 to R9.

  The third control unit 50 is connected to two output terminals Po3 and Po4 excluding the output terminal Po2 among the three output terminals Po2 to Po4 connected to the second control unit 40. Of the three output voltages Vo2, Vo3, and Vo4 fed back to (2), the remaining output voltages Vo3 and Vo4 excluding one output voltage Vo2 are supplied. Specifically, the third control unit 50 is connected to output terminals Po3 and Po4 electrically connected to the output terminal of the switch SW32 included in the second-stage switch circuit 22 in the switch circuit 20, Output voltages Vo3 and Vo4 generated respectively at the output terminals Po3 and Po4 are supplied. Based on the result of combining the input output voltages Vo3 and Vo4 (the combined voltage Vout3), the third control unit 50 makes the combined voltage Vout3 close to the target voltage (third target value). The switches SW31 and SW32 of the switch circuit 22 are turned on / off. In other words, the third control unit 50 adjusts the ON time of the switch SW32 based on the combined voltage Vout3 so that desired power is supplied to the loads 4 and 5. Specifically, the third control unit 50 supplies the control signals VH3 and VL3 whose frequency (cycle) is constant and whose pulse width varies according to the power supplied to the loads 4 and 5 to the switches SW31 and SW32.

The third control unit 50 includes a third feedback voltage generation circuit 51, an error amplification circuit 52, and a PWM control circuit 53.
The third feedback voltage generation circuit 51 generates a third feedback voltage VFB3 corresponding to the combined voltage Vout3 obtained by adding the output voltage Vo3 and the output voltage Vo4. The third feedback voltage generation circuit 51 includes resistors R10 and R11 connected to the output terminals Po3 and Po4, respectively, and a resistor R12 connected in common with the resistors R10 and R11. Specifically, the output terminal Po3 is connected to the first terminal of the resistor R10, and the second terminal of the resistor R10 is connected to the first terminal of the resistor R12. The output terminal Po4 is connected to the first terminal of the resistor R11, and the second terminal of the resistor R11 is connected to the first terminal of the resistor R12. The second terminal of the resistor R12 is connected to the ground. A node N3 between the resistors R10 and R11 and the resistor R12 is connected to the inverting input terminal of the error amplifier circuit 52.

  In such a third feedback voltage generation circuit 51, the resistors R10 and R12 generate divided voltages obtained by dividing the output voltage Vo3 according to the respective resistance values, and the resistors R11 and R12 have respective resistance values. Accordingly, a divided voltage obtained by dividing the output voltage Vo4 is generated. Then, a third feedback voltage VFB3 obtained by adding the divided voltage of the output voltage Vo3 and the divided voltage of the output voltage Vo4 is generated at the node N3. Here, the value of the divided voltage of the output voltage Vo3 corresponds to the ratio of the resistance values of the resistors R10 and R12 and the potential difference between the output voltage Vo3 and the ground, and the value of the divided voltage of the output voltage Vo4 is This corresponds to the ratio of the resistance values of the resistors R11 and R12 and the potential difference between the output voltage Vo4 and the ground. Therefore, the third feedback voltage generation circuit 51 (resistors R10 to R12) generates the third feedback voltage VFB3 proportional to the combined voltage Vout3 obtained by adding the output voltage Vo3 and the output voltage Vo4. The third feedback voltage VFB3 is supplied to the inverting input terminal of the error amplifier circuit 52.

  The reference voltage Vr generated by the reference power supply E1 is supplied to the non-inverting input terminal of the error amplifier circuit 52. Here, the reference voltage Vr is a voltage that matches the third feedback voltage VFB3 when the combined voltage Vout3 reaches a target voltage (standard value).

The error amplifier circuit 52 compares the third feedback voltage VFB3 with the reference voltage Vr, and outputs an error signal S3 obtained by amplifying the difference voltage between the two voltages to the PWM control circuit 53.
A periodic signal CK is supplied from the oscillator 70 to the PWM control circuit 53. Since the PWM control circuit 53 has substantially the same configuration as the PWM control circuit 33 shown in FIG. 2, illustration and detailed description thereof are omitted here. The PWM control circuit 53 generates control signals VH3 and VL3 for performing on / off control of the switches SW31 and SW32 in a complementary manner according to the comparison result between the error signal S3 and the periodic signal CK. For example, the PWM control circuit 53 generates an H level control signal VH3 and an L level control signal VL3 when the periodic signal CK is lower than the error signal S3, and when the periodic signal CK is higher than the error signal S3. , L level control signal VH3 and H level control signal VL3 are generated. These control signals VH3 and VL3 have the same period as the period T of the periodic signal CK. The switch SW31 is turned on in response to the H level control signal VH3 and turned off in response to the L level control signal VH3. The switch SW32 is turned on in response to the H level control signal VL3 and turned off in response to the L level control signal VL3.

  In such a third control unit 50, control signals VH3 and VL3 for generating on / off control of the switches SW31 and SW32 in a complementary manner are generated so that the third feedback voltage VFB3 corresponding to the combined voltage Vout3 approaches the reference voltage Vr. Is done. As a result, the combined voltage Vout3 of the output voltages Vo3 and Vo4 is controlled so as to approach the target voltage based on the reference voltage Vr and the resistance values of the resistors R10 to R12.

  One output terminal Po4 excluding the output terminal Po3 is connected to the fourth control unit 60 out of the two output terminals Po3 and Po4 connected to the third control unit 50, and is fed back to the third control unit 50. The remaining output voltage Vo4 excluding one output voltage Vo3 out of the two output voltages Vo3 and Vo4 thus supplied is supplied. Specifically, the output terminal Po4 connected to the output terminal of the switch SW42 included in the third-stage switch circuit 23 in the switch circuit 20 is connected to the fourth control unit 60, and the output terminal Po4 is connected to the output terminal Po4. The generated output voltage Vo4 is supplied. The fourth control unit 60 performs on / off control of the switches SW41 and SW42 based on the output voltage Vo4 so that the output voltage Vo4 approaches the target voltage (second target value). In other words, the fourth control unit 60 adjusts the ON time of the switch SW42 included in the third-stage switch circuit 23 so that desired power is supplied to the load 5 based on the output voltage Vo4. Specifically, the fourth control unit 60 supplies the switches SW41 and SW42 with control signals VH4 and VL4 having a constant frequency (period) and varying pulse widths according to the power supplied to the load 5.

The fourth control unit 60 includes a fourth feedback voltage generation circuit 61, an error amplification circuit 62, and a PWM control circuit 63.
The fourth feedback voltage generation circuit 61 generates a fourth feedback voltage VFB4 corresponding to the output voltage Vo4. The fourth feedback voltage generation circuit 61 includes resistors R13 and R14. Specifically, the output terminal Po4 is connected to the first terminal of the resistor R13, and the second terminal of the resistor R13 is connected to the first terminal of the resistor R14. The second terminal of the resistor R14 is connected to the ground. A node N4 between the resistors R13 and R14 is connected to the inverting input terminal of the error amplifier circuit 62. Here, the resistors R13 and R14 generate a fourth feedback voltage VFB4 obtained by dividing the output voltage Vo4 at the node N4 according to the respective resistance values. The value of the fourth feedback voltage VFB4 corresponds to the ratio of the resistance values of the resistors R13 and R14 and the potential difference between the output voltage Vo4 and the ground. Therefore, the resistors R13 and R14 generate the fourth feedback voltage VFB4 that is proportional to the output voltage Vo4. The fourth feedback voltage VFB4 is supplied to the inverting input terminal of the error amplification circuit 62.

  The reference voltage Vr is supplied to the non-inverting input terminal of the error amplifier circuit 62. Here, the reference voltage Vr is a voltage that matches the fourth feedback voltage VFB4 when the output voltage Vo4 reaches the target voltage (standard value).

The error amplification circuit 62 compares the fourth feedback voltage VFB4 with the reference voltage Vr, and outputs an error signal S4 obtained by amplifying the difference voltage between the two voltages to the PWM control circuit 63.
A periodic signal CK is supplied from the oscillator 70 to the PWM control circuit 63. Since the PWM control circuit 63 has substantially the same configuration as the PWM control circuit 33 shown in FIG. 2, illustration and detailed description thereof are omitted here. The PWM control circuit 63 generates control signals VH4 and VL4 for performing on / off control of the switches SW41 and SW42 in a complementary manner according to the comparison result between the error signal S4 and the periodic signal CK. For example, the PWM control circuit 63 generates an H level control signal VH4 and an L level control signal VL4 when the periodic signal CK is lower than the error signal S4, and when the periodic signal CK is higher than the error signal S4. , An L level control signal VH4 and an H level control signal VL4 are generated. These control signals VH4 and VL4 have the same period as the period T of the periodic signal CK. The switch SW41 is turned on in response to the H level control signal VH4 and turned off in response to the L level control signal VH4. The switch SW42 is turned on in response to the H level control signal VL4 and turned off in response to the L level control signal VL4.

  In such a fourth control unit 60, control signals VH4 and VL4 for complementary on / off control of the switches SW41 and SW42 are generated so that the fourth feedback voltage VFB4 corresponding to the output voltage Vo4 approaches the reference voltage Vr. Is done. Thereby, the output voltage Vo4 is controlled so as to approach the target voltage based on the reference voltage Vr and the resistance values of the resistors R13 and R14.

  In this embodiment, the switch SW11 is an example of a first switch circuit, the switch circuit 20 is an example of a second switch circuit, the switch circuits 21, 22, and 23 are examples of a third switch circuit, and the switch circuit 21 is a first-stage switch. An example of the circuit, the switch circuits 22 and 23, is an example of a switch circuit in the second and subsequent stages. The switches SW21, SW22, SW31, SW32, SW41, and SW42 are examples of switch elements, the switches SW31 and SW41 are examples of first switch elements, and the switches SW32 and SW42 are examples of second switch elements. The output terminals Po1 to Po4 are examples of the first output terminal, the output voltage Vo1 is an example of the first output voltage, the output voltages Vo2 to Vo4 are examples of the second output voltage, and the first control unit 30 is the first control unit. The second to fourth control units 40, 50, 60 are examples of the second control unit. The control signals VH1 and VL1 are examples of the first control signal, the control signals VH2, VL2, VH3, VL3, VH4, and VL4 are examples of the second control signal, the combined voltage Vout1 is an example of the first combined voltage, and the combined voltage Vout2 Is an example of the second synthesized voltage, and the synthesized voltage Vout3 and the output voltage Vo4 are examples of the third synthesized voltage.

Next, the operation of the DC-DC converter 1 will be described with reference to FIGS. In FIG. 5, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
When the periodic signal CK is reset to the reference value at a constant period T at time t1 shown in FIG. 5, the level of the periodic signal CK becomes lower than the error signals S1, S2, S3, S4. Then, H level control signals VH1, VH2, VH3, and VH4 are output from the PWM control circuits 33, 43, 53, and 63, respectively, and L level control signals VL1, VL2, VL3, and VL4 are output. As a result, the switches SW11, SW21, SW31, SW41 are turned on, and the switches SW12, SW22, SW32, SW42 are turned off. Then, as shown in FIG. 3A, the input terminal Pi is connected to the first terminal LX of the coil L through the switch SW11, and the second terminal LY of the coil L is connected to the output terminal Po1 through the switch SW21. For this reason, a current path from the input terminal Pi to the output terminal Po1 through the coil L is formed. During this connection state, specifically, in the first period P1 from time t1 to time t2 shown in FIG. 5, the coil current IL corresponding to the input voltage Vin flows through the coil L, and energy is stored in the coil L. Is done. In the first period P1, the coil current IL increases with a predetermined slope as time passes. Specifically, the increasing slope m1 of the coil current IL in the first period P1 is that the voltage values of the input voltage Vin and the output voltage Vo1 are Vin and Vo1, respectively, and the inductance value of the coil L is L.

It becomes. That is, the coil current IL in the first period P1 increases in proportion to the potential difference between the input voltage Vin and the output voltage Vo1.

  Next, when the level of the periodic signal CK that gradually increases with a predetermined rising characteristic from time t1 becomes higher than the error signal S1 (see time t2), the PWM control circuit 33 controls the L level control signals VH1 and H level. Signal VL1 is output. The switch SW11 is turned off in response to the L level control signal VH1, and the switch SW12 is turned on in response to the H level control signal VL1. Then, as shown in FIG. 3B, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po1 through the switch SW21. For this reason, a current path from the ground to the output terminal Po1 through the coil L is formed. During this connection state, specifically, in the second period P2 from time t2 to time t3 shown in FIG. 5, the energy stored in the coil L in the first period P1 is directed toward the output terminal Po1. The induced current flows through the coil L. In the second period P2, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decreasing slope m2 of the coil current IL in the second period P2 is

It becomes. That is, the coil current IL in the second period P2 decreases in proportion to the output voltage Vo1.

  Subsequently, when the level of the periodic signal CK becomes higher than the error signal S2 (see time t3), the PWM control circuit 43 outputs an L level control signal VH2 and an H level control signal VL2. The switch SW21 is turned off in response to the L level control signal VH2, and the switch SW22 is turned on in response to the H level control signal VL2. Then, as shown in FIG. 4A, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po2 through the switch SW22 and the switch SW31. . For this reason, a current path from the ground to the output terminal Po2 through the coil L is formed. During this connection state, specifically, in the third period P3 from time t3 to time t4 shown in FIG. 5, the energy stored in the coil L in the first period P1 is directed toward the output terminal Po2. The induced current flows through the coil L. In the third period P3, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decrease slope m3 of the coil current IL in the third period P3 is given by assuming that the voltage value of the output voltage Vo2 is Vo2.

It becomes. That is, the coil current IL in the third period P3 decreases in proportion to the output voltage Vo2.

  Next, when the level of the periodic signal CK becomes higher than the error signal S3 (see time t4), the PWM control circuit 53 outputs an L level control signal VH3 and an H level control signal VL3. The switch SW31 is turned off in response to the L level control signal VH3, and the switch SW32 is turned on in response to the H level control signal VL3. Then, as shown in FIG. 4B, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po3 through the switch SW22, the switch SW32, and the switch SW41. Connected. For this reason, a current path from the ground to the output terminal Po3 through the coil L is formed. During this connection state, specifically, in the fourth period P4 from time t4 to time t5 shown in FIG. 5, the energy stored in the coil L in the first period P1 is directed toward the output terminal Po3. The induced current flows through the coil L. In the fourth period P4, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decrease slope m4 of the coil current IL in the fourth period P4 is given by assuming that the voltage value of the output voltage Vo3 is Vo3.

It becomes. That is, the coil current IL in the fourth period P4 decreases in proportion to the output voltage Vo3.

  Next, when the level of the periodic signal CK becomes higher than the error signal S4 (see time t5), the PWM control circuit 63 outputs an L level control signal VH4 and an H level control signal VL4. The switch SW41 is turned off in response to the L level control signal VH4, and the switch SW42 is turned on in response to the H level control signal VL4. Then, as shown in FIG. 4C, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po4 through the switch SW22, the switch SW32 and the switch SW42. Connected. For this reason, a current path from the ground to the output terminal Po4 through the coil L is formed. During this connection state, specifically, in the fifth period P5 from time t5 to time t6 shown in FIG. 5, the energy stored in the coil L in the first period P1 is directed toward the output terminal Po4. The induced current flows through the coil L. In the fifth period P5, the coil current IL decreases with a predetermined slope as time passes. Specifically, the decrease slope m5 of the coil current IL in the fifth period P5 is given by assuming that the voltage value of the output voltage Vo4 is Vo4.

It becomes. That is, the coil current IL in the fifth period P5 decreases in proportion to the output voltage Vo4.

  Thereafter, when the periodic signal CK is reset to the reference value again at a constant period T (see time t6), the switches SW11, SW21, SW31, SW41 are turned on, and the switches SW12, SW22, SW32, SW42 are turned off. The Thereby, the next period T is started, and in the period T, the first period P1, the second period P2, the third period P3, the fourth period P4, and the fifth period P5 are executed in this order. Is done.

  Here, the average value of the coil current IL in each cycle T (the first period P1 to the fifth period P5) is the sum of the output currents Io1, Io2, Io3, and Io4 supplied to the loads 2, 3, 4, and 5. The value is Io1 + Io2 + Io3 + Io4. Further, an average value obtained by averaging the total amount of the coil current IL (refer to the area A1) in the period in which the switch SW21 is on (first period P1 and second period P2) in the period T is supplied to the load 2. Output current Io1. In addition, an average value obtained by averaging the total amount of the coil current IL (refer to the region A2) in the period T during the period when the two switches SW22 and SW31 are on (third period P3) in the period T is the load 3. The output current Io2 is supplied. In addition, an average value obtained by averaging the total amount of the coil current IL (refer to the region A3) in the period T during the period in which the three switches SW22, SW32, and SW41 are on (fourth period P4) is obtained. The output current Io3 supplied to the load 4 is obtained. And the average value which averaged the total amount (refer area | region A4) of the coil electric current IL in the period (5th period P5) in which the three switches of switch SW22, switch SW32, and switch SW42 are ON in the period T is obtained. The output current Io4 is supplied to the load 5.

  Next, feedback control by the first control unit 30, the second control unit 40, the third control unit 50, and the fourth control unit 60 will be described in detail. First, feedback control by the first control unit 30 will be described.

  In the series of operations in each cycle T described above, when the combined voltage Vout1 of the output voltages Vo1 to Vo4 becomes higher than the target voltage, that is, when the first feedback voltage VFB1 becomes higher than the reference voltage Vr, the error amplification circuit 32 outputs it. Error signal S1 decreases. Then, the H level pulse width of the control signal VH1 is shortened, and the ON time of the switch SW11, that is, the first period P1 in which energy is stored in the coil L is shortened. As a result, the amount of coil current IL flowing through the coil L in the first period P1 decreases, and the energy accumulated in the coil L decreases. Accordingly, the energy released from the coil L toward the output terminals Po1 to Po4 in the second period P2 to the fifth period P5 decreases. Accordingly, the total amount of the coil current IL supplied to the capacitors C1 to C4 is reduced, so that the combined voltage Vout1 is lowered.

  On the contrary, when the combined voltage Vout1 becomes lower than the target voltage, that is, when the first feedback voltage VFB1 becomes lower than the reference voltage Vr, the error signal S1 increases. Then, the H level pulse width of the control signal VH1 becomes longer, and the first period P1 in which energy is stored in the coil L becomes longer. As a result, the amount of coil current IL flowing through the coil L in the first period P1 increases, and the energy accumulated in the coil L increases. Along with this, energy released from the coil L toward the output terminals Po1 to Po4 in the second period P2 to the fifth period P5 increases. Therefore, since the total amount of the coil current IL supplied to the capacitors C1 to C4 increases, the combined voltage Vout1 increases. By such an operation, the combined voltage Vout1 is maintained at a target voltage (a constant value) based on the reference voltage Vr and the resistors R1 to R5.

  As described above, in the first control unit 30, based on the combined voltage Vout1 (first combined voltage), the ON time of the switch SW11 is set so that the combined voltage Vout1 approaches the target voltage based on the reference voltage Vr and the resistors R1 to R5. Is controlled. In other words, in the first control unit 30, the coil current IL is such that a desired current supplied to the loads 2 to 5, that is, the total value Io1 + Io2 + Io3 + Io4 of the output currents Io1, Io2, Io3, and Io4 flows based on the combined voltage Vout1. The total amount of current is controlled (see areas A1 and A2 shown in FIG. 5).

Next, feedback control by the second control unit 40 will be described.
In the series of operations in each cycle T, when the combined voltage Vout2 of the output voltages Vo2 to Vo4 becomes higher than the target voltage, that is, when the second feedback voltage VFB2 becomes higher than the reference voltage Vr, the error amplification circuit 42 outputs the voltage. The error signal S2 decreases. Then, the H level pulse width of the control signal VL2 becomes longer, and the ON time of the switch SW22, that is, the time during which the second terminal LY of the coil L is connected to the output terminals Po2, Po3, Po4 (the third period P3 to the third period). 5 period P5) becomes longer. That is, the output terminals Po2, Po3, Po4 (capacitors C2, C3, C4) are connected to the ground through the coil L, and the time during which the coil current IL is supplied to the capacitors C2, C3, C4 becomes longer. As a result, the combined voltage Vout2 of the output voltages Vo2 to Vo4 is lowered. On the other hand, assuming that the combined voltage Vout1 is constant, when the combined voltage Vout2 becomes higher than the target voltage, the remaining output voltage Vo1 becomes lower than the target voltage. At this time, when the error signal S2 decreases as described above, the H level pulse width of the control signal VH2 is shortened, and the time for which both the switch SW12 and the switch SW21 are turned on is shortened. That is, the output terminal Po1 (capacitor C1) is connected to the ground through the coil L, and the time during which the coil current IL is supplied to the capacitor C1 is shortened. As a result, the output voltage Vo1 increases.

  On the contrary, when the synthesized voltage Vout2 becomes lower than the target voltage, that is, when the second feedback voltage VFB2 becomes lower than the reference voltage Vr, the error signal S2 increases. Then, the H-level pulse width of the control signal VL2 is shortened, and the ON time of the switch SW22, that is, the times of the third to fifth periods P3 to P5 are lengthened. As a result, the combined voltage Vout2 of the output voltages Vo2 to Vo4 increases. On the other hand, assuming that the combined voltage Vout1 is constant, when the combined voltage Vout2 becomes lower than the target voltage, the remaining output voltage Vo1 becomes higher than the target voltage. At this time, when the error signal S2 rises as described above, the H level pulse width of the control signal VH2 becomes longer, and the time during which both the switch SW12 and the switch SW21 are turned on becomes longer. As a result, the output voltage Vo1 is lowered. By such an operation, the combined voltage Vout2 is maintained at a target voltage (a constant value) based on the reference voltage Vr and the resistors R6 to R9. Accordingly, the output voltage Vo1 is also maintained at the target voltage (constant).

  As described above, in the second control unit 40, based on the composite voltage Vout2 (second composite voltage), the switch SW22 is turned on so that the composite voltage Vout2 approaches the target voltage based on the reference voltage Vr and the resistors R6 to R9. Time is controlled. In other words, in the second control unit 40, the capacitors C 2, I 2, Io 3, Io 4 so that the desired current supplied to the loads 3, 4, 5, that is, the total value Io 2 + Io 3 + Io 4, flows based on the combined voltage Vout 2. The time width necessary for supplying the coil current IL to C3 and C4 (output terminals Po2, Po3 and Po4) is controlled (determined). The remaining time excluding the determined time width from the cycle T or the ON time of the switch SW12 (OFF time of the switch SW11) is a capacitor connected to the output terminal Po1 not connected to the second control unit 40. This is used as the time for supplying the coil current IL to C1. Thus, in the second control unit 40, the ratio of the period for distributing the coil current IL to the capacitors C2 to C4 and the capacitor C1 based on the three output voltages Vo2 to Vo4 of the four output voltages Vo1 to Vo4 is Be controlled.

  Next, feedback control by the third control unit 50 will be described. The feedback control by the third control unit 50 is performed in the same manner as the feedback control by the second control unit 40 described above, and detailed description thereof is omitted here.

  In the third control unit 50, similar to the second control unit 40, based on the combined voltage Vout3 (third combined voltage) of the output voltages Vo3 and Vo4, the combined voltage Vout3 is based on the reference voltage Vr and the resistors R10 to R12. The on-time of the switch SW32 is controlled so as to approach the target voltage. In other words, in the third control unit 50, the capacitors C3 and C4 (output terminals) so that a desired current supplied to the loads 4 and 5, that is, the total value Io3 + Io4 of the output currents Io3 and Io4 flows based on the combined voltage Vout3. The time width required to supply the coil current IL to Po3, Po4) is controlled (determined). In order to supply the coil current IL to the capacitors C1 and C2 connected to the output terminals Po1 and Po2, which are not connected to the third control unit 50, the remaining time excluding the determined time width from the period T. Used as a time. As described above, the third control unit 50 distributes the coil current IL to the capacitors C3 and C4 and the capacitors C1 and C2 based on the two output voltages Vo3 and Vo4 out of the four output voltages Vo1 to Vo4. The rate is controlled. By such feedback control by the third control unit 50, the combined voltage Vout3 is maintained at a target voltage (a constant value) based on the reference voltage Vr and the resistors R10 to R12. Accordingly, the remaining output voltage Vo2 obtained by removing the combined voltage Vout3 from the combined voltage Vout2 is also maintained at the target voltage (a constant value).

  Next, feedback control by the fourth control unit 60 will be described. The feedback control by the fourth control unit 60 is performed in the same manner as the feedback control by the second control unit 40 described above, and thus detailed description thereof is omitted here.

  In the fourth control unit 60, as in the second control unit 40, based on the output voltage Vo4 (third combined voltage), the output voltage Vo4 approaches the target voltage based on the reference voltage Vr and the resistors R13 and R14. The on-time of the switch SW42 is controlled. In other words, the fourth control unit 60 is necessary to supply the coil current IL to the capacitor C4 (output terminal Po4) so that the desired output current Io4 supplied to the load 5 flows based on the output voltage Vo4. The time width is controlled (determined). The remaining time obtained by removing the determined time width from the period T is the coil current IL applied to the capacitors C1, C2, C3 connected to the output terminals Po1, Po2, Po3 not connected to the fourth control unit 60. Used as time to supply. As described above, in the fourth control unit 60, the ratio of the period for distributing the coil current IL to the capacitor C4 and the capacitors C1, C2, and C3 based on only one output voltage Vo4 out of the four output voltages Vo1 to Vo4. Is controlled. By such feedback control by the fourth control unit 60, the output voltage Vo4 is maintained at a target voltage (a constant value) based on the reference voltage Vr and the resistors R13 and R14. Accordingly, the remaining output voltage Vo3 obtained by removing the output voltage Vo4 from the combined voltage Vout3 is also maintained at the target voltage (a constant value).

  The control signals VH1 and VL1 generated by the first control unit 30 and the control signals VH2, VL2, VH3, VL3, VH4 and VL4 generated by the second to fourth control units 40, 50 and 60 are provided. It is a signal with the same period (same frequency). Therefore, the switches SW11 and SW12 on the input side and the switches SW21, SW22, SW31, SW32, SW41, and SW42 on the output side are turned on / off at the same switching frequency. Thereby, even when the DC-DC converter 1 is operated by the CCM, the output voltages Vo1 to Vo4 can be stably generated. More specifically, when the frequency fsw1 of the control signal for controlling on / off of the switches SW11 and SW12 is different from the frequency fsw2 of the control signal for controlling on / off of the switches SW21, SW22, SW31, SW32, SW41, and SW42. In the CCM region, a low frequency component of fsw1 × fsw2 appears in the output voltages Vo1 to Vo4. On the other hand, in the DC-DC converter 1 according to the present embodiment, the control signals VH1 and VL1 and the control signals VH2 to VH4 and VL2 to VL4 have the same frequency (period), and thus the above-described even in the CCM region. Such low frequency components do not occur. Therefore, the output voltages Vo1 to Vo4 can be stably generated even in the CCM region.

  From another point of view, when the output voltages Vo1 and Vo2 are in a steady state, feedback control by the first to fourth control units 30, 40, 50, and 60 is performed at the start time of each cycle T (see time t1). Control is performed so that the current value of the coil current IL coincides with the current value of the coil current IL at the end time of each cycle T (see time t4). More specifically, the amount of increase in the coil current IL in the first period P1 is controlled to be equal to the amount of decrease in the coil current IL in the period from the second period P2 to the fifth period P5. The relationship between the increase and decrease of the coil current IL is as follows. When the times of the first to fifth periods P1 to P5 are P1, P2, P3, P4 and P5, respectively,

It becomes. The relationship between the cycle T and the first to fifth periods P1 to P5 is as follows:

It becomes. The time widths of the first to fifth periods P1 to P5 are controlled by the feedback control by the first to fourth control units 30, 40, 50, and 60 so that the relationship of Expression 6 and Expression 7 is satisfied. Is done. That is, the time width of the first period P1 (the H level pulse width of the control signal VH1) is controlled by the feedback control by the first control unit 30 so that the relationship of Expression 6 and Expression 7 is satisfied. Further, the time width of the third to fifth periods P3 to P5 (the H level pulse width of the control signal VL2) is set so that the relationship of Expression 6 and Expression 7 is satisfied by the feedback control by the second control unit 40. As a result, the time width of the second period P2 is controlled. Further, the time width of the fourth and fifth periods P4 and P5 (the H level pulse width of the control signal VL3) is set so that the relationship of Expressions 6 and 7 is satisfied by the feedback control by the third control unit 50. As a result, the time width of the third period P3 is controlled. The time width of the fifth period P5 (the H level pulse width of the control signal VL4) is controlled by the feedback control by the fourth control unit 60 so that the relationship of Expression 6 and Expression 7 is satisfied. The time width of the fourth period P4 is controlled.

  As described above, in the DC-DC converter 1, the total amount of the coil current IL in the predetermined period T is determined based on the combined voltage Vout1 of the four output voltages Vo1 to Vo4. Further, each of the capacitors C1 to C4 (each output terminal Po1) according to a combination of signal levels of the control signals VH2, VL2, VH3, VL3, VH4, and VL4 generated by the second to fourth control units 40, 50, and 60. The time width for supplying the coil current IL necessary for .about.Po4) is determined. More specifically, based on the combined voltage Vout2 of the three output voltages Vo2 to Vo4 excluding the output voltage Vo1, the time width required to supply the coil current IL to the capacitors C2 to C4 is determined within the period T. The remaining time in the period T is distributed as the time for supplying the coil current IL to the capacitor C1. Further, based on the combined voltage Vout3 of the two output voltages Vo3 and Vo4 excluding the output voltages Vo1 and Vo2, a time width necessary for supplying the coil current IL to the capacitors C3 and C4 is determined within the period T. The remaining time in the period T is distributed as time for supplying the coil current IL to the capacitors C1 and C2. Based on one output voltage Vo4 excluding the output voltages Vo1, Vo2, and Vo3, a time width necessary for supplying the coil current IL to the capacitor C4 is determined within the period T, and the remaining time within the period T is determined. The time is distributed as the time for supplying the coil current IL to the capacitors C1 to C3. Accordingly, even when the number of the coils L is one, the four output voltages Vo1, Vo2, Vo3, and Vo4 can be controlled continuously within one period T. For this reason, even when the current values of the output currents Io1, Io2, Io3, and Io4 are different from each other, the operation can be stably performed in the CCM region. Further, as described above, the current value of the coil current IL at the start time (see time t1) of each cycle T matches the current value of the coil current IL at the end time (see time t6) of each cycle T. Even in the CCM region, the output voltages Vo1 to Vo4 can be generated more stably.

  Also, the output voltage Vo4 is maintained at the target voltage (second and third target values) by feedback control by the fourth control unit 60, and the combined voltage Vout3 of the output voltages Vo3 and Vo4 by feedback control by the third control unit 50. Is maintained at the target voltage (third target value). As a result, the output voltage Vo3 that is a voltage obtained by subtracting the output voltage Vo4 from the combined voltage Vout3 is also maintained at the target voltage (second target value). Further, the composite voltage Vout2 of the output voltages Vo2 to Vo4 is maintained at the target voltage (third target value) by feedback control by the second control unit 40, and the output voltages Vo1 to Vo4 are controlled by feedback control by the first control unit 30. The combined voltage Vout1 is maintained at the target voltage (first target value). As a result, the output voltage Vo2 that is the voltage obtained by subtracting the output voltages Vo3 and Vo4 from the combined voltage Vout2 is also maintained at the target voltage (second target value), and the voltage obtained by subtracting the output voltages Vo2, Vo3, and Vo4 from the combined voltage Vout1 The output voltage Vo1 is maintained at the target voltage (second target value). Specifically, the direct current components Vo1 to Vo4 of the output voltages Vo1 to Vo4 are determined by the following equations, assuming that the resistance values of the resistors R1 to R14 are R1 to R14, and the voltage value of the reference voltage Vr is Vr.

In other words, from the above equations 8 to 11, the voltage value of the reference voltage Vr and the resistance values of the resistors R1 to R14 are set so that the output voltages Vo1 to Vo4 become the corresponding target voltages (second target values), respectively. ing.

  Here, as apparent from the above equation 8, the output voltage Vo4 is determined by the same voltage setting equation as that used when one output voltage is generated by one coil. For this reason, the voltage accuracy of the output voltage Vo4 is high. Specifically, since the voltage value of the output voltage Vo4 is controlled only by the feedback loop by the fourth control unit 60, the voltage accuracy is controlled by the variation of the resistors R13 and R14 and the offset variation of the error amplification circuit 62. Determined. Therefore, the voltage accuracy of the output voltage Vo4 is higher than the output voltages Vo1 to Vo3 that depend on the relative variation in resistance existing in two or more feedback loops and the offset variation in the error amplifier circuit. Thus, in the DC-DC converter 1 of this embodiment, the ratio of the period during which the coil current IL is distributed to the output terminals Po1 to Po3 and the output terminal Po4 is set to one output voltage among the four output voltages Vo1 to Vo4. The determination was made according to Vo4 only. For this reason, the voltage accuracy of the one output voltage Vo4 can be increased.

According to this embodiment described above, the following effects can be obtained.
(1) The total amount of the coil current IL in a predetermined period T is determined based on the four output voltages Vo1 to Vo4, and based on the three output voltages Vo2 to Vo4 (the combined voltages Vout1, Vout2 and the output voltage Vo4). Thus, the ratio of the period during which the coil current IL is distributed to the capacitors C1 to C4 is determined within the period T. In the DC-DC converter 1 of the present embodiment, the ratio of the period for distributing the coil current IL to the output terminal Po4 is determined according to only one output voltage Vo4 among the output voltages Vo1 to Vo4. Thereby, the voltage accuracy of the output voltage Vo4 can be made higher than that of the conventional DC-DC converter in which the output side switch circuit is controlled to be turned on / off based on the difference voltage between the plurality of output voltages.

  (2) Control signals VH1, VL1 for controlling on / off of the switches SW11, SW12 and control signals VH2, VL2, VH3, VL3, VH4 for controlling on / off of the switches SW21, SW22, SW31, SW32, SW41, SW42 VL4 is a signal having the same period. Thereby, even in the CCM region, the output voltages Vo1 to Vo4 can be stably generated.

  (3) With a simple circuit configuration, it can be stably operated in the CCM region, and the voltage accuracy of the output voltage can be improved. In detail, while reducing the number of coils by three compared to a conventional four-output type DC-DC converter having a coil for each output, in the CCM region, almost no other components are added. A single-coil multi-output type DC-DC converter 1 that can be stably operated can be realized.

  Further, the output side switch circuit 20 has a configuration in which a plurality of switch circuits 21, 22, and 23 are connected in cascade, and one of the output terminals Po1 to Po4 depending on the combination of the signal levels of the control signals VH1 to VH3 and VL1 to VL3. One output terminal and the coil L are connected. Furthermore, the time width for supplying the necessary coil current IL to each output terminal Po1 to Po4 (each capacitor C1 to C4) is determined by the combination of the signal levels of the control signals VH1 to VH3 and VL1 to VL3. . That is, the control signals VH1 to VH3 and VL1 to VL3 function as control signals for controlling the time width for connecting the output terminals Po1 to Po4 and the coil L, and any one of the output terminals Po1 to Po4. Functions as a selection signal for selecting as an output terminal to be connected to the coil L. For this reason, it is not necessary to provide a logic circuit or the like for generating a selection signal for connecting any one of the plurality of output terminals Po1 to Po4 to the coil L. Thus, for example, a control circuit (control IC) incorporating four PWM control circuits used in a conventional four-output type DC-DC converter having a coil for each output is used as it is. This can be realized by changing the connection method of components to be connected. That is, the DC-DC converter 1 can realize its circuit configuration by using a conventional general-purpose control circuit (control IC).

(Application example of the DC-DC converter according to the first embodiment)
Next, a method for realizing the circuit configuration of the DC-DC converter 1 using the control circuit used in the conventional DC-DC converter as described above will be described with reference to FIGS. For convenience of explanation, in FIGS. 6 to 8, the same members as those shown in FIG. 1 are denoted by the same reference numerals, and detailed descriptions of these elements are omitted.

First, the configuration of the conventional DC-DC converter 6 will be briefly described.
As shown in FIG. 8, the DC-DC converter 6 is a four-output type DC-DC converter having coils L1, L2, L3, and L4 for output voltages Vo11, Vo12, Vo13, and Vo14, respectively. The DC-DC converter 6 is a synchronous rectification step-down DC-DC converter that generates output voltages Vo11, Vo12, Vo13, and Vo14 lower than the input voltage Vin. The DC-DC converter 6 has a control circuit 80B formed on a one-chip semiconductor integrated circuit device.

  As illustrated in FIG. 7, the control circuit 80B includes a first control circuit 81B, a second control circuit 82B, a third control circuit 83B, a fourth control circuit 84B, and an oscillator 70. The first control circuit 81B has an error amplification circuit 32 and a PWM control circuit 33, and the second control circuit 82B has an error amplification circuit 42 and a PWM control circuit 43. The third control circuit 83B has an error amplification circuit 52 and a PWM control circuit 53, and the fourth control circuit 84B has an error amplification circuit 62 and a PWM control circuit 63. The PWM control circuit 33 includes a PWM comparison circuit 34, an AST 35, and driver circuits 36 and 37. The PWM control circuits 43, 53 and 63 are similar to the PWM control circuit 33 in that the PWM comparison circuits 44, 54 and 64, AST 45, 55 and 65, driver circuits 46, 56 and 66, and driver circuit 47, 57, 67.

  As shown in FIGS. 7 and 8, the first control circuit 81B maintains the output voltage Vo11 at the target voltage based on the reference voltage Vr based on the feedback voltage VFB11 corresponding to the output voltage Vo11 output from the output terminal Po11. As described above, the N-channel MOS transistors T1 and T2 are complementarily controlled on and off. More specifically, when the transistor T1 is turned on at a constant period based on the periodic signal CK of the oscillator 70, a coil current corresponding to the input voltage Vin flows and energy is accumulated in the coil L1. Further, when the error signal S1 between the feedback voltage VFB11 and the reference voltage Vr becomes lower than the periodic signal CK, the transistor T1 is turned off. Then, the energy accumulated in the coil L1 is released toward the output terminal Po11. At this time, when the output voltage Vo11 increases, the error signal S1 decreases and the on-time of the transistor T1 decreases. On the other hand, when the output voltage Vo11 decreases, the error signal S1 increases and the on-time of the transistor T2 increases. By such an operation, the output voltage Vo11 is maintained at the target voltage based on the reference voltage Vr.

  Similarly, the second control circuit 82B uses the N channel so that the output voltage Vo12 is maintained at the target voltage based on the reference voltage Vr based on the feedback voltage VFB12 corresponding to the output voltage Vo12 output from the output terminal Po12. The MOS transistors T3 and T4 are complementarily turned on / off. The third control circuit 83B controls the N-channel MOS transistor T5 so that the output voltage Vo13 is maintained at the target voltage based on the reference voltage Vr based on the feedback voltage VFB13 corresponding to the output voltage Vo13 output from the output terminal Po13. , T6 are complementarily turned on / off. The fourth control circuit 84B uses the N-channel MOS transistor T7 so that the output voltage Vo14 is maintained at the target voltage based on the reference voltage Vr based on the feedback voltage VFB14 corresponding to the output voltage Vo14 output from the output terminal Po14. , T8 are complementarily controlled on and off.

Next, the configuration of the DC-DC converter 1 using the same control circuit 80A as the control circuit 80B will be described.
As shown in FIGS. 6 and 7, the control circuit 80A includes a first control circuit 81A, a second control circuit 82A, a third control circuit 83A, a fourth control circuit 84A, and an oscillator 70. Yes. The first control circuit 81A, the second control circuit 82A, the third control circuit 83A, and the fourth control circuit 84A are the same as the first control circuit 81B, the second control circuit 82B, the third control circuit 83B, and the fourth control circuit 84B. Each has the same configuration. However, since the first control circuit 81A and the first control circuit 81B are functionally different, and the second control circuit 82A and the second control circuit 82B are functionally different, they are given different reference numerals. Also, the third control circuit 83A and the third control circuit 83B are functionally different, and the fourth control circuit 84A and the fourth control circuit 84B are functionally different, and therefore are given different reference numerals. Here, various connection terminals included in the control circuit 80A and the connection relationship between the connection terminals and internal circuit elements will be mainly described.

  The first feedback terminal FB1 of the control circuit 80A is connected to the input terminal of the first control circuit 81A (specifically, the inverting input terminal of the error amplifier circuit 32). The first feedback terminal FB1 in this example is a connection terminal for inputting the first feedback voltage VFB1 corresponding to the combined voltage Vout1 of the output voltages Vo1 to Vo4.

  The output terminal of the error amplifier circuit 32 is connected to the error output terminal ERR1 of the control circuit 80A. The output terminal of the error amplifier circuit 32 is connected to the non-inverting input terminal of the PWM comparison circuit 34, and the output terminal of the PWM comparison circuit 34 is connected to the input terminal of the AST 35. One output terminal of the AST 35 is connected to the input terminal of the driver circuit 36, and the other output terminal of the AST 35 is connected to the input terminal of the driver circuit 37.

  The output terminal of the high-side driver circuit 36 (the output terminal of the first control circuit 81A) is connected to the drive output terminal DH1 for driving the switch SW11 on the main side. The drive output terminal DH1 is connected to a control terminal (gate) of a switch SW11 that is an N-channel MOS transistor. The output terminal of the low side driver circuit 37 (the output terminal of the first control circuit 81A) is connected to the drive output terminal DL1 for driving the synchronous switch SW12. The drive output terminal DL1 is connected to a control terminal (gate) of a switch SW12 that is an N-channel MOS transistor.

  Further, the driver circuit 36 has a high potential side power supply terminal connected to the first power supply terminal VC1 and a low potential side power supply terminal connected to the first coil connection terminal LX1. The driver circuit 37 has a high potential side power supply terminal connected to the power supply terminal VCC1 and a low potential side power supply terminal connected to the ground terminal GND. A power supply line to which a high potential power supply voltage VCC is supplied is connected to the power supply terminal VCC1, and a ground is connected to the ground terminal GND. Further, the cathode of the diode D11 and the first terminal of the capacitor C11 are connected to the first power supply terminal VC1. The anode of the diode D11 is connected to the power line, and the second terminal of the capacitor C11 is connected to the first coil connection terminal LX1. Such a charging voltage of the capacitor C11 is supplied to the high potential side power supply terminal of the driver circuit. The first coil connection terminal LX1 is connected to the second terminal (for example, source) of the switch SW11 that is an N-channel MOS transistor and the first terminal LX of the single coil L. The first terminal (for example, drain) of the switch SW11 is connected to the input terminal Pi to which the input voltage Vin is supplied.

  Here, the function of the capacitor C11 will be described. In order to turn on the switch SW11, it is necessary to apply a voltage higher than that of the source to the gate of the switch SW11 (N-channel MOS transistor). When the switch SW11 is turned on, the source and drain of the switch SW11 are both at the input voltage Vin. For this reason, when the switch SW11 to which the input voltage Vin is supplied is an N-channel MOS transistor, it is necessary to generate a gate voltage higher than the input voltage Vin.

  The capacitor C11 has the first terminal connected to the power supply line via the diode D11, and the second terminal connected to the first terminal LX of the coil L. Here, the high potential power supply voltage VCC is a voltage lower than the input voltage Vin, and the forward voltage drop of the diode D11 is 0.7V. When the switch SW11 is turned off and the potential of the first terminal LX becomes the ground level, the capacitor C11 is charged to a voltage of VCC−0.7 V via the diode D11. Next, when the switch SW11 is turned on and the voltage of the first terminal LX of the coil L rises to the input voltage Vin, the potential on the second terminal side of the capacitor C11 becomes the input voltage Vin, and therefore the first terminal side of the capacitor C11. Increases to Vin + VCC-0.7V. Therefore, the driver circuit 36 to which the voltage is supplied from the first terminal side of the capacitor C11 to the high potential side power supply terminal always has the source voltage of the switch SW11 regardless of whether the switch SW12 is on or the switch SW11 is on. The voltage higher than VCC-0.7V can be received. As a result, the driver circuit 36 can stably drive the gate. Thus, the capacitor C11 functions as a bootstrap circuit. The diode D11 has a function of preventing current from flowing from the capacitor C11 side toward the power supply line when the potential on the first terminal side of the capacitor C11 rises to Vin + VCC−0.7V.

  The second feedback terminal FB2 of the control circuit 80A is connected to the input terminal of the second control circuit 82A (specifically, the inverting input terminal of the error amplifier circuit 42). The second feedback terminal FB2 of this example is a connection terminal for inputting the second feedback voltage VFB2 corresponding to the combined voltage Vout2 of the output voltages Vo2 to Vo4.

  The output terminal of the error amplifier circuit 42 is connected to the error output terminal ERR2 of the control circuit 80A. The output terminal of the error amplifier circuit 42 is connected to the non-inverting input terminal of the PWM comparison circuit 44, and the output terminal of the PWM comparison circuit 44 is connected to the input terminal of the AST 45. One output terminal of the AST 45 is connected to the input terminal of the driver circuit 46, and the other output terminal of the AST 45 is connected to the input terminal of the driver circuit 47.

  The output terminal of the driver circuit 46 (the output terminal of the second control circuit 82A) is connected to the drive output terminal DH2. The drive output terminal DH2 is connected to the control terminal (gate) of the switch SW21 that is an N-channel MOS transistor. The output terminal of the driver circuit 47 (the output terminal of the second control circuit 82A) is connected to the drive output terminal DL2. The drive output terminal DL2 is connected to the control terminal (gate) of the switch SW22 that is an N-channel MOS transistor. In the conventional DC-DC converter 6 shown in FIG. 8, the drive output terminal DH2 is a drive output terminal for driving the main-side transistor T3 provided corresponding to the output voltage Vo12, and the drive output terminal DL2 is This is a drive output terminal for driving the transistor T4 on the synchronization side provided corresponding to the output voltage Vo12.

  As shown in FIG. 7, the driver circuit 46 has a high potential side power supply terminal connected to the second power supply terminal VC2 and a low potential side power supply terminal connected to the second coil connection terminal LX2. The driver circuit 47 has a high potential side power supply terminal connected to the power supply terminal VCC1 and a low potential side power supply terminal connected to the ground terminal GND. As shown in FIG. 6, a power supply line to which a high potential power supply voltage VCC is supplied is connected to the second power supply terminal VC2. Here, in the conventional DC-DC converter 6 shown in FIG. 8, the diode D12 and the capacitor C12 having the same functions as the diode D11 and the capacitor C11 described above are connected to the second power supply terminal VC2. The reason for providing the diode D12 and the capacitor C12 is to apply a voltage higher than the input voltage Vin to the gate of the transistor T3. On the other hand, in the DC-DC converter 1 shown in FIG. 6, the switch SW21 driven by the driver circuit 46 is set to be higher than the input voltage Vin regardless of the on / off state of the other switches SW11, SW12, SW22 and the like. It can always be turned on by a low high potential power supply voltage VCC. For this reason, in the DC-DC converter 1, the diode D12 and the capacitor C12 can be omitted.

  The third feedback terminal FB3 of the control circuit 80A is connected to the input terminal of the third control circuit 83A (specifically, the inverting input terminal of the error amplifier circuit 52). The third feedback terminal FB3 of this example is a connection terminal for inputting a third feedback voltage VFB3 corresponding to the combined voltage Vout3 of the output voltages Vo3 and Vo4.

  The output terminal of the error amplifier circuit 52 is connected to the error output terminal ERR3 of the control circuit 80A. The output terminal of the error amplifier circuit 52 is connected to the non-inverting input terminal of the PWM comparison circuit 54, and the output terminal of the PWM comparison circuit 54 is connected to the input terminal of the AST 55. One output terminal of the AST 55 is connected to the input terminal of the driver circuit 56, and the other output terminal of the AST 55 is connected to the input terminal of the driver circuit 57.

  The output terminal of the driver circuit 56 (the output terminal of the third control circuit 83A) is connected to the drive output terminal DH3. The drive output terminal DH3 is connected to the control terminal (gate) of the switch SW31 that is an N-channel MOS transistor. The output terminal of the driver circuit 57 (the output terminal of the third control circuit 83A) is connected to the drive output terminal DL3. The drive output terminal DL3 is connected to the control terminal (gate) of the switch SW32 that is an N-channel MOS transistor. In the conventional DC-DC converter 6 shown in FIG. 8, the drive output terminal DH3 is a drive output terminal for driving the main transistor T5 provided corresponding to the output voltage Vo13, and the drive output terminal DL3 is This is a drive output terminal for driving the transistor T6 on the synchronous side provided corresponding to the output voltage Vo13.

  As shown in FIG. 7, the driver circuit 56 has a high potential side power supply terminal connected to the third power supply terminal VC3 and a low potential side power supply terminal connected to the third coil connection terminal LX3. The driver circuit 57 has a high potential side power supply terminal connected to the power supply terminal VCC1 and a low potential side power supply terminal connected to the ground terminal GND. As shown in FIG. 6, a power supply line to which a high potential power supply voltage VCC is supplied is connected to the third power supply terminal VC3. Here, as in the case of the second control circuit 82A, in the DC-DC converter 1, the diode D13 and the capacitor C13 provided in the conventional DC-DC converter 6 shown in FIG. 8 can be omitted.

  The fourth feedback terminal FB4 of the control circuit 80A is connected to the input terminal of the fourth control circuit 84A (specifically, the inverting input terminal of the error amplifier circuit 62). The fourth feedback terminal FB4 in this example is a connection terminal for inputting a fourth feedback voltage VFB4 corresponding to the output voltage Vo4.

  The output terminal of the error amplifier circuit 62 is connected to the error output terminal ERR4 of the control circuit 80A. The output terminal of the error amplifier circuit 62 is connected to the non-inverting input terminal of the PWM comparison circuit 64, and the output terminal of the PWM comparison circuit 64 is connected to the input terminal of the AST 65. One output terminal of the AST 65 is connected to the input terminal of the driver circuit 66, and the other output terminal of the AST 65 is connected to the input terminal of the driver circuit 67.

  The output terminal of the driver circuit 66 (the output terminal of the fourth control circuit 84A) is connected to the drive output terminal DH4. This drive output terminal DH4 is connected to a control terminal (gate) of a switch SW41 which is an N-channel MOS transistor. The output terminal of the driver circuit 67 (the output terminal of the fourth control circuit 84A) is connected to the drive output terminal DL4. The drive output terminal DL4 is connected to the control terminal (gate) of the switch SW42 that is an N-channel MOS transistor. In the conventional DC-DC converter 6 shown in FIG. 8, the drive output terminal DH4 is a drive output terminal for driving the main-side transistor T7 provided corresponding to the output voltage Vo14, and the drive output terminal DL4 is This is a drive output terminal for driving the synchronous transistor T8 provided corresponding to the output voltage Vo14.

  As shown in FIG. 7, the driver circuit 66 has a high potential side power supply terminal connected to the fourth power supply terminal VC4 and a low potential side power supply terminal connected to the fourth coil connection terminal LX4. The driver circuit 67 has a high potential side power supply terminal connected to the power supply terminal VCC1 and a low potential side power supply terminal connected to the ground terminal GND. As shown in FIG. 6, a power supply line to which a high potential power supply voltage VCC is supplied is connected to the fourth power supply terminal VC4. Here, as in the case of the second control circuit 82A, in the DC-DC converter 1, the diode D14 and the capacitor C14 provided in the conventional DC-DC converter 6 shown in FIG. 8 can be omitted.

  The second coil connection terminal LX2 is connected to the connection point between the first terminals of the switches SW21 and SW22 and the second terminal LY of the single coil L. The third coil connection terminal LX3 is connected to a connection point between the first terminals of the switches SW31 and SW32 and a second terminal (for example, a source) of the switch SW22. The fourth coil connection terminal LX4 is connected to a connection point between the first terminals of the switches SW41 and SW42 and a second terminal (for example, a source) of the switch SW32.

  Here, in the conventional DC-DC converter 6 shown in FIG. 8, the first coil connection terminal LX1 described above is connected to the first terminal LX11 of the coil L1, and the second coil connection terminal LX2 is the first terminal of the coil L2. Connected to LX12. The third coil connection terminal LX3 is connected to the first terminal LX13 of the coil L3, and the fourth coil connection terminal LX4 is connected to the first terminal LX14 of the coil L4. Furthermore, the second terminal of the coil L1 is connected to the first terminal of the capacitor C1 and the output terminal Po11, and the second terminal of the coil L2 is connected to the first terminal of the capacitor C2 and the output terminal Po12. The second terminal of the coil L3 is connected to the first terminal of the capacitor C3 and the output terminal Po13, and the second terminal of the coil L4 is connected to the first terminal of the capacitor C4 and the output terminal Po14. Thus, in the DC-DC converter 6, the coil L1 is provided for the output terminal Po11 (output voltage Vo11), the coil L2 is provided for the output terminal Po12 (output voltage Vo12), and the output terminal Po13 (output). A coil L3 is provided for the voltage Vo13), and a coil L4 is provided for the output terminal Po14 (output voltage Vo14).

  On the other hand, in the DC-DC converter 1 shown in FIG. 6, the first coil connection terminal LX1 is connected to the first terminal LX of the coil L, and the second coil connection terminal LX2 is connected to the second terminal LY. . The second terminal (for example, source) of the switch SW21 is connected to the first terminal of the capacitor C1 and the output terminal Po1, and the second terminal (for example, source) of the switch SW22 is connected to the first terminals of the switches SW31 and SW32. Has been. The second terminal (for example, source) of the switch SW31 is connected to the first terminal of the capacitor C2 and the output terminal Po2, and the second terminal (for example, source) of the switch SW32 is connected to the first terminals of the switches SW41 and SW42. Yes. Further, the second terminal (for example, source) of the switch SW41 is connected to the first terminal and the output terminal Po3 of the capacitor C3, and the second terminal (for example, source) of the switch SW42 is connected to the first terminal and the output terminal Po4 of the capacitor C4. It is connected to the. With this connection, a single coil L can be shared by the four output terminals Po1, Po2, Po3, Po4. Thereby, three coils can be reduced rather than the DC-DC converter 6.

  The output terminals Po1 to Po4 are connected to the first feedback voltage generation circuit 31. The output terminal (node N1) of the first feedback voltage generation circuit 31 is connected to the first feedback terminal FB1 of the control circuit 80A. In this example, the node N1 is also connected to the first terminal of the resistor R31, and the second terminal of the resistor R31 is connected to the first terminal of the capacitor C31. The second terminal of the capacitor C31 is connected to the error output terminal ERR1 of the control circuit 80A. Therefore, the output terminal of the error amplifier circuit 32 in the first control circuit 81A is fed back to the inverting input terminal of the error amplifier circuit 32 via the capacitor C31 and the resistor R31. The gain of the error amplifier circuit 32 is determined by the resistance values of the resistors R1, R2, R3, R4, R5, and R31 and the capacitance value of the capacitor C31.

  The output terminals Po2 to Po4 are connected to the second feedback voltage generation circuit 41. The output terminal (node N2) of the second feedback voltage generation circuit 41 is connected to the second feedback terminal FB2 of the control circuit 80A. In this example, the node N2 is also connected to the first terminal of the resistor R32, and the second terminal of the resistor R32 is connected to the first terminal of the capacitor C32. The second terminal of the capacitor C32 is connected to the error output terminal ERR2 of the control circuit 80A. For this reason, the output terminal of the error amplifier circuit 42 in the second control circuit 82A is fed back to the inverting input terminal of the error amplifier circuit 42 via the capacitor C32 and the resistor R32. The gain of the error amplifier circuit 42 is determined by the resistance values of the resistors R6, R7, R8, R9, and R32 and the capacitance value of the capacitor C32.

  The output terminals Po3 and Po4 are connected to the third feedback voltage generation circuit 51. The output terminal (node N3) of the third feedback voltage generation circuit 51 is connected to the third feedback terminal FB3 of the control circuit 80A. In this example, the node N3 is also connected to the first terminal of the resistor R33, and the second terminal of the resistor R33 is connected to the first terminal of the capacitor C33. The second terminal of the capacitor C33 is connected to the error output terminal ERR3 of the control circuit 80A. Therefore, the output terminal of the error amplifier circuit 52 in the third control circuit 83A is fed back to the inverting input terminal of the error amplifier circuit 52 via the capacitor C33 and the resistor R33. The gain of the error amplifier circuit 52 is determined by the resistance values of the resistors R10, R11, R12, and R33 and the capacitance value of the capacitor C33.

  The output terminal Po4 is connected to the fourth feedback voltage generation circuit 61. The output terminal (node N4) of the fourth feedback voltage generation circuit 61 is connected to the fourth feedback terminal FB4 of the control circuit 80A. In this example, the node N4 is also connected to the first terminal of the resistor R34, and the second terminal of the resistor R34 is connected to the first terminal of the capacitor C34. The second terminal of the capacitor C34 is connected to the error output terminal ERR4 of the control circuit 80A. Therefore, the output terminal of the error amplifier circuit 62 in the fourth control circuit 84A is fed back to the inverting input terminal of the error amplifier circuit 62 via the capacitor C34 and the resistor R34. The gain of the error amplifying circuit 62 is determined by the resistance values of the resistors R13, R14, R34 and the capacitance value of the capacitor C34.

  Here, the DC-DC converter 1 has resistances R2 to R4, R7, R8, and R11 added as compared with the DC-DC converter 6 shown in FIG. However, since the DC-DC converter 1 can reduce the three diodes D12, D13, D14, the three capacitors C12, C13, C14, and the three coils from the DC-DC converter 6 as described above, As a whole, the circuit area can be greatly reduced. In particular, since it is possible to reduce three coils that are difficult to reduce among various circuit elements, it is possible to achieve a significant reduction in circuit area and cost reduction.

  As described above, the DC-DC converter 1 uses the same control circuit 80A as the control circuit 80B used in the conventional DC-DC converter 6, and most circuit elements are externally attached to the control circuit 80A. The circuit configuration can be realized without change. Nevertheless, the DC-DC converter 1 can achieve the excellent effects (1) to (3) described above.

  6 and 7, the switch SW11 is an example of the first switch circuit, the switch SW21 is an example of the first switch element, the switch SW22 is an example of the second switch element, and the switch SW31 is the third switch element. For example, the switch SW32 is an example of a fourth switch element. The capacitor C1 is an example of a first capacitor, the capacitor C2 is an example of a second capacitor, and the capacitor C3 is an example of a third capacitor. The drive output terminal DH1 is an example of a first drive output terminal, the drive output terminal DH2 is an example of a second drive output terminal, the drive output terminal DL2 is an example of a third drive output terminal, and the drive output terminal DH3 is a fourth drive output. An example of a terminal, the drive output terminal DL3, is an example of a fifth drive output terminal. The output terminal Po1 is an example of a first output terminal, the output terminal Po2 is an example of a second output terminal, the output terminal Po3 is an example of a third output terminal, the output voltage Vo1 is an example of a first output voltage, The output voltage Vo2 is an example of a second output voltage, and the output voltage Vo3 is an example of a third output voltage.

(Modification of the first embodiment)
In the first embodiment, a single inductor multi-output DC-DC converter that generates four output voltages Vo1 to Vo4 with one coil L is embodied. For example, a single inductor multi-output type DC-DC converter that generates three output voltages with one coil L may be embodied, or five or more output voltages are generated with one coil L. A single inductor multiple output type DC-DC converter may be embodied. In this case, the number of stages of switch circuits connected in cascade within the switch circuit 20 on the output side and the number of control units that perform on / off control of the switch circuits are appropriately adjusted. Specifically, when N (for example, five) output voltages are generated by one coil L, (N−1) (for example, four) switch circuits are cascaded in the switch circuit 20. And (N-1) control units for turning on and off the (N-1) switch circuits. Here, a single inductor multi-output type DC-DC converter 1A that generates three output voltages Vo1, Vo2, and Vo3 with one coil L will be briefly described.

  As shown in FIG. 9, the DC-DC converter 1A is a synchronous rectification step-down DC-DC converter that generates three output voltages Vo1, Vo2, and Vo3 lower than the input voltage Vin.

  The DC-DC converter 1A includes a converter unit 10, an output-side switch circuit 20A, capacitors C1 to C3, a first control unit 30A, a second control unit 40A that controls on / off of the switch circuit 20A, and a third control circuit. And a control unit 50A.

  The switch circuit 20A includes (N−1) (two in this case) switch circuits 21 and 22 connected in cascade between the second terminal LY of the coil L and the output terminals Po1 to Po4. Yes. That is, in the switch circuit 20A, the switch circuit 23 is omitted from the switch circuit 20 of the first embodiment.

  The switch circuit 22 includes a switch SW31 and a switch SW32 that are commonly connected to the second terminal of the switch SW22. The switches SW31 and SW32 are connected in series with the switch SW22. These switches SW31 and SW32 are, for example, N-channel MOS transistors.

  The first terminal of the switch SW31 is connected to the second terminal of the switch SW22, and the second terminal of the switch SW31 is connected to the first terminal of the capacitor C2 and the output terminal Po2. That is, the second terminal LY of the coil L is connected to the output terminal Po2 via the switch SW31 and the switch SW22 connected in series (cascade).

  The first terminal of the switch SW32 is connected to the second terminal of the switch SW22, and the second terminal of the switch SW32 is connected to the first terminal of the capacitor C3 and the output terminal Po3. That is, the second terminal LY of the coil L is connected to the output terminal Po3 via the switch SW32 and the switch SW22 connected in series (cascade).

  The control signal VH3 is supplied from the third control unit 50A to the control terminal of the switch SW31, and the control signal VL3 is supplied from the third control unit 50A to the control terminal of the switch SW32. These switches SW31 and SW32 are turned on / off complementarily in response to the control signals VH3 and VL3.

  All three output terminals Po1 to Po3 are connected to the first control unit 30A, and all three output voltages Vo1 to Vo3 are fed back. The first control unit 30A, based on the result of combining the output voltage Vo1, the output voltage Vo2 and the output voltage Vo3 (the combined voltage Vout1), brings the combined voltage Vout1 closer to the target voltage (first target value). The switches SW11 and SW12 are turned on / off.

The first control unit 30A includes a first feedback voltage generation circuit 31A, an error amplification circuit 32, and a PWM control circuit 33.
The first feedback voltage generation circuit 31A generates a first feedback voltage VFB1 corresponding to the combined voltage Vout1 obtained by adding all three output voltages of the output voltage Vo1, the output voltage Vo2, and the output voltage Vo3. The first feedback voltage generation circuit 31A includes resistors R1, R2, and R3 connected to the output terminals Po1, Po2, and Po3, respectively, and a resistor R5 that is connected in common to the resistors R1, R2, and R3. Yes. A node N1 between the resistors R1, R2, R3 and the resistor R5 is connected to the inverting input terminal of the error amplifier circuit 32. In such a first feedback voltage generation circuit 31A, the first feedback voltage VFB1 obtained by adding the divided voltage of the output voltage Vo1, the divided voltage of the output voltage Vo2, and the divided voltage of the output voltage Vo3 is the node N1. Is generated. The first feedback voltage VFB1 is supplied to the inverting input terminal of the error amplifier circuit 32.

  Of the three output terminals Po1 to Po3, two output terminals Po2 and Po3 other than the output terminal Po1 are connected to the second control unit 40A, and one output voltage Vo1 of the three output voltages Vo1 to Vo3 is connected. The remaining output voltages Vo2 and Vo3 (second output voltage) excluding (first output voltage) are supplied. Specifically, output terminals Po2 and Po3 electrically connected to the output terminal of the switch SW22 included in the first-stage switch circuit 21 in the switch circuit 20A are connected to the second control unit 40A. Output voltages Vo2 and Vo3 generated respectively at the output terminals Po2 and Po3 are supplied. Based on the result of combining the input output voltages Vo2 and Vo3 (synthetic voltage Vout2), the second control unit 40A makes the combined voltage Vout2 close to the target voltage (third target value). The switches SW21 and SW22 included in the switch circuit 21 are turned on / off.

The second control unit 40A includes a second feedback voltage generation circuit 41A, an error amplification circuit 42, and a PWM control circuit 43.
The second feedback voltage generation circuit 41A generates a second feedback voltage VFB2 corresponding to the combined voltage Vout2 obtained by adding the output voltage Vo2 and the output voltage Vo3. The second feedback voltage generation circuit 41A has resistors R6 and R7 connected to the output terminals Po2 and Po3, respectively, and a resistor R9 connected in common with the resistors R6 and R7. A node N2 between the resistors R6, R7 and the resistor R9 is connected to the inverting input terminal of the error amplifying circuit 42. In such a second feedback voltage generation circuit 41A, a second feedback voltage VFB2 obtained by adding the divided voltage of the output voltage Vo2 and the divided voltage of the output voltage Vo3 is generated at the node N2. The second feedback voltage VFB2 is supplied to the inverting input terminal of the error amplifier circuit 42.

  The third control unit 50A is connected to one output terminal Po3 excluding the output terminal Po2 out of the two output terminals Po2 and Po3 connected to the second control unit 40A, and is fed back to the second control unit 40A. The remaining output voltage Vo3 excluding one output voltage Vo2 out of the two output voltages Vo2 and Vo3 is supplied. Specifically, the output terminal Po3 connected to the output terminal of the switch SW32 included in the second-stage switch circuit 22 in the switch circuit 20A is connected to the third control unit 50A, and the output terminal Po3 is connected to the output terminal Po3. The generated output voltage Vo3 is supplied. Based on the output voltage Vo3, the third control unit 50A performs on / off control of the switches SW31 and SW32 so that the output voltage Vo3 approaches the target voltage (second target value and third target value).

The third control unit 50A includes a third feedback voltage generation circuit 51A, an error amplification circuit 52, and a PWM control circuit 53.
The third feedback voltage generation circuit 51A generates a third feedback voltage VFB3 corresponding to the output voltage Vo3. The third feedback voltage generation circuit 51A has resistors R10 and R12. A node N3 between the resistors R10 and R12 is connected to the inverting input terminal of the error amplifier circuit 52. In such a third feedback voltage generation circuit 51A, a third feedback voltage VFB3 that is a divided voltage of the output voltage Vo3 is generated at the node N3. The third feedback voltage VFB3 is supplied to the inverting input terminal of the error amplifier circuit 52.

Next, the operation of the DC-DC converter 1A will be briefly described. In FIG. 10, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
When the periodic signal CK is reset to the reference value at a constant period T at time t11 shown in FIG. 10, control signals VH1, VH2, and VH3 at H level and control signals VL1, VL2, and VL3 at L level are generated. . As a result, the switches SW11, SW21, and SW31 are turned on, and the switches SW12, SW22, and SW32 are turned off. Then, the input terminal Pi is connected to the first terminal LX of the coil L through the switch SW11, and the second terminal LY of the coil L is connected to the output terminal Po1 through the switch SW21. For this reason, a current path from the input terminal Pi to the output terminal Po1 through the coil L is formed, the coil current IL corresponding to the input voltage Vin and the output voltage Vo1 flows through the coil L, and energy is accumulated in the coil L (first). 1 period P1).

  Next, when the level of the periodic signal CK that gradually increases with a predetermined rising characteristic from time t11 becomes higher than the error signal S1 (see time t12), the L level control signal VH1 and the H level control signal VL1 are output. The The switch SW11 is turned off in response to the L level control signal VH1, and the switch W12 is turned on in response to the H level control signal VL1. Then, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po1 through the switch SW21. For this reason, a current path from the ground to the output terminal Po1 through the coil L is formed, energy stored in the coil L in the first period P1 is released toward the output terminal Po1, and an induced current flows through the coil L. (Second period P2).

  Subsequently, when the level of the periodic signal CK becomes higher than the error signal S2 (see time t13), the L level control signal VH2 and the H level control signal VL2 are output. The switch SW21 is turned off in response to the L level control signal VH2, and the switch SW22 is turned on in response to the H level control signal VL2. Then, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po2 through the switch SW22 and the switch SW31. For this reason, a current path is formed from the ground to the output terminal Po2 through the coil L, the energy stored in the coil L in the first period P1 is released toward the output terminal Po2, and an induced current flows through the coil L. (Third period P3).

  Next, when the level of the periodic signal CK becomes higher than the error signal S3 (see time t14), the L level control signal VH3 and the H level control signal VL3 are output. The switch SW31 is turned off in response to the L level control signal VH3, and the switch SW32 is turned on in response to the H level control signal VL3. Then, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po3 through the switch SW22 and the switch SW32. For this reason, a current path from the ground to the output terminal Po3 through the coil L is formed, energy stored in the coil L in the first period P1 is released toward the output terminal Po3, and an induced current flows through the coil L. (Fourth period P4).

  Thereafter, when the periodic signal CK is reset again to the reference value at a constant period T (see time t15), the switches SW11, SW21, and SW31 are turned on, and the switches SW12, SW22, and SW32 are turned off. Thereby, the next period T is started, and in the period T, the first period P1, the second period P2, the third period P3, and the fourth period P4 are executed in this order.

  In such a DC-DC converter 1A, the total amount of the coil current IL in the predetermined period T is determined based on the combined voltage Vout1 of the three output voltages Vo1 to Vo3. Further, depending on the combination of signal levels of the control signals VH2, VL2, VH3, and VL3 generated by the second and third control units 40A and 50A, each capacitor C1 to C3 (each output terminal Po1 to Po3) is necessary. A time width for supplying the coil current IL is determined. More specifically, based on the combined voltage Vout2 of the two output voltages Vo2 and Vo3 excluding the output voltage Vo1, a time width necessary for supplying the coil current IL to the capacitors C2 and C3 is determined within the period T. The remaining time in the period T is distributed as the time for supplying the coil current IL to the capacitor C1. Further, based on one output voltage Vo3 excluding the output voltages Vo1 and Vo2, a time width necessary for supplying the coil current IL to the capacitor C3 is determined within the period T, and the remaining time within the period T is determined. It is distributed as time for supplying the coil current IL to the capacitors C1 and C2.

  The output voltage Vo3 is maintained at the target voltage by such feedback control by the third control unit 50A, and the combined voltage Vout2 of the output voltages Vo2 and Vo3 is maintained at the target voltage by feedback control by the second control unit 40A. As a result, the output voltage Vo2 that is a voltage obtained by subtracting the output voltage Vo3 from the combined voltage Vout2 is also maintained at the target voltage. Further, the combined voltage Vout1 of the output voltages Vo1 to Vo3 is maintained at the target voltage by the feedback control by the first control unit 30A. As a result, the output voltage Vo1 that is a voltage obtained by subtracting the output voltages Vo2 and Vo3 from the combined voltage Vout1 is also maintained at the target voltage. Specifically, the direct current components Vo1 to Vo3 of the output voltages Vo1 to Vo3 are determined by the following equations.

As is clear from the above equation 12, the output voltage Vo3 is determined by the same voltage setting equation as in the case where one output voltage is generated by one coil. For this reason, in the DC-DC converter 1A, the voltage accuracy of one output voltage Vo3 among the three output voltages Vo1 to Vo3 can be increased.

Even with such a DC-DC converter 1A, the same effects as (1) to (3) of the first embodiment can be obtained.
(Second Embodiment)
Hereinafter, a second embodiment will be described with reference to FIGS. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 10 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 11, the DC-DC converter 1B is a single inductor multi-output DC-DC converter that generates N (here, four) output voltages with one coil L. Further, the DC-DC converter 1B has four output voltages Vo1, Vo2, Vo3... Lower than the input voltage Vin based on the input voltage Vin supplied to the input terminal Pi. This is a synchronous rectification step-down DC-DC converter that generates Vo4.

  The DC-DC converter 1B includes a converter unit 10, an output side switch circuit 20B, capacitors C1 to C4, a first control unit 30, a second control unit 40B that controls on / off of the switch circuit 20B, and a third control circuit. The controller 50B, the fourth controller 60, and the oscillator 70 are included.

  The switch circuit 20B has (N−1) (three in this case) switch circuits 25, 26, and 27 connected in cascade between the second terminal LY of the coil L and the output terminals Po1 to Po4. doing. Specifically, in the switch circuit 20B, the switch circuit 25 and the switch circuit 26 are connected in cascade between the second terminal LY of the coil L and the output terminals Po1 and Po2, and the second terminal LY of the coil L and the output A switch circuit 25 and a switch circuit 27 are connected in cascade between the terminals Po3 and Po4.

  The switch circuit 25 includes a switch S21 and a switch S22 that are commonly connected to the second terminal LY of the coil L. These switches S21 and S22 are, for example, N-channel MOS transistors.

  The first terminal of the switch S21 is connected to the second terminal LY of the coil L, and the second terminal (output terminal) of the switch S21 is connected to the switch circuit 26. The first terminal of the switch S22 is connected to the second terminal LY of the coil L, and the second terminal (output terminal) of the switch S22 is connected to the switch circuit 27. The control signal VH2 is supplied from the second control unit 40B to the control terminal of the switch S21, and the control signal VL2 is supplied from the second control unit 40B to the control terminal of the switch S22. These switches S21 and S22 are complementarily turned on and off in response to control signals VH2 and VL2.

  The switch circuit 26 includes a switch S31 and a switch S32 that are commonly connected to the second terminal (output terminal) of the switch S21. The switches S31 and S32 are connected in series with the switch S21. These switches S31 and S32 are, for example, N-channel MOS transistors.

  The first terminal of the switch S31 is connected to the second terminal of the switch S21, and the second terminal (output terminal) of the switch S31 is connected to the first terminal of the capacitor C1 and the output terminal Po1. That is, the second terminal LY of the coil L is connected to the output terminal Po1 via the switch S31 and the switch S21 connected in series (cascade). The first terminal of the switch S32 is connected to the second terminal of the switch S21, and the second terminal (output terminal) of the switch S32 is connected to the first terminal of the capacitor C2 and the output terminal Po2. That is, the second terminal LY of the coil L is connected to the output terminal Po2 via the switch S32 and the switch S21 connected in series (cascade).

  The control signal VH3 is supplied from the third control unit 50B to the control terminal of the switch S31, and the control signal VL3 is supplied from the third control unit 50B to the control terminal of the switch S32. These switches S31 and S32 are complementarily turned on / off in response to control signals VH3 and VL3.

  The switch circuit 27 includes a switch S41 and a switch S42 that are commonly connected to the second terminal of the switch S22. The switches S41 and S42 are connected in series with the switch S22. These switches S41 and S42 are, for example, N-channel MOS transistors.

  The first terminal of the switch S41 is connected to the second terminal of the switch S22, and the second terminal (output terminal) of the switch S41 is connected to the first terminal of the capacitor C3 and the output terminal Po3. That is, the second terminal LY of the coil L is connected to the output terminal Po3 via the switch S41 and the switch S22 connected in series (cascade). The first terminal of the switch S42 is connected to the second terminal of the switch S22, and the second terminal (output terminal) of the switch S42 is connected to the first terminal of the capacitor C4 and the output terminal Po4. That is, the second terminal LY of the coil L is connected to the output terminal Po4 via the switch S42 and the switch S22 connected in series (cascade).

  The control signal VH4 is supplied from the fourth control unit 60 to the control terminal of the switch S41, and the control signal VL4 is supplied from the fourth control unit 60 to the control terminal of the switch S42. These switches S41, S42 are complementarily turned on / off in response to control signals VH4, VL4.

  Two output terminals Po3 and Po4, except for the output terminals Po1 and Po2, out of the four output terminals Po1 to Po4 are connected to the second control unit 40B, and two outputs of the four output voltages Vo1 to Vo4 are output. The remaining output voltages Vo2 to Vo4 (second output voltage) excluding the voltages Vo1 and Vo2 are supplied. Specifically, the second control unit 40B has an output terminal that is not connected to the output terminal of the switch S21 included in the first-stage switch circuit 25 in the switch circuit 20B (electrically connected to the output terminal of the switch S22). Output terminals Po3, Po4 are connected, and output voltages Vo3, Vo4 generated respectively are supplied to the output terminals Po3, Po4. The second control unit 40B brings the combined voltage Vout2 closer to the target voltage (second target value and third target value) based on the result of combining the input output voltages Vo3 and Vo4 (the combined voltage Vout2). The switches S21 and S22 included in the first-stage switch circuit 25 are turned on / off. In other words, the second control unit 40B adjusts the ON times of the switches S21 and S22 so that desired power is supplied to the loads 4 and 5 based on the combined voltage Vout2. Specifically, the second control unit 40B supplies the control signals VH2 and VL2 having a constant frequency (period) and varying pulse widths according to the power supplied to the loads 4 and 5 to the switches S21 and S22.

The second control unit 40B includes a second feedback voltage generation circuit 41B, an error amplification circuit 42, and a PWM control circuit 43.
The second feedback voltage generation circuit 41B generates a second feedback voltage VFB2 corresponding to the combined voltage Vout2 obtained by adding the output voltage Vo3 and the output voltage Vo4. The second feedback voltage generation circuit 41B includes resistors R15 and R16 connected to the output terminals Po3 and Po4, respectively, and a resistor R17 connected in common to the resistors R15 and R16. Specifically, the output terminal Po3 is connected to the ground via resistors R15 and R17, and the output terminal Po4 is connected to the ground via resistors R16 and R17. A node N2 between the resistors R15 and R16 and the resistor R17 is connected to the inverting input terminal of the error amplifier circuit. In such a second feedback voltage generation circuit 41B, a second feedback voltage VFB2 obtained by adding the divided voltage of the output voltage Vo3 and the divided voltage of the output voltage Vo4 is generated at the node N2. The second feedback voltage VFB2 is supplied to the inverting input terminal of the error amplifier circuit 42.

  Of the four output terminals Po1 to Po4, three output terminals Po2 to Po4 other than the output terminal Po1 are connected to the third control unit 50B, and one output voltage Vo1 of the four output voltages Vo1 to Vo4 is connected. The remaining output voltages Vo2 to Vo4 (second output voltage) excluding (first output voltage) are supplied. Specifically, the third control unit 50B is connected to output terminals Po2, Po3, Po4 that are not connected to the output terminal of the switch S31 of the switch circuit 26, and the output terminals Po2, Po3, Po4 are connected to the output terminals Po2, Po3, Po4. Output voltages Vo2, Vo3, and Vo4 generated respectively are supplied. The third control unit 50B brings the combined voltage Vout3 closer to the target voltage (second target value and third target value) based on the result of combining the input output voltages Vo2, Vo3, and Vo4 (the combined voltage Vout3). As described above, the switches S31 and S32 included in the switch circuit 25 are on / off controlled. In other words, the third control unit 50B adjusts the ON time of the switch S32 so that desired power is supplied to the loads 3, 4, and 5 based on the combined voltage Vout3. Specifically, the third control unit 50B supplies the switches S31 and S32 with control signals VH3 and VL3 having a constant frequency (period) and varying pulse widths according to the power supplied to the loads 3, 4, and 5. To do.

The third control unit 50B includes a third feedback voltage generation circuit 51B, an error amplification circuit 52, and a PWM control circuit 53.
The third feedback voltage generation circuit 51B generates a third feedback voltage VFB3 corresponding to the combined voltage Vout3 obtained by adding the output voltage Vo2, the output voltage Vo3, and the output voltage Vo4. This third feedback voltage generation circuit 51B has resistors R18, R19, R20 connected to the output terminals Po2, Po3, Po4, respectively, and a resistor R21 connected in common with these resistors R18, R19, R20. Yes. Specifically, the output terminal Po2 is connected to the ground via resistors R18 and R21, the output terminal Po3 is connected to the ground via resistors R19 and R21, and the output terminal Po4 is connected to the ground via resistors R20 and R21. It is connected. A node N3 between the resistors R18, R19, R20 and the resistor R21 is connected to the inverting input terminal of the error amplifier circuit 52. In such a third feedback voltage generation circuit 51B, the third feedback voltage VFB3 obtained by adding the divided voltage of the output voltage Vo2, the divided voltage of the output voltage Vo3, and the divided voltage of the output voltage Vo4 is the node N3. Is generated. The third feedback voltage VFB3 is supplied to the inverting input terminal of the error amplifier circuit 52.

  The fourth control unit 60 includes a fourth feedback voltage generation circuit 61, an error amplification circuit 62, and a PWM control circuit 63. The fourth control unit 60 is connected to the remaining output terminals Po4 except for the output terminals Po1, Po2 and Po3 among the four output terminals Po1 to Po4, and three of the four output voltages Vo1 to Vo4 are connected. The remaining output voltage Vo4 excluding the output voltages Vo1, Vo2, and Vo3 is supplied. Specifically, the output terminal Po4 connected to the output terminal of one switch S42 included in the switch circuit 27 is connected to the fourth control unit 60, and the output voltage Vo4 generated at the output terminal Po4 is supplied to the fourth control unit 60. Supplied. Based on the output voltage Vo4, the fourth control unit 60 performs on / off control of the switches S41 and S42 so that the output voltage Vo4 approaches the target voltage (third target value). In other words, the fourth control unit 60 adjusts the ON time of the switch S42 so that desired power is supplied to the load 5 based on the output voltage Vo4. Specifically, the fourth control unit 60 supplies the control signals VH4 and VL4 whose frequency (cycle) is constant and whose pulse width varies according to the power supplied to the load 5, to the switches S41 and S42.

  In the present embodiment, the switch circuit 20B is an example of a second switch circuit, the switch circuits 25, 26, and 27 are examples of a third switch circuit, the switch circuit 25 is an example of a first-stage switch circuit, and the switch circuits 26 and 27 are An example of the second and subsequent switch circuits, the switch circuit 26 is an example of a fourth switch circuit, and the switch circuit 27 is an example of a fifth switch circuit. The switches S21, S22, S31, S32, S41, and S42 are examples of switch elements, the switch S21 is an example of one switch element, the switch S22 is an example of the other switch element, and the second to fourth control units 40B and 50B. , 60 is an example of the second control unit, and the second control unit 40B is an example of the third control unit. The combined voltage Vout1 is an example of a first combined voltage, the combined voltage Vout2 and the output voltage Vo4 are an example of a third combined voltage, and the combined voltage Vout3 is an example of a second combined voltage.

  Next, the operation of the DC-DC converter 1B will be described with reference to FIGS. In FIG. 12, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  When the periodic signal CK is reset to the reference value at a constant period T at time t21 shown in FIG. 12, the level of the periodic signal CK becomes lower than the error signals S1, S2, S3, S4. Then, H level control signals VH1, VH2, VH3, and VH4 are output from the PWM control circuits 33, 43, 53, and 63, respectively, and L level control signals VL1, VL2, VL3, and VL4 are output. As a result, the switches SW11, S21, S31, and S41 are turned on, and the switches SW12, S22, S32, and S42 are turned off. Then, as shown in FIG. 13A, the input terminal Pi is connected to the first terminal LX of the coil L through the switch SW11, and the second terminal LY of the coil L is connected to the output terminal Po1 through the switch S21 and the switch S31. Is done. For this reason, a current path from the input terminal Pi to the output terminal Po1 through the coil L is formed. During this connection state, specifically, in the first period Q1 from time t21 to time t22 shown in FIG. 12, the coil current IL corresponding to the input voltage Vin flows through the coil L, and energy is stored in the coil L. Is done. In the first period Q1, the coil current IL increases with time with a predetermined slope (a slope proportional to the potential difference between the input voltage Vin and the output voltage Vo1).

  Next, when the level of the periodic signal CK that gradually rises with a predetermined rising characteristic from time t21 becomes higher than the error signal S1 (see time t22), the PWM control circuit 33 controls the L level control signal VH1 and the H level. Signal VL1 is output. The switch SW11 is turned off in response to the L level control signal VH1, and the switch SW12 is turned on in response to the H level control signal VL1. Then, as shown in FIG. 13B, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po1 through the switch S21 and the switch S31. . For this reason, a current path from the ground to the output terminal Po1 through the coil L is formed. During this connection state, specifically, in the second period Q2 from time t22 to time t23 shown in FIG. 12, the energy stored in the coil L in the first period Q1 is directed toward the output terminal Po1. The induced current flows through the coil L. In the second period Q2, the coil current IL decreases with a predetermined inclination (an inclination proportional to the output voltage Vo1) as time elapses.

  Subsequently, when the level of the periodic signal CK becomes higher than the error signal S2 (see time t23), the PWM control circuit 53 outputs an L level control signal VH3 and an H level control signal VL3. The switch S31 is turned off in response to the L level control signal VH3, and the switch S32 is turned on in response to the H level control signal VL3. Then, as shown in FIG. 13C, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po2 through the switch S21 and the switch S32. . For this reason, a current path from the ground to the output terminal Po2 through the coil L is formed. During this connection state, specifically, in the third period Q3 from time t23 to time t2 shown in FIG. 12, the energy stored in the coil L in the first period Q1 is directed toward the output terminal Po2. The induced current flows through the coil L. In the third period Q3, the coil current IL decreases with a predetermined inclination (an inclination proportional to the output voltage Vo2) with the passage of time.

  Next, when the level of the periodic signal CK becomes higher than the error signal S3 (see time t24), the PWM control circuit 43 outputs an L level control signal VH2 and an H level control signal VL2. The switch S21 is turned off in response to the L level control signal VH2, and the switch S22 is turned on in response to the H level control signal VL2. Then, as shown in FIG. 14A, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po3 through the switch S22 and the switch S41. . For this reason, a current path from the ground to the output terminal Po3 through the coil L is formed. During this connection state, specifically, in the fourth period Q4 from time t24 to time t25 shown in FIG. 12, the energy stored in the coil L in the first period Q1 is directed toward the output terminal Po3. The induced current flows through the coil L. In the fourth period Q4, the coil current IL decreases with a predetermined inclination (an inclination proportional to the output voltage Vo3) with the passage of time.

  Next, when the level of the periodic signal CK becomes higher than the error signal S4 (see time t25), the PWM control circuit 63 outputs an L level control signal VH4 and an H level control signal VL4. The switch S41 is turned off in response to the L level control signal VH4, and the switch S42 is turned on in response to the H level control signal VL4. Then, as shown in FIG. 14B, the ground is connected to the first terminal LX of the coil L through the switch SW12, and the second terminal LY of the coil L is connected to the output terminal Po4 through the switch S22 and the switch S42. . For this reason, a current path from the ground to the output terminal Po4 through the coil L is formed. During this connection state, specifically, in the fifth period Q5 from time t25 to time t26 shown in FIG. 12, the energy stored in the coil L in the first period Q1 is directed toward the output terminal Po4. The induced current flows through the coil L. In the fifth period Q5, the coil current IL decreases with a predetermined inclination (an inclination proportional to the output voltage Vo4) with the passage of time.

  Thereafter, when the periodic signal CK is reset to the reference value again at a constant period T (see time t26), the switches SW11, S21, S31, and S41 are turned on, and the switches SW12, S22, S32, and S42 are turned off. The Thereby, the next period T is started, and in the period T, the first period Q1, the second period Q2, the third period Q3, the fourth period Q4, and the fifth period Q5 are executed in this order. Is done.

  Here, the average value of the coil current IL in each cycle T (the first period Q1 to the fifth period Q5) is the sum of the output currents Io1, Io2, Io3, and Io4 supplied to the loads 2, 3, 4, and 5. The value is Io1 + Io2 + Io3 + Io4. In addition, an average value obtained by averaging the total amount of coil current IL (refer to region B1) in the period T during the period in which the switch S31 is on (first period Q1 and second period Q2) is supplied to the load 2. Output current Io1. Further, an average value obtained by averaging the total amount of the coil current IL (refer to the region B2) in the period T during the period in which the two switches S21 and S32 are ON (third period Q3) is the load 3 The output current Io2 is supplied. Further, an average value obtained by averaging the total amount of the coil current IL (refer to the region B3) in the period T during the period in which the two switches S22 and S41 are on (fourth period Q4) is applied to the load 4. The output current Io3 is supplied. An average value obtained by averaging the total amount of the coil current IL (refer to the region B4) in the period T during the period when the two switches S22 and S42 are on (fifth period Q5) is applied to the load 5. The output current Io4 is supplied.

  In such a DC-DC converter 1B, the total amount of the coil current IL in the predetermined period T is determined based on the combined voltage Vout1 of the four output voltages Vo1 to Vo4. Further, each of the capacitors C1 to C4 (each output terminal Po1) according to a combination of signal levels of the control signals VH2, VL2, VH3, VL3, VH4, and VL4 generated by the second to fourth control units 40B, 50B, and 60. The time width for supplying the coil current IL necessary for .about.Po4) is determined. More specifically, the time width required to supply the coil current IL to the capacitors C3 and C4 is determined within the period T based on the combined voltage Vout2 of the two output voltages Vo3 and Vo4 excluding the output voltages Vo1 and Vo2. The remaining time in the period T is distributed as the time for supplying the coil current IL to the capacitors C1 and C2. Further, a time width required for supplying the coil current IL to the capacitors C2, C3, C4 is determined within the period T based on the combined voltage Vout3 of the three output voltages Vo2, Vo3, Vo4 excluding the output voltage Vo1. The remaining time in the period T is distributed as the time for supplying the coil current IL to the capacitor C1. Based on one output voltage Vo4 excluding the output voltages Vo1, Vo2, and Vo3, a time width necessary for supplying the coil current IL to the capacitor C4 is determined within the period T, and the remaining time within the period T is determined. The time is distributed as the time for supplying the coil current IL to the capacitors C1 to C3. Accordingly, even when the number of the coils L is one, the four output voltages Vo1, Vo2, Vo3, and Vo4 can be controlled continuously within one period T. For this reason, even when the current values of the output currents Io1, Io2, Io3, and Io4 are different from each other, the operation can be stably performed in the CCM region.

  Further, the output voltage Vo4 is maintained at the target voltage by the feedback control by the fourth control unit 60, and the combined voltage Vout2 of the output voltages Vo3 and Vo4 is maintained at the target voltage by the feedback control by the second control unit 40B. As a result, the output voltage Vo3, which is a voltage obtained by subtracting the output voltage Vo4 from the combined voltage Vout2, is also maintained at the target voltage. Further, the combined voltage Vout3 of the output voltages Vo2 to Vo4 is maintained at the target voltage by feedback control by the third control unit 50B, and the combined voltage Vout1 of the output voltages Vo1 to Vo4 is maintained by the feedback control by the first control unit 30. Maintained. As a result, the output voltage Vo2 that is the voltage obtained by subtracting the output voltages Vo3 and Vo4 from the combined voltage Vout3 is also maintained at the target voltage, and the output voltage Vo1 that is the voltage obtained by subtracting the output voltages Vo2, Vo3, and Vo4 from the combined voltage Vout1 is also the target. Maintained at voltage. Specifically, the direct current components Vo1 to Vo4 of the output voltages Vo1 to Vo4 are determined by the following equations.

In other words, the voltage value of the reference voltage Vr and the resistance values of the resistors R1 to R5 and R13 to R21 are set so that the output voltages Vo1 to Vo4 are respectively corresponding target voltages from the above equations 8 to 11. .

  Here, as is apparent from the above equation 15, the output voltage Vo4 is determined by the same voltage setting equation as that when one output voltage is generated by one coil. For this reason, in the DC-DC converter 1B, the voltage accuracy of one output voltage Vo4 out of the four output voltages Vo1 to Vo4 can be increased.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) to (3) of the first embodiment.
(4) ²ⁿ (2 ² = 4 in this example) output terminals Po1 to Po4 are connected to one coil L. Further, N / 2 ¹ (in this example, 2) of the output terminals Po1 to Po4, the switch S21 connected to the output terminals Po1 and Po2, and the other N / 2 ^{1 of the} output terminals Po1 to Po4. A switch circuit 25 having a switch S22 connected to the output terminals Po3 and Po4 is provided. Further, the switch S31 connected to N / 2 ² (1 in this example) output terminals Po1 among the output terminals Po1 and Po2, and the other N / 2 ² output terminals among the output terminals Po1 and Po2. A switch circuit 26 having a switch S32 connected to Po2 and cascaded to the switch S21 is provided. Further, the switch S41 connected to N / 2 ² (1 in this example) output terminals Po3 among the output terminals Po3 and Po4, and the other N / 2 ² output terminals among the output terminals Po3 and Po4. A switch circuit 27 having a switch S42 connected to Po4 and cascaded to the switch S22 is provided. Thereby, the same number (two in this example) of switches are interposed between the output terminals Po1 to Po4 and the second terminal LY of the coil L. For this reason, the influence of manufacturing variations of the switches S21, S22, S31, S32, S41, and S42 can be reduced, and the voltage accuracy of the output voltages Vo1 to Vo4 can be increased.

(Application example of the DC-DC converter according to the second embodiment)
Next, a method for realizing the circuit configuration of the DC-DC converter 1B using a control circuit used in a conventional DC-DC converter will be described with reference to FIGS. For convenience of explanation, in FIG. 15, the same members as those shown in FIGS. 6 and 11 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 15, the drive output terminal DH1 to which the output terminal of the first control circuit 81A is connected is connected to the control terminal (gate) of the switch SW11 that is an N-channel MOS transistor. The drive output terminal DL1 to which the output terminal of the first control circuit 81A is connected is connected to the control terminal (gate) of the switch SW12 that is an N-channel MOS transistor.

  The drive output terminal DH2 to which the output terminal of the second control circuit 82A is connected is connected to the control terminal (gate) of the switch S21 that is an N-channel MOS transistor. The drive output terminal DL2 connected to the output terminal of the second control circuit 82A is connected to the control terminal (gate) of the switch S22 that is an N-channel MOS transistor.

  The drive output terminal DH3 connected to the output terminal of the third control circuit 83A is connected to the control terminal (gate) of the switch S31 that is an N-channel MOS transistor. The drive output terminal DL3 connected to the output terminal of the third control circuit 83A is connected to the control terminal (gate) of the switch S32 that is an N-channel MOS transistor.

  The drive output terminal DH4 connected to the output terminal of the fourth control circuit 84A is connected to the control terminal (gate) of the switch S41 which is an N channel MOS transistor. The drive output terminal DL4 connected to the output terminal of the fourth control circuit 84A is connected to the control terminal (gate) of the switch S42 which is an N-channel MOS transistor.

  The first coil connection terminal LX1 is connected to the first terminal LX of the coil L. The second coil connection terminal LX2 is connected to the connection point between the first terminals of the switches S21 and S22 and the second terminal LY of the single coil L.

  The third coil connection terminal LX3 is connected to a connection point between the first terminals of the switches S31 and S32 and a second terminal (for example, a source) of the switch S21. That is, the first terminal of the switch S31 and the first terminal of the switch S32 are connected to the second terminal of the switch S21. The second terminal of the switch S31 is connected to the first terminal of the capacitor C1 and the output terminal Po1, and the second terminal of the switch S32 is connected to the first terminal of the capacitor C2 and the output terminal Po2.

  The fourth coil connection terminal LX4 is connected to a connection point between the first terminals of the switches S31 and S32 and a second terminal (for example, a source) of the switch S22. That is, the first terminal of the switch S41 and the first terminal of the switch S42 are connected to the second terminal of the switch S22. The second terminal of the switch S41 is connected to the first terminal of the capacitor C3 and the output terminal Po3, and the second terminal of the switch S42 is connected to the first terminal of the capacitor C4 and the output terminal Po4.

  With this connection, a single coil L can be shared by the four output terminals Po1, Po2, Po3, Po4. Thereby, three coils can be reduced rather than the DC-DC converter 6. Furthermore, the DC-DC converter 1B can reduce the three diodes D12, D13, D14 and the three capacitors C12, C13, C14 from the DC-DC converter 6.

  The output terminals Po1 to Po4 are connected to the first feedback voltage generation circuit 31. The output terminal (node N1) of the first feedback voltage generation circuit 31 is connected to the first feedback terminal FB1 of the control circuit 80A. The output terminals Po3 and Po4 are connected to the second feedback voltage generation circuit 41B. The output terminal (node N2) of the second feedback voltage generation circuit 41B is connected to the second feedback terminal FB2 of the control circuit 80A. The output terminals Po2, Po3, Po4 are connected to the third feedback voltage generation circuit 51B. The output terminal (node N3) of the third feedback voltage generation circuit 51B is connected to the third feedback terminal FB3 of the control circuit 80A. The output terminal Po4 is connected to the fourth feedback voltage generation circuit 61. The output terminal (node N4) of the fourth feedback voltage generation circuit 61 is connected to the fourth feedback terminal FB4 of the control circuit 80A.

  Here, in the DC-DC converter 1B, resistors R2 to R4, R16, R19, and R20 are added as compared with the DC-DC converter 6 shown in FIG. However, since the DC-DC converter 1B can reduce the three diodes D12, D13, D14, the three capacitors C12, C13, C14 and the three coils from the DC-DC converter 6 as described above, As a whole, the circuit area can be greatly reduced. In particular, since it is possible to reduce three coils that are difficult to reduce among various circuit elements, it is possible to achieve a significant reduction in circuit area and cost reduction.

  As described above, the DC-DC converter 1B uses the same control circuit 80A as the control circuit 80B used in the conventional DC-DC converter 6, and most circuit elements are externally attached to the control circuit 80A. The circuit configuration can be realized without change. Nevertheless, the DC-DC converter 1B can exhibit the excellent effects (1) to (4) described above.

(Modification of the second embodiment)
In the second embodiment, a single inductor multi-output type DC-DC converter that generates four output voltages Vo1 to Vo4 with one coil L is embodied. For example, the present invention may be embodied as a single inductor multi-output DC-DC converter that generates five or more output voltages with one coil L, for example. In this case, the number of stages of switch circuits connected in cascade in the output-side switch circuit 20B and the number of control units that perform on / off control of the switch circuits are appropriately adjusted. However, when the number (N) of output terminals connected to the coil L is a number other than 2 ⁿ , that is, when the number of output voltages other than 2 ⁿ is generated by one coil L, the output side In the switch circuit 20B, (N-1) switch circuits are provided by using the switch circuit cascade method of the second embodiment and the switch circuit cascade method of the first embodiment. Here, a case where six output terminals Po1 to Po6 are connected to one coil L and six output voltages Vo1 to Vo6 are generated by one coil L will be briefly described. In this case, the switch S21 included in the first-stage switch circuit 25 in the switch circuit 20B is electrically connected to N / 2 (here, three) output terminals Po1 to Po3, and the switch S22 is , N / 2 output terminals Po4 to Po6 are electrically connected. Then, two switch circuits are connected to the output terminal of the switch S21 by the cascade method of the first embodiment. That is, a switch circuit 26 having switches S31 and S32 whose first terminals are connected in series (cascade) to the output terminal of the switch S21 is provided, and two switches connected in series (cascade) to the output terminal of the switch S32 are provided. A switch circuit is provided. At this time, the output terminal of the switch S31 is connected to, for example, the output terminal Po1, and the output terminals of the two switches are connected to the output terminals Po2 and Po3, respectively.

  Similarly, two switch circuits are connected to the output terminal of the switch S22 by the cascade method of the first embodiment. That is, a switch circuit 27 having switches S41 and S42 whose first terminals are connected in series (cascade) to the output terminal of the switch S22 is provided, and two switches connected in series (cascade) to the output terminal of the switch S42 are provided. A switch circuit is provided. At this time, the output terminal of the switch S41 is connected to the output terminal Po4, for example, and the output terminals of the two switches are connected to the output terminals Po5 and Po6, respectively.

Even when the number of output voltages to be generated is increased, the same effects as the effects (1) to (3) of the first embodiment and the second embodiment can be obtained.
In FIG. 15, the switch SW11 is an example of a first switch circuit, the switch S21 is an example of a first switch element, the switch S22 is an example of a second switch element, and the switch S31 is an example of a third switch element. S32 is an example of a fourth switch element. The switch S41 is an example of a fifth switch element, the switch S42 is an example of a sixth switch element, the capacitor C1 is an example of a first capacitor, the capacitor C2 is an example of a second capacitor, and the capacitor C3 is an example of a third capacitor. The capacitor C4 is an example of a fourth capacitor. The drive output terminal DH1 is an example of a first drive output terminal, the drive output terminal DH2 is an example of a second drive output terminal, the drive output terminal DL2 is an example of a third drive output terminal, and the drive output terminal DH3 is a fourth drive output. An example of a terminal, the drive output terminal DL3 is an example of a fifth drive output terminal, the drive output terminal DH4 is an example of a sixth drive output terminal, and the drive output terminal DL4 is an example of a seventh drive output terminal. The output terminal Po1 is an example of a first output terminal, the output terminal Po2 is an example of a second output terminal, the output terminal Po3 is an example of a third output terminal, the output terminal Po4 is an example of a fourth output terminal, The output voltage Vo1 is an example of a first output voltage, the output voltage Vo2 is an example of a second output voltage, the output voltage Vo3 is an example of a third output voltage, and the output voltage Vo4 is an example of a fourth output voltage.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the above embodiments, the step-down DC-DC converters 1, 1 </ b> A, 1 </ b> B that generate N output voltages Vo <b> 1 to Vo <b> 4 (N is a natural number of 3 or more) lower than the input voltage Vin by one coil L It was materialized. However, the present invention is not limited to this, and may be embodied as a step-up DC-DC converter that generates N output voltages higher than the input voltage Vin by one coil L, for example. Further, for example, the present invention may be embodied as an inverting DC-DC converter that generates N output voltages obtained by inverting the input voltage Vin with one coil L. Furthermore, the present invention may be embodied in a single inductor multiple output type DC-DC converter that combines the step-down type, the step-up type, and the inverting type as described above. For example, a single coil L may be embodied in a DC-DC converter that combines a step-up type and an inverting type that generate an output voltage higher than the input voltage Vin and an output voltage obtained by inverting the input voltage Vin.

  In each of the above embodiments and each of the above modifications, an N-channel MOS transistor is disclosed as an example of the switch SW11 (first switch circuit), but a P-channel MOS transistor may be used. A bipolar transistor may be used as the switch SW11. Alternatively, a switch circuit including a plurality of transistors may be used as the switch SW11.

  In each of the above embodiments and each of the above modifications, an N-channel MOS transistor is disclosed as an example of the switches SW21, SW22, SW31, SW32, SW41, SW42, S21, S22, S31, S32, S41, and S42 (switch elements). However, a P-channel MOS transistor may be used. A bipolar transistor may be used as the switch element. Alternatively, a switch circuit including a plurality of transistors may be used as the switch element.

  In each of the above embodiments and each of the above modifications, an N-channel MOS transistor is disclosed as an example of the switch SW12 (synchronous switch circuit), but a P-channel MOS transistor may be used. A bipolar transistor may be used as the switch SW12. Alternatively, a switch circuit including a plurality of transistors may be used as the switch SW12.

In each of the above embodiments and modifications, the synchronous rectification type DC-DC converter is embodied, but the asynchronous rectification type DC-DC converter may be embodied.
The internal configurations of the first control unit 30, 30A, the second control unit 40, 40A, 40B, the third control unit 50, 50A, 50B, and the fourth control unit 60 in each of the above embodiments and each of the modifications are particularly limited. Not.

  -The oscillator 70 in each said embodiment and said each modification was made to produce | generate the periodic signal CK which is a sawtooth wave signal. Not limited to this, the oscillator 70 may generate a triangular wave signal.

In each of the above embodiments and each of the modifications, the voltage control mode DC-DC converter is embodied. However, the current control mode DC-DC converter may be embodied.
In each of the above embodiments and each of the modifications, the PWM control type DC-DC converter is embodied. However, a PFM (Pulse Frequency Modulation) control type DC-DC converter or a PSM (Pulse Skipping Modulation) control type DC is used. -It may be embodied in a DC converter. However, even in this case, the control signals VH1 and VL1 for controlling on / off of the switches SW11 and SW12 on the input side are the same as the control signals for controlling on / off of the switch circuits 20, 20A and 20B on the output side. A periodic signal is preferred.

1,1A, 1B DC-DC converter (power supply)
2, 3, 4, 5 Load 10 Converter section 20, 20A, 20B Switch circuit (second switch circuit)
21, 22, 23, 25, 26, 27 Switch circuit (third switch circuit)
30, 30A 1st control part (1st control part)
31, 31A First feedback voltage generation circuit 40, 40A Second control unit (second control unit)
40B 2nd control part (2nd control part and 3rd control part)
41, 41A, 41B Second feedback voltage generation circuit 50, 50A, 50B Third control unit (second control unit)
51, 51A, 51B Third feedback voltage generation circuit 60 Fourth control unit (second control unit)
61 Fourth feedback voltage generation circuit 70 Oscillator 80A Control circuit 81A First control circuit 82A Second control circuit 83A Third control circuit 84A Fourth control circuit L Coil C1 Capacitor (first capacitor)
C2 capacitor (second capacitor)
C3 capacitor (third capacitor)
C4 capacitor (4th capacitor)
SW11 switch (first switch circuit)
SW21, SW22, SW31, SW32, SW41, SW42 switch S21, S22, S31, S32, S41, S42 switch Po1, Po2, Po3, Po4 output terminal (first output terminal)
Vin input voltage Vo1, Vo2, Vo3, Vo4 output voltage VFB1 first feedback voltage VFB2 second feedback voltage VFB3 third feedback voltage VFB4 fourth feedback voltage

Claims (10)

Coils,
A first switch circuit connected to the first terminal of the coil for storing energy in the coil;
A second switch circuit provided between the second terminal of the coil and N (N is a natural number of 3 or more) first output terminals;
On / off control of the first switch circuit based on an error signal corresponding to a difference voltage between a first synthesized voltage obtained by synthesizing N output voltages generated at the N first output terminals and a reference voltage, respectively. A first control unit for generating a first control signal to be
Based on the error signals corresponding to the remaining (N−1) second output voltages excluding one first output voltage among the N output voltages, in the same cycle as the first control signal. A second control unit that generates a plurality of second control signals for controlling on / off of the second switch circuit,
The second switch circuit is connected in cascade between a second terminal of the coil and the N first output terminals, and according to a combination of signal levels of the plurality of second control signals, (N-1) third switch circuits for selectively connecting any one of the N first output terminals to the second terminal of the coil;
Each of the third switch circuits includes two switch elements, and the two switch elements included in the third switch circuit in the first stage among the (N-1) third switch circuits are the second switch elements of the coil. The two switch elements that are connected in common to the terminal and that are included in the second and subsequent third switch circuits among the (N−1) third switch circuits are the two switch elements included in the preceding third switch circuit. A power supply apparatus characterized by being connected in common to an output terminal of one of the switch elements.   The second control unit determines a second output voltage to be input from a second combined voltage obtained by combining (N−1) second output voltages and the (N−1) second output voltages. Based on M (M-2 (N−2),..., 1) second output voltages, which are reduced one by one, and the (N−2) different third synthesized voltages, The power supply device according to claim 1, wherein on / off control is performed. The second and subsequent third switch circuits are connected in cascade only to the output terminal of one of the two switch elements of the first switch circuit.
The other switch element of the two switch elements included in the first switch circuit of the first stage is directly connected to a first output terminal that generates the first output voltage among the N first output terminals. ,
The two switch elements included in the second and subsequent third switch circuits are directly connected to any one first output terminal of the first output terminals from which the second output voltage is generated. One switch element and the third switch circuit of the next stage are cascade-connected, or directly connected to any one first output terminal of the first output terminals from which the second output voltage is generated The power supply device according to claim 2, further comprising a second switch element.   The second control unit is configured to electrically connect an output terminal of one of the two switch elements included in the third switch circuit of the i-th stage (i is a natural number from 1 to (N-1)). L first outputs that are connected to each other (L is a natural number from 1 to (N-1)) are connected, and the L second outputs that are generated at the L first outputs The control circuit according to claim 1, further comprising: (N-1) control units that generate the second control signal for on / off control of the i-th third switch circuit based on a result of combining the voltages. 4. The power supply device according to 3. The second and subsequent third switch circuits include a fourth switch circuit connected in cascade to one of the two switch elements of the first stage third switch circuit, and the first stage A fifth switch circuit connected in cascade to the other switch element of the two switch elements of the third switch circuit of the eye,
The two switch elements included in the fourth switch circuit and the fifth switch circuit are connected in cascade with the third switch circuit in the next stage, or one of the N first output terminals. The power supply device according to claim 2, wherein the power supply device is directly connected to two first output terminals.   The second control unit is connected to a predetermined number of first output terminals not connected to the one switch element of the first switch circuit of the first stage, and connected to the predetermined number of first output terminals. A third control unit configured to generate the second control signal for performing on / off control of the third switch circuit at the first stage based on a result of synthesizing the predetermined number of second output voltages to be generated; The power supply device according to claim 5. 7. The power supply device according to claim 5, wherein the N first output terminals are 2 ⁿ (n is a natural number of 2 or more) first output terminals. 8. At least a first control circuit, a second control circuit, and a third control circuit, the first feedback terminal connected to the input terminal of the first control circuit, and the output terminal of the first control circuit; A first drive output terminal; a second feedback terminal connected to the input terminal of the second control circuit; second and third drive output terminals connected to the output terminal of the second control circuit; A control circuit having a third feedback terminal connected to the input terminal of the control circuit, and fourth and fifth drive output terminals connected to the output terminal of the third control circuit;
A first switch circuit having a control terminal connected to the first drive output terminal, a first terminal connected to an input terminal to which an input voltage is supplied, and a second terminal connected to the first terminal of the coil;
A first switch element having a control terminal connected to the second drive output terminal, a first terminal connected to a second terminal of the coil, and a second terminal connected to the first capacitor and the first output terminal; ,
A second switching element having a control terminal connected to the third drive output terminal and a first terminal connected to a second terminal of the coil;
A control terminal is connected to the fourth drive output terminal, a first terminal is connected to a second terminal of the second switch element, and a second terminal is connected to a second capacitor and a second output terminal. Switch elements of
A control terminal is connected to the fifth drive output terminal, a first terminal is connected to a second terminal of the second switch element, and a second terminal is connected to a third capacitor and a third output terminal; or A fourth switch element connected in cascade with two switch elements different from the first to third switch elements;
At least a first output voltage generated at the first output terminal, a second output voltage generated at the second output terminal, and a third output voltage generated at the third output terminal; A first feedback voltage generation circuit that outputs a first feedback voltage corresponding to the synthesized voltage to the first feedback terminal;
A second feedback voltage generation circuit that outputs a second feedback voltage to the second feedback terminal according to a voltage obtained by combining at least the second output voltage and the third output voltage;
A third feedback voltage generation circuit that outputs at least a third feedback voltage corresponding to the third output voltage to the third feedback terminal;
A power supply device comprising: A first feedback terminal having a first control circuit, a second control circuit, a third control circuit, and a fourth control circuit, connected to an input terminal of the first control circuit, and an output terminal of the first control circuit A first drive output terminal connected to the second control circuit; a second feedback terminal connected to the input terminal of the second control circuit; and second and third drive output terminals connected to the output terminal of the second control circuit; A third feedback terminal connected to the input terminal of the third control circuit, fourth and fifth drive output terminals connected to the output terminal of the third control circuit, and an input terminal of the fourth control circuit. A control circuit having a connected fourth feedback terminal and sixth and seventh drive output terminals connected to an output terminal of the fourth control circuit;
A first switch circuit having a control terminal connected to the first drive output terminal, a first terminal connected to an input terminal to which an input voltage is supplied, and a second terminal connected to the first terminal of the coil;
A first switching element having a control terminal connected to the second drive output terminal and a first terminal connected to a second terminal of the coil;
A second switching element having a control terminal connected to the third drive output terminal and a first terminal connected to a second terminal of the coil;
A control terminal is connected to the fourth drive output terminal, a first terminal is connected to the second terminal of the first switch element, and a second terminal is connected to the first capacitor and the first output terminal. Switch elements of
A control terminal is connected to the fifth drive output terminal, a first terminal is connected to a second terminal of the first switch element, and a second terminal is connected to a second capacitor and a second output terminal. Switch elements of
A control terminal is connected to the sixth drive output terminal, a first terminal is connected to a second terminal of the second switch element, and a second terminal is connected to a third capacitor and a third output terminal. Switch elements of
A control terminal is connected to the seventh drive output terminal, a first terminal is connected to a second terminal of the second switch element, and a second terminal is connected to a fourth capacitor and a fourth output terminal. Switch elements of
A first output voltage generated at the first output terminal; a second output voltage generated at the second output terminal; a third output voltage generated at the third output terminal; A first feedback voltage generation circuit that outputs to the first feedback terminal a first feedback voltage corresponding to a voltage obtained by combining the fourth output voltage generated at the four output terminals;
A second feedback voltage generation circuit for outputting a second feedback voltage to the second feedback terminal according to a voltage obtained by combining the third output voltage and the fourth output voltage;
A third feedback voltage generation circuit that outputs a third feedback voltage to the third feedback terminal according to a voltage obtained by combining the second output voltage, the third output voltage, and the fourth output voltage;
A fourth feedback voltage generation circuit that outputs a fourth feedback voltage corresponding to the fourth output voltage to the fourth feedback terminal;
A power supply device comprising: (N-1) pieces connected in cascade between the coil, a first switch circuit for storing energy in the coil, and the first output terminal of the coil and N pieces (N is a natural number of 3 or more) And a second switch circuit having a switch circuit of
Based on a first synthesized voltage obtained by synthesizing N output voltages respectively generated at the N first output terminals, the first switch circuit is configured to bring the first synthesized voltage closer to a first target value. ON / OFF control,
Based on the remaining (N−1) second output voltages excluding one first output voltage among the N output voltages, the second output voltages are brought close to the corresponding second target values. And a method of controlling the power supply, wherein the second switch circuit is on / off controlled at the same frequency as the switching frequency of the first switch circuit.