JP2014093637A - Switch device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce fluctuations in voltage caused at an input/output terminal when a control signal rises and falls.SOLUTION: A switch device includes: an analog switch circuit 3 having a pair of input/output terminals 11, 12, a control terminal 13 fed with a control signal S2, a main switch 16 comprising MOS transistors, and a control circuit 19; a voltage generation circuit 4 for generating a reference voltage Vr at a set voltage to be output from a voltage output terminal 4a; and a make/break circuit 5 disposed between the input/output terminal 12 of the analog switch circuit 3 and the voltage output terminal 4a to switch on/off the output of the reference voltage Vr to the input/output terminal 12. The analog switch circuit 3 is transitioned from either of an on state and an off state to the other while the make/break circuit 5 turned on outputs the reference voltage Vr to the input/output terminal 12.

Description

  The present invention relates to a switch device having an analog switch circuit in which a main switch is composed of MOS transistors.

  As a general analog switch circuit used in this type of switch device, an analog switch circuit disclosed as a conventional technique in Patent Document 1 below is known. As shown in FIG. 4, the analog switch circuit 3 includes a pair of input / output terminals 11 and 12 to which a transmission signal S1 is input / output, a control terminal 13 to which a control signal S2 is input, and a high potential voltage Vdd. Input high potential power supply terminal 14, low potential power supply terminal 15 to which low potential voltage Vss is input, main switch 16 composed of p channel MOS transistor Q1 and n channel MOS transistor Q2, p channel MOS transistor Q3 and n channel One control switch 17 comprising a MOS transistor Q4 and controlling the back gate of the main switch 16, the other control switch comprising a p-channel MOS transistor Q5 and an n-channel MOS transistor Q6 and controlling the back gate of the main switch 16 18. Each MOS transistor Q Includes n-channel MOS transistors Q7 and control circuit 19, the pull-down controlling the back gate potential of the MOS transistor Q2 via Q4, Q5, Q6.

  The control circuit 19 operates with the high potential voltage Vdd having the low potential voltage Vss as a reference potential as an operation voltage, and also with an inverted signal (reverse phase to the control signal S2) based on the control signal S2 input from the control terminal 13. Signal) S3 and a control signal S4 (a signal in phase with the control signal S2) are generated and supplied to the gate terminals of the MOS transistors Q1 to Q7. As a result, the control circuit 19 turns the main switch 16 on and off. In this case, the inversion signal S3 and the control signal S4 are configured such that the control circuit 19 operates using the high potential voltage Vdd with the low potential voltage Vss as the reference potential as the operating voltage, and therefore the L level is in the vicinity of the low potential voltage Vss. The H level becomes a voltage in the vicinity of the high potential voltage Vdd.

  In the switch device using the analog switch circuit 3, the maximum potential (maximum rating on the high voltage side) V + and the negative power supply voltage for the positive power supply voltage of the analog switch circuit 3 as the high potential voltage Vdd and the low potential voltage Vss. In general, a configuration for supplying a maximum rating (maximum rating on the low voltage side) V− is adopted. For this reason, in this configuration, the inverted signal S3 and the control signal S4 output from the control circuit 19 have an L level near the maximum rating V− and an H level near the maximum rating V +.

  In this analog switch circuit 3, when the control signal S2 of H level is input to the control circuit 19, the control circuit 19 detects the inverted signal S3 of the voltage (L level) near the maximum rating V− and the vicinity of the maximum rating V +. The control signal S4 of the voltage (H level) is output. As a result, the p-channel MOS transistors Q1, Q3 and Q5 to which the inverted signal S3 of L level is supplied to the gate terminal are turned on, and the control signal S4 of H level is supplied to the gate terminal. N channel MOS transistors Q2, Q4 and Q6 are simultaneously turned on. On the other hand, the n-channel MOS transistor Q7 to which the inverted signal S3 of L level is supplied to the gate terminal shifts to the off state. As a result, the analog switch circuit 3 shifts to an ON state in which the transmission signal S1 can be transmitted (bidirectional transmission) between the pair of input / output terminals 11 and 12.

  On the other hand, when an L level control signal S2 is input to the control circuit 19, the control circuit 19 outputs an inverted signal S3 of a voltage (H level) near the maximum rating V + and a voltage (L level) near the maximum rating V−. ) Control signal S4. As a result, the p-channel MOS transistors Q1, Q3, and Q5 to which the H level inversion signal S3 is supplied to the gate terminal are turned off, and the L level control signal S4 is supplied to the gate terminal. N channel MOS transistors Q2, Q4 and Q6 are simultaneously turned off. On the other hand, the n-channel MOS transistor Q7 to which the H level inversion signal S3 is supplied to the gate terminal is turned on, and the back gate potential of the MOS transistor Q2 of the main switch 16 is pulled down to the low potential voltage Vss. Thereby, the analog switch circuit 3 shifts to an off state in which transmission of the transmission signal S1 between the pair of input / output terminals 11 and 12 is impossible.

Japanese Patent Laid-Open No. 3-48520 (2nd page, FIG. 3)

  By the way, in the analog switch circuit configured as described above, the main signal is supplied at the rise and fall of the inverted signal S3 and the control signal S4 supplied to the gate terminal (that is, at the rise and fall of the control signal S2). Each MOS transistor Q1, Q2 constituting the switch 16 and each MOS transistor Q3, Q4, Q5, Q6 constituting each control switch 17, 18 for controlling the back gate of the main switch 16 have a gate Charge transfer occurs between each gate terminal and the pair of input / output terminals 11 and 12 via the source-to-source capacitance and the gate-drain capacitance. When an input transmission signal is output from the other input / output terminal 12, Phenomenon voltage fluctuates (voltage of the input and output terminal 12 is swung) always occurs.

  However, in the configuration in which the maximum ratings V + and V− of the analog switch circuit 3 are set to the high potential voltage Vdd and the low potential voltage Vss as in the above-described conventional switch device using the analog switch circuit 3, the analog switch circuit 3 As described above, the gate terminal of each of the MOS transistors Q1 to Q6 changes from the voltage near the maximum rating V + (H level) to the voltage near the maximum rating V− (L level), and from this L level. Since the inverted signal S3 and the control signal S4 that change to the H level are supplied, a large voltage fluctuation always occurs at the other input / output terminal 12 in accordance with the potential difference between the maximum ratings V + and V−. There is a problem to be solved that is difficult to reduce.

  The present invention has been made in view of such a problem, and a main object of the present invention is to provide a switch device that can reduce fluctuations in voltage generated at an input / output terminal when a control signal rises and falls.

  In order to achieve the above object, a switching device according to claim 1 includes a pair of input / output terminals, a control terminal to which a control signal is input, a high potential power supply terminal, a low potential power supply terminal, a p-channel MOS transistor and an n-channel MOS transistor. The main switch and the control circuit are operated by a high potential voltage input to the high potential power supply terminal and a low potential voltage input to the low potential power supply terminal. The control circuit generates an inverted signal of the control signal and outputs the control signal and the inverted signal to the main switch, and the MOS transistors of the main switch are turned on based on the control signal and the inverted signal. By simultaneously shifting to either the state or the off state, the pair An analog switch circuit that turns on and off the output from the other input / output terminal of the transmission signal input to one of the input / output terminals, and a voltage output by generating a reference voltage with the set voltage A voltage generation circuit that outputs from a terminal, and is disposed between the other input / output terminal of the analog switch circuit and the voltage output terminal to turn on the output of the reference voltage to the other input / output terminal. A connection circuit that turns off, and the analog switch circuit is either in an on state or an off state when the connection circuit in the on state outputs the reference voltage to the other input / output terminal. The state is shifted to the other state.

  According to a second aspect of the present invention, the switch device according to the first aspect has an enable terminal, and outputs a signal input to the input terminal from the output terminal to the analog switch circuit as the transmission signal. There is provided a buffer capable of transitioning to any one of a state and a state where the output terminal is set to high impedance.

  The switch device according to claim 1 is provided between the other input / output terminal of the analog switch circuit and the voltage output terminal of the voltage generation circuit for outputting the reference voltage, and outputs the reference voltage to the other input / output terminal. When the on / off circuit outputs a reference voltage to the other input / output terminal, the analog switch circuit is in either the on or off state. To the other state.

  Therefore, according to this switch device, when the analog switch circuit is turned on / off (at the time of rising and falling of the control signal), the gate / source inherent in each of the MOS transistors constituting the analog switch circuit Even if charge transfer occurs between each gate terminal and a pair of input / output terminals via the inter-capacitance and gate-drain capacity, the other input / output terminal generates a voltage via a disconnection circuit. Since the reference voltage is applied from the circuit and the output signal is regulated to this reference voltage Vr, the fluctuation of the voltage generated at the other input / output terminal due to the movement of the charge can be greatly reduced. .

  According to the switching device of the second aspect of the present invention, since the signal input from the outside through the buffer having the enable terminal is output to the one input / output terminal of the analog switch circuit as a transmission signal, bidirectional Even when the analog switch circuit is switched to the ON state, the buffer is disabled even if the connection circuit is turned ON and the reference voltage is output from the voltage generation circuit to the other input / output terminal of the analog switch circuit. By doing so, it is possible to avoid the occurrence of a situation where the reference voltage and the transmission signal collide via the analog switch circuit in the on state.

1 is a configuration diagram showing a configuration of a switch device 1 using an analog switch circuit 3. FIG. FIG. 4 is a circuit diagram of the disconnect circuit 5. 4 is a waveform diagram for explaining the operation of the switch device 1. FIG. 3 is a circuit diagram of an analog switch circuit 3. FIG.

  Hereinafter, embodiments of a switch device having an analog switch circuit will be described with reference to the accompanying drawings.

  First, the configuration of the switch device 1 will be described with reference to FIGS. As shown in FIG. 1, the switch device 1 includes a buffer 2, an analog switch circuit 3, a voltage generation circuit 4, and a disconnection circuit 5. In the switch device 1, the buffer 2, the analog switch circuit 3, the voltage generation circuit 4, and the connection / disconnection circuit 5 are supplied from a power source (not shown) provided in the switch device 1 (or a power source external to the switch device 1). The high potential voltage Vdd and the low potential voltage Vss are operated as operating voltages.

  The buffer 2 has an enable terminal as shown in FIG. As a result, the buffer 2 uses the signal Sin input to the input terminal (an AC signal in which the maximum voltage Vmax is less than the high potential voltage Vdd and the minimum voltage Vmin exceeds the low potential voltage Vss) as the transmission signal S1 from the output terminal. It is configured to be able to shift to one of a state of outputting to the analog switch circuit 3 and a state of setting the output terminal to high impedance. In this example, as an example, when the enable operation for setting the enable signal Sen input to the enable terminal to the H level is performed, the buffer 2 transmits the signal Sin input to the input terminal from the output terminal to the transmission signal S1. When the disabling operation for setting the enable signal Sen to the L level is being performed, the state shifts to the state where the output terminal is set to high impedance (disenable state). To do. It is also possible to use a buffer whose polarity of the enable signal Sen input to the enable terminal is opposite to that of the above configuration.

  As shown in FIG. 1, the analog switch circuit 3 includes a pair of input / output terminals 11, 12, a control terminal 13, a high potential power terminal 14, a low potential power terminal 15, a main switch 16, control switches 17, 18, And a control circuit 19, which is the same as the conventional analog switch circuit 3. In this case, the maximum voltage Vmax and the minimum voltage Vmin are included in one of the input / output terminals 11 and 12 (in this example, the input / output terminal 11) so as to be included in the input rating of the analog switch circuit 3. When a known transmission signal S1 is input from the outside and the main switch 16 is in an ON state, the transmission signal S1 is transmitted through the analog switch circuit 3 and output from the other input / output terminal (in this example, the input / output terminal 12). Output as Sout. A control signal S2 is input to the control terminal 13. The high potential power supply terminal 14 is supplied with a high potential voltage Vdd, and the low potential power supply terminal 15 is supplied with a low potential voltage Vss.

  The main switch 16 is composed of a p-channel MOS transistor Q1 and an n-channel MOS transistor Q2. One control switch 17 includes a p-channel MOS transistor Q3 and an n-channel MOS transistor Q4, and controls the back gate of the main switch 16. The other control switch 18 is also composed of a p-channel MOS transistor Q5 and an n-channel MOS transistor Q6, and controls the back gate of the main switch 16. N channel MOS transistor Q7 controls the back gate potential of MOS transistor Q2 through MOS transistors Q3, Q4, Q5 and Q6.

  The control circuit 19 includes two inverters connected in series as an example. Based on the control signal S2 input from the control terminal 13, the control circuit 19 has an inverted signal S3 having a phase opposite to that of the control signal S2 and the same phase as that of the control signal S2. The control signal S4 is generated and supplied to the gate terminals of the MOS transistors Q1 to Q6, whereby the main switch 16 is turned on / off. Control circuit 19 supplies inverted signal S3 to the gate terminal of n channel MOS transistor Q7 to turn on / off n channel MOS transistor Q7. The control circuit 19 operates using the high potential voltage Vdd and the low potential voltage Vss as operating voltages. Therefore, the control circuit 19 outputs the inverted signal S3 and the control signal S4 in which the H level becomes a voltage near the high potential voltage Vdd and the L level becomes a voltage near the low potential voltage Vss.

  With this configuration, when a switch-off operation that regulates the control signal S2 to L level is performed, the analog switch circuit 3 is in a high impedance state for each of the input / output terminals 11 and 12, and the pair of input / output terminals. When a switch-on operation is performed in which the control signal S2 is set to the H level when the transmission signal S1 between the terminals 11 and 12 cannot be transmitted (bidirectional transmission), and the control signal S2 is set to the H level. 11 and 12 shift to an ON state in which the transmission signal S1 can be transmitted (bidirectional transmission). As for the polarity of the control signal S2, a configuration in which the analog switch circuit 3 shifts to either the on state or the off state with a polarity opposite to the above polarity may be employed.

  As shown in FIG. 1, the voltage generation circuit 4 is composed of a variable voltage power source capable of controlling a reference voltage Vr as a DC voltage to be generated. Specifically, when voltage data Dv is input, the voltage generation circuit 4 generates a reference voltage Vr with an arbitrary voltage defined by the voltage data Dv and outputs the reference voltage Vr from the voltage output terminal 4a. In this example, the voltage generation circuit 4 outputs two different voltages, that is, a low potential voltage Vss and zero volt as the reference voltage Vr, as will be described later. For this reason, the voltage generation circuit 4 replaces the above-described configuration for generating the reference voltage Vr with an arbitrary voltage defined by the voltage data Dv, for example, according to the level of the switching signal, the low potential voltage Vss and zero volt. A configuration in which the reference voltage Vr is generated with one of the two voltages may be employed.

  The connection / disconnection circuit 5 is disposed (connected) between the other input / output terminal 12 of the analog switch circuit 3 and the voltage output terminal 4 a of the voltage generation circuit 4. In addition, the connection / disconnection circuit 5 shifts to an arbitrary state of an on state and an off state based on the control voltage Vcnt, and when it is in the on state, the reference output from the voltage output terminal 4a of the voltage generation circuit 4 The voltage Vr is output to the other input / output terminal 12 of the analog switch circuit 3, and the voltage of the other input / output terminal 12 is defined as the reference voltage Vr. On the other hand, in the off state, the voltage output terminal 4a and the input / output terminal 12 is separated.

  In this example, as an example, the connection / disconnection circuit 5 is composed of one n-channel MOS transistor 5a (hereinafter also referred to as “MOS transistor 5a”) as shown in FIG. The voltage output terminal 4 a is connected to the input / output terminal 12 of the analog switch circuit 3. As a result, the connection / disconnection circuit 5 has a control voltage Vcnt at which the difference (= Vcnt−Vr) from the reference voltage Vr is equal to or higher than the threshold voltage with reference to the source terminal to which the reference voltage Vr is applied from the voltage generation circuit 4. When a connection operation applied to the gate terminal is performed, the voltage is switched to the ON state, and the other input / output terminal 12 is pulled down to the reference voltage Vr, thereby pulling up or pulling up the voltage of the other input / output terminal 12. The voltage is specified as Vr. Further, the disconnection circuit 5 is a disconnection operation in which the control voltage Vcnt that makes the difference from the reference voltage Vr less than the threshold voltage is applied to the gate terminal with reference to the source terminal to which the reference voltage Vr is applied from the voltage generation circuit 4. When the operation is performed, the state shifts to the off state. As a result, the voltage output terminal 4a of the voltage generation circuit 4 and the other input / output terminal 12 of the analog switch circuit 3 are disconnected. By configuring the disconnection circuit 5 with the MOS transistor 5a as in this example, the disconnection circuit 5 can be formed on the same semiconductor chip as the analog switch circuit 3 configured with the same MOS transistor. . Note that the connection / disconnection circuit 5 can be configured by a relay or the like that shifts to any state of the on state and the off state based on the control voltage Vcnt, for example, instead of the MOS transistor 5a.

  Next, the operation together with the operation method of the switch device 1 will be described.

  First, the operation of each component of the switch device 1 will be described together with the operation when the switch device 1 is turned off (the state in which the signal Sin is input but not output as the output signal Sout).

  The switch device 1 executes the above-described disenable operation to shift the buffer 2 to the disable state, and also executes the switch-off operation to shift the analog switch circuit 3 to the off state. Thus, the above connection operation is executed, and the reference voltage Vr output from the voltage output terminal 4a of the voltage generation circuit 4 is supplied to the other input of the analog switch circuit 3 via the ON / OFF connection circuit 5. By outputting to the output terminal 12, it is possible to shift to the off state.

  However, in the switch device 1, the analog switch circuit 3 is shifted to the off state by executing the switch off operation, and the connection operation is controlled to shift the analog switch circuit 3 from the off state to the on state. In order to reduce the fluctuation of the voltage generated at the other input / output terminal 12 at the rising edge of the signal S2 and at the falling edge of the control signal S2 for shifting the analog switch circuit 3 from the on state to the off state, control is performed. It is executed only during a period including the rising time of the signal S2 (period Tc shown in FIG. 3) and a period including the falling time of the control signal S2 (period Th shown in FIG. 3). A disconnect operation is performed on

  The disable operation is executed in the following cases. That is, in a state where the switch-on operation is performed and the bidirectional analog switch circuit 3 is turned on, the connection operation is performed and the reference voltage Vr is supplied from the voltage generation circuit 4 to the other side of the analog switch circuit 3. When the transmission signal S1 is output from the buffer 2 when the signal is output to the input / output terminal 12, the reference voltage Vr and the transmission signal S1 collide via the analog switch circuit 3 in the ON state. In order to avoid this collision, the disable operation is performed over a period including the entire period in which both the analog switch circuit 3 and the connection / disconnection circuit 5 are in the ON state.

  Specifically, as shown in FIG. 3, when the analog switch circuit 3 is shifted from the OFF state to the ON state, the disable operation is performed after the connection / disconnection circuit 5 is shifted to the ON state. Execution is started before the signal S2 is shifted from the L level to the H level (the analog switch circuit 3 is shifted to the on state), and the execution is stopped after the connection circuit 5 is shifted from the on state to the off state. . Further, when the analog switch circuit 3 is shifted from the on state to the off state, the disenable operation is started before the disconnect circuit 5 is shifted from the off state to the on state, and the disconnect circuit 5 is turned on. Execution is stopped after the transition to the state and before the control signal S2 is shifted from the H level to the L level (the analog switch circuit 3 is shifted to the OFF state). Since the output terminal of the buffer 2 is maintained in a high impedance state (the transmission signal S1 is in an indefinite state) when the buffer 2 is shifted to the disable state by executing this disable operation, the analog switch circuit 3 and the connection / disconnection circuit 5 are both in the ON state, the collision between the transmission signal S1 and the reference voltage Vr is avoided. In FIG. 3, the output terminal of the buffer 2 and the input / output terminal 12 of the analog switch circuit 3 are in a high impedance state (when the output signal from these terminals is in an indefinite state). Represents.

  Next, the operation of each component of the switch device 1 will be described together with the operation for shifting the switch device 1 from the off state to the on state and outputting the signal Sin as the output signal Sout.

  In this case, in the period Ta, the switch-off operation for the analog switch circuit 3 is executed, and the analog switch circuit 3 is maintained in the off state. As a result, the input / output terminal 12 is maintained in a high impedance state. Further, during this period Ta, the disconnection operation for the disconnection circuit 5 is executed and the disconnection circuit 5 is maintained in the OFF state, whereby the input / output terminal 12 and the voltage output terminal 4a of the voltage generation circuit 4 are disconnected. It is. In this cutting operation during the period Ta, the control voltage Vcnt having the same voltage as the low potential voltage Vss is output to the disconnection circuit 5 and the voltage data Dv for defining the reference voltage Vr as the low potential voltage Vss is generated in the voltage generation circuit. It is executed by outputting to 4. For this reason, the lowest low-potential voltage Vss of the voltages supplied to the switch device 1 is applied as the reference voltage Vr to the source terminal of the MOS transistor 5a constituting the disconnection circuit 5. Therefore, even if the voltage of the input / output terminal 12 in the analog switch circuit 3 changes within the range of the high potential voltage Vdd and the low potential voltage Vss, the current from the voltage output terminal 4a of the voltage generation circuit 4 to the input / output terminal 12 Inflow (through the parasitic diode of the MOS transistor 5a) and inflow of current from the input / output terminal 12 to the voltage output terminal 4a are both blocked by the disconnection circuit 5. As a result, the output signal Sout is maintained in a high impedance state (the output signal Sout is indefinite).

  As shown in FIG. 3, in the period Tb following the period Ta, the switch-off operation for the analog switch circuit 3 is continued and the disconnection operation for the connection / disconnection circuit 5 is also continued. However, since the reference potential of the signal Sin that is an AC signal (sine wave signal) is zero volts as in this example, the cutting operation in this period Tb outputs the control voltage Vcnt of zero volts to the disconnection circuit 5, And it is executed by outputting voltage data Dv for defining the reference voltage Vr to zero volts to the voltage generation circuit 4. For this reason, a zero volt reference voltage Vr is applied from the voltage generation circuit 4 to the source terminal of the MOS transistor 5 a constituting the disconnection circuit 5. Therefore, when the voltage of the input / output terminal 12 in the analog switch circuit 3 changes within a range exceeding zero volt, the inflow of current from the voltage output terminal 4a of the voltage generation circuit 4 to the input / output terminal 12, and the input / output terminal Any inflow of current from 12 to the voltage output terminal 4 a is interrupted by the disconnection circuit 5. As a result, the output signal Sout is maintained in a high impedance state (the output signal Sout is indefinite).

  As shown in FIG. 3, in the period Tc following the period Tb, the switch-on operation is performed on the analog switch circuit 3 to shift the analog switch circuit 3 to the on state. Therefore, before the analog switch circuit 3 is turned on, a connection operation to the connection / disconnection circuit 5 is executed, and the reference voltage Vr output from the voltage generation circuit 4 is used as the input / output terminal 12 of the analog switch circuit 3. Apply to. Specifically, since the reference potential of the signal Sin is zero volts, a control voltage Vcnt of a predetermined voltage that makes the potential difference with the reference voltage Vr equal to or higher than the threshold voltage of the MOS transistor 5a is maintained while maintaining the reference voltage Vr at zero volts. A connection operation of outputting to the disconnection circuit 5 is executed to shift the disconnection circuit 5 to the on state. As a result, in the period Tc, the input / output terminal 12 and the voltage output terminal 4a are connected via the ON / OFF connection circuit 5, and the connection / disconnection circuit 5 is connected to the input / output terminal 12 of the analog switch circuit 3. The reference voltage Vr (zero volt) is applied from the voltage generation circuit 4 via Therefore, the voltage at the input / output terminal 12 (the voltage of the output signal Sout) is defined as the reference voltage Vr (zero volts). Further, before the execution of the switch-on operation for the analog switch circuit 3 is started, the disable operation for the buffer 2 is executed to shift the buffer 2 to the disable state.

  In this way, by performing the switch-on operation when the buffer 2 is disabled in the period Tc in which the reference voltage Vr (zero volt) is applied to the input / output terminal 12 from the voltage generation circuit 4, The switch circuit 3 is shifted from the off state to the on state. In this case, in the analog switch circuit 3, when the control signal S2 rises from the L level to the H level (that is, when the inverted signal S3 falls and when the control signal S4 rises) Gate-source capacitances and gates, which are inherent in each of the MOS transistors Q3, Q4, Q5, Q6 constituting the MOS transistors Q1, Q2 and the control switches 17, 18 for controlling the back gate of the main switch 16, respectively. Charge transfer occurs between each gate terminal and the pair of input / output terminals 11 and 12 via the inter-drain capacitance. However, in the switch device 1, when the analog switch circuit 3 shifts from the off state to the on state, the reference voltage Vr (zero volts) is applied from the voltage generation circuit 4 to the input / output terminal 12, and the output signal Sout Is defined as the reference voltage Vr. For this reason, the fluctuation of the voltage generated in the output signal Sout due to the movement of the charge is greatly reduced. Further, since the buffer 2 is shifted to the disable state, even if the reference voltage Vr applied to the input / output terminal 12 is transmitted to the input / output terminal 11 side through the analog switch circuit 3 in the on state, Signal collisions are avoided.

  As shown in FIG. 3, in the period Td following the period Tc, the switch-on operation for the analog switch circuit 3 is continued and the disconnection operation for the connection / disconnection circuit 5 is executed. However, the cutting operation in this period Tb is the same as in the period Tb described above, and voltage data Dv for outputting the control voltage Vcnt of zero volts to the connection / disconnection circuit 5 and defining the reference voltage Vr to zero volts. Is output to the voltage generation circuit 4. Further, during this period Td, since the cutting operation for the connection / disconnection circuit 5 is executed, the application of the reference voltage Vr to the input / output terminal 12 is stopped. For this reason, even if the analog switch circuit 3 is in the on state, the collision of the signals is avoided. For this reason, the disenable operation for the buffer 2 continued from the period Tc is stopped after the disconnection operation for the connection / disconnection circuit 5 is executed.

  As shown in FIG. 3, in the period Te following the period Td, the switch-on operation for the analog switch circuit 3 is continued and the disconnection operation for the connection / disconnection circuit 5 is continued. However, the cutting operation during this period Te outputs the control voltage Vcnt of the low potential voltage Vss to the connection circuit 5 and the voltage data Dv for defining the reference voltage Vr to the low potential voltage Vss as the voltage generation circuit 4. It is executed by outputting to.

  In this period Te, the source terminal of the MOS transistor 5a constituting the connection / disconnection circuit 5 is defined as the lowest low-potential voltage Vss of the voltages supplied to the switch device 1, and therefore in the analog switch circuit 3 Even if the voltage of the input / output terminal 12 changes within the range of the high potential voltage Vdd and the low potential voltage Vss (even if the transmission signal S1 is output from the input / output terminal 12 as the output signal Sout), the voltage generation circuit 4 Both current inflow from the voltage output terminal 4a to the input / output terminal 12 (inflow through the parasitic diode of the MOS transistor 5a) and current inflow from the input / output terminal 12 to the voltage output terminal 4a are disconnected. Interrupted by circuit 5. Thereby, in this period Te, the analog switch circuit 3 can output the input transmission signal S1 from the input / output terminal 12 as the output signal Sout in a state where the waveform is not distorted.

  Therefore, as shown in FIG. 3, during this period Te, the enable operation for the buffer 2 is executed, and the signal Sin input to the buffer 2 is transmitted from the output terminal of the buffer 2 to the analog switch circuit 3 as the transmission signal S1. By outputting the signal, the switch device 1 outputs the input signal Sin from the input / output terminal 12 of the analog switch circuit 3 as the output signal Sout during the period Tf in which the H level enable signal Sen is input. Note that when the enable signal Sen is switched from the H level to the L level within the period Te, the buffer 2 stops outputting the transmission signal S1 to the analog switch circuit 3 and shifts the output terminal to a high impedance state. . Therefore, in this case, the switching device 1 shifts the input / output terminal 12 to the high impedance state and stops the operation of outputting the transmission signal S1 as the output signal Sout (the output signal Sout is in an indefinite state). Transition).

  Subsequently, the operation of each component of the switch device 1 will be described together with the operation for shifting the switch device 1 from the on state to the off state and stopping the output of the signal Sin as the output signal Sout.

  In this case, as shown in FIG. 3, in the period Tg following the period Te, the switch-on operation for the analog switch circuit 3 is continued and the disconnection operation for the connection / disconnection circuit 5 is executed. However, the cutting operation in this period Tg is the same as in the above-described period Td, and the voltage data Dv for outputting the control voltage Vcnt of zero volts to the disconnection circuit 5 and defining the reference voltage Vr to zero volts. Is output to the voltage generation circuit 4 and executed. Further, in a period Th following this period Tg, as will be described later, the connection operation for the connection / disconnection circuit 5 is executed, and the connection / disconnection circuit 5 is shifted to the ON state. As a result, both of the analog switch circuit 3 and the connection / disconnection circuit 5 may be turned on to cause the above-described signal collision at the input / output terminal 11 of the analog switch circuit 3. In order to avoid this, a disable operation for the buffer 2 is executed during this period Tg.

  As shown in FIG. 3, in a period Th following the period Tg, a switch-off operation is performed on the analog switch circuit 3 to shift the analog switch circuit 3 to an off state. Therefore, before the analog switch circuit 3 is shifted to the OFF state, a connection operation to the connection / disconnection circuit 5 is executed, and the reference voltage Vr output from the voltage generation circuit 4 is used as the input / output terminal 12 of the analog switch circuit 3. Apply to. Specifically, as in the period Tc, the connection operation of outputting the control voltage Vcnt of the predetermined voltage to the connection / disconnection circuit 5 is performed while maintaining the reference voltage Vr at zero volt. The circuit 5 is turned on. As a result, in the period Th, the input / output terminal 12 and the voltage output terminal 4a are connected via the ON / OFF connection circuit 5, and the connection / disconnection circuit 5 is connected to the input / output terminal 12 of the analog switch circuit 3. The reference voltage Vr (zero volt) is applied from the voltage generation circuit 4 via Thus, when the analog switch circuit 3 shifts from the on state to the off state, the voltage (output signal Sout) of the input / output terminal 12 is regulated to the reference voltage Vr (zero volts).

  Therefore, in the analog switch circuit 3, as in the above-described period Tc, in the analog switch circuit 3, when the control signal S2 falls from the H level to the L level (that is, when the inverted signal S3 rises and when the control signal S4 falls) Each gate terminal and a pair of input / output terminals via the gate-source capacitance and the gate-drain capacitance inherent in each of the MOS transistors Q1, Q2, Q3, Q4, Q5, Q6. Although the movement of charge occurs between 11 and 12, the fluctuation of the voltage generated in the output signal Sout due to the movement of the charge is greatly reduced. Further, in the period Tg preceding this period Th, since the buffer 2 has already shifted to the disable state, the analog switch generated when both the analog switch circuit 3 and the connection / disconnection circuit 5 shift to the ON state. The above signal collision at the input / output terminal 11 of the circuit 3 is avoided. Note that, during this period Th, after the control signal S2 falls from the H level to the L level, the analog switch circuit 3 shifts to the off state, so that the above-described signal collision does not occur. For this reason, the disable operation for the buffer 2 is stopped.

  As shown in FIG. 3, in the period Ti following the period Th, the switch-off operation for the analog switch circuit 3 is continued and the disconnection operation for the connection / disconnection circuit 5 is also continued. However, in the cutting operation during this period Ti, the control voltage Vcnt of zero volts is output to the connection / disconnection circuit 5 and the voltage data Dv for defining the reference voltage Vr to zero volts is output to the voltage generation circuit 4. Run. As a result, the output signal Sout is maintained in a high impedance state (the output signal Sout is indefinite).

  Finally, as shown in FIG. 3, in the period Tj following the period Ti, the switch-off operation for the analog switch circuit 3 is continued and the disconnection operation for the connection / disconnection circuit 5 is also continued. However, in the cutting operation in this period Tj, the control voltage Vcnt of the low potential voltage Vss is output to the connection circuit 5 and the voltage data Dv for defining the reference voltage Vr to the low potential voltage Vss is the voltage generation circuit. It is executed by outputting to 4. As a result, the output signal Sout continues to be in a high impedance state (the output signal Sout continues to be indefinite).

  As described above, in the switch device 1, the analog switch circuit 3, the voltage generation circuit 4 that generates the reference voltage Vr with the voltage specified by the voltage data Dv and outputs the reference voltage Vr from the voltage output terminal 4 a, and the analog switch circuit 3 A connection circuit 5 is provided between the other input / output terminal 12 and the voltage output terminal 4a, and turns on / off the output (application) of the reference voltage Vr to the other input / output terminal 12. .

  Therefore, according to the switch device 1, when the switch-on operation is performed on the analog switch circuit 3 (when the control signal S2 is raised from the L level to the H level) or when the switch-off operation is performed (the control signal S2 is switched from the H level). When the analog switch circuit 3 is shifted from one of the on state and the off state to the other state (when the analog switch circuit 3 is shifted from the on state to the off state) Gates inherent in each of the MOS transistors Q1, Q2, Q3, Q4, Q5, and Q6 constituting the analog switch circuit 3 both at the time of being turned on and at the time of transition from the off state to the on state) Each gate terminal and a pair of input / output terminals 11 via the source-to-source capacitance and the gate-to-drain capacitance Even if a charge transfer occurs between the input and output terminals 2, the reference voltage Vr (zero volts) is applied to the input / output terminal 12 from the voltage generation circuit 4, and the output signal Sout is defined by the reference voltage Vr. Thus, the fluctuation of the voltage generated in the output signal Sout due to the movement of the charge can be greatly reduced.

  Further, according to the switch device 1, since the signal Sin input from the outside through the buffer 2 having the enable terminal is output to the input / output terminal 11 of the analog switch circuit 3 as the transmission signal S1, the switch on In a state where the bidirectional analog switch circuit 3 is shifted to the ON state by performing the operation, the connection operation is performed to supply the reference voltage Vr from the voltage generation circuit 4 to the other input / output terminal 12 of the analog switch circuit 3. Even when the signal is output to the reference voltage, by executing a disable operation for the buffer 2 (an operation for outputting the L level enable signal Sen to the enable terminal), the reference voltage is supplied via the analog switch circuit 3 in the ON state. Occurrence of a situation where Vr and transmission signal S1 collide can be avoided.

  In the above switch device 1, as shown in FIG. 3, when the connection / disconnection circuit 5 is shifted from the off state to the on state, or vice versa, the control voltage Vcnt is zero volts. And a period Tb, Td, Tg, Ti for outputting the zero volt reference voltage Vr from the voltage generation circuit 4 is employed, but these periods Tb, Td, Tg, Ti are not interposed. Configuration, for example, when the disconnection circuit 5 is shifted from the OFF state of the period Ta to the ON state of the period Tc, the state of the period Tb is omitted, and the low potential voltage Vss is output as the control voltage Vcnt, and the voltage generation circuit The potential difference between the reference voltage Vr and the reference voltage Vr as the control voltage Vcnt from the state where the reference voltage Vr of the low potential voltage Vss is output from 4 (state of the period Ta) is MO. It is also possible to output the predetermined voltage equal to or higher than the threshold voltage of the transistor 5a, and adopts a configuration to directly transition from the voltage generating circuit 4 in the state in which to output a zero volt reference voltage Vr (state period Tc).

  Further, in the external device that supplies the signal Sin to the switch device 1, when the output terminal of the external device is configured to be able to shift to a high impedance state in the output stop state of the signal Sin, the buffer 2 of the switch device 1. It is also possible to adopt a configuration that eliminates the above.

DESCRIPTION OF SYMBOLS 1 Switch apparatus 2 Buffer 3 Analog switch circuit 4 Voltage generation circuit 5 Connection circuit 11,12 Input / output terminal 13 Control terminal 14 High potential power supply terminal 15 Low potential power supply terminal 16 Main switch 19 Control circuit Q1 p channel MOS transistor Q2 n channel MOS transistor S1 Transmission signal S2, S4 Control signal S3 Inverted signal Vdd High potential voltage Vr Reference voltage Vss Low potential voltage

Claims (2)

A pair of input / output terminals, a control terminal to which a control signal is input, a high potential power supply terminal, a low potential power supply terminal, a main switch composed of a p-channel MOS transistor and an n-channel MOS transistor, and a control circuit, The main switch and the control circuit are operated by a high potential voltage input to a potential power supply terminal and a low potential voltage input to the low potential power supply terminal, and the control circuit generates an inverted signal of the control signal. The control signal and the inverted signal are output to the main switch, and the MOS transistors of the main switch simultaneously shift to either the on state or the off state based on the control signal and the inverted signal. Input to one of the pair of input / output terminals An analog switch circuit for turning on and off the output from the other output terminal of transmission signals,
A voltage generation circuit that generates a reference voltage with a set voltage and outputs the reference voltage from the voltage output terminal;
A connection circuit disposed between the other input / output terminal of the analog switch circuit and the voltage output terminal, and for turning on and off the output of the reference voltage to the other input / output terminal;
The analog switch circuit is shifted from one of an on state and an off state to the other when the connection circuit in the on state outputs the reference voltage to the other input / output terminal. Switch device.   It has an enable terminal, and it shifts to one of the state of outputting the signal input to the input terminal from the output terminal to the analog switch circuit as the transmission signal and the state of setting the output terminal to high impedance. 2. The switch device according to claim 1, further comprising a possible buffer.

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