JP2014093600A - Forced uninterruptible changeover system of communication node device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a forced uninterruptible changeover system of a communication node device capable of forced uninterruptible changeover with a simple circuit even if skew between lanes when transmitting a backboard in parallel expansion and a differential delay in a 0/1 system are large.SOLUTION: An input IF, a switch board and an output IF are provided, and a signal is transferred from an MLD upon signal transmission to the switch board from the input IF. The output IF consists of frame synchronization units 201 and 202 that perform frame synchronization of each lane from the MLD in relation to an input signal, and lane number recognition units 211 and 212 that recognize each lane number from MFAS in relation to a signal after frame synchronization, and based on the MFAS and a frame synchronization phase of each lane of the MLD, adjusts skew of all signals from the switch board, as well as switches selector 231 at the time of forced changeover, while including the selector 231 and an MLD synchronizer 221 that make a selection and restore rotation of the MLD of the two systems.

Description

  The present invention relates to a forced uninterruptible switching system for a communication node device including a plurality of input interface boards, a duplex switch board, and a plurality of output interface boards.

In general, a communication node device used for optical communication includes an interface board and a switch board.
As this type of communication node device, SDH (Synchronous Digital Hierarchy) -XC (Cross Connect) or ATM (Asynchronous Transfer Mode) -XC is known.

In addition, a plurality of interface boards of communication node devices are mounted on one communication node device in order to accommodate a plurality of interfaces. However, even if an interface board fails, the interface board is affected. Only.
However, when a switch board that transmits and receives signals to and from all interface boards fails, all the interface boards are affected.

In view of this, the switch substrate which is a common part is generally duplicated for the purpose of improving reliability.
By duplicating in this way, the main signal transmission can be continued by switching to the normal switch board in the event of a failure.

In the duplex switch board, the actually used one is called “active system”, and the unused one is called “standby system”.
Also, depending on the mounting position of the board, it is also referred to as “0 system” or “1 system”. When “0 system” is the active system, “1 system” is the standby system, and conversely, “1 system” is the active system. Sometimes “system 0” becomes a standby system.

  Since the time at which the failure occurs is unknown, the main signal is “OFF” from the moment of the failure, and the “OFF” state of the main signal continues until the switch board is switched, but thereafter the main signal is restored. At this time, if the switch board is not duplicated, the “off” state of the main signal continues until the switch board is replaced (the current board is removed and a new board is inserted).

Therefore, the switch board is duplicated in preparation for a failure. However, when the switch board is duplicated, the following can be performed even if it is not related to the failure.
For example, if you want to replace the switch board with a new one (with parts replacement, firmware update, etc.) in order to increase the functionality or price of the switch board, insert the new switch board in the spare system. The new switch board can be used by switching the new switch board to the working system in accordance with an instruction from the operator.

Furthermore, after switching the switch board, the old switch board that has become a standby system is removed, and a new switch board is inserted in the same manner, so that the versions of the two switch boards can be matched.
In this way, switching a substrate by an operator's instruction when no failure has occurred is referred to as forced switching (or manual switching). On the other hand, switching when a failure occurs is referred to as failure switching (or automatic switching).

  In the communication node device, when switching the switch unit by forcible switching, unlike the case of failure switching, it is desirable to switch the main signal without interruption (a state in which the signal is not “off”). Various forced uninterruptible switching systems for devices have been conventionally proposed (see, for example, Patent Document 1).

FIG. 8 is a block diagram schematically showing a communication node device described in Patent Document 1, and shows a configuration in which switch boards 531 and 532 are duplicated (system 0, system 1).
FIG. 9 is a block diagram showing the uninterruptible switching circuit 542 in FIG. 8, and shows a configuration when the transmission path is duplicated.

In the conventional communication node device 501 shown in FIG. 8, the input side interface boards (input IFs) 511 and 512 include a two-branch driver 541, and two (0 system and 1 system) switch boards 531 and 532. The same signal is input to.
On the other hand, the output side interface boards (output IFs) 521 and 522 receive signals via the two switch boards 531 and 532, and switch the uninterruptible switching circuit 542 at the forcible switching timing. Switching is realized.

  At this time, if the transmission rate of the communication signal is low, the wiring delay of the back board (BWB) between the 0 system and the 1 system is relatively small, and the delay difference between the 0 system and the 1 system is reduced. Since it can be ignored, it can be forcibly switched by a simple uninterruptible switching circuit 542.

  In addition, as another similar technique, an uninterruptible switching system by duplicating the transmission path instead of duplicating the switch unit has been proposed, but when the transmission path is duplexed, The delay difference is generally larger than when the switch board is duplicated, and a large buffer (FIFO) is required for absorbing the delay difference.

  In the conventional uninterruptible switching circuit 542 shown in FIG. 9, the transmission line receiving side device finds the frame head by the phase difference absorption units (FIFOs) 601 and 602 independently for each of the 0-system and the 1-system, and performs synchronous control. The unit 603 combines the signals between the 0-system and the 1-system in units of frames, and outputs them from the phase difference absorption FIFOs 601 and 602, and then switching by the selector 604, thereby realizing forced uninterruptible switching.

The prior art described in Patent Document 1 (FIGS. 8 and 9) discloses a non-instantaneous switching circuit in the apparatus that realizes a combination of a duplex switch unit and a duplex transmission path.
In this case, since the transmission rate is low, it is easy to find the head of the frame, so it is also easy to match the two phases of the 0 system / 1 system.

  On the other hand, when the transmission speed is increased (40 Gbps or 100 Gbps), multi-lane distribution (MLD) is known as a system that performs parallel transmission of OTU (Optical Transport Channel Unit) frame signals and transfers them. (For example, see Non-Patent Document 1).

In MLD, high-speed (40 Gbps, 100 Gbps) OTU frames are transferred in parallel (multiple lanes) and transferred even if a delay difference (skew) occurs between the lanes due to wiring delays, etc. A mechanism to match is included.
FIG. 10 shows ITU-T_G. It is explanatory drawing which shows the signal transfer system of MLD by 709 standard.

As shown in FIG. 10, in a signal transfer system using MLD, frame synchronization and lane identification are performed by the leading area (FAS: Frame Alignment Signal) of an OTU frame and periodic rotation between lanes. Done.
In the case of the MLD shown in FIG. 10, the skew up to 385 μsec is matched for the speed standard OTU3 (40 Gbps), and the skew up to 139 μsec is matched for the speed standard OTU4 (100 Gbps).

JP-A-8-256159

ITU-T G. 709 (Annex D)

  The conventional communication node device forced uninterruptible switching system has a BWB (backboard) wiring delay difference that is very small compared to the transmission rate in the forced switching in the communication node device having a double switch unit. Although it can be realized with a simple selector configuration, if the transmission rate increases and the wiring delay difference of the backboard cannot be ignored compared to the transmission rate, it cannot be realized using a simple selector. There was a problem.

  In addition, the transmission line uninterruptible switching system in the case where the delay time is large has also been presented conventionally, but after the signal of the delay time difference due to the transmission line length difference between the two systems is used as a buffer, the frame phase is adjusted. Only the switching technique is disclosed, and the case where the delay difference (skew) of the signals developed in parallel becomes a problem is not disclosed.

  In addition, an MLD system is defined as a technique for transferring high-speed signals by developing them in parallel. This is a technique for adjusting the skew between lanes when transferring and transferring OTU frames in parallel. However, there is a problem that the system for synchronizing the main signals of the two standby systems is not defined.

  The present invention has been made in order to solve the above-described problems. In a communication node device in which a switch unit is duplicated, the transmission rate is high and the backboard needs to be transmitted in parallel development. Yes, even if the delay difference between the wiring via the backboard cannot be ignored compared to the transmission rate and the delay difference between the 0 system and 1 system cannot be ignored along with the skew between lanes, it is enforced with a simple circuit. An object of the present invention is to obtain a forced uninterruptible switching system for a communication node device that can realize uninterruptible switching.

  A communication node device forced uninterruptible switching system according to the present invention includes a plurality of input interface boards, two switch boards connected to each of the plurality of input interface boards, and each of the two switch boards. A communication node device forced uninterruptible switching system including a plurality of output interface boards, wherein each of the plurality of input interface boards transmits an ITU- TG. A signal is transferred by MLD defined in 709, and each of the two switch boards inputs a signal received from a plurality of input interface boards to each of the plurality of output interface boards, and Each is a frame synchronization unit that performs frame synchronization of each lane of the MLD with respect to signals input from two switch boards, and each of the signals after frame synchronization is performed with MFAS (Multi-Frame Alignment Signal). Based on the lane number recognition unit that recognizes the lane number, and the frame synchronization phase and MFAS of each lane of the MLD, all the skews of the signals from the two switch boards are matched and based on the rotation of the MLD of the two systems Including two MLD synchronizers and selectors to select back. By switching the selector when a forced switching signal is input to the switch board, switching without instantaneous interruption of signals input from the two switch boards is realized.

  According to the present invention, the conventionally known MLD lane synchronization function is expanded to include synchronization including the delay time difference between the 0-system / 1 system, and based on the MLD circuit. Forcible uninterruptible switching can be realized only by adding a simple MLD synchronization unit and selector.

It is a block diagram which shows the forced uninterruptible switching system of the communication node apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the function structure of the MLD switching circuit in FIG. It is explanatory drawing which shows the functional structure of the MLD synchronizing part in FIG. 2 with a block. It is explanatory drawing which shows the switching timing by Embodiment 2 of this invention. It is a block diagram which shows the forced uninterruptible switching system of the communication node apparatus which concerns on Embodiment 3 of this invention. It is a block diagram which shows the function structure of the MLD switching circuit by Embodiment 4 of this invention. It is a block diagram which shows the forced uninterruptible switching system of the communication node apparatus concerning Embodiment 5 of this invention. It is a block diagram which shows roughly the conventional uninterruptible switching system of the communication node apparatus. It is a block diagram which shows the function structure of the conventional uninterruptible switching circuit. It is explanatory drawing which shows the signal transfer system by general MLD.

Embodiment 1 FIG.
1 is a block diagram showing a forced uninterruptible switching system for a communication node device according to Embodiment 1 of the present invention.
1, the communication node device 101 includes a plurality of input interface boards (input IFs) 111, 112,..., A plurality of output interface boards (output IFs) 121, 122,. And two switch boards 131 and 132 (duplicated to 0 system / 1 system) interposed between the interface boards.

Each of the plurality of input interface boards 111, 112,... Provides signals to both the MLD conversion circuit 141 that converts an OTU frame (input signal from the outside) into MLD and the two switch boards 131, 132. And a driver 142 for outputting.
Each of the plurality of output interface boards 121, 122,... Includes an MLD switching circuit 143 that receives and switches signals from both systems of the two switch boards 131, 132.

FIG. 2 is a block diagram showing a functional configuration of the MLD switching circuit 143 in FIG.
In FIG. 2, the MLD switching circuit 143 includes frame synchronization units 201 and 202 to which MLD signals from each of the two switch boards 131 and 132 are individually input, and signals via the frame synchronization units 201 and 202. The lane number recognizing units 211 and 212 that are individually input, the MLD synchronizing unit 221 that is input with the signals via the lane number recognizing units 211 and 212, and the N-bit 2-system signal via the MLD synchronizing unit 221 And a selector 231 that selects and outputs one of them.

First, the frame synchronization units 201 and 202 receive the MLD signals of each system from the two switch boards 131 and 132, and perform frame synchronization for each lane independently by FAS.
Next, the lane number identification units 211 and 212 receive the signals synchronized by the frame synchronization units 201 and 202, and lane identification divided by MLD by the MFAS included in the FAS (identification process defined by MLD). ) Is performed independently for each system.

  The above operations by the frame synchronization units 201 and 202 and the lane number identification units 211 and 212 are performed independently for each of the 0 system / 1 system. The frame synchronization unit 201 and the lane number identification unit 211 are connected to the 0 system switch board 131. Correspondingly, the frame synchronization unit 202 and the lane number identification unit 212 correspond to the 1-system switch board 132.

Next, the MLD synchronization unit 221 performs a 0-system / 1-system skew adjustment (skew adjustment) process and a rotation return process based on frame synchronization and MFAS.
That is, based on the information obtained by the frame synchronization units 201 and 202 and the lane number identification units 211 and 212, the MLD synchronization unit 221 performs the skew adjustment and rotation adjustment of each lane of each system, as well as the mutual 0 system / 1 system. Delay time adjustment (phase synchronization) is performed.

  At this time, as in the case of the MLD described above (FIG. 10), the delay time difference up to 385 μsec can be adjusted in OTU3, and the delay time difference up to 139 μsec can be adjusted in OTU4. The backboard transfer delay time difference can be within the above range.

Thereafter, two systems of N-bit signals that are skew-adjusted, rotationally-adjusted, and phase-synchronized are input to a selector 231 disposed in the subsequent stage.
At this time, since the signal phase of the 0 system / 1 system is aligned at the time when it is input to the selector 231, even if switching is performed immediately after the forced switching instruction from the operator is input, the main signal is “ Since there is no “disconnection”, switching without interruption is possible.

  FIG. 3 is an explanatory diagram showing the functional configuration of the MLD synchronization unit 221 in FIG. 2 as a block, and schematically shows a specific example of skew adjustment (skew alignment) processing and rotation adjustment (rotation alignment) processing.

  In FIG. 3, first, the MLD synchronization unit 221 receives 20 lanes (lanes 0 to 19) of an OTN (Optical Transport Network) frame from the 0-system switch board 131 via the frame synchronization unit 201 and the lane number recognition unit 211. ).

  Similarly, the MLD synchronization unit 221 receives the OTN frame from the 1-system switch board 132 in 20 lanes (lanes 0 to 19) via the frame synchronization unit 202 and the lane number recognition unit 212.

At this time, the skew between the lanes may be different due to the difference in transfer delay of the backboard, the individual difference of the elements, and the like, and the frame phase in the 0 system / 1 system may be different.
3 shows a frame phase shift φ between the 0-system OTN frame numbers # 1 and # 2 and the 1-system OTN frame numbers #m and #n.

  The MLD synchronization unit 221 writes the received signal via the lane number recognition units 211 and 212 to the individual buffers 261 and 262 for each of the 0 system and the 1 system, and then based on the FAS and MFAS signals, the skew, rotation, and Then, all the 0 / system 1 frame phases are adjusted (combined) and read from the buffers 261 and 262.

  As a result, as shown in FIG. 3, OTN frames # 1 and # in which the skew, rotation, and 0/1 frame phases are all adjusted, and before the selector 231 located at the subsequent stage of the MLD synchronization unit 221. Thus, since the frame timing of the 0 system / 1 system is aligned, it can be switched by a simple selector 231.

  In the above description, in the MLD switching circuit 143 in the output interface boards 121, 122,... That receive signals from the switch boards 131, 132, the MLD synchronization unit 221 in front of the selector 231 uses the two systems. Although the rotation of the MLD has been restored, the signal input to the switch boards 131 and 132 from the input interface boards 111, 112,... The circuit may be configured to return.

  As described above, the forced uninterruptible switching system of the communication node device 101 according to the first embodiment (FIGS. 1 to 3) of the present invention includes a plurality of input interface boards 111, 112,. Two switch boards 131, 132 connected to each of the input interface boards 111, 112, ..., and a plurality of output interface boards 121, 122, ... connected to each of the two switch boards 131, 132,・ ・.

Each of the plurality of input interface boards 111, 112,... Transmits a signal to the two switch boards 131, 132 when the ITU-T G.D. A signal is transferred by the MLD defined in 709.
Each of the two switch boards 131, 132 inputs a signal received from the plurality of input interface boards 111, 112,... To each of the plurality of output interface boards 121, 122,.

  Each of the plurality of output interface boards 121, 122,... Has a frame synchronization unit 201 that performs frame synchronization of each lane of the MLD with respect to signals input from the two switch boards 131, 132, and frame synchronization. Based on the lane number recognition unit 211 that recognizes each lane number by the MFAS and the frame synchronization phase and MFAS of each lane of the MLD, the skews of the signals from the two switch boards are matched with the subsequent signal. An MLD synchronization unit 221 and a selector 231 that select and restore the rotation of the MLDs of the two systems, and by switching the selector 132 when a forced switching signal is input to the two switch boards 131 and 132 The switching between the signals input from the two switch boards 131 and 132 is realized without instantaneous interruption.

  As described above, the MLD lane synchronization function that has been conventionally known is expanded to include synchronization including the delay time difference between the 0 and 1 systems, thereby simplifying the MLD circuit as a base. Only by adding the MLD synchronization unit 221 and the selector 231, forced uninterruptible switching can be realized.

  Therefore, the transmission rate is high, the backboard needs to be transmitted in parallel development, the wiring delay difference through the backboard cannot be ignored compared to the transmission rate, and the 0 system / Even if the delay difference between the 1 systems cannot be ignored, the forced uninterruptible switching can be realized with a simple circuit.

  Embodiment 2. FIG.

  In the first embodiment, the selector 231 in the MLD switching circuit 143 is immediately switched when a forced switching instruction is input to the switch boards 131 and 132. However, as shown in FIG. The selector 231 may be switched after waiting until a correction (FEC: Forward Error Correction) area passes.

  FIG. 4 is an explanatory diagram showing the switching timing according to the second embodiment of the present invention. The waiting time from the generation timing of the forced switching request to the switch boards 131 and 132 to the switching timing of the selector 231 (the FEC area passing timing). Is shown.

  For example, when the selector 231 is composed of N bits as in the first embodiment (FIG. 2), the selector 231 is actually divided into a plurality of selector units (not shown). . At this time, the wiring length of the switching signal to each selector unit is not necessarily the same, and may be different from each other in a plurality of selector units.

  In the first embodiment described above, the selector 231 is immediately switched by the switching signal when the forced switching instruction is input. However, the setup of the flip-flop arranged at the subsequent stage of the selector 231 due to the wiring length difference of the switching signal. There is a possibility that a signal error of 1 CLK may occur at the time of switching because the time and the hold time are insufficient, resulting in a metastable (malfunction) state.

  In order to prevent the malfunction, if the MLD switching circuit 143 attempts to set each switching signal to a plurality of selector units to the equal length wiring, restrictions on the internal wiring of the LSI or FPGA or the pattern wiring on the substrate As a result, circuit configuration conditions become severe.

Therefore, instead of immediately switching the selector 231 when a forced switching instruction is input to the switch boards 131 and 132, as shown in FIG. 4, after waiting until the error correction area FEC of the OTU frame of the main signal passes. It is desirable to switch the selector 231.
Since the FEC area is not used in the communication node device 101, even if an error occurs in the FEC area when the selector 231 is switched, the main signal is not affected.

  As described above, according to the second embodiment (FIG. 4) of the present invention, each of the plurality of output interface boards 121, 122,... Is input with a forced switching signal to the two switch boards 131, 132. Sometimes, the selector 231 is switched after waiting until the transfer timing of the FEC area of the OTU frame, so that the wiring length condition of the switching signal to the selector 231 is relaxed, and the circuit can be easily configured.

Embodiment 3 FIG.
In the second embodiment (FIG. 4), the selector 231 is switched after waiting for the FEC area when the switching signal is input. However, as in the first embodiment, the selector 231 (FIG. 2) is input when the switching signal is input. Even if a signal error occurs at this time, as shown in FIG. 5, in the output interface boards 121A, 122A,..., The framers 161, 162,. In addition, an FEC and an FEC check function may be inserted to make it possible to correct an error.

  FIG. 5 is a block diagram showing a forced uninterruptible switching system of the communication node device 101A according to the third embodiment of the present invention. Components similar to those described above (see FIG. 1) are denoted by the same reference numerals as described above. Or, “A” is added after the reference numerals, and the detailed description is omitted.

In FIG. 5, in-device FECs are inserted into the framers 151, 152,... In the input interface boards 111A, 112A,.
Further, the transmission FEC and the in-device FEC check function are inserted in the framers 161, 162,... In the output interface boards 121A, 122A,.

  In the above-described second embodiment, the FEC area is not used in the communication node device 101. However, in the third embodiment of the present invention, as shown in FIG. In the arranged interface boards, FECs are inserted into the framers 151, 152, ..., 161 in the input interface boards 111A, 112A, ..., and the framers 161 in the output interface boards 121A, 122A, ... 162, FEC and FEC check function are inserted.

  Thus, even if a signal error occurs when the selector 231 is immediately switched when a switching signal is input, the error is detected when an error is detected in the FEC check function in the subsequent stage in the output interface boards 121A, 122A,. Can do.

  As described above, according to the third embodiment (FIG. 5) of the present invention, each of the plurality of input interface boards 111A, 112A,... Has a framer (FEC area) during signal transfer in the communication node device 101A. , 151, 152,... Are inserted into the device, and each of the plurality of output interface boards 121A, 122A,. Since the FEC check and correction are performed using the signal after switching, the wiring length condition of the switching signal to the selector 231 is relaxed, and the circuit can be easily configured.

Embodiment 4 FIG.
In the first embodiment (FIGS. 1 to 3) described above, the single selector 231 is used in the MLD switching circuit 143. However, as shown in FIG. 6, a selector 231B composed of a plurality of selector units 241 to 244 is used. May be used.

  FIG. 6 is a block diagram showing an MLD switching circuit 143B used in the forced uninterruptible switching system for a communication node device according to the fourth embodiment of the present invention. As in the second and third embodiments, the MLD switching is performed. The example of a structure which implement | achieved wiring relaxation in a circuit is shown.

In FIG. 6, the same components as those described above (see FIG. 2) are denoted by the same reference numerals as those described above, or “B” after the reference numerals, and detailed description thereof is omitted.
Moreover, the overall configuration of a forced uninterruptible switching system (not shown) for a communication node device according to Embodiment 4 of the present invention is as shown in FIG.

In this case, the MLD switching circuit 143B includes a selector 231B including a plurality of selector units 241 to 244, an FEC, in addition to the frame synchronization units 201 and 202, the lane number recognition units 211 and 212, and the MLD synchronization unit 221 similar to those described above. A correction unit 251 (FEC in Embodiment 3).
Here, although the case where it is divided into four selector units 241 to 244 is shown, it goes without saying that it can be divided into an arbitrary number as required.

  In general, in the MLD switching circuit, when the number of parallel expansions (N bits output from the MLD synchronization unit 221) is large (for example, when N = 512), the error in the FEC correction unit 251 remains unchanged when the selector is switched. Errors can occur beyond the correctable burst strength.

Therefore, as shown in FIG. 6, the selector 231B is divided into selector units 241 to 244 for each number of parallel expansions (M bits) within the burst tolerance range of the FEC correction unit 251, and the forced switching signal from the operator is At the time of input, the selector units 241 to 244 that are divided are sequentially switched in units of FEC frame time.
In this case, since the maximum number of errors at the time of switching is M bits, the FEC correction unit 251 can perform correction.

  As described above, according to the fourth embodiment (FIG. 6) of the present invention, each of the plurality of input interface boards 111, 112,... A monitoring FEC is inserted, and each of the plurality of output interface boards 121, 122,... Divides a selector 231B so that the number of bits M or less that can be corrected by the FEC correction unit 251 is equal to or less. The selector units 241 to 244 are configured so that when the forced switching signal is input to the two switch boards 131 and 132, the selector units 241 to 244 are sequentially switched at a time interval equal to or greater than the FEC frame interval. Even if the number of bit expansions N is large, even if an error occurs when the selector 231B is switched, the error can be corrected by the FEC correction unit 251. It is possible to increase the degree of freedom in selecting the opening number and FEC scheme.

Embodiment 5 FIG.
In Embodiments 1 to 4 (FIGS. 1 to 6), only switching within the communication node device is shown. However, as shown in FIG. Switching circuits 341 and 342 may be provided in the switch boards 131C and 132C.

  FIG. 7 is a block diagram showing forced uninterruptible switching of the communication node device 101C according to Embodiment 5 of the present invention to which transmission path switching is applied. The same as the above (see FIG. 1) is described above. The same reference numerals are attached, or “C” is attached after the reference numerals, and the detailed description is omitted.

  7, the communication node device 101C corresponding to the transmission path switching includes input interface boards 111a, 111b,... In which the transmission paths are duplicated, and a 0-system switch board 131C on which the switching circuit 341 is mounted. , 1 system switch board 132C on which switching circuit 342 is mounted, and output interface boards 121C, 122C,.

The input interface board 111a is connected to the 0-system transmission line of the duplexed transmission lines, and the input interface board 111b is connected to the 1-system transmission line.
The switch boards 131C and 132C are duplicated in the communication node device 101C, and switching circuits 341 and 342 for switching transmission lines are mounted.

  By using the circuit configuration of FIG. 7, when the transmission lines are duplicated, the delay time difference caused by the distance difference between the 0 system / 1 system transmission lines is matched and the transmission lines are forcibly switched without interruption. Is possible.

The functional configurations and circuit operations of the switching circuits 341 and 342 are the same as those of the MLD switching circuit 143 described above (FIG. 2), and the switching circuits 341 and 342 include the input interface boards 111a, 111b,. The input signal is transferred to and from 131C in the form of an MLD signal.
However, in the first embodiment (FIG. 2), only the delay difference in the backboard is matched, but in the fifth embodiment of the present invention, it is based on the distance difference between the duplexed transmission lines. The difference from the above is that the delay of the 0 system / 1 system is matched including the delay difference.

  As described above, the forced uninterruptible switching system for the communication node device 101C according to the fifth embodiment (FIG. 7) of the present invention includes a plurality of input interface boards 111a, 111b,. 111a, 111b,..., Two switch boards 131C, 132C connected to each of the two switch boards 131C, 132C, and a plurality of output interface boards 121C, 122C,. It is equipped with.

The plurality of input interface boards 111a, 111b,... Are each composed of a pair of input interface boards that individually take in signals from the duplexed transmission lines.
Each of the two switch boards 131C and 132C has switching circuits 341 and 342 for switching signals from each pair of input interface boards, and receives signals received from the plurality of input interface boards 111a, 111b,. When transmitting signals to a plurality of output interface boards, ITU-T G. A signal is transferred by the MLD defined in 709.

  The switching circuits 341 and 342 include frame synchronization units 201 and 202 (see FIG. 2) that perform frame synchronization of each lane of the MLD with respect to signals input from the plurality of input interface boards 111a, 111b,. A plurality of input interface boards 111a, 111b,... Based on the lane number recognition units 211 and 212 for recognizing each lane number by MFAS, and the frame synchronization phase and MFAS of each lane of the MLD, with respect to the signal after frame synchronization. A MLD synchronization unit 221 and a selector 231 that match all the skews of the signals from the two and return the MLD rotation of the two systems to the original and select them, and provide a forced switching signal for the two switch boards. At the time of input, the signal from the duplex transmission line is switched and the selector 231 is switched. It allows to implement the instantaneous switching of a plurality of input from the input interface board signals.

  Thus, as described above, in the case of OTU3 (40 Gbps), a delay time difference of up to 385 μsec, in the case of OTU4 (100 Gbps), a delay time difference of up to 139 μsec, even if a distance difference occurs in the duplex transmission line, With a simple circuit, the phase can be adjusted in units of bits, and the transmission line can be switched without forced interruption.

  In FIG. 7, the switching circuits 341 and 342 are mounted on the switch boards 131C and 132C in the communication node device 101C corresponding to the transmission path switching, but a dedicated board (not shown) for the switching circuits 341 and 342 is provided. May be arranged between the input interface boards 111a, 111b,... And the switch boards 131C, 132C.

In addition, switching circuits 341 and 342 may be installed on the output interface boards 121C, 122C,.
In either case, only the mounting positions of the switching circuits 341 and 342 are different, and the forced uninterruptible switching can be similarly realized.

  101, 101A, 101C Communication node device, 111, 111A, 111a, 111b Input interface board (input IF), 121, 121A, 121C Output interface board (output IF), 131, 132, 131C, 132C Switch board, 132 selector, 141 MLD conversion circuit, 142 driver, 143, 143B MLD switching circuit, 151, 152, 161, 162 framer, 201, 202 Frame synchronization unit, 211, 212 Lane number recognition unit, 221 MLD synchronization unit, 231, 231B selector, 241 ˜244 Selector unit, 251 FEC correction unit, 261, 262 buffer, 341, 342 switching circuit.

Claims (5)

Multiple input interface boards;
Two switch boards connected to each of the plurality of input interface boards;
A plurality of output interface boards connected to each of the two switch boards;
A communication node device forced uninterruptible switching system comprising:
When each of the plurality of input interface boards transmits a signal to the two switch boards, the ITU-T G. The signal is transferred by MLD defined in 709,
Each of the two switch boards inputs a signal received from the plurality of input interface boards to each of the plurality of output interface boards,
Each of the plurality of output interface boards is
A frame synchronization unit that performs frame synchronization of each lane of the MLD with respect to signals input from the two switch boards;
A lane number recognition unit that recognizes each lane number by MFAS for a signal after frame synchronization;
Based on the frame synchronization phase of each lane of the MLD and the MFAS, all the skews of the signals from the two switch boards are matched, and the MLD synchronization unit for selecting and returning the rotation of the MLDs of the two systems And a selector,
A forced uninterruptible switching system for a communication node device that realizes uninterrupted switching of signals input from the two switch boards by switching the selector when a forced switching signal is input to the two switch boards. Each of the plurality of output interface boards is
2. The forced uninterruptible switching system for a communication node device according to claim 1, wherein when the forcible switching signal is input to the two switch boards, the selector is switched after waiting for the timing to transfer the FEC area of the OTU frame. Each of the plurality of input interface boards inserts an FEC for in-device monitoring into the FEC area at the time of signal transfer in the communication node device,
2. Each of the plurality of output interface boards performs switching of the selector immediately when a forced switching signal is input to the two switch boards, and performs FEC check and correction using the signal after switching. A forced uninterruptible switching system for the described communication node device. Each of the plurality of input interface boards inserts an FEC for in-device monitoring into the FEC area at the time of signal transfer in the communication node device,
Each of the plurality of output interface boards is configured by a plurality of selector units by dividing the selector so that the burst error can be corrected to be less than or equal to the number of bits that can be corrected by FEC, and a forced switching signal input to the two switch boards 2. The forced uninterruptible switching system for a communication node device according to claim 1, wherein switching is performed in order at a time interval equal to or greater than an FEC frame interval in order for each selector. Multiple input interface boards;
Two switch boards connected to each of the plurality of input interface boards;
A plurality of output interface boards connected to each of the two switch boards;
A communication node device forced uninterruptible switching system comprising:
The plurality of input interface boards are each composed of a pair of input interface boards that individually take in signals from the duplexed transmission lines,
Each of the two switch boards has a switching circuit for switching signals from the pair of input interface boards, and transmits signals received from the plurality of input interface boards to the plurality of output interface boards. ITU-T G. The signal is transferred by MLD defined in 709,
The switching circuit is
A frame synchronization unit that performs frame synchronization of each lane of the MLD with respect to signals input from the plurality of input interface boards;
A lane number recognition unit that recognizes each lane number by MFAS for a signal after frame synchronization;
Based on the frame synchronization phase of each lane of the MLD and the MFAS, all the skews of the signals from the plurality of input interface boards are matched, and the MLD synchronization unit that selects and restores the rotation of the MLDs of the two systems And a selector,
When a forced switching signal is input to the two switch boards, a signal from a duplicated transmission path is switched, and the selectors are switched so that signals input from the plurality of input interface boards are not instantaneously interrupted. A forced uninterruptible switching system for communication node devices that realizes switching.

Images