JP2014090203A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which electrical connection among semiconductor circuit elements which are three-dimensionally integrated can be achieved not by wired connection but by a simple composition.SOLUTION: A semiconductor integrated circuit device 100 comprises: a first semiconductor integrated circuit element 1 which includes a pair of strip-shaped differential transmission lines 12A, 12B which are arranged in the same plane and in parallel with each other, and each has a predetermined length, and includes a differential signal transmission element 11 for outputting differential signals to the first differential transmission lines 12A, 12B; and a second semiconductor integrated circuit element 2 which includes a pair of second differential transmission lines 22A, 22B arranged opposite to the first differential transmission lines 12A, 12B in an overlapping manner and a differential signal reception element 21 connected to one ends of the second differential transmission lines 22A, 22B. The second semiconductor integrated circuit element 2 is stacked on the first semiconductor integrated circuit element 1 via a dielectric substance 4. When signals flow in the first differential transmission lines 12A, 12B, the signals are transmitted to the second differential transmission lines 22A, 22B primarily by capacitive coupling.

Description

  The present invention relates to a semiconductor integrated circuit device.

  In recent years, semiconductor integrated circuits have been miniaturized, but due to the demand for higher performance, attempts have been made to implement a system by mounting a plurality of functional blocks in one package.

  As a representative example, a system called SoC (System on Chip) that integrates a plurality of functional blocks into one bare chip to form a system, and a system called SiP (System in Package) that encloses a plurality of bare chips in one package There is.

  SoC has a problem that it is difficult to realize an element by a different process on one bare chip, and the cost is increased due to a decrease in yield due to an increase in element area.

  In addition, SiP has the merit that functions realized by different processes can be easily aggregated, but it is necessary to interconnect a plurality of bare chips. Therefore, even if the yield of individual bare chips is good, the total yield is poor. There is a problem. Therefore, the connection between bare chips is a major factor in the reliability of SiP.

  One method for connecting the bare chips is a wire bonding method. However, in this wire bonding method, the number of connection pads is less than that of a single chip package using wire bonding, and the communication bandwidth cannot be increased.

  In addition, as another connection method, there is a method of connecting by micro bumps, but there is a great limitation in mounting, such as a need to make a chip stacked on top small. This method using micro bumps can secure a larger number of connection pads than the wire bonding method, but is less reliable when connecting a large number of bumps side by side. Further, in order to mount a large number of elements, it is necessary to provide an electrode or the like penetrating the chip itself or the build-up substrate, and high processing accuracy by an advanced process technique is required.

  In order to solve the problem of the connection method between the bare chips described above, a plurality of chips are mounted in one package, and the signal transmission between the plurality of chips is not directly connected to each other, but the chips are mounted face to face. A method of performing communication by capacitive coupling between bumps by stacking (1) is known (for example, see Non-Patent Document 1).

  In addition, a plurality of LSI chips each having a transmission coil and a reception coil formed by wiring are stacked so that the centers of the openings of a pair of transmission and reception coils coincide with each other to form an inductive coupling to enable communication. Has been proposed (see, for example, Patent Documents 1 and 2).

Stephen Mick, Lei Luo, John Wilson and Paul Franzon “Buried Bump and AC Coupled Interconnection Technology” IEEE TRANSACTIONS ON ADVANCED PACKAGING VOL.27, NO.1 (2004)

JP 2005-228981 A JP 2005-203657 A

  An object of the present invention is to provide a semiconductor integrated circuit device that enables wireless connection while suppressing electrical interference between semiconductor circuit elements.

  In order to achieve the above object, one embodiment of the present invention provides the following semiconductor integrated circuit device.

[1] A first semiconductor integrated circuit element including a differential signal transmitting element and a pair of first differential transmission lines that transmit signals from the differential signal transmitting element and are disposed on the same plane; ,
The pair of first differential transmission lines so as to form a coupled line system by capacitive coupling and inductive coupling with the pair of first differential transmission lines (except for inter-line coupling of microstrip lines). A pair of second differential transmission lines disposed opposite to each other in parallel with a predetermined distance on the lines, and a differential signal receiving element connected to the end of the pair of second differential transmission lines A second semiconductor integrated circuit element stacked on the first semiconductor integrated circuit element,
The first and second differential transmission lines have a time when a signal passes through the first and second differential transmission lines as td and a rise time of a reception signal in the differential signal receiving element as tr. The semiconductor integrated circuit device is characterized in that the length of the parallel portion is set to td ≧ tr by the opposing arrangement.

[2] The semiconductor according to [1], wherein the first and second differential transmission lines are arranged in the vicinity of a stacked surface of the first and second semiconductor integrated circuit elements. Integrated circuit device.
[3] The first and second differential transmission lines are terminated or a connection end of the differential signal receiving element is terminated with a resistor having a value equal to the characteristic impedance of the first and second differential transmission lines. The semiconductor integrated circuit device according to [1], wherein the semiconductor integrated circuit device is provided.
[4] The first and second differential transmission lines are wider and have a sufficient length as compared to the case where they are arranged close to each other, and are arranged at positions where the distance between them is farthest. The semiconductor integrated circuit device according to [1], wherein the semiconductor integrated circuit device is provided.
[5] Each of the first and second differential transmission lines has a line width of 50 μm or less and an interval between the two lines arranged in parallel is 50 μm or less. The semiconductor integrated circuit device according to the above [1], wherein the length of the portion that is uniformly parallel to the portion is 500 μm or less.
[6] The pair of second differential transmission lines includes a plurality of differential signal transmitting elements connected to one end and a differential signal receiving element connected to the other end. The semiconductor integrated circuit device according to [1].
[7] In the first semiconductor integrated circuit element, the differential signal transmitting element is connected to one end of the pair of first differential transmission lines, and a differential signal receiving element is connected to the other end.
In the second semiconductor integrated circuit element, the differential signal receiving element is connected to one end of the pair of second differential transmission lines, and a differential signal transmitting element is connected to the other end. The semiconductor integrated circuit device according to [1].
[8] In the first and second semiconductor integrated circuit elements, a differential signal transmitting element and a differential signal receiving element are connected in parallel to one end of the pair of first and second differential transmission lines. The semiconductor integrated circuit device according to [1], wherein a terminal resistor is connected to an end.
[9] The first and second semiconductor integrated circuit elements each have a metal wiring layer to which the pair of first and second differential transmission lines are wired, and the metal wiring layers are arranged to face each other. The semiconductor integrated circuit device according to [1], wherein the semiconductor integrated circuit device is provided.
[10] The first semiconductor integrated circuit element includes a pair of first differential transmission lines for supplying power configured similarly to the pair of first differential transmission lines, and a pair of supplying power. Oscillation means for applying a high-frequency current to one end of the first differential transmission line,
The second semiconductor integrated circuit element includes a pair of second differential transmission lines for supplying power configured similarly to the pair of second differential transmission lines, and a second difference for supplying power. The semiconductor integrated circuit device according to [1], further comprising: a rectifier circuit connected to a terminal end of the dynamic transmission line.
[11] The differential signal receiving element is connected to a data demodulation circuit that demodulates the differential signal by inverting the logic at the rising and falling timings of the differential signal input to the differential input terminal. The semiconductor integrated circuit device according to [1], wherein the semiconductor integrated circuit device is provided.

According to the semiconductor integrated circuit device of the first aspect, it is possible to perform wireless connection while suppressing electrical interference between the semiconductor circuit elements. In addition, a signal required by the signal receiving semiconductor element can be reliably transmitted from the first semiconductor integrated circuit element to the second semiconductor integrated circuit element.
According to the semiconductor integrated circuit device of the second aspect, the capacitive coupling between the first differential transmission line and the second differential transmission line can be easily configured.
According to the semiconductor integrated circuit device of the third aspect, the characteristic impedance of the transmission line can be maintained at a desired value.
According to the semiconductor integrated circuit device of the fourth aspect, the first differential transmission line and the second differential transmission line can be electrically coupled without being placed in close proximity to each other.
According to the semiconductor integrated circuit device of the fifth aspect, data can be transmitted in a state having no frequency characteristic.
According to the semiconductor integrated circuit device of the sixth aspect, data can be transmitted from one transmission line to a plurality of transmission lines.
According to the semiconductor integrated circuit device of the seventh aspect, data can be transmitted from either the first semiconductor integrated circuit device or the second semiconductor integrated circuit device to the other semiconductor integrated circuit device.
According to the semiconductor integrated circuit device of the eighth aspect, a semiconductor integrated circuit element having a configuration in which a signal transmitting semiconductor element and a signal receiving semiconductor element are adjacent to each other can be formed, and a semiconductor element is not connected to the other end. It can also be.
According to the semiconductor integrated circuit device of the ninth aspect, the first and second differential transmission lines can be formed in different layers from the semiconductor integrated circuit element, and the first differential transmission line and the second differential transmission line. Can be easily brought close together.
According to the semiconductor integrated circuit device of the tenth aspect, the signal receiving semiconductor element can be operated without providing a power source to the semiconductor integrated circuit element on which the signal receiving semiconductor element is mounted.
According to the semiconductor integrated circuit device of the eleventh aspect, binary logic data can be accurately demodulated.

1 is a perspective view showing a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a circuit diagram of the data demodulation circuit connected to a differential signal receiving element. FIG. 3 is a block diagram illustrating a specific circuit configuration of the data demodulation circuit of FIG. 2. It is a wave form diagram which shows operation | movement of a differential signal receiving element. It is sectional drawing which shows the semiconductor integrated circuit device based on the 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor integrated circuit device based on the 3rd Embodiment of this invention. It is sectional drawing which shows the semiconductor integrated circuit device based on the 4th Embodiment of this invention. FIG. 10 is a connection diagram illustrating a semiconductor integrated circuit device according to a fifth embodiment of the present invention. FIG. 10 is a connection diagram showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. FIG. 10 is a connection diagram illustrating a semiconductor integrated circuit device according to a seventh embodiment of the present invention. It is a connection diagram which shows the semiconductor integrated circuit device based on the 8th Embodiment of this invention. It is a connection diagram which shows the semiconductor integrated circuit device based on the 9th Embodiment of this invention. (A), (b) is a transmission characteristic figure concerning the example of the present invention.

[First Embodiment]
FIG. 1 is a perspective view showing a semiconductor integrated circuit device according to the first embodiment of the present invention. In the figure, in order to make it easy to understand the arrangement of each member arranged inside, each member arranged inside is shown by a solid line.

(Configuration of semiconductor integrated circuit device)
The semiconductor integrated circuit device 100 includes a first semiconductor integrated circuit element 1 having a differential signal transmitting element 11 for transmitting data and a differential signal receiving element 21 for receiving data, and is made of thin silicon or the like. And a second semiconductor integrated circuit element 2 stacked on the first semiconductor integrated circuit element 1 with a dielectric 4 formed therebetween. A space may be provided without providing the dielectric 4 between the first and second semiconductor integrated circuit elements 1 and 2.

  The first semiconductor integrated circuit element 1 is connected to the differential output terminal of the differential signal transmission element 11 so as to face the dielectric 4 and is arranged in parallel with a pair of first differential transmission lines having a predetermined length. 12A and 12B, and a termination resistor 13 connected between the terminations of the first differential transmission lines 12A and 12B.

  The termination resistor 13 is a resistor having a value equal to the characteristic impedance of the first differential transmission lines 12A and 12B. As a result, the differential transmission lines 12A and 12B of the first semiconductor integrated circuit element 1 are matched and terminated on the same principle as the dummy load of the pseudo antenna, the electromagnetic field is closed in the near field, and no radiated electromagnetic field is generated. Can be configured.

  The second semiconductor integrated circuit element 2 has the same length as the first differential transmission lines 12A and 12B, and faces the dielectric 4 in a state of overlapping in parallel with the first differential transmission lines 12A and 12B. And a pair of second differential transmission lines 22A and 22B in which the differential input terminal of the differential signal receiving element 21 is connected to the terminal side of the first differential transmission lines 12A and 12B, and the difference A termination resistor 23 connected between the differential input terminals of the dynamic signal receiving element 21 is provided.

  The termination resistor 23 is a resistor having a value equal to the characteristic impedance of the second differential transmission lines 22A and 22B. As a result, the differential transmission lines 22A and 22B of the second semiconductor integrated circuit element 2 are matched and terminated on the same principle as the dummy load of the pseudo antenna, the electromagnetic field is closed in the near field, and no radiated electromagnetic field is generated. Can be configured.

(Configuration of data demodulation circuit)
FIG. 2 is a block diagram of a data demodulating circuit connected to the differential signal receiving element. The data demodulating circuit 30 includes first and second threshold detectors 31 and 32 connected to the output terminal of the differential signal receiving element 21 and both output terminals of the first and second threshold detectors 31 and 32. And a logic inversion means 33 connected to the.

(Specific configuration of data demodulation circuit)
FIG. 3 is a circuit diagram showing a specific circuit configuration of the data demodulation circuit shown in FIG. The data demodulating circuit 30 includes comparators 34 and 35 as first and second threshold detection means 31 and 32, and an RS (reset set) flip-flop (RS-FF) circuit 36 as a logic inversion means 33. And is configured.

  The comparators 34 and 35 are configured using differential operational amplifiers. A threshold value VTH1 is input to a negative input terminal of the comparator 34 from a threshold setting circuit (not shown), and the threshold value setting circuit is supplied to a positive input terminal of the comparator 35. The threshold value VTH2 is input. The output signal of the comparator 34 is input to the S input terminal of the RS flip-flop circuit 36, and the output signal of the comparator 35 is input to the R input terminal of the RS flip-flop circuit 36.

  The data demodulating circuit 30 is not limited to the circuit configuration described above. For example, the data demodulating circuit 30 may be configured to demodulate the original trapezoidal wave using an integrating circuit that restores the differential characteristics of the coupling portion.

(Operation of semiconductor integrated circuit device and data demodulation circuit)
FIG. 4 is a waveform diagram showing the operation of the differential signal receiving element. The operation of the semiconductor integrated circuit device and the data demodulation circuit in the first embodiment will be described with reference to FIGS.

  When a differential data signal is output from the differential signal transmission element 11, the differential data signal is output to the first differential transmission lines 12A and 12B, proceeds toward the terminal end, and becomes a matching load. The resistor 13 is reached.

  At the same time, the capacitance of the differential data signal is mainly present between the second differential transmission lines 22A and 22B by the dielectric 4 in the process of transmitting the first differential transmission lines 12A and 12B. Is transmitted to the second differential transmission lines 22A and 22B, is input to the differential signal receiving element 21 via the second differential transmission lines 22A and 22B, and is terminated by the termination resistor 23.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21 and then input to the first and second threshold detection means 31 and 32. Further, threshold values VTH1 and VTH2 are input to the first and second threshold detection means 31 and 32, respectively.

  In the configuration of FIG. 3, a differential data signal is input to the + input terminal of the comparator 31 and the − input terminal of the comparator 32, and threshold values VTH <b> 1 and VTH <b> 2 are input to the − input terminal of the comparator 31 and the + input terminal of the comparator 32. .

  The signal received by the differential signal receiving element 21 has a shape obtained by differentiating the trapezoidal wave of the signal from the transmission side from the characteristics of the differential transmission lines 12A, 12B, 22A, and 22B connecting the semiconductor integrated circuit elements 1 and 2. become.

  Therefore, it is detected by the first threshold detection means 31 that the change point from the logic L to the logic H has exceeded the threshold value VTH1, and the change point from the logic H to the logic L is detected by the second threshold detection means 32. VTH2 is detected and the output of the logic inversion means 33 (RS flip-flop circuit 36) is changed to H at the change point from the logic L to the logic H, and to L at the change point from the logic H to the logic L. By changing to, the original binary logic (transmission signal) is demodulated as shown in FIG.

[Second Embodiment]
FIG. 5 is a sectional view showing a semiconductor integrated circuit device according to the second embodiment of the present invention.

(Configuration of semiconductor integrated circuit device)
In the first embodiment, the first and second semiconductor integrated circuit elements 1 and 2 are each provided with a differential signal transmitting element and a differential signal receiving element in the first embodiment. Other configurations are the same as those of the first embodiment. A space may be provided without providing the dielectric 4 between the first and second semiconductor integrated circuit elements 1 and 2.

  The first semiconductor integrated circuit element 1 is a semiconductor integrated circuit in which a metal wiring layer 15 provided with first differential transmission lines 12A and 12B, a differential signal transmitting element 11 and a differential signal receiving element 14 are provided. Layer 16.

  The second semiconductor integrated circuit element 2 includes a metal wiring layer 25 provided with second differential transmission lines 22A and 22B each having a differential signal receiving element 21 and a terminating resistor 23 connected to one end, and a differential signal receiving. It comprises a semiconductor integrated circuit layer 26 provided with a differential signal transmission element 24 connected to the other end of the second differential transmission lines 22A and 22B together with the element 21. A data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. 2 and 3 is connected to the differential signal transmitting element 24.

  The first differential transmission lines 12A and 12B are connected to the differential signal transmitting element 11 and the differential signal receiving element 14 via connection electrodes 17A to 17D.

  The second differential transmission lines 22A and 22B are connected to the differential signal transmitting element 24 and the differential signal receiving element 21 via connection electrodes 27A to 27D.

(Operation of semiconductor integrated circuit device)
Next, the operation of the semiconductor integrated circuit device according to the second embodiment will be described.

(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmission element 11, the differential data signal is output to the first differential transmission lines 12A and 12B via the connection electrodes 17A and 17B, and toward the terminal. Then, the signal is terminated by the termination resistor 13 through the connection electrodes 17C and 17D and input to the differential signal receiving element 14.

  Note that the differential signal receiving element 14 can receive the differential data signal from the differential signal transmitting element 11 or can reject the reception.

  At the same time, the differential data signal from the differential signal transmission element 11 is transmitted between the second differential transmission lines 22A and 22B by the dielectric 4 in the process of transmitting the first differential transmission lines 12A and 12B. Since the capacitance is mainly present, the signal is transmitted to the second differential transmission lines 22A and 22B and input to the differential signal receiving element 21 via the connection electrodes 27C and 27D.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21 and then processed by the data demodulating circuit 30 shown in FIGS. 2 and 3 according to the first embodiment. Is done.

(Transmission from the differential signal transmitting element 24 to the differential signal receiving element 14)
Next, when a differential data signal is output from the differential signal transmission element 24, the differential data signal is output to the second differential transmission lines 22A and 22B via the connection electrodes 27A and 27B. Proceeding toward the termination, the termination resistor 23 is terminated via the connection electrodes 27C and 27D and the differential signal receiving element 21 is input.

  The differential signal receiving element 21 can receive or reject the differential data signal from the differential signal transmitting element 24.

  At the same time, the differential data signal from the differential signal transmission element 24 is transmitted between the first differential transmission lines 12A and 12B by the dielectric 4 in the process of transmitting the second differential transmission lines 22A and 22B. The signal is transmitted to the first differential transmission lines 12A and 12B via the existing capacitance, and input to the differential signal receiving element 14 via the connection electrodes 17C and 17D.

  The differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14 and then the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

[Third Embodiment]
FIG. 6 is a sectional view showing a semiconductor integrated circuit device according to the third embodiment of the present invention.

(Configuration of semiconductor integrated circuit device)
In the present embodiment, in the second embodiment, the third semiconductor integrated circuit element 3 is laminated on the second semiconductor integrated circuit element 2 via the dielectric 5, and the first and second semiconductor integrated circuits are stacked. The layer structure and the element arrangement of the circuit elements 1 and 2 are changed, and further, a differential signal transmitting element, a differential transmission line and a differential signal receiving element are added to the second semiconductor integrated circuit element 2, and others The configuration is the same as that of the second embodiment. A space may be provided without providing the dielectric 4 between the first and first two semiconductor integrated circuit elements 1, 2. It is good also as space without providing the dielectric material 5 in between.

  That is, the first semiconductor integrated circuit element 1 includes a back wiring layer 101 disposed on the dielectric 4 side, and a semiconductor integrated circuit layer 102 and a metal wiring layer 103 sequentially provided on the back wiring layer 101. It has a laminated structure.

  The back wiring layer 101 includes first differential transmission lines 12A and 12B.

  The semiconductor integrated circuit layer 102 includes a through electrode 41A, 41B, 41C, 41D having one end connected to the first differential transmission line 12A, 12B, and a differential signal transmission connected to the other end of the through electrode 41A, 41B. An element 11, a differential signal receiving element 14 connected to the other end of the through electrodes 41 </ b> C and 41 </ b> D, and a termination resistor 13 connected between the differential input terminals of the differential signal receiving element 14 are provided.

  The metal wiring layer 103 is provided with connection electrodes 17A, 17B, 17C, and 17D connected to the through electrodes 41A to 41D.

  The second semiconductor integrated circuit element 2 includes a back wiring layer 201 disposed on the dielectric 5 side, a semiconductor integrated circuit layer 202 and a metal wiring layer 203 sequentially provided on the back wiring layer 201. It has a laminated structure.

  The back wiring layer 201 includes third differential transmission lines 42 </ b> A and 42 </ b> B provided facing the dielectric 5.

  The semiconductor integrated circuit layer 202 includes a differential signal receiving element 21, differential signal transmitting elements 24 and 43, a differential signal receiving element 44, through electrodes 45A, 45B, 45C and 45D, and a differential signal transmitting element 21. , 43 are provided with termination resistors 23 and 46 connected between the differential input terminals.

  The metal wiring layer 203 is connected to the second differential transmission lines 22A and 22B opposite to the first differential transmission lines 12A and 12B, and to both ends of the second differential transmission lines 22A and 22B. Electrodes 27A, 27B, 27C, and 27D, and connection electrodes 47A, 47B, 47C, and 47D connected to the differential signal transmitting element 43 and the differential signal receiving element 44.

  The third semiconductor integrated circuit element 3 includes a back wiring layer 301 disposed on the dielectric 5 side and a semiconductor integrated circuit layer 302 stacked on the back wiring layer 301.

  The back wiring layer 301 is connected to the fourth differential transmission lines 49A, 49B facing the third differential transmission lines 42A, 42B and to both ends of the fourth differential transmission lines 49A, 49B. Connection electrodes 50A, 50B, 50C, and 50D.

  The semiconductor integrated circuit layer 302 includes a differential signal transmission element 51 connected to the connection electrodes 50A and 50B, a differential signal reception element 52 connected to the connection electrodes 50C and 50D, and a differential signal reception element 52. And a terminating resistor 53 connected between the differential input terminals.

(Operation of semiconductor integrated circuit device)
Next, the operation of the semiconductor integrated circuit device in the third embodiment will be described.

(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmitting element 11 of the first semiconductor integrated circuit element 1, the differential data signal is transmitted through the connection electrodes 17A and 17B and the through electrodes 41A and 41B to the first. After being output to the differential transmission lines 12A and 12B and proceeding toward the termination, the differential transmission lines 12A and 12B are terminated by the termination resistor 13 through the through electrodes 41C and 41D and the connection electrodes 17C and 17D, and the differential signal receiving element 14 Is input.

  Note that the differential signal receiving element 14 can receive the differential data signal from the differential signal transmitting element 11 or can reject the reception.

  At the same time, the differential data signal from the differential signal transmission element 11 is transmitted between the second differential transmission lines 22A and 22B by the dielectric 4 in the process of transmitting the first differential transmission lines 12A and 12B. The signal is transmitted to the second differential transmission lines 22A and 22B via the existing capacitance, and input to the differential signal receiving element 21 via the connection electrodes 27C and 27D.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21 and then explained in the first embodiment by the data demodulation circuit 30 shown in FIGS. Processing is performed.

(Transmission from the differential signal transmitting element 24 to the differential signal receiving element 14)
Next, when a differential data signal is output from the differential signal transmission element 24 of the second semiconductor integrated circuit element 2, the differential data signal is transmitted through the connection electrodes 27A and 27B to the second differential signal. After being output to the transmission lines 22A and 22B and proceeding toward the termination, the signal is terminated by the termination resistor 23 via the connection electrodes 27C and 27D and also input to the differential signal receiving element 21.

  Note that the differential signal receiving element 21 can receive the differential data signal from the differential signal transmitting element 24 or can reject the reception.

  At the same time, the differential data signal from the differential signal transmission element 24 is transmitted between the first differential transmission lines 12A and 12B by the dielectric 4 in the process of transmitting the second differential transmission lines 22A and 22B. The signal is transmitted to the first differential transmission lines 12A and 12B mainly through the existing capacitance, and is input to the differential signal receiving element 14 through the through electrodes 41C and 41D and the connection electrodes 17C and 17D.

  After the differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14, the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

(Transmission from the differential signal transmitting element 43 to the differential signal receiving element 52)
Next, when a differential data signal is output from the differential signal transmitting element 43, the differential data signal is transmitted to the third differential transmission line 42A via the connection electrodes 47A and 47B and the through electrodes 45A and 45B. , 42B and proceeding toward the end thereof, and then terminated by the termination resistor 46 through the through electrodes 45C, 45D and the connection electrodes 47C, 47D, and input to the differential signal receiving element 44.

  At the same time, the differential data signal from the differential signal transmission element 43 is transmitted between the fourth differential transmission lines 49A and 49B by the dielectric 5 in the process of transmitting the third differential transmission lines 42A and 42B. The signal is transmitted to the fourth differential transmission lines 49A and 49B through the existing capacitance, and is input to the differential signal receiving element 52 through the connection electrodes 50C and 50D.

  The differential data signal input to the differential signal receiving element 52 is amplified by the differential signal receiving element 52 and then the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

(Transmission from the differential signal transmitting element 51 to the differential signal receiving element 44)
Next, when a differential data signal is output from the differential signal transmitting element 51, the differential data signal is output to the fourth differential transmission lines 49A and 49B via the connection electrodes 50A and 50B. After proceeding toward the termination, the termination resistor 53 is terminated via the connection electrodes 50C and 50D and the differential signal receiving element 52 is input.

  Note that the differential signal receiving element 52 can receive the differential data signal from the differential signal transmitting element 51 or reject the reception.

  At the same time, the differential data signal from the differential signal transmission element 51 is transmitted between the third differential transmission lines 42A and 42B by the dielectric 5 in the process of transmitting the fourth differential transmission lines 49A and 49B. The signal is transmitted to the third differential transmission lines 42A and 42B through the existing capacitance, and is input to the differential signal receiving element 44 through the through electrodes 45C and 45D and the connection electrodes 47C and 47D.

  The differential data signal input to the differential signal receiving element 44 is amplified by the differential signal receiving element 44 and then the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

  As described above, the semiconductor integrated circuit device 100 can perform bidirectional data transmission between layers regardless of the number of semiconductor integrated circuit elements.

[Fourth Embodiment]
FIG. 7 is a sectional view showing a semiconductor integrated circuit device according to the fourth embodiment of the present invention.

(Configuration of semiconductor integrated circuit device)
Similar to the second embodiment, the semiconductor integrated circuit device 100 has a configuration in which the first to third semiconductor integrated circuit elements 1 to 3 are stacked. However, the semiconductor integrated circuit device 100 is not arranged so that the metal wiring layers face each other. The integrated circuit layers and the metal wiring layers are alternately arranged. The metal wiring layers of the first to third semiconductor integrated circuit elements 1 to 3 are both arranged on the upper side. A space may be provided without providing the dielectric 4 between the first and first two semiconductor integrated circuit elements 1, 2. It is good also as space without providing the dielectric material 5 in between.

  That is, the first semiconductor integrated circuit element 1 includes a semiconductor integrated circuit layer 104 including the differential signal transmitting element 11 and the differential signal receiving element 14, a line width larger than that of each of the embodiments, and Metal wiring layer 105 including first differential transmission lines 55A and 55B having an extended length and connection electrodes 56A, 56B, 56C and 56D connected to both ends of the first differential transmission lines 55A and 55B. Are laminated.

  The second semiconductor integrated circuit element 2 has the same shape as the semiconductor integrated circuit layer 204 including the differential signal receiving element 21 and the differential signal transmitting element 24 and the first differential transmission lines 55A and 55B. Two differential transmission lines 57A, 57B and a metal wiring layer 205 having connection electrodes 58A, 58B, 58C, 58D connected to both ends of the second differential transmission lines 57A, 57B are laminated. ing.

  The third semiconductor integrated circuit element 3 has the same shape as the semiconductor integrated circuit layer 303 including the differential signal transmitting element 52 and the differential signal receiving element 51, and the first differential transmission lines 55A and 55B. The third differential transmission line 59A, 59B and the back wiring layer 304 having connection electrodes 60A, 60B, 60C, 60D connected to both ends of the third differential transmission line 59A, 59B are laminated. It is configured.

  In FIG. 7, illustration of the termination resistors connected to the differential signal input terminals of the differential signal receiving elements 14, 21, 52 is omitted.

(Operation of semiconductor integrated circuit device)
Next, the operation of the semiconductor integrated circuit device according to the fourth embodiment will be described.

(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmitting element 11 of the first semiconductor integrated circuit element 1, the differential data signal is transmitted through the connection electrodes 56A and 56B to the first differential transmission line 55A, After being output to 55B and proceeding toward the terminal, it is terminated by a termination resistor via the connection electrodes 56C and 56D and is input to the differential signal receiving element 14.

  Note that the differential signal receiving element 14 can receive the differential data signal from the differential signal transmitting element 11 or can reject the reception.

  At the same time, since there is mainly inductive coupling between the first differential transmission lines 55A and 55B and the second differential transmission lines 57A and 57B, the differential data signal from the differential signal transmission element 11 is present. Is transmitted from the first differential transmission lines 55A and 55B to the second differential transmission lines 57A and 57B, and transmitted to the differential signal receiving element 21 via the connection electrodes 58C and 58D.

  The spread of the electromagnetic field forming the coupling between the first differential transmission lines 55A and 55B and the second differential transmission lines 57A and 57B relates to the operation of individual functional elements inside each semiconductor integrated circuit element. Since it is larger by one digit or more than the spread of the electromagnetic field, the internal operation of the semiconductor integrated circuit elements 1 to 3 is not affected.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21, and then explained in the first embodiment by the data demodulating circuit 30 shown in FIGS. Processing is performed.

(Transmission from the differential signal transmitting element 24 to the differential signal receiving element 14)
Next, when a differential data signal is output from the differential signal transmission element 24 of the second semiconductor integrated circuit element 2, the differential data signal is supplied to the second differential signal via the connection electrodes 58A and 58B. The signals are output to the transmission lines 57A and 57B, travel toward the terminal ends, and are transmitted to the differential signal receiving element 21 through the connection electrodes 58C and 58D.

  Note that the differential signal receiving element 21 can receive the differential data signal from the differential signal transmitting element 24 or can reject the reception.

  At the same time, since there is mainly inductive coupling between the second differential transmission lines 57A and 57B and the first differential transmission lines 55A and 55B, a differential data signal from the differential signal transmission element 24 is present. Are transmitted from the second differential transmission lines 57A and 57B to the first differential transmission lines 55A and 55B, and transmitted to the differential signal receiving element 14 via the connection electrodes 56C and 56D.

  After the differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14, the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

  Communication between the second semiconductor integrated circuit element 2 and the third semiconductor integrated circuit element 3 is performed in the same manner.

  In the fourth embodiment, the number of stacked semiconductor circuit elements is not limited to three, but can be any number.

[Fifth Embodiment]
FIG. 8 is a connection diagram showing a semiconductor integrated circuit device according to the fifth embodiment of the present invention. In FIG. 8, the metal wiring layer, the semiconductor integrated circuit layer, and the dielectric are not shown. Moreover, it is good also as space without providing a dielectric material.

  The semiconductor integrated circuit device 100 of FIG. 8 is obtained by replacing the arrangement of the differential signal receiving element 21 and the differential signal transmitting element 24 in the second embodiment shown in FIG. Below, signal transmission is demonstrated.

(Operation of semiconductor integrated circuit device)
(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmission element 11, this differential data signal is output to the first differential transmission lines 12A and 12B, and proceeds toward the end thereof. The signal is terminated and input to the differential signal receiving element 14.

  Note that the differential signal receiving element 14 can receive the differential data signal from the differential signal transmitting element 11 or can reject the reception.

  At the same time, the differential data signal from the differential signal transmission element 11 is transmitted through the second difference via the electrostatic coupling between the first differential transmission lines 12A and 12B and the second differential transmission lines 22A and 22B. The signals are transmitted to the dynamic transmission lines 22 </ b> A and 22 </ b> B, terminated by the termination resistor 23, and input to the differential signal receiving element 21.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21 and then processed by the data demodulating circuit 30 shown in FIGS. 2 and 3 according to the first embodiment. Is done.

(Transmission from the differential signal transmitting element 24 to the differential signal receiving element 14)
Next, when a differential data signal is output from the differential signal transmitting element 24, the differential data signal is output to the second differential transmission lines 22A and 22B, and proceeds toward the end of the differential data signal. The signal is terminated by the resistor 23 and input to the differential signal receiving element 21.

  The differential signal receiving element 21 can receive or reject the differential data signal from the differential signal transmitting element 24.

  At the same time, the differential data signal from the differential signal transmission element 24 is transmitted to the first differential transmission lines 12A and 12B that are electrostatically coupled to the second differential transmission lines 22A and 22B, and receives the differential signal. Input to the element 14.

  The differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14 and then the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

[Sixth Embodiment]
FIG. 9 is a connection diagram showing a semiconductor integrated circuit device according to the sixth embodiment of the present invention. In FIG. 9, the metal wiring layer, the semiconductor integrated circuit layer, and the dielectric are not shown. Moreover, it is good also as space without providing a dielectric material.

  The semiconductor integrated circuit device 100 of FIG. 9 has the configuration of the fifth embodiment shown in FIG. 8 between one end of each of the first differential transmission lines 12A and 12B and the second differential transmission lines 22A and 22B. Terminating resistors 18 and 28 are connected, the differential signal transmitting element 11 and the differential signal receiving element 14 are connected in parallel to the other ends of the first differential transmission lines 12A and 12B, and the second differential transmission line 22A. , 22B, the differential signal transmitting element 24 and the differential signal receiving element 21 are connected in parallel. Below, signal transmission is demonstrated.

(Operation of semiconductor integrated circuit device)
(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmitting element 11, the differential data signal is applied to the terminating resistor 13 and the differential signal receiving element 14, and to the first differential transmission lines 12A and 12B. After being output and proceeding toward its end, it is terminated with a termination resistor 18.

  The differential signal receiving element 14 can receive or reject the differential data signal from the differential signal transmitting element 11.

  At the same time, the differential data signal from the differential signal transmission element 11 is transmitted to the second differential transmission lines 22A and 22B mainly electrostatically coupled to the first differential transmission lines 12A and 12B, and directed toward both ends. And proceed. The second differential transmission lines 22 </ b> A and 22 </ b> B are terminated by the termination resistor 28 at the right end and terminated by the termination resistor 23 at the left end and input to the differential signal receiving element 21.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21 and then processed by the data demodulating circuit 30 shown in FIGS. 2 and 3 according to the first embodiment. Is done.

(Transmission from the differential signal transmitting element 24 to the differential signal receiving element 14)
Next, the differential data signal output from the differential signal transmitting element 24 is applied to the terminating resistor 23 and the differential signal receiving element 21 and also terminated via the second differential transmission lines 22A and 22B. Terminated at 28.

  The differential signal receiving element 21 can receive or reject the differential data signal from the differential signal transmitting element 24.

  At the same time, the differential data signal from the differential signal transmission element 24 travels toward both ends of the first differential transmission lines 12A and 12B mainly electrostatically coupled to the second differential transmission lines 22A and 22B. . The first differential transmission lines 12 </ b> A and 12 </ b> B are terminated by the termination resistor 18 at the right end and further terminated by the termination resistor 13 at the left end and input to the differential signal receiving element 14.

  The differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14 and then the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

[Seventh Embodiment]
FIG. 10 is a connection diagram showing a semiconductor integrated circuit device according to the seventh embodiment of the present invention. In FIG. 10, the metal wiring layer, the semiconductor integrated circuit layer, and the dielectric are not shown. Moreover, it is good also as space without providing a dielectric material.

  The semiconductor integrated circuit device 100 of FIG. 10 is obtained by replacing the differential signal transmitting element 11, the terminating resistor 13, the differential signal receiving element 14, and the terminating resistor 18 in the configuration of the sixth embodiment shown in FIG. It is. Below, signal transmission is demonstrated.

(Operation of semiconductor integrated circuit device)
(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmitting element 11, the differential data signal is applied to the termination resistor 13 and the differential signal receiving element 14, and also to the first differential transmission lines 12A and 12B. After being output and proceeding toward its end, it is terminated with a termination resistor 18.

  The differential signal receiving element 14 can receive or reject the differential data signal from the differential signal transmitting element 11.

  At the same time, the differential data signal from the differential signal transmission element 11 is transmitted to the second differential transmission lines 22A and 22B mainly electrostatically coupled to the first differential transmission lines 12A and 12B, and directed toward both ends. And proceed. The second differential transmission lines 22 </ b> A and 22 </ b> B are terminated by a termination resistor 28 at the right end and further terminated by a termination resistor 23 at the left end and input to the differential signal receiving element 21.

  The differential data signal input to the differential signal receiving element 21 is amplified by the differential signal receiving element 21 and then processed by the data demodulating circuit 30 shown in FIGS. 2 and 3 according to the first embodiment. Is done.

(Transmission from the differential signal transmitting element 24 to the differential signal receiving element 14)
Next, when a differential data signal is output from the differential signal transmitting element 24, the differential data signal is applied to the terminating resistor 23 and the differential signal receiving element 21, and the second differential transmission line. It is terminated with a termination resistor 28 via 22A and 22B.

  The differential signal receiving element 21 can receive or reject the differential data signal from the differential signal transmitting element 24.

  At the same time, the differential data signal from the differential signal transmission element 24 travels toward both ends of the first differential transmission lines 12A and 12B mainly electrostatically coupled to the second differential transmission lines 22A and 22B. . The first differential transmission lines 12 </ b> A and 12 </ b> B are terminated at the left end by the termination resistor 18, and further terminated at the right end by the termination resistor 13 and input to the differential signal receiving element 14.

  The differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14 and then the first data demodulating circuit similar to the data demodulating circuit 30 shown in FIGS. The processing described in the embodiment is performed.

[Eighth Embodiment]
FIG. 11 is a connection diagram showing a semiconductor integrated circuit device according to the eighth embodiment of the present invention. In the present embodiment, the first differential transmission lines 12A and 12B are made longer than those in the above embodiments, and the second semiconductor integrated circuit element 2 shown in the second embodiment in FIG. The fifth to seventh differential transmission lines 80A, 80B, 81A, 81B, 82A, 82B made up of three sets of the respective members are arranged at predetermined intervals so as to face the first differential transmission lines 12A, 12B. It is.

  The differential signal transmitting element 91A and the differential signal receiving element 92A are connected to both ends of the fifth differential transmission lines 80A and 80B, and the differential signal transmitting element is connected to both ends of the sixth differential transmission lines 81A and 81B. 91B and the differential signal receiving element 92B are connected, and the differential signal transmitting element 91C and the differential signal receiving element 92C are connected to both ends of the seventh differential transmission lines 82B and 82B. Further, termination resistors 90A to 90C are connected to the differential input terminals of the differential signal receiving elements 92A to 92C, respectively.

  In FIG. 11, the differential signal transmission elements 91A to 91C are arranged on the left side and the differential signal reception elements 92A to 92C are arranged on the right side. The differential signal receiving elements 92A to 92C may be replaced.

(Operation of semiconductor integrated circuit device)
Next, the operation of the semiconductor integrated circuit device 100 will be described.

(Transmission from the differential signal transmitting element 11 to the differential signal receiving element 21)
When a differential data signal is output from the differential signal transmission element 11 to the first differential transmission lines 12A and 12B, the differential data signal travels toward the end and is terminated by the termination resistor 13. And input to the differential signal receiving element 14.

  The differential signal receiving element 14 can receive or reject the differential data signal from the differential signal transmitting element 11.

  At the same time, the differential data signal from the differential signal transmission element 11 is transmitted through the fifth to seventh differential transmission lines 80A, 80B, 81A, 81B mainly electrostatically coupled to the first differential transmission lines 12A, 12B. , 82A, 82B, and proceeds toward both ends of each differential transmission line.

  The fifth differential transmission lines 80A and 80B are terminated by a termination resistor 90A and input to the differential signal receiving element 92A. Similarly, the sixth differential transmission lines 81A and 81B are terminated by a termination resistor 90B and input to the differential signal receiving element 92B, and the seventh differential transmission lines 82A and 82B are terminated. Are terminated by the terminating resistor 90C and input to the differential signal receiving element 92C.

  Note that the differential signal receiving elements 92A to 92C do not necessarily receive a differential signal, and perform reception when in a receiving operation mode.

  The differential data signal input to the differential signal receiving element 92A is amplified by the differential signal receiving element 92A, and then processed by the data demodulating circuit 30 shown in FIGS. 2 and 3 in the first embodiment. Is done.

  In the differential signal receiving elements 92B and 92C, amplification and demodulation processes are performed in the same manner as the differential signal receiving element 92A.

(Transmission from the differential signal transmitting element 91A to the differential signal receiving element 14)
When a differential data signal is output from the differential signal transmitting element 91A,
It is terminated by the terminating resistor 90A via the fifth differential transmission lines 80A and 90B and applied to the differential signal receiving element 92A.

  The differential signal receiving element 92A can receive or reject the differential data signal from the differential signal transmitting element 91A.

  At the same time, the differential data signal from the differential signal transmission element 91A travels toward the end of the first differential transmission lines 12A and 12B mainly electrostatically coupled to the second differential transmission lines 80A and 80B. . The differential data signal is terminated by the terminating resistor 13 at the left end of the first differential transmission lines 12A and 12B and is input to the differential signal receiving element.

  The differential data signal input to the differential signal receiving element 14 is amplified by the differential signal receiving element 14, and then processed by the data demodulating circuit 30 shown in FIGS. 2 and 3 in the first embodiment. Is done.

  The above is the transmission from the differential signal transmitting element 91A to the differential signal receiving element 14, but the transmission from the differential signal transmitting elements 91B and 91C to the differential signal receiving element 14 is performed in the same manner.

  In each of the above embodiments, the operation power supply of the differential signal receiving elements 14, 24, 44, 52, and 92A to 92C is prepared in the semiconductor integrated circuit element on which the differential signal receiving element is mounted. Power can also be supplied via a differential transmission line. Hereinafter, description will be given with reference to the drawings.

[Ninth Embodiment]
FIG. 12 is a connection diagram showing a semiconductor integrated circuit device according to the ninth embodiment of the present invention. In the present embodiment, a power supply circuit for supplying power from the transmission side to the reception side is added to the first embodiment.

  The power supply circuit 70 includes a pair of first differential transmission lines 12A ′ and 12B ′ for power supply having the same configuration as the first differential transmission lines 12A and 12B, and the first differential transmission line 12A. An oscillation circuit 71 as an oscillating means for applying a high frequency signal (high frequency current) to one end of ', 12B' is provided in the first semiconductor integrated circuit element 1 and has the same configuration as the second differential transmission lines 22A, 22B. And a pair of second differential transmission lines 22A ′ and 22B ′ for power supply, and the first differential transmission line 12A ′ connected to the other ends of the second differential transmission lines 22A ′ and 22B ′. , 12B ′ is provided in the second semiconductor integrated circuit element 2 with a rectifier circuit 72 that rectifies a high-frequency signal induced from the second differential transmission lines 22A ′, 22B ′ to obtain a DC voltage.

  The oscillation circuit 71 includes, for example, a CMOS (Complementary Metal Oxcide Semiconductor) device, a resistor (R), and a capacitor (C) (not shown), and oscillates a signal having a frequency of f = 1 / (2.2CR). The transmission output is applied to one end of the first differential transmission lines 12A ′ and 12B ′. Note that the oscillation circuit 71 can substitute the clock signal of the clock circuit mounted on the first semiconductor integrated circuit element 1.

  The rectifier circuit 72 includes four diodes 721A to 721D made of diodes having the same specifications, and a smoothing capacitor 722 connected between the rectified outputs. The input end of the rectifier circuit 72 is the second differential transmission line 22A. It is connected to the terminal side of ', 22B'.

  The diodes 721A to 721D are bridge-connected so as to form a bridge rectifier circuit, and the connection point between the diodes 721A and 721B and the connection point between the diodes 721A and 721B connected in series with the same polarity is the second differential transmission. The other ends of the lines 22A and 22B are connected.

(Power supply operation)
In FIG. 12, when the oscillation circuit 71 oscillates at a high frequency, the oscillation signal is applied to one end of the first differential transmission lines 12A ′ and 12B ′. Since the second differential transmission lines 22A ′ and 22B ′ are coupled to the first differential transmission lines 12A ′ and 12B ′ by capacitive coupling and inductive coupling, the high-frequency signal from the oscillation circuit 71 is The two differential transmission lines 22A ′ and 22B ′ are transmitted to the rectifier circuit 72.

  The rectifier circuit 72 applies a high-frequency signal from the second differential transmission lines 22 </ b> A ′ and 22 </ b> B ′, that is, a DC voltage obtained by rectifying an alternating current using the diodes 721 </ b> A to 721 </ b> D to the smoothing capacitor 722. The smoothing capacitor 722 smoothes the pulsating wave from the diodes 721A to 721D and removes the ripple. The terminal voltage of the smoothing capacitor 722 is applied to the power supply terminal of the differential signal receiving element 21 of the second semiconductor integrated circuit element 2.

Next, examples of the present invention will be described.
FIG. 13 is a transfer characteristic diagram according to the embodiment of the present invention. The inventors of the present invention configured the semiconductor integrated circuit device 100 shown in the first embodiment with the following parameters and analyzed its characteristics. In FIG. 13, “S21” indicates 20 log (out / in), and 1 mil is 25.4 μm.

  FIG. 13A shows the measurement of transfer characteristics from the differential signal transmitting element 11 to the differential signal receiving element 21 under the following conditions.

  That is, the wirings of the first differential transmission lines 12A and 12B and the second differential transmission lines 22A and 22B have a line width of 50 μm and a metal thickness of 25 μm, and the first and first differential transmission lines. The distance between the two lines 12A, 12B, 22A and 22B is 50 μm, and the currents flowing through the first differential transmission lines 12A and 12B and the second differential transmission lines 22A and 22B are parallel to each other (uniformly When the distance between the first differential transmission lines 12A and 12B and the second differential transmission lines 22A and 22B in the parallel part) is 25 μm, the length of the parallel part is changed from 75 μm to 500 μm. Show.

  As is clear from FIG. 13A, it can be seen that if the length of the coupling portion is 500 μm, a component of 10 GHz or more can be transmitted without substantially having a frequency characteristic.

  In FIG. 13B, the line structure is the same as that in FIG. 11A, the length of the coupling portion (a portion that is uniformly parallel) is 200 μm, and the first differential transmission lines 12A, 12B and the second The transmission characteristics when the distance between the differential transmission lines 22A and 22B is changed are shown.

  As is clear from FIG. 13B, if the distance between the first differential transmission lines 12A and 12B and the second differential transmission lines 22A and 22B is further reduced, the frequency characteristic can be obtained up to a lower frequency. It can be seen that the signal can be transmitted without any loss, and that the same frequency can be transmitted even if the length of the coupling portion is shorter.

  According to the study by the present inventors, leakage signals from the first differential transmission lines 12A and 12B to the second differential transmission lines 22A and 22B are transmitted from the first differential transmission lines 12A and 12B. It was found that when the signal strength is 1/10 or more, a reception signal that can be demodulated by the data demodulation circuit 30 can be applied to the differential signal receiving element 21.

  Specifically, the length of the parallel portion of the first and first differential transmission lines 12A, 12B, 22A, and 22B is l, the time for the signal to pass through the length l is td, It has been found that the best result can be obtained by setting td ≧ tr, where tr is the rise time of the received signal in the signal receiving semiconductor element.

  In addition, the present inventors have confirmed by analysis that the frequency transfer characteristics do not deteriorate even if the structure is uniformly reduced three-dimensionally and further miniaturization is possible.

[Other embodiments]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the combination of the components between the embodiments can be arbitrarily performed.

  For example, in each of the above embodiments, the differential transmission structure is configured by the differential signal transmission element, the differential transmission line, and the differential signal reception element. It may be.

DESCRIPTION OF SYMBOLS 1 1st semiconductor integrated circuit element 2 2nd semiconductor integrated circuit element 3 3rd semiconductor integrated circuit element 4 and 5 Dielectric materials 11 and 21 Differential signal transmission element 14, 24, 44, 52 Differential signal receiving element 12A , 12B, 12A ′, 12B ′, 55A, 55B First differential transmission lines 22A, 22B, 22A ′, 22B ′, 57A, 57B Second differential transmission lines 13, 18, 23, 28, 46, 53 Termination resistors 15 and 25 Metal wiring layers 16 and 26 Semiconductor integrated circuit layers 17A to 17D and 27A to 27D Connection electrodes 30 Data demodulating circuit 31 First threshold detection means 32 Second threshold detection means 33 Logic inversion means 34 and 35 Comparator 36 RS flip-flop circuits 41A to 41D, 45A to 45D Through electrodes 42A, 42B, 59A, 59B Third differential transmission line 43 , 51 Differential signal transmission elements 47A-47D, 50A-50D Connection electrodes 49A, 49B Fourth differential transmission lines 56A-56D, 58A-58D, 60A-60D Connection electrodes 70 Power supply circuit 71 Oscillation circuit 72 Rectification Circuits 80A, 80B, 81A, 81B, 82A, 82B Fifth to seventh differential transmission lines 90A to 90C Termination resistors 91A to 91C Differential signal transmitting elements 92A to 92C Differential signal receiving elements 100 and 102 Semiconductor integrated circuit device 101, 201, 301 Rear wiring layers 103, 105, 203, 205 Metal wiring layers 104, 202, 204 Semiconductor integrated circuit layers 302, 303 Semiconductor integrated circuit layers 721A to 721D Diodes 722 Smoothing capacitors VTH1, VTH2 Thresholds

Claims (11)

A differential signal transmission element and a first semiconductor integrated circuit element that transmits a signal from the differential signal transmission element and includes a pair of first differential transmission lines disposed on the same plane;
The pair of first differential transmission lines so as to form a coupled line system by capacitive coupling and inductive coupling with the pair of first differential transmission lines (except for inter-line coupling of microstrip lines). A pair of second differential transmission lines disposed opposite to each other in parallel with a predetermined distance on the lines, and a differential signal receiving element connected to the end of the pair of second differential transmission lines A second semiconductor integrated circuit element stacked on the first semiconductor integrated circuit element,
The first and second differential transmission lines have a time when a signal passes through the first and second differential transmission lines as td and a rise time of a reception signal in the differential signal receiving element as tr. The semiconductor integrated circuit device is characterized in that the length of the parallel portion is set to td ≧ tr by the opposing arrangement.   2. The semiconductor integrated circuit device according to claim 1, wherein the first and second differential transmission lines are arranged in the vicinity of a stacked surface of the first and second semiconductor integrated circuit elements.   The first and second differential transmission lines are terminated or a connection end of the differential signal receiving element is terminated with a resistor having a value equal to the characteristic impedance of the first and second differential transmission lines. The semiconductor integrated circuit device according to claim 1.   The first and second differential transmission lines are wider and have a sufficient length as compared to the case where they are arranged close to each other, and are arranged at positions where the distance between them is farthest. The semiconductor integrated circuit device according to claim 1.   Each of the first and second differential transmission lines has a line width of 50 μm or less and a distance between the two lines arranged in parallel is 50 μm or less, and is uniform with respect to the other differential transmission line. 2. The semiconductor integrated circuit device according to claim 1, wherein the length of the portion parallel to the semiconductor device is 500 [mu] m or less.   2. The pair of second differential transmission lines includes a plurality of differential signal transmission elements connected to one end and a differential signal reception element connected to the other end of each of the pair of second differential transmission lines. A semiconductor integrated circuit device according to 1. In the first semiconductor integrated circuit element, the differential signal transmitting element is connected to one end of the pair of first differential transmission lines, and a differential signal receiving element is connected to the other end.
In the second semiconductor integrated circuit element, the differential signal receiving element is connected to one end of the pair of second differential transmission lines, and a differential signal transmitting element is connected to the other end. The semiconductor integrated circuit device according to claim 1.   In the first and second semiconductor integrated circuit elements, a differential signal transmitting element and a differential signal receiving element are connected in parallel to one end of the pair of first and second differential transmission lines, and terminated at the other end. The semiconductor integrated circuit device according to claim 1, wherein a resistor is connected.   The first and second semiconductor integrated circuit elements have a metal wiring layer to which the pair of first and second differential transmission lines are wired, and the metal wiring layers are arranged to face each other. The semiconductor integrated circuit device according to claim 1. The first semiconductor integrated circuit element includes a pair of first differential transmission lines for power supply configured similarly to the pair of first differential transmission lines, and a pair of first differential transmission lines. An oscillation means for applying a high-frequency current to one end of the differential transmission line,
The second semiconductor integrated circuit element includes a pair of second differential transmission lines for supplying power configured similarly to the pair of second differential transmission lines, and a second difference for supplying power. The semiconductor integrated circuit device according to claim 1, further comprising: a rectifier circuit connected to a terminal end of the dynamic transmission line. The differential signal receiving element is connected to a data demodulating circuit that demodulates the differential signal by inverting the logic at the rising and falling timings of the differential signal input to the differential input terminal. The semiconductor integrated circuit device according to claim 1.

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