JP2014089499A - Layout designing method of semiconductor integrated circuit, layout design program, and layout design device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress iteration in layout design of a semiconductor integrated circuit to improve a design efficiency.SOLUTION: A layout design device comprises: a wiring resource calculation part 1 calculating a wiring possible wiring resource in a first area of a semiconductor integrated circuit; a cell arrangement part 2 arranging a plurality of cells on the first area on the basis of the size of the cell; a network connection cost calculation part 3 calculating a network connection cost of the plurality of cells arranged on the first area on the basis of connection information of the cells; a virtual extension area provision part 4 providing a virtual extension area for virtually increasing a size to the cells arranged on the first area, when on the first area the wiring resource is insufficient for the network connection cost; and a cell rearrangement part 5 rearranging the plurality of cells including the cell on the first area, on the basis of the size of the cells increased by the provided virtual extension area.

Description

  The present invention relates to a layout design method, a layout design program, and a layout design apparatus for a semiconductor integrated circuit. For example, the present invention is suitable for a layout design method, a layout design program, and a layout design apparatus for a semiconductor integrated circuit in which cells are arranged based on a netlist. It can be used.

  In recent years, large scale integration of a semiconductor integrated circuit (LSI: Large Scale Integration) has progressed, and further high performance such as operation at a high frequency has been demanded. For this reason, the degree of difficulty in designing a semiconductor integrated circuit becomes higher and the design period tends to become longer, so that improvement in design efficiency is strongly desired.

  In LSI design, macro and cell functions and connection relationships are designed in the circuit design process. Thereafter, in the layout design process, placement and routing including macro placement, cell placement and wiring is performed, and further, delay time is calculated and timing analysis is performed. For example, Patent Documents 1 to 3 are known as techniques related to LSI cell arrangement.

  FIG. 17 shows a configuration of a conventional cell placement device described in Patent Document 1. As shown in FIG. 17, the conventional cell arrangement apparatus includes an input unit 901, a partitioning-based arrangement processing unit 902, an extraction unit 903, and a resistive network type arrangement processing unit 904.

  The partitioning-based arrangement processing unit 902 assigns each cell to an area where the semiconductor chip is divided and determines a temporary arrangement of each cell. The extraction unit 903 extracts a region where the number of nets exceeding a certain value is congested, a region of a net having a large signal transmission delay, and the like. Resistive network type arrangement processing means 904 regards each cell as a virtual net from the provisional arrangement, considers the net as a spring, generates a repulsive force, and drives the cell out of that area. Determine cell placement.

  If there is a cell arrangement result in advance, the input means 901 inputs the cell arrangement result, and it is assumed that a virtual net is extended to each cell from the position of each cell in the inputted arrangement result. The arrangement result is improved by the arrangement processing means 904 of the resistive network type.

JP 2002-083004 A Japanese Patent Laid-Open No. 11-312185 JP 2003-282711 A

  The prior art described in Patent Document 1 is a technique aimed at obtaining an arrangement result with little iteration of timing convergence without causing local wiring congestion in LSI development and design. This prior art has a feature of compensating for each of the disadvantages of the partitioning base and the resistive network by combining the partitioning base and the resistive network arrangement method when the LSI cells are arranged. In the initial stage of chip division, which is a drawback of partitioning base, it is difficult to predict the final placement result of the cell, and it is difficult to determine whether the wiring performance improves or worsens when processing is advanced. It compensates for the drawbacks, and also compensates for the disadvantage of the resistive network, since the net is approximated as a spring between two cells, and the wiring length is difficult to estimate.

  The present inventor examined the conventional technique described in Patent Document 1, and found that this conventional technique has a problem that the iteration of timing convergence increases due to the occurrence of a local wiring congestion area.

  The reason is that modern LSIs are equipped with tens of millions of gates of logic, and the logical connection of each cell is complicated. In the case of provisional placement, the cells are placed so that the cell area of each region is uniform. Therefore, in regions where there are many cells with complicated logical connections, local wiring congestion areas and associated wiring detours occur. This is because the possibility of doing so increases.

  Specifically, in an LSI having 20 million gate logic, a wiring congested area occurs about 10% in the entire LSI, and in particular, in recent LSIs, the logical connection of each cell is complicated, so that the local area is localized. As a result, a congested wiring area is generated. Then, if the local wiring congestion area is concentrated in the provisional placement in which all the cells based on the partitioning base method of the prior art are uniformly arranged in the area, the cell moving distance by the resistive network method becomes large, and further, the timing The repeater (buffer) for converging the signal cannot be arranged at a desired position, and the cell cannot be arranged at the desired position when the size of the cell is increased in order to converge the timing. Therefore, the timing cannot be converged and the timing convergence iteration is increased.

  As described above, the prior art has a problem in that it causes iteration in the layout design of the semiconductor integrated circuit, and the design efficiency deteriorates.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a layout design apparatus for a semiconductor integrated circuit includes a wiring resource calculation unit, a cell placement unit, a net connection cost calculation unit, a virtual extension region assignment unit, and a cell rearrangement unit. The wiring resource calculation unit calculates a wiring resource that can be wired to the first region of the semiconductor integrated circuit based on the input netlist. The cell arrangement unit arranges a plurality of cells included in the net list in the first area based on the size of the cell. The net connection cost calculation unit calculates a net connection cost indicating a degree of connection of a plurality of cells arranged in the first area based on connection information of cells included in the net list. When the wiring resource is insufficient with respect to the net connection cost in the first area, the virtual extension area providing unit assigns a virtual extension area that virtually expands the size of the cell arranged in the first area. The cell rearrangement unit rearranges a plurality of cells including the cell in the first area based on the size of the cell to which the added virtual extension area is added.

  According to the embodiment, it is possible to suppress the iteration in the layout design of the semiconductor integrated circuit and improve the design efficiency.

It is a block diagram which shows the main characteristics of the layout design apparatus of the semiconductor integrated circuit which concerns on embodiment. 1 is a configuration diagram showing a system configuration for realizing a layout design apparatus for a semiconductor integrated circuit according to a first embodiment; 1 is a configuration diagram illustrating a hardware configuration of a computer system for realizing a layout design apparatus for a semiconductor integrated circuit according to a first embodiment; 1 is a block diagram illustrating a functional configuration of a semiconductor integrated circuit layout design apparatus according to a first embodiment; 5 is a flowchart showing a layout design method for a semiconductor integrated circuit according to the first embodiment. 6 is an explanatory diagram for explaining a net connection cost calculating operation of the semiconductor integrated circuit layout design method according to the first embodiment; FIG. FIG. 6 is an explanatory diagram for explaining an arrangement region dividing operation of the semiconductor integrated circuit layout design method according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a wiring resource calculation operation of the semiconductor integrated circuit layout design method according to the first embodiment; 6 is an explanatory diagram for explaining a cell group division operation of the semiconductor integrated circuit layout design method according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a halo deletion operation of the layout design method for a semiconductor integrated circuit according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a cell group net connection cost calculating operation of the layout design method for the semiconductor integrated circuit according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a wiring resource determination operation of the layout design method of the semiconductor integrated circuit according to the first embodiment; FIG. 6 is an explanatory diagram for explaining a halo giving operation of the layout design method for a semiconductor integrated circuit according to the first embodiment; FIG. FIG. 6 is an explanatory diagram for explaining an arrangement region dividing operation of the semiconductor integrated circuit layout design method according to the first embodiment; 6 is a block diagram showing a functional configuration of a layout design apparatus for a semiconductor integrated circuit according to a second embodiment. FIG. 6 is a flowchart illustrating a layout design method for a semiconductor integrated circuit according to a second embodiment. It is a block diagram which shows the structure of the conventional cell arrangement | positioning apparatus.

(Outline of the embodiment)
Prior to the description of the embodiment, the outline of the main features of the embodiment will be described with reference to FIG.

  As shown in FIG. 1, a layout design apparatus for a semiconductor integrated circuit according to an embodiment includes a wiring resource calculation unit 1, a cell placement unit 2, a net connection cost calculation unit 3, a virtual extension region assignment unit 4, and a cell rearrangement unit 5 is provided.

  The wiring resource calculation unit 1 calculates a wiring resource that can be wired to the first region of the semiconductor integrated circuit based on the input netlist. The cell placement unit 2 places a plurality of cells included in the netlist in the first region based on the size of the cell. The net connection cost calculation unit 3 calculates a net connection cost indicating the connection degree of a plurality of cells arranged in the first area based on connection information of cells included in the net list. When the wiring resource is insufficient for the net connection cost in the first area, the virtual extension area providing unit 4 assigns a virtual extension area that virtually expands the size of the cell arranged in the first area. . The cell rearrangement unit 5 rearranges a plurality of cells including the cell in the first area based on the size of the cell to which the added virtual extension area is added.

  As described above, in the embodiment, the wiring resources in the placement area (first area) of the semiconductor integrated circuit and the net connection cost of the cell placed in the placement area are calculated, and the wiring resources are insufficient for the net connection cost. If so, the cells are rearranged based on the size of the cell to which the virtual extension area is assigned.

  By using the net connection cost of the cell and the wiring resource, it is possible to determine the possibility of wiring congestion in the process before wiring. In layout design, cells with virtual extension areas are rearranged in response to a shortage of wiring resources, so wiring areas can be secured in areas where wiring congestion occurs, and wiring congestion is caused by wiring after cell placement. Can be prevented. For this reason, it is possible to suppress the iteration due to the congestion of wiring and improve the design efficiency.

(Embodiment 1)
The first embodiment will be described below with reference to the drawings. FIG. 2 shows a system configuration for realizing a layout design apparatus for a semiconductor integrated circuit according to the present embodiment, and FIG. 3 shows a hardware configuration of a computer device included in the system.

  As shown in FIG. 2, the semiconductor integrated circuit layout design system according to the present embodiment includes a computer device 10 and a server 20. The computer apparatus 10 and the server 20 are connected via a network 30, and the server 20 includes a recording medium 21.

  The recording medium 21 stores a layout design program for executing the layout design method for the semiconductor integrated circuit according to the present embodiment. The server 20 is connected to a computer apparatus 10 such as an engineering workstation via a network 30 such as the Internet. The layout design program stored in the recording medium 21 is downloaded to the computer apparatus 10 via the network 30. The downloaded layout design program is stored in a local hard disk or a memory of the computer device 10 and is executed.

  The computer device 10 is an information processing device such as a workstation or a personal computer. As shown in FIG. 3, the computer device 10 includes a CPU 12, a main memory 13, a hard disk 14, and the like, a display unit 15 that displays a screen in accordance with an instruction from the main unit 11, and a user's A keyboard 16 for inputting instructions and character information, and a mouse 17 for designating an arbitrary position on the screen of the display device 15 and inputting an instruction corresponding to an icon or the like displayed at the position.

  The CPU 12 and the main memory 13 are examples of a control unit that executes a program and controls each unit, and the hard disk 14 is an example of a storage unit that stores a program and the like. The control unit and the storage unit may be a single device or a plurality of devices. For example, it may be distributed to a plurality of control devices or a plurality of storage devices. The display device 15 is an example of an output device that performs various outputs to the user, and the keyboard 16 and the mouse 17 are examples of an input device that allows the user to perform various input operations.

  The hard disk 14 stores, for example, a layout design program 18 downloaded from the server 20 and other various data 19 necessary for layout design processing and the like. The layout design program 18 is a program for executing processing of a layout design method described later in FIG. The various data 19 is data stored in each storage unit described later with reference to FIG.

  The computer device 10 loads the layout design program 18 and various data 19 into the main memory 13, and the CPU 12 executes the layout design program 18 loaded into the main memory 13, whereby each of the layout design methods according to the present embodiment. The processing is performed to realize a layout design apparatus (functional configuration described later in FIG. 4).

  The basic operation of the computer device 10 is executed via an operating system (OS) that is a basic program stored in the hard disk 14.

  FIG. 4 shows a configuration of a semiconductor integrated circuit layout design apparatus according to the present embodiment. The layout design device 100 includes a processing unit 101 that is realized by executing a layout design program on the computer device 10 and a storage unit 102 for various data corresponding to the hard disk 14 and the like of the computer device 10. Note that each processing unit and each storage unit may be realized by one computer device 10 or a plurality of computer devices 10.

  As illustrated in FIG. 4, the storage unit 102 of the layout design apparatus 100 includes a pre-placement netlist storage unit 201, a placement information storage unit 202, a net connection cost storage unit 203, a wiring resource storage unit 204, a Halo storage unit 205, a placement. A rear net list storage unit 206 is provided. The processing unit 101 of the layout design apparatus 100 includes a cell placement processing unit 110, a net connection cost calculation processing unit 120, a wiring resource calculation processing unit 130, a Halo processing unit 140, and a schematic wiring processing unit 150.

  The pre-placement netlist storage unit 201 stores a pre-designed netlist. This netlist is a netlist that has been macro-arranged and has not been cell-arranged, and defines the macro configuration, connection relationship and arrangement position, cell configuration, connection relationship, and the like. In particular, the netlist describes connection relationships for each input terminal and output terminal of a cell. The netlist stored in the pre-placement netlist storage unit 201 is input information of the processing unit 101, and the processing unit 101 performs cell placement based on the input netlist.

  The arrangement information storage unit 202 stores information necessary for the cell arrangement processing by the cell arrangement processing unit 110 of the processing unit 101. For example, the arrangement information storage unit 202 stores information on divided areas obtained by dividing the arrangement area, information on cell groups obtained by dividing the area, information on cell groups allocated (arranged) to the divided areas, and the like.

  The net connection cost storage unit 203 stores the net connection cost calculated by the net connection cost calculation processing unit 120 of the processing unit 101. The net connection cost storage unit 203 stores the net connection cost of all the cells included in the net list and the net connection cost of the cell group allocated for each divided area.

  The wiring resource storage unit 204 stores the wiring resource calculated by the wiring resource calculation processing unit 130 of the processing unit 101. The wiring resource storage unit 204 stores wiring resources for each divided area.

  The Halo storage unit 205 stores information (Halo information) related to the Halo (virtual extension area) of the cell assigned to the Halo processing unit 140 of the processing unit 101. The Halo information includes the size of Halo and is stored in association with the assigned cell.

  The post-placement net list storage unit 206 stores a net list of processing results (output information) of the processing unit 101. This net list is a net list in which cells are arranged, and defines a macro configuration, connection relationship and arrangement position, cell configuration, connection relationship and arrangement position, and the like. The net list in the post-placement net list storage unit 206 is a net list in which local wiring congestion is suppressed by the cell placement according to the present embodiment.

  The cell placement processing unit 110 (corresponding to the cell placement unit 2 and the cell rearrangement unit 5 in FIG. 1) divides the placement area of the semiconductor integrated circuit and assigns the cells, and repeats this to place the cells in the divided areas. To do. In addition, when the cell is assigned a halo, the cell arrangement processing unit 110 performs division of the arrangement area and cell allocation again. The cell arrangement processing unit 110 includes an arrangement area division processing unit 111, a cell group division processing unit 112, a cell group allocation processing unit 113, an arrangement region division determination unit 114, a wiring congestion area confirmation processing unit 115, and an overlap loosening processing unit 116. ing.

  The arrangement area division processing unit 111 divides the arrangement area of the semiconductor integrated circuit into a plurality of division areas using cut lines. The cell group division processing unit 112 divides (assigns) the cell group into the divided areas. In particular, the cell group division processing unit 112 divides the cell group using the size including the halo when the halo is given to the cell. The cell group assignment processing unit 113 assigns (places) the divided cell group to each divided region.

  The arrangement area division determination unit 114 determines whether or not to end the arrangement area division process (end arrangement). Specifically, the arrangement region division determination unit 114 determines whether or not the number of cells for each divided region is smaller than a predetermined number.

  The wiring congestion area confirmation processing unit 115 confirms the presence or absence of a local wiring congestion area after cell placement. When the cell arrangements overlap (arrangement areas overlap), the overlap unraveling processing unit 116 changes the cell arrangements so that there is no overlap (disentanglement). In particular, when the halo is assigned to the cell, the overlap unraveling processing unit 116 uses the size including the halo to loosen the overlap of the cells.

  The net connection cost calculation processing unit 120 (corresponding to the net connection cost calculation unit 3 in FIG. 1) calculates the net connection cost of the cell based on the cell connection relationship. The net connection cost calculation processing unit 120 includes a cell net connection cost calculation processing unit 121 and a cell group net connection cost calculation processing unit 122. The cell net connection cost calculation processing unit 121 calculates net connection costs of all cells included in the net list. The cell group net connection cost calculation processing unit 122 calculates the net connection cost of the cell group allocated to each divided region.

  The wiring resource calculation processing unit 130 (corresponding to the wiring resource calculation unit 1 in FIG. 1) calculates a wiring resource for each divided region based on the number of wiring tracks.

  The halo processing unit 140 (corresponding to the virtual extension area adding unit 4 in FIG. 1) assigns / deletes the halo to the cell. The Halo processing unit 140 includes a Halo grant determination unit 141, a Halo grant processing unit 142, a Halo deletion processing unit 143, and a Halo reassignment processing unit 144.

  The halo assignment determination unit 141 determines whether halo assignment is necessary for each cell of the divided cell group. Specifically, the Halo grant determination unit 141 determines whether or not the wiring resource is insufficient with respect to the net connection cost. The halo grant processing unit 142 grants the halo to the cell when the wiring resource is insufficient for the net connection cost. The halo deletion processing unit 143 deletes the halo assigned to the cell. The halo reassignment processing unit 144 reassigns the halo to the cell when a local wiring congestion area occurs after the cell placement.

  The schematic wiring processing unit 150 performs schematic wiring in order to confirm local wiring congestion after the cells are arranged.

  The flowchart of FIG. 5 shows the layout design method of the semiconductor integrated circuit according to the present embodiment. In the layout design of a semiconductor integrated circuit, macro placement is performed, and after the net list after the macro placement is generated, the following processing is executed.

  First, the layout design apparatus 100 calculates a net connection cost for every cell included in the net list of the semiconductor integrated circuit according to the number of input terminals, the number of output terminals, and the number of cells connected to the output terminals. (Step S1).

  Next, the layout design apparatus 100 divides the placement area by the min-cut method or the like (step S2), and calculates the wiring resources of the divided placement area based on the wiring track (step S3).

  Next, the layout design apparatus 100 divides (assigns) the cell group so that the number of wires crossing the cut line is minimized and the cell area is not biased by the min-cut method, and allocates the divided arrangement area. (Steps S4 and S5) When virtual cell size information (hereinafter also referred to as Halo) for virtually expanding the size of the cell is given, Halo is deleted (step S6).

  Next, the layout design apparatus 100 calculates the net connection cost of the cell group in the region based on the net connection cost calculated in step S1 (step S7), and calculates the net connection cost calculated in step S7 in step S3. If the number of wiring tracks thus obtained is insufficient, a halo for virtually inflating the cell is assigned, and the process returns to the division of the cell group in step S4 (steps S8 and S9). In this case, the cell group is divided and allocated with the size of the cell to which Halo is assigned (steps S4 to S7).

  Next, when there are enough wiring tracks, the layout design apparatus 100 determines whether the number of cells belonging to the divided region is a sufficiently small number of cells that is a target function of the min-cut method. If the number of cells is large, step S2 Return to (step S10). In this case, the arrangement area is further divided, and cell groups are divided and assigned to the divided areas (steps S2 to S8).

  The layout design apparatus 100 executes schematic wiring when all the cells have been arranged by the min-cut method, and checks whether there is a local wiring congestion area (steps S11 and S12).

  When there is local wiring congestion, the layout design apparatus 100 assigns Halo that virtually expands the cells to the cells included in the area, loosens the overlapping of the cells, and returns to step S11 (step S11). S13, S14). The layout design apparatus 100 completes the process when there is no local wiring congestion area (step S12).

  As a result, cell placement is completed, wiring is performed, and delay time calculation and timing analysis are performed. The cell arrangement according to the present embodiment does not cause local wiring congestion, so that iterating from timing analysis to layout design (cell arrangement) can be suppressed.

Hereinafter, the processing flow of the layout design method of FIG. 5 will be described in detail with reference to FIGS. First, the cell net connection cost calculation processing unit 121 connects to all cells included in the net list of the semiconductor integrated circuit according to the number of input terminals, the number of output terminals, and the number of cells connected to the output terminals. Cost is calculated (step S1). The cell net connection cost calculation processing unit 121 refers to the net list of the semiconductor integrated circuit before the cell placement stored in the pre-placement net list storage unit 201 and calculates the net connection cost of all the cells included in the net list. Then, the calculated net connection cost is stored in the net connection cost storage unit 203. The net connection cost indicates the degree of connection with other cells and is one index for determining the degree of congestion of the wiring, and is based on wiring connected to at least the input terminal and output terminal of the cell. Furthermore, the net connection cost is calculated by, for example, the following (Formula 1).
Net connection cost = number of input terminals connected to the net + Σ (each output terminal × number of cells connected to each output terminal) (Equation 1)

  The number of all input / output wirings connected to the cell can be set as the net connection cost by (Expression 1). FIG. 6 shows an example of the net connection cost set in the cell included in the net list in step S1. Note that a cell is a primitive cell (basic cell: a functional cell of a minimum unit) composed of one flip-flop, a gate circuit, or the like as shown in FIG.

  In the example of FIG. 6, the cell 301 in FIG. 6A and the cell 304 in FIG. 6D both have one input terminal and one output terminal, and have the same number of inputs and output terminals. . Here, with regard to the input terminals, both the cell 301 and the cell 304 are connected to the net, and the number of input terminals connected to the net is the same as one. On the other hand, as for the output terminal, one cell is connected to the output terminal of the cell 301, but there are three cells connected to the output terminal of the cell 304 and two more than the cell 301.

  For this reason, using the formula for calculating the net connection cost in (Equation 1), the net connection cost of the cell 301 in FIG. 6A = 1 + 1 × 1 = 2, and the net connection in the cell 304 in FIG. 6D. Cost = 1 + 1 × 3 = 4.

  Similarly, the cell 302 in FIG. 6B has the number of input terminals = 3, the number of output terminals = 1, and the number of cells connected to the output terminals = 1, so that the net connection cost = 3 + 1 × 1 = 4. . In the cell 303 in FIG. 6C, the number of input terminals = 1, the number of output terminals = 3, and the number of cells connected to the output terminals = 1, so that the net connection cost = 1 + 3 × 1 = 4. The cell 305 in FIG. 6E has the number of input terminals = 3, the number of output terminals = 3, and the number of cells connected to the output terminals = 3, so that the net connection cost = 3 + 1 × 3 + 1 × 3 + 1 × 3 = 12. Become.

  The subsequent processing may be performed using the value calculated by (Equation 1) as the network connection cost, or may be converted (changed) to another value. In the example of FIG. 6, a specific range is determined for the net connection cost calculated by (Equation 1), and the net connection cost within the range is treated as the same net connection cost. By rounding the net connection cost to a predetermined range, processing can be simplified, and parameter adjustment for comparison with wiring resources can be performed.

  For example, the range where the net connection cost is 1 to 3 is 1, the range 4 to 5 is 2, the range 6 to 8 is 3, the range 9 to 10 is 4, and the range 11 to 12 is 5. Accordingly, as shown in FIG. 6, the net connection costs of cell 301 = 2, cell 302 = 4, cell 303 = 4, cell 304 = 4, and cell 305 = 12, calculated in the example of net connection cost calculation, Based on the range of the net connection cost, the cell 301 = 1, the cell 302, the cell 303, the cell 304 = 2, and the cell 305 = 5 are set for the respective net connection costs.

  Next, the arrangement area division processing unit 111 divides the arrangement area of the semiconductor integrated circuit by the cut line (step S2). The division of the arrangement area may be performed using a general arrangement technique such as a min-cut method. The arrangement area division processing unit 111 specifies an arrangement area in which cells are arranged by referring to the net list of the semiconductor integrated circuit before the cell arrangement stored in the pre-placement net list storage unit 201, and, for example, the arrangement area is equalized. The information is divided into two, and the information of the divided area divided into two is stored in the arrangement information storage unit 202.

  FIG. 7 shows an example of a divided area obtained by dividing the arrangement area of the semiconductor integrated circuit in step S2. The example of FIG. 7 is an example in which the arrangement area A1 is divided by the cut line C1. That is, the arrangement region A1 is divided into the divided region B1 and the divided region B2 by the cut line C1 so that the respective areas are halved. In this example, a macro M1 having a certain function is already arranged in the divided area B2. A macro is a circuit block composed of a plurality of circuits so as to realize a predetermined function.

  Next, the wiring resource calculation processing unit 130 calculates a wiring resource based on the number of wiring tracks existing in each divided region divided in step S2 (step S3). The wiring resource calculation processing unit 130 refers to the divided area stored in the arrangement information storage unit 202, calculates the wiring resource of this divided area, and stores the calculated wiring resource in the wiring resource storage unit 204.

  FIG. 8 shows an example of the wiring track of the divided area used for calculating the wiring resource in step S3. The example of FIG. 8 is an example of the wiring track existing in the divided area B2 divided in step S2 of FIG. FIG. 8A shows that the wiring track L1 extends in the horizontal direction (X direction: lateral direction) in the metal 1 layer in the divided region B2, and FIG. 8B shows the vertical direction in the metal 2 layer in the divided region B2. 8 shows that the wiring track L2 extends in the direction (Y direction: vertical direction), and FIG. 8C shows that the wiring track L3 extends in the horizontal direction in the metal 3 layer of the divided region B2. (D) shows that the wiring track L4 extends vertically in the metal 4 layer of the divided region B2. Note that the wiring track L4 of the metal 4 layer in FIG. 8D is doubled with respect to the wiring tracks L1, L2, and L3 of the other layers in FIGS. 8A, 8B, and 8C. Wiring tracks extend at intervals of. That is, when the wiring track density of the wiring tracks L1, L2, and L3 for the regions of FIGS. 8A, 8B, and 8C is 1, the wiring of the wiring track L4 in FIG. The track density is half, which is 0.5.

  The wiring resource is one index for determining the degree of congestion of the wiring, and is based on the number of effective wiring tracks that can be used for wiring at least in the divided area. Here, in general, when wiring is performed, wiring is laid along two horizontal wiring tracks in the horizontal direction and the vertical direction of adjacent metal layers to connect the cells. For this reason, the wiring of one input terminal or output terminal requires a wiring track in the horizontal direction and a wiring track in the vertical direction of adjacent metal layers. Accordingly, the wiring resource is a value obtained by adding up the average (1/2) of the number of wiring tracks of two adjacent metal layers. The wiring resources of the divided region B2 in FIG. 8 are the pairs in FIGS. 8A and 8B, the pairs in FIGS. 8B and 8C, and FIGS. 8C and 8D. (Track number of 1 layer + number of tracks of 2 layers) / 2 + (number of tracks of 2 layers + number of tracks of 3 layers) / 2 + (number of tracks of 3 layers + number of tracks of 4 layers) / 2 It becomes a wiring resource. Thereby, it is possible to accurately determine the excess or deficiency of the wiring resources. Note that a wiring resource may be easily obtained by using a value obtained by simply summing the wiring tracks of all the metal layers as a wiring resource.

  At this time, if a wiring track is already used due to power supply wiring or the like, the track is regarded as being used and is not counted. Further, when a macro or the like is arranged in the area, tracks used in the macro are regarded as used and are not counted. As a result, the wiring resource can be calculated using the number of effective wiring tracks that can be reliably used.

  In FIG. 8, the macro M1 is disposed, and the metal 1 layer and the metal 2 layer are already used in the macro M1, and the effective wiring track of the metal 1 layer in FIG. 8A and the metal 2 layer in FIG. The effective wiring track is obtained by excluding tracks used in the macro M1.

Then, an example of a calculation formula for calculating the wiring resource is the following (Formula 2) and (Formula 3).
Wiring resource = Σ (((n layer effective wiring track) + (n + 1 layer effective wiring track)) / 2) (Expression 2)
Effective wiring track = n layer wiring track−n layer used track (Equation 3)

  Next, the cell group division processing unit 112 divides the cell group so as to minimize the number of wires crossing the cut lines of the respective arrangement areas divided in step S2 (distribution) (step S4), and the cell group allocation processing unit 113. Assigns the divided cell groups to the divided regions (step S5). The division of the cell group and the allocation of the cell group to the divided area may be performed by using a general arrangement technique such as a min-cut method, and further, the target of the method is a range where the total cell area is constant. The cell should not be biased to either area, as long as it is within the range.

  The cell group division processing unit 112 refers to the divided areas stored in the arrangement information storage unit 202 and distributes the cell group included in the net list into two divided areas. The cell group allocation processing unit 113 allocates the allocated two cell groups to each divided region, and stores the allocated cell group and divided region information in the arrangement information storage unit 202.

  FIG. 9 shows an example of assigning divided cell groups to divided regions in step S4. In particular, in FIG. 9, the cells are divided into a group of cells of the cell group E1 and the cell group E2 so that the number of wirings D1 crossing the cut lines C1 of the divided areas B1 and B2 divided in step S2 of FIG. The cell groups E1 and E2 divided into the divided areas B1 and B2 are assigned.

  Next, the halo deletion processing unit 143 deletes the halo when the halo for virtually expanding the size of the cell is assigned to each cell (step S6). If Step S9 has not been executed yet, since Halo has not been assigned, Halo is deleted in Step S6 after Step S9 has been executed and Halo has been assigned. The halo deletion processing unit 143 refers to the halo storage unit 205 and deletes the halo assigned to each cell from the halo storage unit 205.

  FIG. 10 shows an example of deleting Halo in step S6. In the example of FIG. 10, since Halo H2 is assigned to the cell H1, Halo H2 is deleted, and the size of the cell is set to the size of the original cell H1. That is, by deleting Halo H2 assigned to the cell H1, the virtual expansion of the cell is deleted. In this way, by deleting the halo assigned to each cell, the halo is prevented from being assigned to cells other than the cell to which the halo is to be assigned in the halo grant process for subsequent cells.

  Next, the cell group net connection cost calculation processing unit 122 refers to the net connection cost of each cell in step S1, and calculates the net connection cost of the cell group divided in step S4 (step S7). The cell group net connection cost calculation processing unit 122 refers to the net connection cost stored in the net connection cost storage unit 203, refers to the information of the divided cell groups stored in the arrangement information storage unit 202, and The net connection cost of the cell group is calculated, and the calculated net connection cost is stored in the net connection cost storage unit 203.

  FIG. 11 shows an example of calculating the net connection cost of each cell group in step S7. The example of FIG. 11 is an example of a cell group obtained by dividing and allocating the divided areas B1 and B2 divided at step S2 of FIG. 7 at steps S4 and S5 of FIG. The net connection cost of each cell is calculated in step S1, and FIG. 11 shows a state in which cell groups are classified for each net connection cost.

  The cell group C11 is included in the cell group E1 assigned to the divided area B1 in FIG. 9, and the cell group C21 is included in the cell group E2 assigned to the divided area B2 in FIG. In other words, the cell group has one input and one output terminal, one cell connected to the output, and one net connection cost.

  The cell group C12 is included in the cell group E1 assigned to the divided area B1 in FIG. 9, and the cell group C22 is included in the cell group E2 assigned to the divided area B2 in FIG. That is, a cell group having three input terminals, one output terminal and one connected cell, and a net connection cost of two.

  The cell group C13 is included in the cell group E1 assigned to the divided area B1 in FIG. 9, and the cell group C23 is included in the cell group E2 assigned to the divided area B2 in FIG. In other words, the cell group has three input terminals, three output terminals, three cells connected to each output terminal, and a net connection cost of five.

  In the cell groups C11 to C13 assigned to the divided region B1 in FIG. 9, the cell group C11 has four cells with a net connection cost of 1, the cell group C12 has three cells with a net connection cost of 2, and the cell group C13. There are two cells with a net connection cost of 5. For this reason, the net connection cost of the cell group in the divided region B1 is 1 × 4 + 2 × 3 + 5 × 2 = 20 by “Σ (net connection cost × number of cells)”.

  Similarly, in the cell groups C21 to C23 assigned to the divided region B2 in FIG. 9, the cell group C21 has three cells with a net connection cost of 1, the cell group C22 has two cells with a net connection cost of 2, Since the cell group C23 has three cells with a net connection cost of 5, the net connection cost of the cell group in the divided region B2 is 1 × 3 + 2 × 2 + 5 × 3 = 22.

  Next, the halo assignment determination unit 141 determines whether the wiring resources existing in each divided region obtained in step S3 are sufficient for the net connection cost of the divided cell group obtained in step S7 (step S8). The halo grant determining unit 141 refers to the net connection cost of the divided cell group stored in the net connection cost storage unit 203, refers to the wiring resource of the divided area stored in the wiring resource storage unit 204, and Compare network connection costs and wiring resources for each area.

  FIG. 12 shows an example of a cell group and a wiring resource (wiring track) for each divided region determined in step S8. In the example of FIG. 12, as in FIG. 7, the arrangement area is divided into the division area B1 and the division area B2 by the cut line C1, and the macro M1 having a function is arranged in the division area B2. For this reason, the wiring resource obtained in step S3 is smaller in the wiring resource T2 in the divided region B2 than in the wiring resource T1 in the divided region B1. On the other hand, the cell connection cost of the divided cell group obtained in step S7 of FIG. 11 is 20 for the cell group E1, 22 for the cell group E2, and is higher for the cell group E2.

  Here, the wiring resource sufficiency is obtained from “net connection cost / wiring resource”, and when the wiring resource sufficiency exceeds 1, it is determined that the wiring resources of each divided region are insufficient. Note that the criterion for determining the lower limit of the wiring resource sufficiency is variable depending on the process used and the wiring layer used. In this way, it is determined whether the wiring resources of each divided area obtained in step S3 are sufficient for the net connection cost of the divided cell group obtained in step S7.

  Note that instead of the wiring resource sufficiency rate, the net connection cost and the wiring resource may be simply compared to determine whether the wiring resource is excessive or insufficient. If the wiring resource is larger than the net connection cost, it is determined that the wiring resource is sufficient, and if the wiring resource is smaller than the net connection cost, it is determined that the wiring resource is insufficient.

  If it is determined in step S8 that the wiring resource is insufficient in the divided area, the halo grant processing unit 142 virtually assigns the size to the cell group allocated to the divided area determined to be insufficient in the wiring resource. A halo for inflating is applied (step S9). The halo assignment processing unit 142 assigns halos to the cell group in the divided area according to the shortage amount of the wiring resources, and stores the assigned halo information in the halo storage unit 205. FIG. 13 shows an example of adding Halo in step S9. In the example of FIG. 13, Halo H2 for virtually expanding the size is given to the cell H1.

  The size of Halo to be assigned is given in accordance with (according to) the net connection cost of each cell obtained in step S7, and the Halo size to be given to a cell having a high net connection cost is increased. As a result, a wiring area can be secured for a cell that is costly and requires more wiring. Moreover, since the wiring resource is insufficient as the wiring resource satisfaction rate obtained in step S8 is higher, the Halo size assigned to the cell is increased in proportion to the wiring resource satisfaction rate. As a result, a wiring area can be secured for a cell that requires more wiring resources.

  Here, the enlargement ratio of the horizontal direction (X direction) and the vertical direction (Y direction) of the halo to be applied is variable depending on the process used and the wiring layer used. For example, the horizontal wiring track is in the vertical direction. When the number of wiring tracks is larger than that of wiring tracks, the number of vertical wiring tracks is insufficient, so Halo increases the horizontal expansion ratio. As a result, a necessary wiring area can be secured according to the number of wiring tracks in the horizontal and vertical directions.

  After adding Halo in step S9, the processes in and after step S4 are repeated. That is, the cell group is divided and allocated based on the size to which Halo is assigned. For a cell group to which Halo has been assigned, the Halo H2 having a virtual cell size that is the size to which Halo has been assigned is handled as the cell size, thereby expanding the area compared to the original size of the cell H1 and securing wiring resources. Is possible.

  When it is determined in step S8 that the wiring resources are sufficient in the divided area, the arrangement area division determination unit 114 determines whether the cell group divided in step S4 has a sufficiently small number of cells (step S10). If further division is necessary, the process returns to the arrangement area division by the cut line in step S2, and the processes in and after step S2 are repeated. That is, the arrangement area is further divided, and cells are assigned to the divided areas. The determination of whether the cell division is sufficient may be based on a technique such as a min-cut method that is a general arrangement technique.

  FIG. 14A shows an example of division by the second cut line, and FIG. 14B shows an example of division by the final cut line. As shown in FIG. 14A, in the second division, the two divided regions divided by the vertical cut line C1 are divided into two by the horizontal cut line C2, respectively. To do. In FIG. 14A, since the number of cells in the divided area is larger than the predetermined value, the division is further repeated.

  As shown in FIG. 14B, in the final division, the division is performed by the cut lines C1, C3, and C4 in the vertical direction, and is divided by the cut lines C2, C5, and C6 in the horizontal direction to form 16 divided regions. In FIG. 14B, since the number of cells in the divided area is smaller than a predetermined value, division is not necessary and the arrangement of the cells ends.

  For example, the arrangement area division determination unit 114 refers to the arrangement information storage unit 202, and when the cell assigned to each division area is larger than 1, the process after step S2 is repeated to further divide the area, When the number of cells assigned to each divided area is 1, since the arrangement of the cells in the divided areas is completed, the area dividing process is terminated. For example, when the number of cells in the divided area becomes 1, the arrangement area division determination unit 114 generates a netlist after arrangement based on the cell arrangement information and stores it in the netlist storage unit 206 after arrangement.

  Next, the congested part of the wiring is confirmed in the net list after the cell placement. In addition, since the congestion of wiring is suppressed by the process of step S1-step S10, you may complete | finish a process, without performing step S11-step S14. By executing Steps S11 to S14 in addition to Steps S1 to S10, congestion of the wiring can be further suppressed.

  If it is determined in step S10 that the divided cell group has a sufficiently small number of cells, the schematic routing processing unit 150 performs schematic routing on the cell placement results in steps S1 to S10 (step S11). . For the schematic wiring, a general schematic wiring technique may be used. For example, the schematic routing processing unit 150 refers to the post-placement netlist storage unit 206, performs schematic routing between the cells after placement, and stores the netlist after the rough routing in the post-placement netlist storage unit 206.

  Next, the wiring congestion area confirmation processing unit 115 confirms that there is no local wiring congestion area, and completes the processing if there is no congestion area (step S12). For the detection of the wiring congestion area, a general technique may be used. For example, a point where the cost of points and branches is a certain value or more is determined as a wiring congestion portion in the wiring graph of the schematic wiring result. The wiring congestion area confirmation processing unit 115 refers to the net list after rough wiring in the post-placement net list storage unit 206 and detects a local wiring congestion area. In this embodiment, since cells are allocated to the divided areas in consideration of the net connection cost of each cell in steps S1 to S9, an extreme local wiring congestion area does not occur.

  If it is determined in step S12 that there is a local wiring congestion area, the halo reassignment processing unit 144 determines the size of the cell located in the area where the wiring is determined to be locally congested. The halo for virtually inflating is reassigned (step S13). The halo reassignment processing unit 144 assigns halos to the cells according to the degree of wiring congestion, and stores the assigned halo information in the halo storage unit 205.

  The size of the halo assigned to the cell is larger than the halo assigned to the cell in step S9, and is determined according to the level of the congestion area. A cell in the area with a high wiring congestion level is compared with a cell in an area with a low wiring congestion level. Giving a large Halo. Here, in the local wiring congestion area in step S12, if the wiring is congested in the horizontal direction, halo is given in the vertical direction, and if the wiring is congested in the vertical direction, halo is given in the horizontal direction. However, when the wiring is congested in both the horizontal direction and the vertical direction, halo is given to both the vertical direction and the horizontal direction. Thus, by assigning a halo of a size larger than the halo assigned to the cell in the previous step S9, the area determined as the local wiring congestion area in step S12 by unraveling the overlapping cells in the next step, step S14 Wiring resources can be secured.

  Next, the overlap unraveling processing unit 116 unravels the overlap of cells due to the re-assignment of Halo to the cells in step S13 (step S14). The overlap unraveling processing unit 116 refers to the halo storage unit 205, and based on the size to which the halo has been assigned, the overlapping of cells is loosened, and the subsequent netlist is stored in the post-placement netlist storage unit 206. The cell overlap can be removed by using a function installed in a general arrangement technique. At this time, since the halo is reassigned to the cells according to the level of the wiring congestion area in step S13, wiring resources in the wiring congestion area can be secured by loosening the overlapping of the cells.

  After loosening the cell overlap, the process returns to the schematic wiring in step S11. If a local wiring congestion area exists in step S12, the process is repeated by adding Halo to the cell again in step S13. If a local wiring congestion area does not exist in step S12, the process ends.

  In recent years, in the layout design of semiconductor integrated circuits, as the circuit scale of the semiconductor integrated circuit increases and the logic connection becomes more complicated, a congested area of circuit elements and wiring has been generated. In order to converge, circuit elements and wiring tend to become more congested. As a result, iterations that repeat placement and routing and timing analysis are increasing for congestion reduction and timing convergence. Due to the increase in the iteration, the design efficiency of the semiconductor integrated circuit is deteriorated.

  For this reason, in the present embodiment, it is possible to obtain an arrangement result that can converge the timing without generating a local wiring congestion region in the layout design of the semiconductor integrated circuit.

  That is, in the present embodiment as described above, a halo is assigned to a cell according to a shortage of wiring resources with respect to the net connection cost, and the cell is rearranged including the halo. As a result, in the process of deciding the cell arrangement, the arrangement density is made according to the congestion of the wiring, the area where the wiring congestion occurs is made sparse, the wiring congestion is suppressed, and the timing is converged to the sparse arrangement area. Therefore, it is possible to suppress the occurrence of local wiring congestion areas and converge timing. Therefore, it is possible to suppress the iteration due to the congestion of wiring and improve the design efficiency.

  As a conventional layout design method, there is a method of improving a wiring congestion area by executing schematic wiring after arranging cells. In this method, since all the cells are arranged, there is a problem that the iteration of timing convergence increases when local wiring congestion areas are concentrated. On the other hand, in the present embodiment, since cells are arranged so as to prevent wiring congestion during the cell arrangement processing, it is possible to suppress iteration after cell arrangement.

  In addition, as a conventional layout design method, there is a method in which a cell size at a location where wiring congestion specified from connection between modules constituting a netlist and connection of each cell is expected is expanded and then placed. In this method, since all the cells are arranged after expanding the cell size based on the configuration of the netlist without considering the arrangement area and the wiring track existing in the arrangement area, the actual arrangement area and the wiring track are changed. When considered, if local wiring congestion areas are concentrated due to an increase in area due to useless expansion of cells or insufficient expansion of cells, there is a problem that the iteration of timing convergence increases. On the other hand, in the present embodiment, since the cell halo is assigned according to the shortage of the wiring resources with respect to the net connection cost, the halo is appropriately assigned, and the iteration can be effectively suppressed.

  Further, Patent Document 2 secures a wiring resource by increasing the size of a cell located at a location where wiring cannot be performed after each process of rough wiring, detailed wiring, and layout verification. In Patent Document 2, since there is no function of individually changing the cell size in consideration of the wiring property in the placement algorithm of the present embodiment, even if the cell size is expanded after the rough wiring, the local wiring congestion part However, additional wiring resources cannot be secured in an appropriate state, and the layout cannot be converged.

  In Patent Document 2, the size of a cell located at a place where wiring cannot be performed is expanded after execution of each process of rough wiring, detailed wiring, and layout verification. Change the cell size individually considering the above. In the present embodiment, by changing the cell size individually in consideration of the wiring property in the placement algorithm, it is possible to prevent a local wiring congestion area from occurring in the placement result itself.

  In Patent Document 3, cells having the same logic have the same size regardless of the driving capability, so that a wiring region can be secured for a low driving cell. It also describes securing wiring resources by taking a wiring prohibited area in a cell or by providing wiring areas on the left and right sides of a cell.

  In Patent Document 3, since there is no function of individually changing the cell size in consideration of the wiring property in the placement algorithm of the present embodiment, wiring congestion occurs due to the uniform expansion of the size. The area is increased by increasing the size of the unexposed area, and the layout cannot be completed with the optimum area.

  Patent document 3 expands the size of the cell having the same function to the same size regardless of the driving capability before the placement, that is, the cell size is not changed based on the placement / wiring property. In the placement algorithm, the cell size is individually changed in consideration of the wiring property. In this embodiment, by individually changing the cell size in consideration of the wiring property in the placement algorithm, the cell size is expanded only at the location where the wiring congestion occurs, the area increase is suppressed, and the wiring can be performed. It is possible to obtain an arrangement result.

(Embodiment 2)
The second embodiment will be described below with reference to the drawings. In the first embodiment, the arrangement region of the semiconductor integrated circuit is divided and the cells are arranged. In the present embodiment, the cell arrangement is performed without dividing the arrangement region of the semiconductor integrated circuit. Others are the same as those in the first embodiment, and thus description thereof will be omitted as appropriate.

  FIG. 15 shows a configuration of a semiconductor integrated circuit layout design apparatus according to the present embodiment. In the layout design apparatus 100 of FIG. 15, the cell arrangement processing unit 110 includes an arrangement region division processing unit 111, a cell group division processing unit 112, and an arrangement region division determination unit 114, compared to FIG. 4 of the first embodiment. Not. Other configurations are the same as those in FIG. In the present embodiment, the cell group allocation processing unit 113 arranges all the cells of the netlist in the arrangement area of the semiconductor integrated circuit (the arrangement area of the entire chip). The cell group net connection cost calculation processing unit 122 calculates the net connection cost of the cell group arranged in the arrangement region of the semiconductor integrated circuit. The wiring resource calculation processing unit 130 calculates a wiring resource in the arrangement area of the semiconductor integrated circuit.

  FIG. 16 shows a layout design method for a semiconductor integrated circuit according to the present embodiment. Basically, the flowchart of FIG. 16 is a process that excludes the area division process from the flowchart of FIG. 5.

  Differences between FIG. 16 and FIG. 5 are the arrangement area division (step S2), cell group division (step S4), and determination of whether the cell group has a sufficiently small number of cells (step S10). To the point where the step is deleted, the wiring resource calculation (step S3) of the divided area is changed to the wiring resource calculation (step S31) of the entire arrangement area instead of the divided area, and to the divided area. The cell group allocation (step S5) is changed to the cell group arrangement (step S51) in the arrangement area.

  That is, as shown in FIG. 16, the layout design apparatus 100 corresponds to the number of input terminals, the number of output terminals, and the number of cells connected to the output terminals for every cell included in the netlist of the semiconductor integrated circuit. Then, the network connection cost is calculated (step S1).

  Next, the layout design apparatus 100 calculates wiring resources for the entire arrangement region of the semiconductor integrated circuit based on the wiring tracks (step S31).

  Next, the layout design apparatus 100 arranges the cell group so that there is no deviation in the cell area in the entire arrangement region of the semiconductor integrated circuit (step S51), and if the cell is assigned Halo, the Halo is deleted (step S51). S6).

  Next, the layout design apparatus 100 calculates the net connection cost of the cell group in the arrangement area based on the net connection cost calculated in step S1 (step S7), and in step S31 against the net connection cost calculated in step S7. If the calculated wiring track is insufficient, a halo for virtually inflating the cell is assigned, and the process returns to the arrangement of the cell group in step S51 (steps S8 and S9). In this case, the cell group is arranged with the size of the cell to which the halo has been assigned (steps S51 to S8).

  Next, when the wiring track is sufficient, the layout design apparatus 100 performs schematic wiring and checks whether there is a local wiring congestion area (steps S11 and S12).

  When there is local wiring congestion, the layout design apparatus 100 assigns Halo that virtually expands the cells to the cells included in the area, loosens the overlapping of the cells, and returns to step S11 (step S11). S13, S14). The layout design apparatus 100 completes the process when there is no local wiring congestion area (step S12).

  As described above, in the present embodiment, without dividing the placement area, the placement area on the entire surface of the semiconductor integrated circuit is provided with a halo that virtually expands the size of the cell that is determined to be congested with the wiring. Reassign cells to the region. Thus, as in the first embodiment, in the process of determining the placement of the cells, considering the logical connection of each cell, by securing the wiring area by sparsely arranging the areas where the wiring congestion occurs, Generation of local wiring congestion areas can be suppressed and timing can be converged.

(Embodiment 3)
The present embodiment is an example in which cells are arranged by dividing a semiconductor integrated circuit into hierarchical blocks, compared to the first embodiment. The system configuration of the present embodiment is the same as that of the first embodiment, and a description thereof will be omitted. When the circuit scale of a semiconductor integrated circuit increases, the layout is generally performed by dividing the semiconductor integrated circuit into a plurality of hierarchical blocks by a hierarchical layout design method.

  When performing this hierarchical layout design, after the net connection cost calculation processing (step S1) to the cell of FIG. 5, the hierarchical block is divided, and the arrangement area by the cut line of FIG. 5 is applied to each divided block. By executing the processing after the division processing (step S2), the arrangement in the hierarchical block is executed, and after the arrangement of all the hierarchical blocks is completed, the normal hierarchical layout design method is returned.

  When placing cells in a hierarchical block, the wiring congestion is suppressed by sparsely arranging the areas where the wiring is congested and securing the wiring resources, and the cell movement for timing convergence is performed in the area where the arrangement is sparse. By arranging repeaters, local wiring congestion areas can be suppressed and timing can be converged in a large-scale LSI layout to which a hierarchical layout method is applied.

(Embodiment 4)
The present embodiment is an example in which cell groups are grouped and arranged with respect to the first embodiment. The system configuration of the present embodiment is the same as that of the first embodiment, and a description thereof will be omitted. A so-called group arrangement is generally performed in which cell groups are grouped into functional units constituting a semiconductor integrated circuit and arranged in one place.

  When this grouping is performed, group placement is performed after the net connection cost calculation processing (step S1) to the cell in FIG. 5, and the cell group division processing (step S4) in FIG. In the allocation process (step S5), the arranged groups are considered.

  The present embodiment is applied to a group arrangement in which cell groups are grouped and arranged in functional units constituting a semiconductor integrated circuit, and wiring resources are secured by sparse arrangement of wiring congested areas when performing grouping. In a group arrangement in which cell groups are grouped and arranged in functional units constituting a semiconductor integrated circuit by arranging cell movement and repeaters for timing convergence in an area where arrangement is sparse by suppressing wiring congestion The occurrence of local wiring congestion areas can be suppressed and the timing can be converged.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Wiring resource calculation part 2 Cell arrangement | positioning part 3 Net connection cost calculation part 4 Virtual expansion area provision part 5 Cell rearrangement part 10 Computer apparatus 11 Main body part 13 Main memory 14 Hard disk 15 Display apparatus 16 Keyboard 17 Mouse 18 Layout design program 19 Various Data 20 Server 21 Recording medium 30 Network 100 Layout design device 101 Processing unit 102 Storage unit 110 Cell arrangement processing unit 111 Arrangement area division processing unit 112 Cell group division processing unit 113 Cell group allocation processing unit 114 Arrangement area division determination unit 115 Wiring congestion Area confirmation processing unit 116 Overlapping and unraveling processing unit 120 Net connection cost calculation processing unit 121 Cell net connection cost calculation processing unit 122 Cell group net connection cost calculation processing unit 130 Wiring resource calculation processing unit 140 Halo processing unit 1 DESCRIPTION OF SYMBOLS 1 Halo grant determination part 142 Halo grant process part 143 Halo deletion process part 144 Halo re-assignment process part 150 General wiring process part 201 Net-list storage part 202 before arrangement | positioning Information storage part 203 Net connection cost storage part 204 Wiring resource storage part 205 Halo storage unit 206 Netlist storage unit after placement

Claims (20)

Based on the input netlist, a wiring resource that can be wired to the first region of the semiconductor integrated circuit is calculated,
A plurality of cells included in the netlist are arranged in the first area based on the size of the cells,
Based on cell connection information included in the net list, a net connection cost indicating a degree of connection of a plurality of cells arranged in the first region is calculated,
When the wiring resource is insufficient for the net connection cost in the first area, a virtual extension area that virtually expands the size of the cell arranged in the first area is given,
Relocating a plurality of cells including the cell in the first area based on the size of the cell including the assigned virtual extension area;
A method for designing a layout of a semiconductor integrated circuit. The first region is an arrangement region of the entire semiconductor integrated circuit.
The layout design method for a semiconductor integrated circuit according to claim 1. The first region is a divided region obtained by dividing the arrangement region of the entire semiconductor integrated circuit.
The layout design method for a semiconductor integrated circuit according to claim 1. Dividing the semiconductor integrated circuit into a plurality of hierarchical blocks;
The first area is an area of the divided hierarchical block.
The layout design method for a semiconductor integrated circuit according to claim 1. Grouping multiple cells included in the netlist based on function,
In the placement in the first region, the placement is based on the group of cells.
The layout design method for a semiconductor integrated circuit according to claim 1. The net connection cost is a value based on wiring connected to the input terminal and output terminal of the cell,
The layout design method for a semiconductor integrated circuit according to claim 1. The net connection cost is a value obtained by summing the number of terminals of the input terminal, the result of multiplication of the number of terminals of the output terminal and the number of cells connected to the output terminal,
The layout design method for a semiconductor integrated circuit according to claim 6. The net connection cost is a value obtained by converting the total value into a value in a predetermined range.
The layout design method for a semiconductor integrated circuit according to claim 7. The wiring resource is a value based on the number of effective wiring tracks that can be used for wiring in the first region.
The layout design method for a semiconductor integrated circuit according to claim 1. The wiring resource is a value obtained by totaling the average values of the effective wiring tracks of two adjacent wiring layers.
The layout design method for a semiconductor integrated circuit according to claim 9. The number of effective wiring tracks is a value obtained by subtracting the number of wiring tracks used by the circuit block arranged in the first area before the arrangement of the cells from the total number of wiring tracks in the first area. ,
The layout design method for a semiconductor integrated circuit according to claim 9. The net connection cost in the first region is compared with the wiring resource, and when the net connection cost is larger than the wiring resource, it is determined that the wiring resource is insufficient.
The layout design method for a semiconductor integrated circuit according to claim 1. Determining a shortage of the wiring resource according to a wiring resource sufficiency ratio that is a ratio of the net connection cost to the wiring resource in the first region;
The layout design method for a semiconductor integrated circuit according to claim 1. The virtual extension area to be given is a size according to a wiring resource sufficiency ratio that is a ratio of the net connection cost to the wiring resource in the first area.
The layout design method for a semiconductor integrated circuit according to claim 1. The virtual extension area to be given has a size according to the number of wiring tracks in the vertical direction and the number of wiring tracks in the horizontal direction.
The layout design method for a semiconductor integrated circuit according to claim 1. After placing or rearranging the cells, perform schematic wiring,
As a result of the rough wiring, if there is a wiring congestion area, the virtual extension area is reassigned to the cells arranged in the wiring congestion area,
Changing the arrangement of the cells based on the size of the cell plus the re-assigned virtual extension region,
The layout design method for a semiconductor integrated circuit according to claim 1. In the change of the cell arrangement, the cell added with the re-assigned virtual extension region and the other cells are unwrapped.
The layout design method for a semiconductor integrated circuit according to claim 16. The virtual extension area to be reassigned is a size according to the level of wiring congestion.
The layout design method for a semiconductor integrated circuit according to claim 16. A layout design program for a semiconductor integrated circuit that causes a computer to execute a layout design process for a semiconductor integrated circuit, wherein the layout design process includes:
Based on the input netlist, a wiring resource that can be wired to the first region of the semiconductor integrated circuit is calculated,
A plurality of cells included in the netlist are arranged in the first area based on the size of the cells,
Based on cell connection information included in the net list, a net connection cost indicating a degree of connection of a plurality of cells arranged in the first region is calculated,
When the wiring resource is insufficient for the net connection cost in the first area, a virtual extension area that virtually expands the size of the cell arranged in the first area is given,
Relocating a plurality of cells including the cell in the first area based on the size of the cell including the assigned virtual extension area;
A semiconductor integrated circuit layout design program. A wiring resource calculation unit that calculates a wiring resource that can be wired to the first region of the semiconductor integrated circuit based on the input netlist;
A cell placement unit for placing a plurality of cells included in the netlist in the first region based on a size of the cell;
A net connection cost calculation unit that calculates a net connection cost indicating a degree of connection of a plurality of cells arranged in the first region based on connection information of cells included in the net list;
When the wiring resource is insufficient with respect to the net connection cost in the first area, a virtual extension area giving unit that gives a virtual extension area that virtually expands the size of the cell arranged in the first area When,
A cell rearrangement unit that rearranges a plurality of cells including the cell in the first area based on the size of the cell to which the assigned virtual extension area is added;
A semiconductor integrated circuit layout design apparatus.

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