JP2014082299A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that it is popular in a BGA-type device, for example, to plate exposed lands of an organic multilayer interposer with nickel or gold by electrolytic plating and a common plating wire for supplying power to the plurality of lands is arranged for the electrolytic plating; but because an electrical test cannot be performed when the common plating wire is left as it is, the common plating wire is removed together with a solder resist film before the electrical test; but cracks and the like are likely to occur in a semiconductor chip at a part corresponding to an etch back groove which is opened in the solder resist film generated at the time of removing the common plating wire, depending on a shape of the etch back groove, a positional relationship between the etch back groove and the semiconductor chip and the like.SOLUTION: In a BGA-type semiconductor integrated circuit device using an organic multilayer interposer having an etch back groove, the etch back groove crossing a semiconductor chip is split at a part corresponding to an inner region of the semiconductor chip.

Description

  The present application relates to a semiconductor integrated circuit device (or a semiconductor device), and can be applied to, for example, a packaging technique using a multilayer wiring board.

  Japanese Unexamined Patent Application Publication No. 2005-79129 (Patent Document 1) relates to an organic multi-layer wiring interposer of BGA (Ball Grid Array). There is disclosed a technique in which an etch-back groove for removing a connecting line for electrolytic plating is provided in an inner region of the lower surface of an organic multilayer wiring interposer.

  Japanese Unexamined Patent Publication No. 2002-50715 (Patent Document 2) relates to an organic multilayer wiring interposer of BGA. There is disclosed a technique in which an etch-back groove for removing a common plating line is provided on one surface of an organic double-sided wiring interposer.

  Japanese Unexamined Patent Publication No. 9-172104 (Patent Document 3) relates to a BGA organic multilayer wiring interposer. In order to prevent warpage of the organic double-sided wiring interposer, there are disclosed warpage prevention grooves from which the solder resist film on the upper surface is removed, which crosses the semiconductor chip and which does not cross.

JP 2005-79129 A JP 2002-50715 A JP-A-9-172104

  For example, in a BGA type device, nickel or gold is generally plated by electrolytic plating on an exposed land (metal terminal) of an organic multilayer interposer (for example, two layers on both sides). For this electrolytic plating, an organic multilayer interposer in the middle of fabrication is provided with a common plating line that supplies a current during electrolytic plating to a plurality of lands in common. However, when a BGA type device is assembled with this common plated wire as it is, the plurality of lands are limited to use at the same potential. Alternatively, it is conceivable to remove the common plated wire when assembling the BGA type device, but it becomes impossible to perform an electrical test of the interposer itself before this removal, for example, before mounting the semiconductor chip. For this reason, the common plated wire is removed before mounting the semiconductor chip. The groove formed in the solder resist film necessary for removing the common plating line is referred to as an etch back groove.

  According to the examination of the relationship between the etch-back groove and the semiconductor chip by the inventors of the present application, the etch-back groove corresponds to the etch-back groove depending on the shape of the etch-back groove and the positional relationship between the etch-back groove and the semiconductor chip. It has become clear that cracks and the like may occur in some semiconductor chips.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the outline of one embodiment of the present application is that a BGA type semiconductor integrated circuit device using an organic multilayer interposer having an etch-back groove corresponds to an etch-back groove crossing the semiconductor chip corresponding to an internal region of the semiconductor chip. The part to be divided.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the embodiment of the present application, it is possible to prevent the occurrence of cracks or the like in the portion of the semiconductor chip corresponding to the etch-back groove.

1 is a simplified device overall cross-sectional view for explaining a device structure (basic structure: bulk etchback rectangular ring) and the like in a semiconductor integrated circuit device according to an embodiment of the present application; FIG. FIG. 2 is a plan view of the entire back surface of the device of FIG. 1 (in order to ensure visibility, wiring on the back surface, bump electrodes and the like, spacers on the front surface side, uppermost semiconductor chip, etc. are not shown. The same). FIG. 3 is a supplementary plan view of the entire back surface for explaining the planar positional relationship between a lower-layer semiconductor chip, an etch-back rectangular ring, and the like, and a spacer, the uppermost semiconductor chip, and the like. FIG. 3 is a supplementary plan view of the entire back surface for explaining the planar positional relationship between a lower layer semiconductor chip, an etch-back rectangular ring, and the like, and an arrangement of bump electrodes on the back surface of the organic wiring board. FIG. 3 is an enlarged plan view of the back surface of the bulk non-groove periphery cutting region R1 in FIG. 2 (bump electrodes and the like are not shown in order to ensure visibility). FIG. 2 is an enlarged cross-sectional view of a portion substantially corresponding to a partial cross-sectional cutout region R2 in FIG. It is a process block flow diagram for demonstrating the substrate process in the manufacturing method regarding the semiconductor integrated circuit device of the said one Embodiment of this application. It is a whole back surface top view of the organic type wiring panel 61 for demonstrating arrangement | positioning of the plating wire in the completion time of the front and back soldering resist film formation & patterning process 103. FIG. FIG. 9 is a plan view of the entire back surface of the organic wiring sheet 62 in FIG. 8 for explaining the arrangement of plated wires. FIG. 10 is a plan view of the entire back surface of the organic wiring unit substrate 63 of FIG. 9 for explaining the arrangement of plated wires. FIG. 11 is an overall rear enlarged plan view showing bump lands and related wirings in a portion of a substrate corner portion cutout region R3 in FIG. 10; FIG. 11 is an enlarged plan view of the back surface of the bulk non-groove periphery cutting region R1 in FIG. 10 (at the time when the front and back solder resist film formation & patterning step 103 is completed). It is a back surface enlarged plan view (at the time of completion of pad electroplating process 104) of bulk non-groove part circumference cutout region R1 of FIG. FIG. 11 is a plan view of the entire back surface of the organic wiring unit substrate 63 corresponding to FIG. 10 in the plating line removing process 105 (etch back process). It is a back surface enlarged plan view (at the time of completion of the etch back process 105) corresponding to FIG. 14 of bulk non-groove part periphery cutting-out area | region R1 of FIG. It is a process block flowchart for demonstrating the assembly process in the manufacturing method regarding the semiconductor integrated circuit device of the said one Embodiment of this application. FIG. 2 is a simplified device overall cross-sectional view (unit substrate 63 of an organic wiring sheet 62) corresponding to FIG. 1 in the middle of a wire bonding step 112; FIG. 2 is a simplified cross-sectional view of the entire device corresponding to FIG. 1 (in the middle of a resin sealing step 113). FIG. 2 is a simplified cross-sectional view of the entire device (bump electrode attaching step 114) corresponding to FIG. 1; FIG. 5 is a plan view of the entire back surface corresponding to FIG. 3 for explaining a modification (spacer edge non-proximity layout) and the like related to the position of the etch back ring and spacer in the device structure of the semiconductor integrated circuit device of the embodiment of the present application. is there. FIG. 2 is a view for explaining a modified example (chip edge crossing portion non-groove portion etchback ring) regarding both ends (crossing portions) of the etch back ring crossing portion in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a corresponding back surface whole plan view. FIG. 7 is a back side overall plan view corresponding to FIG. 2 for explaining a modification (dot-like etch back ring) and the like related to the overall structure of etch back ring in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. It is a back surface enlarged plan view of bulk non-groove part circumference cutting-out area | region R1 of FIG. 22 (in order to ensure visibility, a bump electrode etc. are not illustrated). FIG. 2 corresponds to FIG. 2 for explaining a modification example (flat placed multi-chip bulk etch-back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. It is a whole back surface top view. FIG. 25 is a supplementary plan view of the entire back surface for explaining the planar positional relationship between a semiconductor chip, an etch-back rectangular ring, and the like, and an arrangement of bump electrodes on the back surface of the organic wiring board, and the like. Corresponding to FIG. 2 for explaining a modification example (flat placed multi-chip dot-like etch-back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. The entire back surface corresponding to FIG. 2 for explaining a modified example (an oblique chip-oriented bulk etch-back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. It is a top view. FIG. 28 is a supplementary plan view of the entire back surface for explaining the planar positional relationship between the semiconductor chip, the etch-back rectangular ring, and the like, and the arrangement of bump electrodes on the back surface of the organic wiring board, and the like. The back surface corresponding to FIG. 2 for explaining a modification example (an oblique chip-oriented dot-like etch-back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a whole top view. Semiconductor chip, etch-back rectangular ring, etc. for explaining a modification (rectangular substrate bulk etch-back rectangular ring) etc. related to the etch back ring and semiconductor chip layout in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application FIG. 3 is a plan view of the entire back surface for explaining the planar positional relationship between the bump electrodes and the arrangement of bump electrodes on the back surface of the organic wiring board. Corresponding to FIG. 5 for explaining a seed modification example (wide wiring, that is, a reinforcing structure by a local grounding & wiring plate), etc., relating to the bulk non-groove portion of the etch back ring in the device structure of the semiconductor integrated circuit device of the embodiment of the present application FIG. 3 is an enlarged plan view of the rear surface of the cut-out region R1 around the bulk non-groove portion of FIG. 2 (bump electrodes and the like are not shown in order to ensure visibility). FIG. 2 corresponding to FIG. 2 for explaining a seed variation (insertion structure of substrate address metal pattern) and the like regarding the bulk non-groove portion of the etch back ring in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. It is a back surface enlarged plan view of bulk non-groove part periphery cutting-out area | region R1 (a bump electrode etc. are not illustrated in order to ensure visibility). 2 is a plan view of the entire back surface corresponding to FIG. 2 for explaining a modified example (bent crossing portion etch back ring) of the crossing side (crossing portion) of the etch back ring in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. In the device structure of the semiconductor integrated circuit device according to the one embodiment of the present application, a modification (bent crossing portion etch back ring) relating to the crossing side (crossing portion) of etch back ring and “linearity” relating to sections 1 to 9 (this section) FIG. 34 is an enlarged plan view of the chip end cutout region R4 of FIG. FIG. 35 is an enlarged plan view corresponding to FIG. 34 illustrating a typical straight crossing portion for explaining “flexibility” in FIG. 34 and “linearity” of the crossing portion in each example of the present application. FIG. 35 is an enlarged plan view corresponding to FIG. 34 showing a limit example of a straight crossing portion for explaining “flexibility” in FIG. 34 and “linearity” of the crossing portion in each example of the present application. FIG. 3 is a plan view of the entire back surface of the device of FIG. 1 corresponding to FIG. 2 for explaining the outline of the device structure in the semiconductor integrated circuit device of the one embodiment of the present application. Etchback rectangular ring for explaining combination example 1 (introduction of bulk element into dot-like etchback rectangular ring) of various types of etchback rectangular ring in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application 2 is a plan layout view of a semiconductor chip. Etch back for explaining examples of combinations of various types of etch-back rectangular rings in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application (introduction of bent-shaped sections of etch-back rectangular rings to combination example 1) It is a plane layout figure of a rectangular ring and a semiconductor chip.

[Outline of Embodiment]
First, an outline of a typical embodiment disclosed in the present application will be described.

1. Semiconductor integrated circuit devices including:
(A) An organic wiring board having a metal wiring pattern at least on the front surface and the back surface and having a rectangular shape;
(B) a first semiconductor chip having a first main surface and a second main surface, having a rectangular shape, and being fixed on the surface of the organic wiring board;
(C) a resin sealing body for sealing the first semiconductor chip on the surface of the organic wiring board;
(D) a large number of bump electrodes provided on the back surface of the organic wiring board;
(E) an etch-back rectangular ring provided on the back surface of the organic wiring board;
Here, the etch-back rectangular ring has the following:
(E1) at least one transverse side that runs parallel to one of the substrate end sides of the organic wiring substrate and intersects the first semiconductor chip;
(E2) a transverse part where the first semiconductor chip and each transverse side overlap in a plane;
(E3) A first non-groove portion provided inside each transverse portion.

  2. In the semiconductor integrated circuit device according to Item 1, the etch-back rectangular ring is provided in a region between the annular bumps in a plan view.

  3. In the semiconductor integrated circuit device according to Item 1 or 2, the both end portions of each transverse portion and the vicinity thereof are integral groove portions.

  4). In the semiconductor integrated circuit device according to any one of Items 1 to 3, each first non-groove portion is provided at or near the center of each transverse portion.

5. In the semiconductor integrated circuit device according to any one of Items 1 to 4,
(I) the first main surface of the first semiconductor chip is a device formation surface;
(Ii) The first semiconductor chip is fixed via a first adhesive layer provided between the surface of the organic wiring board and the second main surface of the first semiconductor chip. And;
(Iii) A plurality of bonding pads on the first main surface of the first semiconductor chip and a plurality of bonding leads on the surface of the organic wiring substrate are connected by bonding wires.

  6). 6. The semiconductor integrated circuit device according to Item 5, wherein the first adhesive layer is a silver paste adhesive layer.

  7). In the semiconductor integrated circuit device according to any one of Items 1 to 6, a spacer substrate or a second semiconductor chip is stacked on the first main surface of the first semiconductor chip.

  8). In the semiconductor integrated circuit device according to Item 7, the first end side of the spacer substrate or the second semiconductor chip is disposed above or near the transverse portion adjacent to the spacer substrate or the second semiconductor chip. Yes.

  9. In the semiconductor integrated circuit device according to any one of Items 5 to 8, the bonding wire is a copper-based wire.

  10. In the semiconductor integrated circuit device according to any one of Items 1 to 9, each crossing portion has a linear shape.

  11. In the semiconductor integrated circuit device according to any one of Items 1 to 10, the thickness of the first semiconductor chip is 100 micrometers or less.

  12 In the semiconductor integrated circuit device according to any one of Items 1 to 11, on at least one of the first non-groove portions and on the back surface of the organic wiring substrate under a solder resist film in the vicinity thereof, A wide metal pattern of the same layer as the metal wiring pattern is disposed.

  13. In the semiconductor integrated circuit device according to any one of Items 1 to 11, the metal is disposed on one of the first non-groove portions and on the back surface of the organic wiring substrate under the solder resist film around the first non-groove portion. Metal substrate address marks in the same layer as the wiring pattern are arranged.

14 Semiconductor integrated circuit devices including:
(A) An organic wiring board having a metal wiring pattern at least on the front surface and the back surface and having a rectangular shape;
(B) a first semiconductor chip having a first main surface and a second main surface, having a rectangular shape, and being fixed on the surface of the organic wiring board;
(C) a resin sealing body for sealing the first semiconductor chip on the surface of the organic wiring board;
(D) a large number of bump electrodes provided on the back surface of the organic wiring board;
(E) an etch-back rectangular ring provided on the back surface of the organic wiring board;
Here, the etch-back rectangular ring has the following:
(E1) A transverse side that runs in parallel with an edge of any one of the organic wiring boards and crosses the first semiconductor chip;
(E2) a transverse part in which each transverse side overlaps the first semiconductor chip in a plane,
Furthermore, here, said transverse part is constituted by an integral groove, which has the following:
(X1) first linear portion;
(X2) a second straight line portion extending in parallel with the first straight line portion;
(X3) a bent portion connecting the first straight portion and the second straight portion,
Here, the first straight part and the second straight part are shifted in the width direction so that their extensions do not overlap.

  15. In the semiconductor integrated circuit device according to Item 14, the etch-back rectangular ring is provided in a region between the annular bumps in a plan view.

16. In the semiconductor integrated circuit device according to Item 14 or 15,
(I) the first main surface of the first semiconductor chip is a device formation surface;
(Ii) The first semiconductor chip is fixed via a first adhesive layer provided between the surface of the organic wiring board and the second main surface of the first semiconductor chip. And;
(Iii) A plurality of bonding pads on the first main surface of the first semiconductor chip and a plurality of bonding leads on the surface of the organic wiring substrate are connected by bonding wires.

  17. In the semiconductor integrated circuit device according to Item 16, the first adhesive layer is a silver paste adhesive layer.

  18. In the semiconductor integrated circuit device according to any one of Items 14 to 17, a spacer substrate or a second semiconductor chip is stacked on the first main surface of the first semiconductor chip.

  19. In the semiconductor integrated circuit device according to Item 18, the first end of the spacer substrate or the second semiconductor chip is disposed above or near the transverse portion adjacent to the spacer substrate or the second semiconductor chip. Yes.

  20. 20. In the semiconductor integrated circuit device according to any one of Items 16 to 19, the bonding wire is a copper-based wire.

  21. In the semiconductor integrated circuit device according to any one of Items 14 to 20, the shift amount in the width direction is equal to or less than a sum of widths of the first straight line portion and the second straight line portion.

  22. In the semiconductor integrated circuit device according to any one of Items 1 to 13, the thickness of the first semiconductor chip is 100 micrometers or less.

  23. In the semiconductor integrated circuit device according to any one of Items 1 to 13 and 22, both ends of each transverse portion and the vicinity thereof are non-groove portions.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). A silicon substrate) or a semiconductor chip packaged. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  The wafer process of today's semiconductor integrated circuit device, that is, LSI (Large Scale Integration), is usually considered in two parts. That is, the first consists of carrying in a silicon wafer as a raw material to a premetal process (formation of an interlayer insulation film between the lower end of the M1 wiring layer and the gate electrode structure, contact hole formation, tungsten plug, embedding, etc. This is a FEOL (Front End of Line) process. The second is BEOL (Back End of Line) starting from the formation of the M1 wiring layer until the formation of the pad opening in the final passivation film on the aluminum-based pad electrode (including the process in the wafer level package process). It is a process.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  3. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  4). The figure, position, attribute, and the like are preferably illustrated, but it is needless to say that the present invention is not strictly limited to this unless it is clearly indicated otherwise and the context clearly does not. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to parallel. Similarly, for example, a deviation of about 10 degrees from complete orthogonality belongs to orthogonality.

  In addition, for a certain region, “whole”, “whole”, “whole area”, and the like include cases of “substantially whole”, “substantially general”, “substantially whole area”, and the like. Therefore, for example, 80% or more of a certain area can be referred to as “whole”, “whole”, and “whole area”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is less than about 20% of the whole, it can be said to be a rectangle. The same applies to “annular” and the like. In this case, when the annular body is divided, a portion obtained by interpolating or extrapolating the divided element portion is a part of the annular body.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is less than about 20%, each element can be said to be “periodic”. . Furthermore, if what is out of this range is, for example, less than about 20% of all the elements to be periodic, it can be said to be “periodic” as a whole.

  Note that the definitions in this section are general, and when there are different definitions in the following individual descriptions, priority is given to the individual descriptions for this part. However, the definition, provisions, etc. of this section are still valid for parts that are not stipulated in the individual description part, unless explicitly denied.

  5. In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  6). The etch back method of the organic multilayer wiring board described in the present application is a “spot etch back method” in which spot-like etch back grooves are arranged relatively randomly, and a ring-like integral or multiple etch in an internal region of the wiring board. It can be divided into a “ring etch back method” that uses an assembly composed of back grooves. Of course, it is possible to use the spot etch back method as a part of the ring etch back method, and the ring etch back method is not excluded. The present application mainly relates to a ring etch back system.

In this application, “etch back ring”, “etch back ring” and the like are grooves from which the solder resist film on the back surface of the interposer has been removed (if there is a metal film, it is also removed) or grooves An assembly of the above, arranged in a linear shape (including straight lines, polygonal lines, and curves), and generally exhibiting a ring shape (rectangular ring, square ring, polygonal ring, circular ring, elliptical ring, etc.) Say. Here, taking a rectangular ring as an example, in order to be a rectangular ring, it is necessary to satisfy all of the following conditions (hereinafter, “length” refers to a length along a side. In addition, the difference in the direction perpendicular to the side is called “width”). That is,
(1) The ratio of the sum total of the length of the groove part which occupies for the perimeter on a ring is 30% or more (this is determined from the necessity that a common plating wiring plays the role);
(2) The length of the single non-groove portion in each side is less than 50% of the length of the side. In addition, when a single non-groove portion extends over adjacent sides, it is considered to be divided into each side (when the length of a single non-groove portion is 50% of the length of the side, recognition of the side is performed. Because it becomes difficult);
(3) In the case where a single non-groove portion extends over adjacent sides, the length of the shorter single non-groove portion is less than 40% of the length of the side (in the adjacent side This is because it is difficult to recognize the rectangle if there is a long non-grooved part connected to each other);
(4) The total sum of the lengths of the grooves in each side is 30% or more of the length of the side (otherwise, it is meaningless to arrange the common plated wiring in a ring shape).

  According to these definitions, the rectangular etch-back ring is called “etch-back rectangular ring”.

Furthermore, “the side of the etch-back rectangular ring crosses the semiconductor chip” is said to be planar, and the side of the etch-back rectangular ring is the two chip edges of the semiconductor chip (opposite chip edge, adjacent Crossing with any edge of the chip). However, subject to the following. That is,
(I) The side does not cross the other chip end side of the semiconductor chip halfway (because once it goes out of the chip, the crossing ends there);
(Ii) The length of the crossing portion is 40% or more of the length of the short chip edge (one chip edge in the case of a square) of the semiconductor chip (because it is slightly squeezed, it cannot be said to be crossing). is there).

  Here, the “crossing portion” refers to a portion of the side crossing the semiconductor chip that overlaps the semiconductor chip in a planar manner. In this regard, “the cross section is linear” means that a straight line that passes through the inside (including the boundary) of all the grooves constituting the cross section and is parallel to one substrate edge of the organic wiring board can be drawn. Say that.

  A portion of the etch-back rectangular ring that intersects the chip end side of the semiconductor chip is referred to as a “crossover portion”.

  The types of etch-back rectangular rings are roughly classified into “dot-shaped etch-back rectangular rings” and “bulk-shaped etch-back rectangular rings”. The dot-like etch-back rectangular ring is formed by arranging dot-like groove portions so that the length of the groove portions constituting the dot-like etchback ring and the distance between adjacent groove portions are less than twice the width of the groove portions. On the other hand, in the bulk-shaped etchback rectangular ring, the lengths of the bulk groove portion and the bulk non-groove portion constituting the bulk etch-back rectangular ring are twice or more the width of the bulk groove portion.

  7). In the present application, the “internal bump arrangement region” refers to a portion where a large number of bump electrodes (or bump electrode formation lands) are densely arranged at the center of the back surface of the interposer. Note that the internal bump arrangement area is also used for a portion corresponding to the area on the back surface of the interposer. This also applies to the following annular bump area, external bump arrangement area, and the like.

  The “inter-annular bump area” refers to an area where the annular bump electrode (or bump electrode forming land) provided around the internal bump arrangement area is not provided on the back surface of the interposer.

  On the other hand, the “annular external bump arrangement region” refers to a portion where a large number of bump electrodes (or bump electrode formation lands) provided outside the inter-annular bump region are densely arranged on the back surface of the interposer. .

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

  In addition, in the present application, the description of each part directly displayed on a drawing is valid only for that drawing in principle.

1. Description of device structure (basic structure: bulk etchback rectangular ring) in the semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 1 to 6)
In the following, regarding the BGA which is a main specific example of the present application, the arrangement of the external bump electrodes is composed of a rectangular internal bump arrangement area and a rectangular ring-shaped external bump arrangement area (annular external bump arrangement area) around it. A specific example will be described by taking an example. However, it goes without saying that the following example can also be applied to a full array type (full spread type) BGA. Needless to say, the annular outer bump arrangement region may be single or multiple.

  Regarding the structure of the interposer (organic multilayer wiring board), here, a core board having double-sided wiring and a four-layer buildup board having one build-up wiring layered on both sides are taken as an example. As described above, the organic multilayer wiring board is not limited to this type. For example, the core substrate may have three or more wiring layers, and the double-sided build-up wiring may be multi-layered. Further, it may be a two-layer wiring substrate (multilayer wiring substrate) having only a core substrate having double-sided wiring.

  In this example, the back surface of the semiconductor chip is directly mounted on the surface of the interposer (organic wiring board) via the adhesive layer. However, the bump electrode on the surface (device surface) of the semiconductor chip is described. Needless to say, it may be mounted on the surface of the organic wiring board (flip chip method).

  Furthermore, in this example, a specific description will be given mainly by taking a laminated chip structure as an example, but a single-layer chip structure (flat placement structure) may be adopted as will be described with reference to FIGS. Needless to say.

  FIG. 1 is a simplified device overall cross-sectional view for explaining a device structure (basic structure: bulk etchback rectangular ring) and the like in a semiconductor integrated circuit device according to an embodiment of the present application. 2 is a plan view of the entire back surface of the device shown in FIG. 1 (in order to ensure visibility, wiring on the back surface, bump electrodes, etc., spacers on the front surface side, uppermost semiconductor chip, etc. are not shown. The same applies to FIG. 3 supplements FIG. 2 and is a plan view of the entire back surface for explaining the planar positional relationship between the lower-layer semiconductor chip, the etch-back rectangular ring, and the like, the spacer, the uppermost semiconductor chip, and the like. FIG. 4 supplements FIG. 2 and is a plan view of the entire back surface for explaining the planar positional relationship between the lower-layer semiconductor chip, the etch-back rectangular ring, and the like, and the arrangement of bump electrodes on the back surface of the organic wiring board. . FIG. 5 is an enlarged plan view of the back surface of the bulk non-groove periphery cutting region R1 of FIG. 2 (bump electrodes and the like are not shown in order to ensure visibility). FIG. 6 is an enlarged cross-sectional view of a portion substantially corresponding to the partial cross-sectional cutout region R2 of FIG. Based on these, a device structure (basic structure: bulk etchback rectangular ring) and the like in the semiconductor integrated circuit device of one embodiment of the present application will be described.

  First, an outline of the entire cross section of the device is shown in FIG. As shown in FIG. 1, the main part of the interposer 1 (organic wiring board) is constituted by a core board part 1s such as a glass epoxy board, and is disposed on the back surface 1r side of the core board part 1s (organic wiring board). Are provided with a back surface wiring 44 made of, for example, a copper metal film and the like, and a bump land 12 (Bump Land) in the same layer as the back surface wiring 44. The back surface 1r of the core substrate portion 1s and the copper metal film are almost covered with a solder resist film 4r, and an etch back groove is formed in the solder resist film 4r in the inner region of the interposer 1. 9 is provided. The etch-back groove 9 is a part of the etch-back rectangular ring 10, and the cross-sectional portion is the groove portion 15. On the bump land 12, for example, a bump electrode 8 such as a solder bump made of lead-free solder is attached. In this example, the opening form of the solder resist film 4r on the back surface 1r is an SMD (Solder-Mask Defined) system. This is because the bump pitch on the back surface is relatively large. Needless to say, an NSMD (Non-Solder-Mask Defined) method may be used.

  On the other hand, on the surface 1f side of the core substrate portion 1s, for example, a bonding finger 11 (bonding finger) of the same layer as the surface wiring 41 (for example, FIG. 6) made of a copper metal film or the like is provided. The surface 1f of 1s is covered with a solder resist film 4f except for openings and the like. Note that the opening form of the solder resist film 4f on the surface 1f is an NSMD (Non-Solder-Mask Defined) system in this example. This is because the finger pitch at the surface is relatively small. Needless to say, an SMD (Solder-Mask Defined) method may be used.

  On the front surface 1f of the interposer 1, a semiconductor chip 2x (first semiconductor chip) is mounted, for example, via its back surface 2r (second main surface), and its front surface 2f (first main surface). On the device surface, for example, a large number of bonding pads 5 mainly composed of an aluminum-based metal film or the like are provided. The semiconductor chip 2x is, for example, a microcomputer chip (or logic chip) including a CPU (Central Processing Unit) circuit or the like (of course, it may be a chip having other functions). Needless to say, the metal film constituting the bonding pad 5 is not limited to aluminum, but may be copper, tungsten, gold, titanium, silver, palladium, or the like. The bonding pads 5 and the bonding fingers 11 are interconnected by, for example, ball and wedge bonding using a copper wire (copper wire). The bonding wire 6 such as a copper wire has an advantage that the material cost is significantly lower than that of gold or the like. Needless to say, the bonding wire 6 may be made of gold, silver, palladium, or the like in addition to copper.

  A spacer 3 or another semiconductor chip (that is, a second semiconductor chip) is mounted on the semiconductor chip 2x, and another semiconductor chip 2y is further mounted on the spacer 3 or the like. The semiconductor chip 2y is a memory chip such as a DDR-SDRAM (Double Data Rate Synchronous DRAM) (of course, it may be a chip having other functions). The surface 1f of the interposer 1 (organic wiring board) has a resin sealing body 7 made of, for example, an epoxy sealing resin so as to cover the semiconductor chip 2y, the bonding wire 6, and the semiconductor chip 2y and the bonding wire 6. It is sealed by.

  Next, the entire back surface of the device is simplified with the etch-back rectangular ring 10 as the center, and shown in FIG. 2 (the position of the chip or the like on the front surface 1f side is indicated by a one-dot chain line or the like). As shown in FIG. 2, in this example, a semiconductor chip 2x is arranged in the same orientation at the center of the surface 1f of an interposer 1 (organic wiring board) having a substantially square rectangle. Here, “the same orientation” means that each side of the interposer 1 and a corresponding side of the chip (or the etch-back rectangular ring 10) are substantially parallel. In the etch-back rectangular ring 10, the upper and lower transverse sides 18g and 18h each cross the semiconductor chip 2x, and the other pair of sides are outside the semiconductor chip 2x. In this example, the external portion is composed of each single bulk groove portion 15b (groove portion 15). Here, in this example, the interposer 1 and the etch-back rectangular ring 10 are arranged in the same orientation. That is, the substrate end sides 17g and 17h of the interposer 1 are substantially parallel to the transverse sides 18g and 18h of the etch-back rectangular ring 10, respectively. Such a stacked structure using spacers or other semiconductor chips is effective in reducing the package area. Although there are two transverse sides in this example, it goes without saying that, for example, as shown in FIG.

  The transverse side 18g is composed of a bulk groove portion 15b (groove portion 15) on both sides and a bulk non-groove portion 16b, that is, a non-groove portion 16 (first non-groove portion) at a substantially central portion, and a pair of intersecting portions 28 near both ends. In this example, the etch-back rectangular ring 10 at the intersection 28 near both ends of the transverse side 18g is a part of the bulk groove 15b. The fact that the crossing portion and the vicinity thereof are the groove portions is disadvantageous in terms of stress concentration, but the layout of the etch-back rectangular ring 10 is relatively easy. Further, the provision of the non-groove portion inside the transverse portion relieves stress at that portion and is effective in preventing chip cracks. In this example, the crossing portion has a straight line shape, and the stress tends to concentrate, but there is an advantage that the width of the etch-back rectangular ring 10 in the portion can be reduced.

  On the other hand, the transverse side 18h is composed of both ends and a bulk groove portion 15b (groove portion 15) at a substantially central portion and a plurality of bulk non-groove portions 16b between them, that is, a non-groove portion 16 (first non-groove portion). Yes. Similarly to the above, in this example, the etch-back rectangular ring 10 at the intersection 28 near both ends of the transverse side 18h is a part of the bulk groove 15b. As described above, the etch-back rectangular ring 10 mainly composed of the bulk groove portion 15b and the bulk non-groove portion 16b is particularly referred to as a bulk-like etch-back rectangular ring 10b.

  Like the crossing side 18g and the crossing side 18h, the non-grooved portion 16 (first non-grooved portion) is provided in the central portion of each crossing portion or in the vicinity thereof. It is advantageous in that it can be subdivided efficiently.

  Next, the same part as FIG. 2 will be described with reference to still another drawing (FIG. 3). As shown in FIG. 3, on the surface 2f of the semiconductor chip 2x, for example, a large number of bonding pads 5 are arranged along the edges 2g and 2h. Although the bonding pads 5 are usually arranged along the other two sides of the semiconductor chip, the display thereof is omitted here (of course, the bonding pads 5 may be arranged along only two specific sides). Needless to say good things). A spacer 3 or the like is mounted on the surface 2f of the semiconductor chip 2x, and its end sides 3g and 3h (first end side) and the like are crossing sides 18g and 18h (crossing portions) of the etch-back rectangular ring 10, respectively. 29) and is arranged along these. “Proximity” in this case means that the orthogonal projection of the edge of the spacer onto the back surface of the interposer falls into the etch-back groove.

  Such an arrangement is a more severe situation from the viewpoint of stress on the semiconductor chip 2x, but there is a high possibility of such a layout for convenience of stacking and the like. The necessity of providing the non-groove portion 16 (first non-groove portion) in the transverse portion 29 of the etch-back rectangular ring 10 is increased. A semiconductor chip 2y is mounted on the spacer 3 and the like, and a large number of bonding pads 5 are arranged on the surface thereof. A large number of bonding pads 5 on the semiconductor chips 2x and 2y are connected to each other by a bonding wire 6 and a large number of bonding fingers 11 (FIG. 6) provided in bonding finger portion openings 35 provided on the surface 1f of the interposer 1. They are connected (bonding wires and fingers are not shown here).

  Next, in order to clarify the relationship with the bump electrode layout 8, the same parts as those in FIGS. 2 and 3 are shown in FIG. As shown in FIG. 4, in this example, the etch-back rectangular ring 10 has bumps 8 or bump lands 12 densely arranged in a matrix on the back surface 1r of the interposer 1 (organic wiring board). The bumps 8 or the bump lands 12 provided between the inner bump arrangement area 21 and the annular outer bump arrangement area 23 are provided in the annular bump area 22. Note that a relatively small number of bumps 8 or bump lands 12 may be exceptionally provided in the annular inter-bump region 22. Providing the etch-back rectangular ring in the area between the annular bumps in a plan view has an advantage that a space can be easily taken, unlike a portion where other bump lands are concentrated.

  Next, FIG. 5 shows an enlarged view of the bulk non-groove periphery cutting region R1 in FIG. As shown in FIG. 5, a bump land opening 20 is provided on the bump land 12, and an electrolytic plating film 19 is formed on the bump land 12 in the bump land opening 20 portion. The electrolytic plating film 19 is composed of, for example, a lower layer (inner side) nickel film and an upper layer (outer side) gold film. The gold film is an antioxidant film or a bonding metal, and the nickel film is a barrier metal film between the copper film and the gold film of the bump land body. Each bump land 12 is integrally connected to a blind via peripheral land 14, and a blind via 24 is provided inside the blind via peripheral land 14. The blind via peripheral land 14 is connected integrally with the back surface wiring 44 for connection to the plating common line 25 (FIG. 12). The back surface wiring 44 reaches the edge of the etch-back groove 9 (bulk groove portion 15b, that is, the groove portion 15). The back surface wiring 44 for connecting to the plating common line 25 may be connected to the bump land 12. In the etch-back groove 9, the plating common line (FIG. 12) is removed to form a portion 25z (dotted line portion) from which the common plating line is removed. The single bulk groove portion 15b is a continuous etch-back groove 9, and a continuous non-groove portion (first non-groove portion) 16, that is, a bulk non-groove portion 16b, is formed between the pair of bulk groove portions 15b. Yes. The ends of the bulk non-groove portion 16b and the pair of bulk groove portions 15b at both ends thereof are portions 40 having no plated wire, and the portions other than the bump land opening 20 and the etch back groove 9 are covered with the solder resist film 4r. It is the part 4c which is doing. Here, the groove width GW of the etch-back groove 9 can be exemplified as a preferable value of about 180 micrometers, for example.

  Next, FIG. 6 shows a part corresponding to the partial cutout region R2 in FIG. 1 and the A-A ′ cross section in FIG. Here, for example, the detailed structure of the core substrate portion 1s of the interposer 1 of FIG. 1 is shown. As shown in FIG. 6, the core substrate portion 1 s has a glass epoxy core substrate 30 at the center and an embedded through via 32 embedded therein. Then, on the surface 1f side of the glass epoxy core substrate 30, a second layer wiring 42 made of a metal film such as a copper film, a second layer through via peripheral land 36 each made of the same metal film, Second-layer blind via peripheral lands 38 and the like are formed, and these upper layers are covered with a surface buildup insulating film 31f (for example, an epoxy organic insulating film) that is also a part of the surface side buildup layer. .

  On the other hand, on the back surface 1r side of the glass epoxy core substrate 30, a third layer wiring 43 made of a metal film such as a copper film, a third layer through via peripheral land 37 each made of the same metal film, Third-layer blind via peripheral lands 39 and the like are formed, and these upper layers are covered with a back surface buildup insulating film 31r (for example, an epoxy organic insulating film) that is also a part of the back surface side buildup layer. .

  On the surface buildup insulating film 31f, a surface wiring 41 made of a metal film such as a copper film, a bonding finger 11 made of the same metal film, a surface blind via peripheral land 45, etc. are formed. Portions other than the bonding finger 11 and its periphery are covered with a solder resist film 4f. In this example, the blind via in the portion of the surface blind via peripheral land 45 is composed of a metal film in the same layer as the surface wiring 41. An electrolytic plating film 19 is formed on the bonding finger 11.

  On the other hand, on the backside build-up insulating film 31r, a backside wiring 44 made of a metal film such as a copper film, a bump land 12 made of a metal film of the same layer, a backside blind via peripheral land 14 and the like are formed. These upper layers are covered with the solder resist film 4r except for the portions where the etch-back grooves 9 and the bump electrodes 8 are formed. In this example, the blind via 24 in the portion of the rear blind via peripheral land 14 is composed of a metal film in the same layer as the rear wiring 44. An electrolytic plating film 19 is formed on the bump land 12.

  A semiconductor chip 2x is mounted on the surface 1f of the interposer 1 (organic wiring board) and on the solder resist film 4f via an adhesive film 26 such as a silver paste film 26g. A bonding pad 5 is provided on 2f (first main surface). The bonding pads 5 and the bonding fingers 11 are connected to each other by bonding wires 6, and an adhesive film 26 (26d) such as DAF (Die Attach Film) is provided on the device surface 2f of the semiconductor chip 2x. A spacer 3 or the like is mounted via the. Further, another semiconductor chip 2y is similarly mounted on the spacer 3 or the like via an adhesive film 26 such as DAF (26d). A resin sealing body 7 is formed on the surface 1f of the interposer 1 so as to cover the semiconductor chips 2x and 2y, the spacers 3 and the like, the bonding wires 6, the bonding fingers 11 and their periphery, the solder resist film 4f and the like. Such a combination of normal die bonding (not flip chip bonding) and wire bonding with an adhesive film is effective in reducing costs. On the other hand, since the adhesive film under the chip is considerably thinner than the thickness of the underfill at the time of flip chip bonding, it is considered that the adhesive film is easily affected by the deformation of the interposer.

  As the adhesive film 26, a silver paste film (conductive adhesive film such as a coated epoxy adhesive film containing a silver filler) having good wettability, coating properties, thixotropy, and the like is suitable. However, if sufficient insulation of the chip is desired, an insulating adhesive film (adhesive sheet such as DAF, coated epoxy adhesive film containing silica powder, etc.) may be used. Compared with DAF, the coating adhesive film has an advantage in terms of material unit price, and a sheet-like adhesive film such as DAF has an advantage that chip cracks are relatively difficult to occur. Needless to say, the bonding of each chip may be a coated adhesive film or an adhesive sheet such as DAF.

  Here, in order to show the structure of the embodiment more specifically, an example of the dimensions and the like of the main part is shown below. That is, with reference to FIG. 6 and the like, the thickness of the semiconductor chip 2x (first semiconductor chip) is, for example, about 70 micrometers (a preferable range is 100 micrometers or less and 5 micrometers or more). Needless to say, the thickness of the chip may exceed 100 micrometers (the upper limit for general use is, for example, about 200 micrometers). The thickness of the interposer 1 is, for example, about 250 micrometers in length (as a general-purpose range, about 200 to 300 micrometers), and the package thickness is, for example, about 1 to 2 millimeters. The thickness of the spacer 3 is, for example, about 50 micrometers (a general-purpose range is about 30 to 70 micrometers), and the thickness of the other semiconductor chip 2y is, for example, about 50 micrometers (generally used). The range is about 30 to 70 micrometers. The mold thickness is, for example, about 750 micrometers (as a general-purpose range, about 500 to 1000 micrometers), and the thickness of the silver paste film 26g is, for example, about 30 micrometers (as a general-purpose range) Is about 20 to 40 micrometers). The thickness of the DAF (26d) is, for example, about 20 micrometers (as a general-purpose range, about 10 to 30 micrometers). The thickness of the nickel film of the electrolytic plating film 19 is, for example, about 3 micrometers (as a general-purpose range, about 2 to 5 micrometers), and the thickness of the gold film is, for example, 0.5 micrometers. It is about (as a general-purpose range, about 0.3 to 0.7 micrometers). The thickness of the glass epoxy core substrate 30 is, for example, about 60 micrometers (as a general-purpose range, about 40 to 80 micrometers) (the glass transition temperature is, for example, about 165 degrees Celsius). The thickness of the build-up insulating films 31f and 31r is, for example, about 40 micrometers (as a general-purpose range, about 30 to 50 micrometers) (the glass transition temperature is, for example, about 156 degrees Celsius). The thickness of the solder resist films 4f and 4r is, for example, about 25 micrometers (as a widely used range, about 20 to 30 micrometers). The thickness of the front surface wiring 41 and the back surface wiring 44 is, for example, about 10 micrometers (as a general-purpose range, about 7 to 15 micrometers). The thicknesses of the second layer wiring 42 and the third layer wiring 43 are, for example, about 22 micrometers (as a general-purpose range, about 15 to 30 micrometers). The diameter of the blind via 24 is, for example, about 80 micrometers (a general-purpose range is about 60 to 100 micrometers). The diameter of the buried through via 32 is, for example, about 100 micrometers (as a general-purpose range, about 90 to 150 micrometers).

  Next, with reference to FIG. 5 and the like, the groove width GW of the etch-back groove 10 is, for example, about 180 micrometers (a preferable range is, for example, about 150 to 210 micrometers). The length of the groove of the bulk non-groove portion 16b is, for example, about 600 micrometers (preferably, for example, about 360 to 2000 micrometers). In particular, a length of 5 times or more the width (for example, a length of about 900 micrometers or more) is called a “long & bulk non-groove portion”, which is considered to have a particularly great effect of stress relaxation. The width of the wiring or the common plating line is, for example, about 50 micrometers (a preferable range is, for example, about 25 to 75 micrometers). The pitch of the bump lands 12 is, for example, about 500 micrometers (preferably, for example, about 300 to 700 micrometers). The diameter of the bump land 12 is, for example, about 400 micrometers (preferably, for example, about 300 to 500 micrometers).

  2 and FIG. 3, the planar dimensions of the semiconductor chip 2x are, for example, about 7.1 millimeters in length (as a general range, about 4 to 10 millimeters), and about 4.2 millimeters in width ( A general range is about 4 to 10 millimeters). The planar dimension of the interposer 1 is, for example, about 12 millimeters in length and width (as a general-purpose range, about 10 to 15 millimeters, as shown in FIG. 30, it is not limited to a square but may be a rectangle). . The planar dimensions of the semiconductor chip 2y are, for example, about 6.4 millimeters in length (about 5 to 12 millimeters as a general range) and about 6.9 millimeters in width (5 to 12 as a general range). Mm). The planar dimensions of the spacer 3 are, for example, about 5.3 millimeters in length (as a general-purpose range, about 3 to 12 millimeters) and about 3.9 millimeters in width (as a general-purpose range, 3 to 12 millimeters). Degree). The planar dimensions of the etch-back rectangular ring 10 are, for example, about 5.7 millimeters in length (as a general-purpose range, about 4 to 10 millimeters) and about 5.2 millimeters in width (as a general-purpose range, 4 millimeters). To about 10 millimeters). The length of the bulk non-groove portion 16b of the transverse side 18g is, for example, about 800 micrometers (preferably, for example, about 600 to 2000 micrometers). The length of each bulk non-groove portion 16b on the transverse side 18h is, for example, about 500 micrometers (preferably, for example, about 360 to 700 micrometers). The length of the intermediate bulk groove 15b in the transverse side 18h is, for example, about 1500 micrometers (a preferable range is, for example, about 1000 to 2000 micrometers).

  Next, referring to FIG. 4, the width of the annular inter-bump region 22 is, for example, about 1100 micrometers (preferably, for example, about 700 to 1500 micrometers).

2. Description of the substrate process in the manufacturing method relating to the semiconductor integrated circuit device of the embodiment of the present application (mainly FIGS. 7 to 15)
In this section, an example of a main part of a manufacturing process of a multilayer wiring board corresponding to the structure of section 1 will be described. It goes without saying that the process described in this section is an example of a manufacturing process of a multilayer wiring board and can be variously modified.

  In the following, the semi-additive method will be specifically described as an example, but it goes without saying that the manufacturing process may be a subtractive method or an additive method in addition to the semi-additive method.

  FIG. 7 is a process block flow diagram for explaining a substrate process in the manufacturing method related to the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 8 is a plan view of the entire back surface of the organic wiring panel 61 for explaining the arrangement of the plating lines at the time when the front and back solder resist film formation & patterning step 103 is completed. FIG. 9 is a plan view of the entire back surface of the organic wiring sheet 62 of FIG. 8 for explaining the arrangement of the plated wires. FIG. 10 is a plan view of the entire back surface of the organic wiring unit substrate 63 of FIG. 9 for explaining the arrangement of the plated wires. FIG. 11 is an overall rear enlarged plan view showing bump lands and related wirings in the portion of the substrate corner cutout region R3 of FIG. FIG. 12 is an enlarged plan view of the back surface of the bulk non-groove periphery cutting region R1 of FIG. 10 (when the front and back solder resist film formation & patterning step 103 is completed). FIG. 13 is an enlarged plan view of the back surface of the bulk non-groove periphery cutting region R1 of FIG. 10 (at the time of completion of the pad electroplating step 104). FIG. 14 is a plan view of the entire back surface of the organic wiring unit substrate 63 corresponding to FIG. 10 in the plating line removing step 105 (etch back step). 15 is an enlarged plan view of the back surface corresponding to FIG. 14 of the cut-out region R1 around the bulk non-groove part of FIG. 10 (when the etch-back process 105 is completed). Based on these, the substrate process in the manufacturing method related to the semiconductor integrated circuit device of the one embodiment of the present application will be described.

  First, as shown in FIG. 7, through-vias, second-layer wiring, third-layer wiring, and the like are patterned on a glass epoxy core substrate 30 (for example, see FIG. 6, the same applies hereinafter), and build-up is performed on both surfaces thereof. An organic panel in which an insulating film is formed and a laser via or the like is provided in a necessary portion thereof is prepared (panel preparation step 101). Next, for example, patterning of the front surface wiring and the back surface wiring (including embedding of blind vias) is performed by a semi-additive method (front and back metal pattern processing step 102). This patterning may be performed by, for example, a subtractive method or an additive method.

  FIG. 8 shows the entire back surface layout focusing on the plating lines of the organic panel 61 when the front and back metal pattern processing step 102 is completed. As shown in FIG. 8, a plurality of sheet regions 62 are provided in a matrix on the organic panel 61, and the periphery thereof is composed of a metal film in the same layer as the back surface wiring 44 (FIG. 6). A rectangular annular panel outer peripheral plating wire 64 is provided. The panel outer peripheral plating wire 64 is similarly provided on the outer peripheral portion of each sheet region 62 via the panel outer peripheral sheet outer peripheral connection line 66 formed of the same metal film. It is connected to a sheet outer peripheral plating wire 65 composed of a layer metal film.

  Next, the detailed common plating wire structure of the sheet | seat area | region 62 of FIG. 8 is shown in FIG. As shown in FIG. 9, each unit substrate region 63 inside the sheet outer peripheral plating line 65 is partitioned by a grid-like unit substrate outer peripheral plating wire 67 made of the same layer metal film. Both are connected to the sheet outer peripheral plating line 65 via the sheet outer peripheral unit substrate outer peripheral connection line 68 made of the same metal film.

  Next, FIG. 10 shows a detailed common plating line structure of the unit substrate region 63 of FIG. As shown in FIG. 10, a rectangular annular unit substrate outer peripheral plating line 67 made of a metal film in the same layer as the back surface wiring 44 (FIG. 6) is provided in the periphery of the unit substrate region 63. In the central portion of the unit substrate region 63, a substantially annular inner ring plating wire 70 is provided which is made of a metal film in the same layer as the unit substrate outer peripheral plating wire 67. In this case, the ring shape is not a closed ring, and there is a portion 40 (corresponding to the bulk non-groove portion 16b in FIG. 2) which is not a closed ring, and is geometrically separated in some places. However, each part of the inner ring plating wire 70 is electrically connected to the unit substrate outer peripheral plating line 67 by an inner / outer connection plating wire 69 made of a metal film in the same layer as the unit substrate outer peripheral plating wire 67. The inner / outer connection plating wire 69 is connected to the inner ring plating wire 70 and the unit substrate outer periphery plating wire 67 via at least one of the back surface wiring 44, the blind via peripheral land 14, and the bump land 12 (FIG. 5). It may be electrically connected. Alternatively, the internal ring plating wire 70 and the unit substrate outer peripheral plating wire (not shown) made of a metal film formed in another layer are electrically connected via one or more of the blind via 24 and the through via 32. You may connect. In particular, the inner / outer connection plating wire 69 is connected via a bonding finger 11 (FIG. 6) to a unit substrate outer peripheral plating wire (not shown) made of a metal film formed in the same layer as the bonding finger 11 (FIG. 6). The formation region of can be reduced. Note that the inner ring plated wire 70 may be closed at this point if necessary.

  Next, FIG. 11 shows an overall plan view of the back surface corresponding to FIG. 10 illustrating in more detail the state of actual wiring and the like in the substrate corner cutout region R3 of FIG. As shown in FIG. 11, a large number of bump lands 12 are arranged in a matrix, and each bump land 12 around the unit substrate region 63 is individually separated from the unit substrate outer peripheral plating line 67 via the back surface wiring 44, for example. It is connected to the. On the other hand, each bump land 12 inside is individually connected to the internal ring plating wire 70 via the back surface wiring 44, for example. Of the internal ring plating line 70, the part indicated by the thick dotted line is the part 40 without the plating line, and the part indicated by the two-dot chain line is etched in the plating line removing step 105 (see FIG. 15) in FIG. This is the portion 27 where the plated wire and the solder resist film are to be removed by the back. That is, in the plated line removal step 105 of FIG. 7, the etch-back groove 9 (bulk groove portion 15b) is formed in this portion, and the portion 40 without the plated wire becomes the bulk non-groove portion 16b.

  Next, FIG. 12 shows the bulk non-groove peripheral cutout region R1 (corresponding to FIG. 5) in FIG. 10 when the front and back solder resist film formation & patterning step 103 in FIG. 7 is completed. As shown in FIG. 12, solder resist films 4f and 4r are formed on both surfaces of the panel 61 and patterned to form, for example, bump land openings 20 (front and back solder resist film formation & patterning step 103 in FIG. 11). ). At this stage, each bump land 12 drawn here is connected to the common plating line 25 which is a part of the internal ring plating line 70 through the back blind via peripheral land 14 and the back wiring 44.

  Next, as shown in FIG. 13, an electrolytic plating film 19 is formed on the bump land opening 20 and the like (for example, the bonding finger 11 on the surface of the panel 61) by electrolytic plating (FIG. 11). Pad plating process 104). The electrolytic plating is performed by supplying a current from, for example, the panel outer peripheral plating wire 64 of FIG. As the electrolytic plating film 19, a laminated film composed of, for example, a nickel film and a gold film can be exemplified from the side close to the copper-based metal film.

  Next, as shown in FIGS. 14 and 15, first, the etch-back of the solder resist films 4f and 4r is performed. On the back surface of the panel 61, there is a portion where the unit substrate outer peripheral plating line 67 (FIG. 10) is present. The etch-back grooves 9 (unit substrate outer peripheral plating line etch-back grooves 71) are formed along the inner ring plating lines 70, and the etch-back grooves 9 are formed along the portions where the internal ring plating lines 70 are present. Further, in that state, copper wet etching is performed to remove the copper wiring in each etch-back groove 9. Thereby, each bulk groove part 15b (15) and each bulk non-groove part 16b (16) are formed. These processes are usually executed on the surface of the panel 61 in consideration of efficiency, but may be executed separately as necessary.

  Next, as shown in FIG. 7, a continuity and short circuit test of the wiring of the panel 61 is performed (electrical test step 106). This is because, in the above process, since the common plating line and the like are removed, the individual bump lands 12 and the like are in a state independent of each other in direct current, so that a continuity test and a short-circuit test are possible. Because it becomes.

  Next, as shown in FIG. 7, the panel 61 is divided into sheets 62 (sheet dividing step 107), and, for example, the process proceeds to the next semiconductor chip mounting step 111 (FIG. 16).

3. Description of assembly process in manufacturing method related to semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 16 to 19)
In this section, an example of a main part of the assembly process of the semiconductor integrated circuit device corresponding to the structure of section 1 will be described. Needless to say, the process described in this section is an example of an assembly process of a semiconductor integrated circuit device and can be variously modified.

  Here, silicon is exemplified as an example of the semiconductor, but it goes without saying that germanium-based and compound semiconductors (SiGe, GaN, SiC, InP, GaAs) may be used in addition to the silicon-based semiconductor.

  Here, the example in which the organic wiring sheet 62 (FIG. 9) is transported and assembled is specifically described, but it goes without saying that the unit may be transported and assembled in units of the unit substrate 63 (FIG. 9). However, the unit of the sheet 62 (FIG. 9) is more efficient and easy to handle.

  In the following description, a MAP (Mold Array Packaging) method in which the entire sheet is sealed in a lump and then divided by package dicing or the like will be described as an example, but it goes without saying that an individual sealing method may be used.

  FIG. 16 is a process block flow diagram for explaining an assembly process in the manufacturing method related to the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 17 is a simplified device overall cross-sectional view (unit substrate 63 of the organic wiring sheet 62) corresponding to FIG. 1 in the middle of the wire bonding step 112. FIG. 18 is a simplified cross-sectional view of the entire device corresponding to FIG. 1 (in the middle of the resin sealing step 113). FIG. 19 is a simplified cross-sectional view of the entire device (bump electrode attaching step 114) corresponding to FIG. Based on these, the assembly process in the manufacturing method related to the semiconductor integrated circuit device of the one embodiment of the present application will be described.

  As shown in FIG. 16, for example, a silver paste is applied to each unit substrate region 63 on the surface of the sheet 62, and a semiconductor chip 2x (first semiconductor chip) is chip-bonded through the silver paste (semiconductor chip mounting). Step 111).

  Next, as shown in FIG. 17, for example, a sheet 62 is set on the wire bonding stage 91 of the wire bonding apparatus, and wire bonding is executed by, for example, a capillary 92 (bonding tool) (wire bonding in FIG. 16). Step 112). In this example, the wire 6 to be used is, for example, a copper wire (for example, pure copper having a purity of 99.99% by weight or more), and the bonding method is, for example, thermosonic bonding. Is, for example, Ball & Wedge Bonding. In addition to the capillary, a wedge may be used as the bonding tool, and the bonding method may be thermocompression bonding or thermosonic bonding or ultrasonic bonding in addition to thermosonic bonding. As for the material of the wire, a copper wire is advantageous from the viewpoint of the unit price of the material, but a gold wire, a palladium wire, etc. are advantageous from the viewpoint of reducing damage to the chip. In addition, as a wire, an aluminum-type wire, a silver-type wire, etc. are applicable. In this example, the bonding pad 5 side is a ball bonding and the bonding finger 11 side is a forward bonding with a wedge bonding, but the bonding pad 5 side is a wedge bonding and the bonding finger 11 side is a ball bonding. Direction bonding may also be used. When the wire bonding of the semiconductor chip 2x is completed, the spacer 3 is further mounted on the device surface 2f (first main surface) of the semiconductor chip 2x via a DAF or the like, for example. In addition, instead of a sheet-based adhesive film such as DAF, a coating-based adhesive film may be used in the same manner as described above. Next, another semiconductor chip 2y is mounted on the spacer 3 via a DAF or the like, for example. In addition, instead of a sheet-based adhesive film such as DAF, a coating-based adhesive film may be used in the same manner as described above. Thereafter, wire bonding or the like is performed on the semiconductor chip 2y as necessary.

  Next, as shown in FIG. 18, for example, the sheet 62 is set between the lower mold 93 and the upper mold 94 (mold cavity) of the molding apparatus, and is sealed with a resin mold by, for example, transfer mold. Stop process 113 (FIG. 16) is executed. In the transfer mold, the resin sealing body 7 is formed by applying a high resin injection pressure 95 to the molten sealing resin and filling the mold cavity with the sealing resin. As a sealing method, a compression mold may be used in addition to the transfer mold. In general, the transfer mold is advantageous for mass production, and the compression mold is advantageous for production of a smaller amount.

  Next, as shown in FIG. 19, for example, the bump electrode 8 is attached onto the bump land 12 on the back surface of the sheet 62 (bump electrode attaching step 114 in FIG. 16). As the bump electrode 8, for example, a solder bump electrode such as a lead-free solder bump electrode is suitable, but it goes without saying that it may be a gold bump electrode, a copper bump electrode, or another bump electrode.

  Next, as shown in FIG. 16, through a device dividing step 115 (for example, by package dicing), the sheet 62 is divided into individual unit substrates 63 to form a final device as shown in FIG.

4). Description of modification examples (spacer edge non-proximity layout) regarding etch back ring and spacer position in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application (mainly FIG. 20)
In this section, a modification of the portion of FIG. 3 in the device structure of section 1 will be described. Therefore, the following description relates to the modified example of FIG. 3, and the descriptions in sections 1 to 3 are basically applied as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  FIG. 20 shows the entire back surface corresponding to FIG. 3 for explaining a modification (spacer edge non-proximity layout) and the like related to the position of the etch back ring and spacer in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a top view. Based on this, a modified example (spacer edge non-proximity layout) and the like regarding the position of the etch back ring and the spacer in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  In the example of section 1, as shown in FIGS. 1, 3, and 6, there is a spacer 3 (or a second semiconductor chip) on a semiconductor chip 2x (first semiconductor chip), and at least one end thereof. The sides 3g and 3h (first end sides) are arranged above or in the vicinity of the crossing portion 29 (or the crossing sides 18g and 18h) adjacent thereto. Therefore, although the layout is easy, the stress applied to the semiconductor chip 2x tends to concentrate on the orthogonal projection portion of the etch-back groove 9 onto the semiconductor chip 2x (between the one-dot chain line in FIGS. 1 and 6).

  Therefore, in the example of FIG. 20, at least one end side 3g, 3h of the spacer 3 or the like is prevented from being close to the transverse portion 29 (or the transverse sides 18g, 18h). Here, “not to be close” specifically means that at least one edge 3g, 3h of the spacer 3 or the like does not enter the orthogonal projection portion of the etch-back groove 9 to the semiconductor chip 2x (non-null). Proximity condition). Note that this non-proximity layout is particularly suitable for laying out so as to satisfy the non-proximity condition for both the pair of end sides 3g and 3h such as the spacer 3, but only one of them satisfies the non-proximity condition. Even if it is laid out like this, it is effective. This is because in semiconductor technology, there are some cases where cracks are difficult to occur in a specific part for various reasons.

5. Description of Modification (Chip Edge Crossover Non-Groove Etch Backring) etc. Regarding Etch Buckling Crossing Crossing Ends (Cross Portion) in Device Structure of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIG. 21)
In this section, a modification of the device structure of section 1 relating to the crossover portion 28 of FIG. 2 will be described. Therefore, the following description relates to the modification of FIG. 2, and the descriptions in sections 1 to 4 basically apply as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  FIG. 21 is a view for explaining a modified example (chip end crossing non-groove etch back ring) regarding both ends (crossing portions) of the etch back ring crossing portion in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 3 is a plan view of the entire back surface corresponding to FIG. 2. Based on this, a modified example (chip end crossing non-groove etch back ring) regarding both ends (crossing portions) of the etch back ring crossing portion in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application will be described. .

  In the example of FIG. 2, the etch-back rectangular ring 10 is a bulk groove portion 15 b at the intersection 28. In such a layout, the layout of the etch-back rectangular ring 10 is easy, but the stress tends to concentrate on the end of the semiconductor chip 2x. When stress is concentrated on the end of the chip, chip cracks are particularly likely to occur. For this reason, in the example of FIG. 21, the etch-back rectangular ring 10 in each crossing portion 28 is locally (or globally) a non-groove portion, that is, the crossing non-groove portion 16 s. Here, the local non-groove portion corresponds to, for example, a single inter-dot non-groove portion 16d described later, and the global non-groove portion refers to, for example, the bulk non-groove portion 16b and the long & long Corresponds to the non-groove part of the bulk (Long & Bulk).

  In this way, by making the etch-back rectangular ring 10 in each crossing portion 28 a non-groove portion (crossing portion non-groove portion 16s) (by making both end portions of the crossing portion and its vicinity non-groove portions), the stress is reduced to the end of the chip. Concentrating on the department can be eased. This “non-grooving of the crossing portion” is particularly suitable when applied to all the crossing portions 28 from the viewpoint of preventing chip cracks, but a certain effect can be expected when applied to at least one crossing portion 28. This is because in semiconductor technology, a plurality of equivalent places are not equivalent due to a combination of complicated elements, and there are places where problems are unlikely to occur.

  As a specific example of the crossing non-groove portion 16s, a local relatively short non-groove portion as shown in FIG. 21 can be exemplified as a preferable one. This is because the intersection is inevitably close to the corner of the interposer, and the number of allocated bump lands per length of the etch-back rectangular ring is large.

  It is also effective to make the crossing non-groove portion 16s an additional bulk non-groove portion 16b. This is because the length becomes macro and the effect of stress relaxation is great.

  Further, a combination of the inter-dot non-groove portion 16d and the dot-like groove portion 15d described in the next section (not a single unit but used globally. 16d) is also effective. This is because, in the case of the combination of the inter-dot non-groove portion 16d and the dot-like groove portion 15d, it is easy to continuously arrange the plated wires in the portion.

6). Description of Modifications (Dot-like Etch Buckling) etc. Regarding Etch Buckling Overall Structure in Device Structure of Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 22 and 23)
In the example of section 1, a bulk-like etch back ring composed of relatively long and continuous grooves and non-grooves has been described. In this section, a dot-like etch composed of relatively finely divided grooves and non-grooves is described. Buckling will be described. However, these classifications show the bipolar structure of the etch back ring, and it goes without saying that an intermediate structure (see FIGS. 38 and 39) may be applied.

  The following description relates to the modified examples of FIGS. 2 and 5, and the descriptions in sections 1 to 5 are basically applied as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  FIG. 22 is a plan view of the entire back surface corresponding to FIG. 2 for explaining a modification (dot-like etch back ring) and the like related to the overall structure of the etch back ring in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. It is. FIG. 23 is an enlarged plan view of the back surface of the cut-out region R1 around the bulk non-groove part of FIG. 22 (bump electrodes and the like are not shown in order to ensure visibility). Based on this, a modified example (dot-like etch back ring) regarding the entire structure of the etch back ring in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  In sections 1 to 5, the etch-back rectangular ring 10 mainly composed of the bulk groove portion 15b and the bulk non-groove portion 16b, that is, the bulk-like etch-back rectangular ring has been described. On the other hand, in this section, as shown in FIGS. 22 and 23, a dot-like etchback rectangular ring 10d (10) mainly composed of dot-like groove portions 15d and inter-dot non-groove portions 16d will be described. That is, as shown in FIG. 23, the dot-shaped groove portion 15d is composed of an etch-back groove 9 having a relatively short length (groove length GL). On the other hand, the inter-dot non-groove portion 16d is composed of a non-groove portion 16 (inter-dot non-groove portion 16d) having a relatively short length (groove interval GS). Here, “relatively short” is considered based on the width of the etch-back groove 9, that is, the groove width GW. Specifically, as described in the definition, when “dot-like groove portion”, “inter-dot non-groove portion”, etc., the respective lengths, that is, the groove length GL and the groove interval GS are equal to the groove width GW. Indicates less than 2 times. On the other hand, those whose corresponding length is twice or more the groove width GW are referred to as “bulk groove portion” and “bulk non-groove portion”. The practical lower limits of the lengths of the dot-like groove portions and the non-groove portions between the dots, that is, the groove length GL and the groove interval GS are about 60% or more of the groove interval GS in consideration of the width of the common plating line or the like Become.

  Here, in order to show the structure of this example more specifically, an example of the dimensions and the like of the main part is shown below. However, most of the dimensions are basically the same as those described in Section 1, and only the differences will be described here. That is, the groove length GL and the groove interval GS are, for example, about 180 micrometers (preferably, for example, about 100 micrometers or more and less than about 360 micrometers).

  Here, it is necessary to pay attention to the difference in structure between the bulk non-groove portion 16b (for example, FIG. 5) and the inter-dot non-groove portion 16d. That is, as can be seen from FIG. 5, the bulk non-grooved portion 16b normally does not have the common plated line 25, but the interdot non-grooved portion 16d has the common plated line 25 that is cut at both ends. In other words, the dot-like etch-back rectangular ring systematically arranges an integrated ring-shaped common plating line regardless of whether it is a groove or a non-groove before the etch-back process 105 (FIG. 7). It has the merit that can be kept. Needless to say, a common plating line may be disposed in the bulk non-grooved portion of the bulk etch-back rectangular ring as necessary.

7). Description of various modifications relating to etch back ring and semiconductor chip layout in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 24 to 30)
In this section, various modifications relating to etch back ring and semiconductor chip layout in the device structure described in sections 1 and 4 to 6 will be described.

  FIG. 24 is a diagram for explaining a modified example (flat multi-chip type bulk etch-back rectangular ring) relating to etch back ring and semiconductor chip layout in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. FIG. 25 supplements FIG. 24 and is a plan view of the entire back surface for explaining a planar positional relationship between a semiconductor chip, an etch-back rectangular ring, and the like, and an arrangement of bump electrodes on the back surface of the organic wiring board. FIG. 26 is a diagram for explaining a modified example (flat placed multi-chip dot-like etch-back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. FIG. FIG. 27 corresponds to FIG. 2 for explaining a modified example (an oblique chip-oriented bulk etch-back rectangular ring) relating to etch back ring and semiconductor chip layout in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. FIG. FIG. 28 supplements FIG. 27 and is a plan view of the entire back surface for explaining the planar positional relationship between the semiconductor chip, the etch-back rectangular ring, and the like, and the arrangement of bump electrodes on the back surface of the organic wiring board. FIG. 29 is a diagram for explaining a modified example (an oblique chip-oriented dot-like etch-back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a corresponding back surface whole plan view. FIG. 30 shows a semiconductor chip and an etch back for explaining a modified example (rectangular substrate bulk etch back rectangular ring) regarding the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a back surface whole plane view explaining the planar positional relationship of a rectangular ring etc. and the arrangement | sequence etc. of the bump electrode of the back surface of an organic type wiring board. Based on these, various modifications and the like relating to the etch back ring and the layout of the semiconductor chip in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

(1) Flat-mounted multichip bulk etch-back rectangular ring (mainly FIGS. 24 and 25):
The following description relates to the modification of FIG. 2 and FIG. 3, and the descriptions so far in sections 1 to 6 and section 7 are basically applicable as they are. Therefore, in the following, those descriptions will be repeated in principle. Absent.

  In the example of FIGS. 2 and 3, the case where a plurality of semiconductor chips 2x, 2y, etc. are stacked has been described. Here, an example where a plurality of semiconductor chips 2x, 2y are placed flat will be described. As shown in FIG. 24, in this case, there is only one transverse side 18g that causes a crack in the semiconductor chip. Although there are L-shaped overlap portions in the semiconductor chip 2y, since there are portions 46 and 47 contributing to stress relaxation, the possibility of reaching a chip crack due to stress concentration is relatively low. Therefore, in this case, when the bulk-like etchback rectangular ring 10b is used, for example, the bulk non-groove portion 16b is introduced into the central portion of the transverse portion 29 of the transverse side 18g, and both sides thereof are, for example, integral bulk groove portions. It may be 15b. As shown in FIG. 25, in this example as well, the etch-back rectangular ring 10 is in the area 22 between the annular bumps.

(2) A flat multi-chip dot-like etch-back rectangular ring (mainly FIG. 26):
The following description relates to the modification of FIG. 24, and the description up to this point in sections 1 to 6 and section 7 is basically applicable as it is. Therefore, in the following, those descriptions will not be repeated in principle.

  As shown in FIG. 26, in this example, the dot-like etchback rectangular ring 10d shown in FIG. 22 is applied to the flat multi-chip mount shown in FIG. In the flat multi-chip mount, the variation of the chip layout is large, and the layout of the bulk-like etch-back rectangular ring 10b is different on a case-by-case basis, but the dot-like etch-back rectangular ring 10d is relatively easily shared. There is a merit that can be made.

(3) Diagonal chip oriented bulk etchback rectangular ring (mainly FIGS. 27 and 28):
The following description relates to the modification of FIGS. 2 and 4, and the descriptions so far of sections 1 to 6 and section 7 are basically applicable as they are. Therefore, in the following, those descriptions will be repeated in principle. Absent.

  Other than this example, the rectangular interposer 1 (organic wiring board) and the semiconductor chip 2x are mounted with the same orientation (referred to as “normal orientation”), but in this case, as shown in FIG. In this example, the semiconductor chip 2x is inclined by 45 degrees around its central axis. Such oblique chip orientation is particularly noticeable in, for example, flip chip bonding, but is also sometimes performed in “normal chip bonding” performed with an adhesive or the like on the back surface of a normal semiconductor chip. In the case of flip chip bonding, since the thickness of the underfill layer is considerably thicker than the thickness of the adhesive film for normal chip bonding, the possibility of chip cracking is relatively small, but not all. In the case of normal chip bonding, the situation is exactly the same as in other cases.

  As shown in FIG. 28, also in this example, the etch-back rectangular ring 10 is in the area 22 between the annular bumps.

(4) Diagonal chip-oriented dot-like etch-back rectangular ring (mainly FIG. 29):
The following description relates to the modified example of FIG. 27, and the description up to this point of sections 1 to 6 and section 7 is basically applicable as it is. Therefore, in the following, those descriptions will not be repeated in principle.

  As shown in FIG. 29, in this example, the dot-like etchback rectangular ring 10d shown in FIG. 22 is applied to the oblique chip orientation shown in FIG. Compared with normal alignment, the layout of the back surface 1r of the interposer 1 (organic wiring substrate) is greatly different in the oblique chip alignment, and if a bulk-like etch-back rectangular ring is adopted, the layout of the plated wire becomes complicated. When the dot-like etch-back rectangular ring 10d is employed, the flexibility is high and the layout can be easily shared. Therefore, it is convenient especially when the oblique chip alignment and the normal mixed alignment are performed.

(5) Rectangular substrate bulk etchback rectangular ring (mainly FIG. 30):
The following description relates to the modified example of FIG. 4, and the descriptions up to this point in sections 1 to 6 and section 7 are basically applicable as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  As shown in FIG. 30, in this example, a bulk-like etchback rectangular ring 10d is applied to an interposer 1 (organic wiring board) having a rectangle whose long side is considerably longer than its short side. Such a rectangular interposer has an advantageous shape when the number of bumps is increased or when the chip is placed flat.

  As shown in FIG. 30, in this example as well, the etch-back rectangular ring 10 is in the area 22 between the annular bumps.

8). Description of various modifications and the like related to the bulk non-groove portion of the etch back ring in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application (mainly FIGS. 31 and 32)
This section describes additional uses of bulk non-grooves for each example of the present application (eg, sections 1, 4, 5 and subsections 1, 3, 5 of section 7).

  FIG. 31 is a diagram for explaining a seed modification example (wide wiring, that is, a reinforcing structure using a local grounding and wiring plate), etc., relating to a bulk non-groove portion of etch back ring in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. 5 is an enlarged plan view of the rear surface of the peripheral non-groove portion cutout region R1 in FIG. 2 corresponding to 5 (bump electrodes and the like are not shown in order to ensure visibility). FIG. 32 corresponds to FIG. 5 for describing a seed modification (substrate address metal pattern insertion structure) and the like regarding the bulk non-groove portion of the etch back ring in the device structure of the semiconductor integrated circuit device according to the one embodiment of the present application. FIG. 3 is an enlarged plan view of the back surface of the bulk non-groove periphery cutting region R1 in FIG. 2 (bump electrodes and the like are not shown in order to ensure visibility). Based on these, various modifications and the like related to the bulk non-groove portion of the etch back ring in the device structure of the semiconductor integrated circuit device according to the one embodiment of the present application will be described.

  For example, since the common plating line 25 is not usually laid out under the solder resist film 4r of the bulk non-groove portion 16b shown in FIG. 5, from the viewpoint of wiring, the bulk non-groove portion 16b and its periphery are called empty spaces. It will be. An example of how to use this empty space is given below.

(1) Reinforcement structure with wide wiring (local grounding & wiring plate) (mainly FIG. 31):
The following description relates to the modified example of FIG. 5, and the descriptions in sections 1 to 7 basically apply as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  As shown in FIG. 31, in this example, a wide wiring 33 such as a local grounding & wiring plate formed of a metal film (copper film in this example) in the same layer as the backside wiring 44 around the bulk non-groove portion 16b and its periphery. This portion is mechanically reinforced by spreading (wide metal pattern). For this purpose, for example, since many local plates for power supply or grounding are usually laid out in the region inside the etch-back rectangular ring 10, one of them is connected via the bulk non-groove portion 16b. What is necessary is just to extend outside the etch-back rectangular ring 10.

  As a result, the interposer 1 (organic wiring board) is deformed by stress along the etch-back rectangular ring 10 in this portion, and as a result, it is possible to prevent stress from being concentrated on the semiconductor chip thereabove. .

(2) Substrate address metal pattern insertion structure (mainly FIG. 32):
The following description relates to the modified example of FIG. 5, and the descriptions up to this point in sections 1 to 7 and section 8 are basically applicable as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  As shown in FIG. 32, in this example, a metal substrate address pattern 34 composed of a metal film (in this example, a copper film) of the same layer as the backside wiring 44 is arranged around the bulk non-groove portion 16b and its periphery. is there. The metal substrate address pattern 34 identifies, for example, the position of the specific unit substrate 63 on the panel 61 (or the sheet 62) after the panel 61 is divided into the sheet 62 and the unit substrate 63. Therefore, in principle, the index is assigned to all the unit substrate regions 63 (see FIGS. 8 and 9). In a general example, it is often arranged in an empty space such as a peripheral corner portion of the unit substrate region 63. However, since the arrangement space tends to be narrowed as the number of bumps increases, the bulk non-groove portion 16b. It is convenient if it can be arranged in the vicinity thereof.

9. In the device structure of the semiconductor integrated circuit device according to the one embodiment of the present application, a modification (bent crossing portion etch back ring) relating to the crossing side (crossing portion) of etch back ring and “linearity” relating to sections 1 to 9 (this section) ”Etc. (mainly FIGS. 33 to 36)
In this section, variations on the transverse side (transverse part) in the device structures of sections 1 and 4 to 8 will be described, and “linearity” of the transverse part appearing in each example of the present application will be considered.

  The following description relates to the modified example of FIG. 2, and the descriptions in sections 1 to 8 are basically applicable as they are. Therefore, in the following, those descriptions will not be repeated in principle.

  FIG. 33 corresponds to FIG. 2 for explaining a modified example (bent transverse portion etch back ring) relating to the transverse side (cross portion) of the etch back ring in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application. It is a whole back surface top view. FIG. 34 relates to a modification (bent transverse cross-section etch back ring) and sections 1 to 9 (this section) relating to the cross-side (cross-section) of etch back ring in the device structure of the semiconductor integrated circuit device according to the one embodiment of the present application. FIG. 34 is an enlarged plan view of a chip end cutout region R4 of FIG. 33 for explaining “linearity” and the like. FIG. 35 is an enlarged plan view corresponding to FIG. 34 illustrating a typical straight crossing portion for describing “flexibility” in FIG. 34 and “linearity” of the crossing portion in each example of the present application. FIG. 36 is an enlarged plan view corresponding to FIG. 34 showing a limit example of the straight crossing portion for explaining “flexibility” in FIG. 34 and “linearity” of the crossing portion in each example of the present application. Based on these, the modified example (bent crossing portion etch back ring) and the sections 1 to 9 (this section) in the device structure of the semiconductor integrated circuit device according to the embodiment of the present application relating to the cross side (cross portion) of the etch back ring ) Will be described.

  As shown in FIG. 33, in this example, the bulk-type transverse portion 29 in the example of FIG. 2 is replaced with a bent transverse portion 29m. The bent transverse portion 29m is basically composed of an integral bulk groove portion 15b, and in this example, the transverse sides 18g and 18h and the etch-back rectangular ring 10 are also composed of the same integral bulk groove portion 15b. ing. However, it is not excluded to introduce a non-groove portion into the etch-back rectangular ring 10 corresponding to the inside or the outside of the semiconductor chip 2x (first semiconductor chip) as necessary. When a non-groove portion is introduced into the etch-back rectangular ring 10 corresponding to the inside of the semiconductor chip 2x (first semiconductor chip), the stress concentration applied to the semiconductor chip can be further reduced as described above. it can.

  Details of the bent transverse portion 29m are shown in FIG. 34 (chip end cutout region R4 in FIG. 33). As shown in FIG. 34, the bent transverse portion 29m of the etch-back groove 9 is composed of a first straight portion 51, a second straight portion 52, and a bent portion 53 between them, which are substantially parallel to each other. Constitutes an integral groove 15 together with other parts. Here, the first straight portion 51 and the second straight portion 52 are mutually shifted in a direction orthogonal to a straight line substantially parallel to the bent transverse portion 29m as a whole, and the shift amount, that is, the groove shift distance SD is The first linear portion 51 and the second linear portion 52 are not more than the extent of mutual extension. In this example, like the other examples, the groove width GW (for example, about 180 micrometers) of each part of the etch-back groove 9 is basically the same. The upper limit value (including the value) of the preferable range of the groove shift distance SD in this example is the sum of the widths of the first straight line portion 51 and the second straight line portion 52. On the other hand, the lower limit value (not including that value) is the thinner one of the widths of the first straight line portion 51 and the second straight line portion 52.

  As shown in FIGS. 35 and 36, when the crossing portion 29 has a straight shape, that is, when it is a “straight crossing portion 29s”, the semiconductor chip is placed inside the etchback groove 9 (including the boundary). This is because a straight line can be drawn and stress is concentrated on the semiconductor chip 2x along the straight line. Therefore, in such a case, as described outside this section, it is necessary to provide a non-groove portion in the transverse portion.

  In addition, in the description so far, each example (FIGS. 2, 20 to 22, 24, 26, 27, 29 to 32) of the present application other than the example of FIG. 33 and FIG. It is an example of a linear crossing part. This linear crossing portion has an advantage that the arrangement width of the etch-back groove 9 can be reduced. This is particularly suitable when the etch-back rectangular ring 10 is disposed in the inter-annular bump region 23 because the width of the inter-annular bump region 23 (for example, see FIG. 4) is relatively small.

  On the other hand, the bent transverse part 29m as shown in FIGS. 33 and 34 has an advantage that the non-groove part 16 (see, for example, FIG. 2) is not required. Note that a plurality of bent portions may be provided instead of only one place as shown in FIG. 34, or may be repeatedly provided as shown in FIG. In general, it is considered that the effect of stress concentration relaxation increases as the number of repetitions increases. However, the lower limit of the repetition cycle is at most about the same as that of the dot-like etchback rectangular ring.

10. Supplementary explanation regarding the above-described embodiment (including modifications) and general consideration (mainly FIGS. 37 to 39)
37 is a plan view of the entire back surface of the device of FIG. 1 corresponding to FIG. 2 for explaining the outline of the device structure in the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 38 is an etch for explaining a combination example 1 (introduction of a bulk element into a dot-like etchback rectangular ring) of various types of etchback rectangular rings in the device structure of the semiconductor integrated circuit device of the one embodiment of the present application. It is a plane layout figure of a back rectangular ring and a semiconductor chip. FIG. 39 is a diagram for explaining examples of combinations of various types of etch-back rectangular rings in the device structure of the semiconductor integrated circuit device according to the one embodiment of the present application (introduction of bent-shaped sections of etch-back rectangular rings to combination example 1). FIG. 5 is a plan layout view of the etch-back rectangular ring and the semiconductor chip. Based on these, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Consideration of etch-back rectangular ring (see FIGS. 2, 6, 10, and 11):
In the production of an interposer (organic wiring board) in a BGA, as shown in FIGS. 6 and 11, for example, an interposer 1 is used for electrolytic plating of bonding fingers 11 (front surface) and bump lands 12 (back surface). Taking the back surface 1r as an example, it is necessary to connect all the bump lands 12 to the unit substrate outer peripheral plating wire 67 by the back surface wiring (that is, the connection plating wire). For this reason, when the number of bump lands 12 is small, most of the bump lands 12 are connected almost directly to the unit substrate outer peripheral plating line 67 with individual connection plating wires for each bump land 12. In this way, after the electrolytic plating, the unit substrate outer peripheral plating line 67 is removed by some method (for example, etch back), so that the presence or absence of a short circuit between wirings of the interposer can be electrically inspected relatively easily.

  However, as shown in FIGS. 4 and 11, the method has become difficult as the density of the bump lands 12 in the annular external bump arrangement region 23 and the number of rows increase. In order to cope with this, as a first method, a large number of spot-like common plating lines are dispersedly arranged and connected to the unit substrate outer peripheral plating line 67, and each spot-like common plating line is connected. In addition, there is a spot etch back method in which the surrounding bump lands 12 are connected by radial wiring. In this case, similarly to the above, the spot-like common plating line is removed by the etch back process.

  On the other hand, as a second method, as shown in FIG. 10, a rectangular annular common plating line (that is, an internal ring plating line 70) is arranged along the annular inter-bump region 22, and this is arranged on the outer periphery of the unit substrate. There is a ring etch back method in which the bump land 12 in the vicinity of the common plating line is connected to the plating line 67 with a substantially vertical wiring.

  This ring etch back method has an advantage that the rectangular annular common plating lines can be systematically laid out, but, as shown in FIG. 2, the macro shape etch back rectangular ring 10 and the semiconductor chip 2x directly interfere with each other. It has been made clear by the inventors of the present application that there is a risk of cracks in the semiconductor chip 2x during the assembly process.

  The cause of the crack is thought to be directly due to the injection pressure of the sealing resin, but the load during semiconductor chip or spacer chip bonding, pressure bonding impact, or the bonding load during wire bonding, pressure bonding impact. It is assumed that there is also an influence of ultrasonic waves and the like.

(2) Description of outline of device structure in semiconductor integrated circuit device of one embodiment of the present application (mainly FIG. 37):
In order to solve such a problem, the semiconductor integrated circuit device according to the embodiment of the present application has a structure as shown in FIG. That is,
(A) The semiconductor chip 2x (first semiconductor chip) is fixed to the surface of the organic wiring board 1 having a rectangular shape,
(B) On the back surface 1r of the organic wiring board 1, an etch-back rectangular ring 10 is disposed,
(C) At least one transverse side 18g of the etch-back rectangular ring 10 is disposed substantially parallel to any one of the substrate end sides 17g of the organic wiring board 1,
(D) A semiconductor integrated circuit device is provided in which the non-groove portion 16 (first non-groove portion) is provided inside the transverse portion 29 of at least one transverse side 18g.

  According to such a device structure, at the time of assembly (for example, a wire bonding process, a sealing process, etc.), the organic wiring substrate 1 is deformed at the portion of the etch-back rectangular ring 10 other than the non-groove portion 16, and the semiconductor Although stress is concentrated to some extent on the chip 2x, it is possible to prevent chip cracks as a result of the stress being relaxed in the non-groove portion 16.

(3) Explanation of the combination relating to the form of the etch-back rectangular ring (mainly FIG. 38 and FIG. 39):
The following description relates to the modified example of FIG. 2, and the description up to this point of sections 1 to 9 and section 10 is basically applicable as it is. Therefore, in the following, those descriptions will not be repeated in principle.

  In the examples described so far, in principle, the bulk-like etchback rectangular ring is composed of a bulk groove portion and a bulk non-groove portion, and the dot-like etchback rectangular ring is composed of a dot-like groove portion and a non-groove portion between dots. However, it does not exclude the use of interlaced groove portions and non-groove portions of both categories. Hereinafter, the mixed etchback rectangle will be described in detail.

(3-1) Description of combination example 1 of various types (introduction of bulk element into dot-like etchback rectangular ring) (mainly FIG. 38):
The example shown in FIG. 38 is a partial combination of a bulk-like etchback rectangular ring and a dot-like etchback rectangular ring. As shown in FIG. 38, in this example, a dot-shaped section 50d is partially embedded based on a bulk-shaped etchback rectangular ring. Since the dot-like etchback rectangular ring has a high degree of freedom in layout, it can be used freely regardless of whether it is inside or outside the semiconductor chip 2x (first semiconductor chip).

(3-2) Introduction of bent section of etch-back rectangular ring to combination example 1 (mainly FIG. 39):
In the example shown in FIG. 39, in a combination of a bulk-like etch-back rectangular ring and a dot-like etch-back rectangular ring, a bent transverse part 29m is introduced into a part of the transverse side 18h, and a bent-shaped section 50m of the etch-back rectangular ring is formed. It is a thing. This example is particularly suitable when the bump lands 12 (for example, see FIG. 11) are densely arranged around the transverse side 18h, and thus the bulk non-groove portion 16b or the like is not provided.

11. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above embodiment, the BGA has been specifically described as an example. However, the present invention is not limited thereto, and the BGA may be used as long as the semiconductor chip is mounted on the multilayer wiring board. Needless to say, it may be an organic multilayer wiring board other than the interposer.

1 Interposer (organic wiring board)
1f Front surface of interposer, etc. 1r Back surface of interposer, etc. 1s Core substrate part of interposer 2f Device surface of semiconductor chip (first main surface)
2r Rear surface of semiconductor chip (second main surface)
2g, 2h edge of semiconductor chip 2x semiconductor chip (first semiconductor chip)
2y Other semiconductor chip 3 Spacer (or second semiconductor chip)
3g, 3h Edge (first edge) of spacer (or second semiconductor chip)
4c Part covered by solder resist film 4f Solder resist film on the surface 4r Solder resist film on the back surface 5 Bonding pad 6 Bonding wire 7 Resin encapsulant 8 Bump electrode 9 Etch back groove 10 Etch back rectangular ring 10b Bulk etch back Rectangular ring 10d Dot-shaped etchback rectangular ring 11 Bonding finger 12 Bump land 14 Backside blind via peripheral land 15 Groove 15b Bulk groove 15d Dot-shaped groove 16 Non-groove (first non-groove)
16b Bulk non-groove portion 16d Non-groove portion between dots 16s Cross-over non-groove portion 17g, 17h Substrate edge 18g, 18h Transverse side 19 Electrolytic plating film 20 Bump land opening 21 Internal bump placement region 22 Ring-to-bump region 23 Ring-shaped external bump placement region 24 Blind via 25 Common plated wire 25z Portion where common plated wire is removed 26 Adhesive film 26d DAF
26 g Silver paste film 27 Part to be removed by etch-back 28 Crossing part 29 Transverse part 29 m Bending transverse part 29 s Linear transverse part 30 Glass epoxy core substrate 31 f Surface buildup insulating film 31 r Backside buildup insulating film 32 Embedded through via 33 Wide wiring (local grounding & wiring plate)
34 substrate address metal pattern 35 surface-side bonding finger opening 36 second layer through via peripheral land 37 third layer through via peripheral land 38 second layer blind via peripheral land 39 third layer blind via peripheral land 40 no plating line Part 41 Surface wiring 42 Second layer wiring 43 Third layer wiring 44 Back surface wiring 45 Front blind via peripheral lands 46, 47 Part contributing to stress relaxation 50d Dot-shaped section of etch-back rectangular ring 50m Bent-shaped section of etch-back rectangular ring 51 First linear portion 52 Second linear portion 53 Bent portion 61 Panel 62 Sheet (or sheet region)
63 Unit board (or unit board area)
64 Panel outer peripheral plated wire 65 Sheet outer peripheral plated wire 66 Panel outer peripheral sheet outer peripheral connecting wire 67 Unit substrate outer peripheral plated wire 68 Sheet outer peripheral unit substrate outer peripheral connecting wire 69 Internal / external connecting plated wire 70 Internal ring plated wire 71 Unit substrate outer peripheral plated wire etch Back groove 91 Wire bonding stage 92 Wire bonding capillary 93 Lower mold 94 Upper mold 95 Resin injection pressure 101 Panel preparation process 102 Front / back metal pattern processing process 103 Front / back solder resist film formation & patterning process 104 Pad electrolytic plating process 105 Plating wire removal Process (etch back process)
106 Electrical test process 107 Dividing the panel into sheets 111 Semiconductor chip mounting process 112 Wire bonding process 113 Resin sealing process 114 Bump electrode attaching process 115 Device dividing process GL Groove length GS Groove interval GW Groove width R1 Bulk non-groove periphery cutting Region R2 Partial cutout region R3 Substrate corner cutout region R4 Chip end cutout region SD Groove shift distance

Claims (20)

Semiconductor integrated circuit devices including:
(A) An organic wiring board having a metal wiring pattern at least on the front surface and the back surface and having a rectangular shape;
(B) a first semiconductor chip having a first main surface and a second main surface, having a rectangular shape, and being fixed on the surface of the organic wiring board;
(C) a resin sealing body for sealing the first semiconductor chip on the surface of the organic wiring board;
(D) a large number of bump electrodes provided on the back surface of the organic wiring board;
(E) an etch-back rectangular ring provided on the back surface of the organic wiring board;
Here, the etch-back rectangular ring has the following:
(E1) at least one transverse side that runs parallel to one of the substrate end sides of the organic wiring substrate and intersects the first semiconductor chip;
(E2) a transverse part where the first semiconductor chip and each transverse side overlap in a plane;
(E3) A first non-groove portion provided inside each transverse portion.     2. The semiconductor integrated circuit device according to claim 1, wherein said etch-back rectangular ring is provided in a region between annular bumps in a plan view.     3. The semiconductor integrated circuit device according to claim 2, wherein both end portions of each transverse portion and the vicinity thereof are integral groove portions.     4. The semiconductor integrated circuit device according to claim 3, wherein each first non-groove portion is provided at a central portion of each transverse portion or in the vicinity thereof. The semiconductor integrated circuit device according to claim 4.
(I) the first main surface of the first semiconductor chip is a device formation surface;
(Ii) The first semiconductor chip is fixed via a first adhesive layer provided between the surface of the organic wiring board and the second main surface of the first semiconductor chip. And;
(Iii) A plurality of bonding pads on the first main surface of the first semiconductor chip and a plurality of bonding leads on the surface of the organic wiring substrate are connected by bonding wires.     6. The semiconductor integrated circuit device according to claim 5, wherein the first adhesive layer is a silver paste adhesive layer.     7. The semiconductor integrated circuit device according to claim 6, wherein a spacer substrate or a second semiconductor chip is stacked on the first main surface of the first semiconductor chip.     8. The semiconductor integrated circuit device according to claim 7, wherein the first end side of the spacer substrate or the second semiconductor chip is disposed above or in the vicinity of the transverse portion adjacent to the spacer substrate or the second semiconductor chip. Yes.     6. The semiconductor integrated circuit device according to claim 5, wherein the bonding wire is a copper-based wire.     6. The semiconductor integrated circuit device according to claim 5, wherein each transverse portion has a linear shape.     6. The semiconductor integrated circuit device according to claim 5, wherein the thickness of the first semiconductor chip is 100 micrometers or less.     6. The semiconductor integrated circuit device according to claim 5, wherein the metal wiring pattern is formed on at least one of the first non-groove portions and on the back surface of the organic wiring substrate under the solder resist film around the first non-groove portion. A wide metal pattern of the same layer is arranged.     6. The semiconductor integrated circuit device according to claim 5, wherein one of the first non-groove portions and the back surface of the organic wiring substrate under the solder resist film around the first non-groove portion are formed in the same layer as the metal wiring pattern. Metal substrate address marks are arranged. Semiconductor integrated circuit devices including:
(A) An organic wiring board having a metal wiring pattern at least on the front surface and the back surface and having a rectangular shape;
(B) a first semiconductor chip having a first main surface and a second main surface, having a rectangular shape, and being fixed on the surface of the organic wiring board;
(C) a resin sealing body for sealing the first semiconductor chip on the surface of the organic wiring board;
(D) a large number of bump electrodes provided on the back surface of the organic wiring board;
(E) an etch-back rectangular ring provided on the back surface of the organic wiring board;
Here, the etch-back rectangular ring has the following:
(E1) A transverse side that runs in parallel with an edge of any one of the organic wiring boards and crosses the first semiconductor chip;
(E2) a transverse part in which each transverse side overlaps the first semiconductor chip in a plane,
Furthermore, here, said transverse part is constituted by an integral groove, which has the following:
(X1) first linear portion;
(X2) a second straight line portion extending in parallel with the first straight line portion;
(X3) a bent portion connecting the first straight portion and the second straight portion,
Here, the first straight part and the second straight part are shifted in the width direction so that their extensions do not overlap.     15. The semiconductor integrated circuit device according to claim 14, wherein said etch-back rectangular ring is provided in a region between annular bumps in a plan view. The semiconductor integrated circuit device according to claim 15.
(I) the first main surface of the first semiconductor chip is a device formation surface;
(Ii) The first semiconductor chip is fixed via a first adhesive layer provided between the surface of the organic wiring board and the second main surface of the first semiconductor chip. And;
(Iii) A plurality of bonding pads on the first main surface of the first semiconductor chip and a plurality of bonding leads on the surface of the organic wiring substrate are connected by bonding wires.     17. The semiconductor integrated circuit device according to claim 16, wherein the first adhesive layer is a silver paste adhesive layer.     18. The semiconductor integrated circuit device according to claim 17, wherein a spacer substrate or a second semiconductor chip is stacked on the first main surface of the first semiconductor chip.     19. The semiconductor integrated circuit device according to claim 18, wherein the first end side of the spacer substrate or the second semiconductor chip is arranged above or in the vicinity of the transverse portion adjacent to the spacer substrate or the second semiconductor chip. Yes.     17. The semiconductor integrated circuit device according to claim 16, wherein the bonding wire is a copper-based wire.

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