JP2014081702A - Layout density verification method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout density verification method capable of shortening time required for layout density verification.SOLUTION: The layout density verification method includes subdividing a verification region A1 of a wafer into a plurality of first blocks A2, performing layout density verification for each of the first blocks A2, determining whether or not layout density is within a reference value, determining a first block A2 the layout density of which is out of the reference value, setting a second block A3 including the first block A2 the layout density of which is out of the reference value, and performing pattern density verification only for the second block A3.

Description

  The present invention relates to a layout density verification method and program.

  For example, in the manufacturing process of a semiconductor integrated circuit, wafer flatness is required. Therefore, layout density verification for verifying the flatness of the wafer is performed.

  A general layout density verification method verifies the layout density of each section while moving a section having a predetermined width in a whole area of the verification area of the wafer by a predetermined step value (see Patent Documents 1 and 2). ).

JP 2011-70630 A JP 2005-228208 A

In the layout density verification methods of Patent Documents 1 and 2, since a section having a predetermined width is moved by a predetermined step value in the entire verification area of the wafer, the area to be verified redundantly is wide. Here, the amount of calculation associated with layout density verification is proportional to the area. For this reason, the layout density verification methods of Patent Documents 1 and 2 require a large amount of calculation and increase the time spent for layout verification.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  In the layout verification method according to the present embodiment, the verification area of the wafer is subdivided into a plurality of first sections, and pattern density verification is performed only on the second section including the first section whose layout density is out of the reference value. Run.

  The program according to the present embodiment causes the computer to subdivide the wafer verification area into a plurality of first sections and perform pattern density verification only on the second section including the first section whose layout density deviates from the reference value. Execute the process to execute.

  Time required for layout density verification can be reduced.

1 is a block diagram schematically showing a computer system. 3 is a flowchart showing a flow of a layout density verification method according to the first embodiment. It is a figure which shows roughly the 1st division in a verification area | region. It is a figure which shows roughly the layout density of a 1st division. It is a figure which shows roughly the 1st division from which layout density remove | deviates from the inside of a reference value. It is a figure which shows schematically the 2nd division containing the 1st division from which layout density remove | deviates from the inside of a reference value. It is a figure which shows schematically the 2nd division containing the 1st division from which layout density remove | deviates from the inside of a reference value. It is a figure which shows schematically the 2nd division containing the 1st division from which layout density remove | deviates from the inside of a reference value. It is a figure which shows roughly the case where there exist two or more 1st divisions from which a layout density remove | deviates from the reference value.

  Hereinafter, embodiments of the layout density verification method and program will be described. However, it is not necessarily limited to the following embodiment. In addition, for clarity of explanation, the following description and drawings are simplified as appropriate. Incidentally, the vertical and horizontal directions in the following description are directions when the drawing is viewed from the front.

<Embodiment 1>
A layout density verification method and program according to the first embodiment will be described. The layout density verification method of this embodiment can be realized by a typical computer system. FIG. 1 shows an example of a computer system. The computer system includes a storage unit 1, an arithmetic processing unit 2, a display unit 3, and an operation unit 4, which are connected to each other via a bus 5. Then, similarly to the program processing using a general computer system, the arithmetic processing unit 2 reads the program stored in the storage unit 1, and the arithmetic processing unit 2 executes the layout density verification method.

  The layout density verification method is executed in the following flow. FIG. 2 is a flowchart showing the flow of the layout density verification method. First, a verification area A1 is set (S1). Specifically, the computer system is activated to activate a program for executing the layout density verification method. Then, the arithmetic processing unit 2 reads layout information of, for example, a semiconductor integrated circuit stored in the storage unit 1, and sets a verification region A1 (see FIG. 3) on the wafer based on the layout information. That is, the arithmetic processing unit 2 sets, for example, all regions where semiconductor integrated circuits are formed as the verification region A1. The arithmetic processing unit 2 stores information indicating the set verification area A1 in the storage unit 1. Here, the layout information is graphic information of a pattern formed on the wafer.

  Next, the verification area A1 is subdivided into a plurality of first sections A2, and density information for executing layout density verification for each first section A2 is acquired (S2). Here, FIG. 3 shows the first section A2 (hatched portion) in the verification area A1, and the numbers in parentheses indicate the position of the first section A2 with the lower left of the verification area A1 as the origin. . For example, A2 (a, b) is the first section A2 that is a-th in the X-axis direction and b-th in the Y-axis direction. Note that a takes a value from 1 to n, and b takes a value from 1 to m. L1x is the width of the first section A2 in the X-axis direction (that is, the length of one side in the X-axis direction), and L1y is the width of the first section A2 in the Y-axis direction (that is, in the Y-axis direction). The length of one side).

  Specifically, the arithmetic processing unit 2 reads information indicating the verification area A1 from the storage unit 1, and subdivides the verification area A1 into a grid shape in the X-axis direction and the Y-axis direction with a preset width, The inner area is set to the first section A2. Here, the preset width is a width that becomes the step value S by multiplying by an integer, and is preferably the step value S. The step value S will be described later. Accordingly, the first section A2 is set in a square shape in which the lengths L1x and L1y of one side are step values S, and the verification area A1 is configured by the plurality of first sections A2. The arithmetic processing unit 2 stores information indicating the set first section A2 in the storage unit 1.

  Then, the arithmetic processing unit 2 reads layout information and information indicating the first section A2 from the storage unit 1, and acquires layout density information of each first section A2 based on the layout information. Here, FIG. 4 shows the layout density D of each first section A2, and the numbers in parentheses indicate the position of the first section A2 with the lower left of the verification area A1 as the origin. For example, D (a, b) is the layout density of the first section A2 that is a-th in the X-axis direction and b-th in the Y-axis direction. The arithmetic processing unit 2 stores the acquired layout density information of the first section A2 in the storage unit 1.

  Next, it is determined whether or not the layout density of the first section A2 is within the reference value (S3). Specifically, the arithmetic processing unit 2 reads the layout density information and the reference value information of all the first sections A2 from the storage unit 1, determines whether the layout density is within the reference value, and stores the determination information. Store in part 1. Here, the reference value information is stored in the storage unit 1 in advance, and is set in various formats such as permitting specified density value or higher, permitting specified density value or lower, permitting specified density value 1 or higher and specified density value 2 or lower Has been. The determination information is information indicating whether or not the layout density of each first section A2 is within the reference value.

  Next, as a result of the determination in S3, if there is a first section A2 in which the layout density deviates from the reference value (YES in S3), the first section A2 in which the layout density deviates from the reference value is specified, and the layout density is A second section A3 including the first section A2 that deviates from the reference value is set (S4). Here, FIG. 5 shows a first section A2 in which the layout density deviates from the reference value. In the illustrated example, the layout density of the first section A2 (k, l) is out of the reference value. Note that k takes a value from 1 to n, and l takes a value from 1 to m.

  Specifically, the arithmetic processing unit 2 reads the determination information from the storage unit 1, identifies the first section A2 whose layout density is outside the reference value based on the determination information, and the specified layout density is within the reference value. Information indicating the first section A2 that is out of the range is stored in the storage unit 1.

  Then, the arithmetic processing unit 2 reads out information indicating the first section A2, information indicating the first section A2 whose layout density is out of the reference value, and layout information from the storage unit 1, and includes the first section A2. The second section A3 is set, and information indicating the set second section A3 is stored in the storage unit 1.

  The second section A3 is an area where the layout density needs to be within a reference value in order to satisfy the flatness of the wafer, and is set as appropriate. Here, FIGS. 6 to 8 show an example of the set second section A3. Note that L2x is the width of the second section A3 in the X-axis direction (that is, the length of one side of the second section A3 in the X-axis direction), and L2y is the width of the second section A3 in the Y-axis direction ( That is, the length of one side of the second section A3 in the Y-axis direction).

  The second section A3 is preferably composed of a plurality of first sections A2. That is, the second section A3 is wider than the first section A2. In the second section A3, the length L2x of one side in the X-axis direction of the second section A3 is an integral multiple of the length L1x of one side in the X-axis direction of the first section A2, and the second section A3 It is preferable that the length L2y of one side in the Y-axis direction of the section A3 is a rectangular shape that is an integral multiple of the length L1y of one side in the Y-axis direction of the first section A2. The second section A3 of the present embodiment is composed of a total of sixteen first sections A2, four in the X-axis direction and four in the Y-axis direction, and the lengths L2x and L2y of one side are the first. It is a square shape that is four times the lengths L1x and L1y of one side of the section A2.

  Such 2nd division A3 is set one after another as follows. For example, as illustrated in FIG. 6, the arithmetic processing unit 2 arranges the first section A2 in which the layout density is out of the reference value in the upper right section among the sixteen sections in which the first section A2 is disposed. As described above, the second section A3 is set, and information indicating the set second section A3 is stored in the storage unit 1.

  Next, as shown in FIG. 7, the arithmetic processing unit 2 moves the second section A3 to the right by a predetermined step value S, sets the second section A3 at a new position, and newly Information indicating the set second section A3 is stored in the storage unit 1. Here, if the length L1x of one side of the first section A2 is equal to the step value S, the second section A3 moves to the right by the first section A2. Incidentally, the step value S is appropriately set in consideration of the width of the second section A3 and the like.

  Thereafter, the arithmetic processor 2 moves the second section A3 in the X-axis direction and the Y-axis direction by a predetermined step value S, and sets the second section A3 at new positions one after another. Here, when the lengths L1x and L1y of one side of the first section A2 are equal to the step value S, the second section A3 is moved by the first section A2 in the X-axis direction or the Y-axis direction. One after another, each second section A3 is composed of a plurality of first sections A2. Then, as shown in FIG. 8, the first section A2 whose layout density deviates from the reference value is arranged at the center of the third section A4, which is an area formed by all the second sections A3.

Next, the arithmetic processing unit 2 reads out the information indicating the set second section A3, the reference value information, and the layout density information of the first section A2 in each second section A3 from the storage unit 1, and each It is determined whether the layout density of the second section A3 is within the reference value, and the second section A3 deviating from the reference value is specified (S5). At this time, as described above, if the lengths L1x and L1y of one side of the first section A2 are equal to the step value S, each second section A3 can be configured by a plurality of first sections A2. . Therefore, when determining whether or not the layout density of each second section A3 is within the reference value, it can be easily determined using the layout density information of the first section A2.
And the arithmetic processing part 2 stores the information which shows 2nd division A3 which remove | deviates from the inside of the specified reference value in the memory | storage part 1 as error information (S6).

  On the other hand, as a result of the determination in S3, if there is no first section A2 in which the layout density deviates from the reference value (NO in S3), the layout density verification ends. In other words, it is the width of the second section A3 that essentially wants to execute the layout density verification, but the layout density of all the first sections A2 in the second section A3 is within the reference value. This is because the layout density of the second section A3 inevitably falls within the reference value.

  Such a layout density verification method and program first subdivide the verification area A1 into a plurality of first sections A2, and determine whether or not the layout density of the first section A2 is within a reference value. Then, only the second section A3 including the first section A2 whose layout density deviates from the reference value is set with a predetermined step value S, and whether or not the layout density of each second section A3 is within the reference value. Determine. Therefore, compared with a general layout verification method, it is possible to reduce the area to be calculated redundantly, and as a result, it is possible to reduce the area for verifying the layout density. Therefore, the amount of calculation can be reduced, and the time required for layout density verification can be reduced.

  Moreover, the verification of the layout density of the second section A3 can be easily executed by using the layout density information of the first section A2 already stored in the storage unit 1.

<Embodiment 2>
In the first embodiment, the case where there is one first section A2 whose layout density is out of the reference value has been described. However, the same applies to the case where there are a plurality of first sections A2 whose layout density is out of the reference value. Can do.

  Here, FIG. 9 shows a case where there are a plurality of first sections A2 whose layout density is out of the reference value. As described above, the second section A3 including the first section A2 whose layout density is out of the reference value may overlap. In such a case, only the verification of the layout density of one second section A3 is performed, and the verification of the layout density of the other second section A3 is not performed. That is, the verification of the layout density of the second section A3 that completely overlaps needs to be executed only once. Thereby, the increase in the amount of calculation accompanying verification of layout density can be suppressed.

<Embodiment 3>
In the above-described embodiment, the software configuration has been described, but it may be realized as a hardware configuration.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The program may be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W and semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (random access memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

DESCRIPTION OF SYMBOLS 1 Memory | storage part 2 Arithmetic processing part 3 Display part 4 Operation part 5 Bus | bath A1 Verification area A2 1st division A3 2nd division A4 3rd division D Layout density S Step value L1x Width of the X-axis direction of the 1st division L1y Width of the first section in the Y-axis direction L2x Width of the second section in the X-axis direction L2y Width of the second section in the Y-axis direction

Claims (7)

Subdividing the verification region of the wafer into a plurality of first sections, and performing layout density verification on each of the first sections;
Determining whether a layout density is within a reference value, and identifying a first section where the layout density is outside the reference value;
A layout density verification method, wherein a second section including a first section where the layout density deviates from the reference value is set, and pattern density verification is executed only on the second section. The first section and the second section are rectangular,
The layout density verification method according to claim 1, wherein the second section includes a plurality of the first sections. The second partition is moved by a predetermined step value in the direction of the first side or the direction of the second side orthogonal to the direction of the first side, and the layout density for each of the second partitions Perform validation,
The layout density verification method according to claim 2, wherein the step value is an integral multiple of the length of the first side or the second side of the first section.   4. The layout density verification according to claim 3, wherein the third section, which is an area formed by all the second sections, is arranged at the center of the first section whose layout density is out of the reference value. Method. Storing a result of layout density verification of the first section;
The layout density verification method according to claim 1, wherein layout density verification of the second section is executed using a result of layout density verification of the first section. When there are a plurality of first sections where the layout density is out of the reference value, and a plurality of the second sections overlap,
The layout density verification method according to claim 1, wherein the layout density verification of the overlapped second section is executed only once. On the computer,
A process of subdividing a wafer verification region into a plurality of first sections and performing layout density verification on each of the first sections;
Determining whether or not the layout density is within a reference value, and identifying a first section in which the layout density is out of the reference value; and
A process of setting a second section including a first section where the layout density is out of the reference value, and executing a layout density verification only on the second section;
A program that executes

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