JP2014078065A - Data communication device and control method thereof, and computer program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data communication device or the like which appropriately reduces electric power consumed by a data bus according to a buffer use ratio in a data buffer.SOLUTION: A data communication device 1 includes a communication buffer 3 which is used when data communication is performed through a data bus 4, and a control unit 2 for controlling data communication by the data bus 4 to which the communication buffer 3 is connected. When a buffer use ratio which shows a ratio of data in the communication buffer 3 does not exceed a first use ratio, the control unit 2 reduces data speed in the data bus 4 which is currently connected and the number of lanes constituting the data bus 4. When the buffer use ratio exceeds a second use ratio which is greater than the first use ratio, the control unit 2 increases data speed in the data bus 4 which is currently connected and the number of lanes.

Description

  The present invention relates to a technical field for reducing, for example, power consumed by a data bus in a data communication apparatus.

  In recent years, an information processing apparatus such as a server apparatus has a PCI_Express whose specification is defined by Peripheral_Component_Interconnect-Special_Interest_Group (hereinafter abbreviated as “PCI-SIG”) as one type of bus used for transferring data. It has a bus (hereinafter sometimes abbreviated as “PCIe bus”).

  The information processing apparatus is connected to a central processing unit Central_Processing_Unit (hereinafter abbreviated as “CPU”) by a system bus and is called a root complex (Root_Complex: hereinafter abbreviated as “RC”) for controlling the PCIe bus. Has a host bridge.

  In addition, the RC is connected to an end point (Endpoint: hereinafter referred to as “EP”), which is a device that controls peripheral devices conforming to the PCIe bus specification, via the PCIe bus.

  Further, the information processing apparatus can connect a PCIe switch having a plurality of ports to the RC in order to add ports (input / output ports) that are connection points for connecting EPs to the PCIe bus.

  In addition, the PCIe switch is connected to RC or a CPU incorporating RC via a port called upstream that indicates a direction toward RC.

  In addition, the PCIe switch is connected to an EP that is a peripheral device via a port called “downstream” indicating a direction away from the RC.

  That is, the data processed by the CPU is branched at the PCIe switch via the upstream port of the PCIe switch, for example, via RC, and the PCIe bus data is exchanged with the EP via the downstream port of the PCIe switch. To do.

  Here, the port connecting the PCIe switch and RC or EP is a lane having a differential pair signal in the physical layer (that is, a differential signal composed of a positive phase and a negative phase) for transmission and reception, respectively. Connected by a bus called.

  One or more lanes are collected to secure a necessary data transmission band. A communication path in which the data transmission band is secured is called a link. The data communication speed in the link is called a link speed (link speed). That is, the link speed is set for each link.

  A data communication apparatus, which is an example of such an information processing apparatus, establishes a link with an EP at the maximum link speed and number of lanes supported by each other device at the time of activation.

  Further, in such a data communication apparatus, a host bus adapter (Host_Bus_Adap: hereinafter referred to as Host_Bus_AdH), which converts an interface between a PCI_Express bus (PCIe bus) and, for example, a Serial_Attached_SCSI (Small_Computer_System_Interface): abbreviated as “SAS” hereinafter. The partner peripheral device connected via the card may be a low-speed device such as a magnetic tape storage device or a device that is not frequently used.

  That is, in such a data communication apparatus, even if the data rate is low or the bus usage rate is low with respect to the SAS_HBA card to which the downstream port in the PCIe switch is connected, for example, the link in the PCI_e bus Since the operation is performed at the maximum link speed and the maximum number of lanes that can be connected to both the PCIe switch and the SAS_HBA card, which are determined in advance at the time of activation, more power is consumed than necessary.

  On the other hand, in the data communication apparatus described above, a serial bus such as the PCI_e bus as described above is used in Input / Output (that is, data input / output unit; hereinafter, abbreviated as “IO”). The communication speed has been increased, and the power consumption in the IO has increased accordingly. Therefore, reduction of power consumption in IO is demanded.

  Here, the description will focus on the reduction in power consumption in the PCIe switch that connects the RC that is upstream from the CPU in the information processing apparatus and the EP that is downstream.

  Here, the technique described in Patent Document 1 discloses a technique for determining a communication speed that optimizes data transfer capability and power consumption in a communication interface in an information processing apparatus.

  More specifically, the technique described in Patent Literature 1 is based on the presence or absence of data to be transmitted or received, the rate at which transmission underrun or reception overrun occurs, or the time when there is no data to be transmitted or received. When there is no data to be transferred or when there is little data, a technique for reducing power consumption consumed when transferring data is disclosed.

  Further, the technique described in Patent Document 2 checks whether the network environment may temporarily block communication depending on the state of the network environment, and determines that communication is not blocked. A technique for reducing link speed (ie, data communication speed) in a connection between a device and a network is disclosed.

  More specifically, the technique described in Patent Document 2 is a Dynamic_Host_Configuration_Protocol (hereinafter, referred to as “Dynamic_Host_Configuration_Protocol”) that automatically assigns necessary information such as an Internet_Protocol (hereinafter abbreviated as “IP”) address to a computer connected to a network. (It is abbreviated as “DHCP”) If it is determined that communication is blocked based on the response time from the server, the link speed is maintained, and if it is determined that communication is not blocked, by reducing the link speed, Disclosed is a technique for improving the power saving effect in a communication apparatus.

Re-specialized WO2003 / 096651 JP2011-239026A

  The technology disclosed in Patent Document 1 described above is such that a communication control unit that controls LAN communication using a local_area_network (hereinafter, abbreviated as “LAN”) function that the information processing apparatus itself has can communicate with peripheral devices. It is triggered by the occurrence of an event in which there is no data to be transmitted and received, and this event must first occur.

  That is, the technique disclosed in Patent Document 1 does not perform control to change the data rate or the like during normal data transfer in which there is no data to be transmitted or received or an event such as transmission underrun or reception overrun does not occur. Can not.

  Further, the technique described in Patent Document 1 does not mention increasing or decreasing the link speed or increasing or decreasing the number of links based on the buffer usage rate in the transmission / reception buffer.

  Further, when the technology disclosed in Patent Document 2 described above determines that communication is temporarily not blocked using a protocol with a network connection device when performing LAN communication with a peripheral device. In addition, it stays connected at a lower link speed than the current speed.

  Further, the technique disclosed in Patent Document 2 is about increasing or decreasing the link speed or increasing or decreasing the number of links based on the buffer usage rate when the transmission / reception buffer is actually used with the host bus. Not mentioned.

  In addition, the techniques disclosed in Patent Document 1 and Patent Document 2 described above are used when a transmission / reception buffer included in a host controller that controls a host bus in a data communication device is used, even if these disclosed techniques are combined. It is not disclosed that the data communication apparatus itself makes a decision based on the buffer usage rate to increase or decrease the link speed or increase or decrease the number of links.

  That is, the main object of the present invention is to provide a data communication apparatus and the like that appropriately reduce the power consumed by the data bus in accordance with the buffer usage rate in the data buffer in order to solve the above-described problems.

The present invention has been made for the purpose of solving the above-described problems.

That is, the data communication apparatus according to the present invention is
A communication buffer used when performing data communication through the data bus, and a control unit that controls data communication by the data bus to which the communication buffer is connected;
The controller is
If the buffer usage rate representing the proportion of data in the communication buffer does not exceed the first usage rate, reduce the data rate in the currently connected data bus and the number of lanes constituting the data bus,
When the buffer usage rate exceeds a second usage rate that is greater than the first usage rate, the data rate and the number of lanes in the currently connected data bus are increased.

As another aspect of the present invention, a method for controlling a data communication apparatus according to the present invention includes:
When controlling the data bus to which the communication buffer used when performing data communication through the data bus is controlled by the control means for controlling the data communication,
By the control means,
If the buffer usage rate representing the proportion of data in the communication buffer does not exceed the first usage rate, reduce the data rate in the currently connected data bus and the number of lanes constituting the data bus,
When the buffer usage rate exceeds a second usage rate that is greater than the first usage rate, the data rate and the number of lanes in the currently connected data bus are increased.

  This object is also achieved by a computer program that implements the above-described data communication apparatus and control method thereof by a computer, and a computer-readable storage medium in which the computer program is stored. .

  According to the present invention, the power consumed by the data bus can be appropriately reduced according to the buffer usage rate in the data buffer.

It is a block diagram which represents notionally the function in the data communication apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which represents notionally the function in the data bus switch which concerns on the 2nd Embodiment of this invention. It is a block diagram which illustrates the speed setting of the PCI_Express bus at the time of starting, and lane number setting in the data communication apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram which illustrates speed setting of a PCI_Express bus at the time of adjusting a link speed in a data communication apparatus concerning a 3rd embodiment of the present invention. It is a figure explaining a mode that the buffer usage rate is monitored in the PCIe switch in the data communication apparatus which concerns on 3rd Embodiment of this invention. It is a flowchart showing the control at the time of performing the link speed adjustment process in the data communication apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart showing the control at the time of performing the lane number change process in the data communication apparatus which concerns on the 3rd Embodiment of this invention. It is a figure explaining the case where the power consumption in a data input / output part is reduced as a result of performing the link speed adjustment process in the data communication apparatus which concerns on 3rd Embodiment. It is a figure which illustrates the structure which the program which performs a link speed adjustment process and a lane number change process operate | moves in an information processing apparatus in the data communication apparatus which concerns on the 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
The configuration of the first embodiment of the present invention will be described. FIG. 1 is a block diagram conceptually showing functions in the data communication apparatus 1 according to the first embodiment of the present invention.

  The data communication apparatus 1 according to the present embodiment includes a control unit 2 and a communication buffer 3.

  The communication buffer 3 is a buffer that buffers (temporarily stores) data so as to communicate with the external device 5 via the data bus 4.

  The control unit 2 monitors a buffer usage rate indicating a rate at which data in the communication buffer 3 is occupied.

  That is, the data communication apparatus 1 according to the present embodiment includes a communication buffer 3 used when performing data communication through the data bus 4, and a control unit 2 that controls data communication by the data bus 4 to which the communication buffer 3 is connected. Have

  When the buffer usage rate representing the ratio of data in the communication buffer 3 does not exceed the first usage rate, the control unit 2 configures the data speed of the currently connected data bus 4 and the data bus 4. When the number of lanes is reduced and the buffer usage rate exceeds the second usage rate that is higher than the first usage rate, the data rate and the number of lanes in the currently connected data bus 4 are increased.

  That is, according to the data communication device 1 according to the present embodiment, the control unit 2 monitors the buffer usage rate in the communication buffer 3 and determines the data communication speed in the data bus 4 based on the monitored buffer usage rate. Deceleration or speed increase, or the number of lanes constituting the data bus 4 in parallel can be reduced or increased.

  In the data communication apparatus 1, the higher the data communication speed and the more lanes used, the greater the power consumption in the communication buffer 3 and the data bus 4.

  The data communication apparatus 1 according to the present embodiment can reduce power consumption in the data bus 4 that connects the communication buffer 3 that buffers data and the external apparatus 5 when performing data communication.

  The reason is that the data communication apparatus 1 can suppress the data communication speed and the number of lanes according to the buffer usage rate in the communication buffer 3 using the control unit 2.

  That is, according to the present embodiment, in the data communication apparatus, the power consumed by the data bus can be appropriately reduced according to the buffer usage rate in the data buffer.

  According to the present embodiment, if the buffer usage rate in the communication buffer 3 is large, the data communication speed and the number of lanes can be increased, so that the data transfer efficiency can be improved.

  The first embodiment of the present invention has been described above by taking the configuration and operation described above as examples. However, the present invention described by taking this embodiment as an example is not necessarily limited to such configurations and operations.

<Second Embodiment>
Next, a second embodiment based on the first embodiment will be described with reference to FIG. The second embodiment represents an example in which the control unit 2 and the communication buffer 3 described in the data communication device 1 described above are applied to a data bus switch 50 that branches a data bus (not shown).

  FIG. 2 is a block diagram conceptually showing functions in the data bus switch 50 according to the second embodiment. As shown in FIG. 2, the control unit 2 described in the first embodiment further includes a buffer monitoring unit 80 and a link control unit 90 in the present embodiment.

  The communication buffer 3 described in the first embodiment corresponds to the communication buffer 30 in the present embodiment. The communication buffer 30 includes a transmission buffer 52 and a reception buffer 53 in an upstream port (Upstream_Port; hereinafter abbreviated as “UP”) 51 connected to the above-described RC (not shown, the same applies hereinafter).

  The communication buffer 30 includes a transmission buffer 62 and a reception buffer 63 in a downstream port (# 1) (Downstream_Port; hereinafter abbreviated as “DP”) 61 connected to an EP (not shown, the same applies hereinafter). Further, the communication buffer 30 includes a transmission buffer 72 and a reception buffer 73 in a downstream port (# 2) 71 (hereinafter abbreviated as “DP71”) connected to another EP.

  That is, the data bus switch 50 terminates the data bus (not shown, the same applies hereinafter) with the first data communication device (not shown, the same applies hereinafter), which is an RC, with the UP 51, and the second data communication device, which is an EP. Data buses between the first data communication device and the second data communication device using the control unit 2 are terminated with DP61 and DP71 respectively. It can be regarded as a data bus switch that is controlled to be distributed or integrated.

  Further, when the data bus switch 50 is activated, communication is established at the maximum data communication speed allowed between the connected RC and EP.

  The buffer monitoring unit 80 also monitors the buffer usage rate in each buffer (transmission buffer and reception buffer) of each port (UP51, DP61, and DP71, the same applies hereinafter) in the communication buffer 30.

  Further, the link control unit 90 changes the link speed, which is the data communication speed at each port, based on the monitoring result of the communication buffer 30 in the buffer monitoring unit 80.

  More specifically, if the buffer usage rate in each buffer of each port described above does not exceed 30%, for example, the data communication rate is switched to a lower data communication rate, for example, the buffer usage rate is reduced to 80%. If exceeded, the data communication speed is switched to a higher data communication speed than the current data communication speed.

  As a result, if the buffer usage rate is low, the control unit 2 has a lower data communication speed when the data communication speed allowed between the RC and EP connected at the time of startup is the maximum data communication speed. Therefore, it is possible to reduce the power consumption at each port as compared with the case of connection at a high data communication speed.

  If the buffer usage rate is high, the control unit 2 can change the data communication speed to a higher data communication speed than the data communication speed changed to a lower speed between the RC and the EP. Is possible.

  Further, the buffer usage rate of the communication buffer in each port can be based on the total value or average value of the transmission buffer and the reception buffer.

  In this embodiment, the buffer monitoring unit 80 and the link control unit 90 have been described as an example, but may be realized by the control unit 2.

  Further, the above-described buffer usage rate is described as an example for the sake of explanation, and is not limited to these values.

  That is, according to the present embodiment, in the data bus switch 50, the power consumed by the data bus can be appropriately reduced according to the buffer usage rate in the data buffer.

  As described above, the configuration and operation described above have been described as examples of the second embodiment of the present invention. However, the present invention described by using this embodiment as an example is not necessarily limited to the configuration and operation.

<Third Embodiment>
Next, a third embodiment based on the first and second embodiments will be described with reference to FIGS. In the third embodiment, an example in which the control unit 2, the communication buffer 3, or the communication buffer 30 described in the data communication device 1 and the data bus switch 50 is applied to a PCIe switch will be described.

  FIG. 3 is a block diagram illustrating the speed setting of the PCI_Express bus (PCIe bus) and the setting of the number of lanes at the time of activation in the data communication apparatus 10 according to the third embodiment.

  As an example, the data communication apparatus 10 illustrated in FIG. 3 includes a CPU 11, a PCIe switch 12, a host bus adapter (SAS) 13 (hereinafter abbreviated as “SAS_HBA 13”) connected to the PCIe slot 1, and a PCIe slot 2. A host bus adapter (FC) 14 (hereinafter abbreviated as “FC_HBA 14”) connected to the LAN, and a LAN card 15 connected to the PCIe slot 3.

  Here, the SAS_HBA 13 converts the data communication format between the PCIe bus that is the upstream in the SAS_HBA 13 and the SAS bus in the SAS_HBA 13.

  The FC_HBA 14 converts the data communication format between the PCIe bus that is upstream in the FC_HBA 14 and a fiber channel (Fiber_Channel: hereinafter abbreviated as “FC”) bus in the FC_HBA 14.

  FIG. 3 shows, as an example, a tape device 16 used when backing up data to the external device 5 and a disk array 17 used in a database (hereinafter referred to as “DB”) device, for example. Have.

  The tape device 16 and the disk array 17 are connected to each other via the SAS_HBA 13 and the FC_HBA 14, which are the host bus adapters described above, in the downstream port of the PCIe switch 12 included in the data communication apparatus 10.

  The upstream port in the LAN card 15 connected to the PCIe slot 3 is connected to the downstream port in the PCI_e bus branched from the RC that the CPU 11 has.

  The downstream port of the LAN card 15 is connected to a communication network 18 (hereinafter, simply referred to as “network”) such as an intranet or the Internet.

  Similarly to the LAN card 15 described above, the upstream port in the PCIe switch 12 is connected to the downstream port in the PCIe bus branched from the RC included in the CPU 11.

  In other words, the data communication apparatus 10 according to the present embodiment is, for example, a DB apparatus in a data center or a server room, for example, in order to appropriately back up with the disk array 17 constituting a database with a relatively high load. A tape device 16 that is used at a relatively low frequency and with a relatively low load is connected to the network 18 via the LAN card 15, such as a server device that is an external device (not shown) connected to the network 18. Necessary data is retrieved from the information processing apparatus or the like.

  Here, PCI_Express (Generation 3; the same applies hereinafter) bus standard defined by PCI-SIG includes 8 Gbps (Gigabit per second, the same applies hereinafter), 5 Gbps, and 2.5 Gbps as link speeds representing transmission rates in the physical layer. Is defined.

  In addition, it is assumed that the HBA and peripheral devices corresponding to the PCI_Express bus standard can support these three types of link speeds (the same applies hereinafter).

  Here, FIG. 4 is a block diagram illustrating speed setting of the PCIe bus when the link speed is adjusted in the data communication apparatus 10 according to the present embodiment.

  As shown in FIG. 4, in the data communication apparatus 10 according to the present embodiment, when the link speed is adjusted, the PCIe switch 12 is, for example, downstream with the SAS_HBA 13 mounted (connected) in the PCIe slot 1 It is determined that the buffer usage rate when transmitting and receiving data to the port (dotted line portion connected to PCIe slot 1 in the figure) is low, and the transfer rate is changed from 8 Gbps to the slowest 2.5 Gbps. A link has been established.

  In the data communication apparatus 10 according to the present embodiment, when the link speed is adjusted, the PCIe switch 12 is connected to, for example, the downstream port (in the figure, the FC_HBA 14 mounted (connected) in the PCIe slot 2). It is determined that the usage rate of the buffer for transmitting or receiving data to the PCIe slot 2) is relatively high, the speed is changed from 8 Gbps to 5 Gbps, and the link is established at that speed.

  Here, FIG. 5 illustrates an internal configuration of the PCIe switch 12 in the data communication apparatus 10 according to the present embodiment. That is, FIG. 5 is a diagram conceptually showing a state in which the buffer usage rate is monitored in the PCIe switch in the data communication apparatus 10 according to the present embodiment.

  In FIG. 5, the PCIe switch 12 has a microcontroller 101. The microcontroller 101 includes a buffer monitoring unit 102 and a link control unit 103.

  The PCIe switch 12 includes an upstream port 104 (hereinafter abbreviated as “UP104”), a downstream port (# 1) 107 (hereinafter abbreviated as “DP107”), and a downstream port (# 2). 110 (hereinafter abbreviated as “DP110”).

  The UP 104 includes a transmission buffer 105 and a reception buffer 106. The DP 107 includes a transmission buffer 108 and a reception buffer 109. The DP 110 includes a transmission buffer 111 and a reception buffer 112.

  Further, the microcontroller 101 uses the link control unit 103 to designate the link speed and the number of lanes in the UP 104, DP 107, and DP 110.

  Then, the microcontroller 101 uses the buffer monitoring unit 102 to monitor the buffer usage rate in the transmission buffer and the reception buffer of each port at a predetermined interval.

  Here, the microcontroller 101 changes the link speed and the number of lanes in the UP and each DP according to the buffer usage rates of the UP 104 obtained from the buffer monitoring unit 102 and the respective transmission and reception buffers at the DP 107 and DP 110 ports. To do.

  The monitoring of the buffer usage rate in the buffer monitoring unit 102 and the control of the link speed and the number of lanes in the link control unit 103 are, for example, lowering the link speed and the number of lanes if the buffer usage rates in the transmission and reception buffers are low. If the buffer usage rate of either the transmission or reception buffer is high, monitoring and control are performed to increase (increase) the link speed and the number of lanes.

  Next, the operation of the data communication apparatus 10 in the present embodiment will be described using the flowcharts shown in FIGS.

  FIG. 6 is a flowchart showing the control when the link speed adjustment process is performed in the data communication apparatus 10 according to the present embodiment.

  FIG. 7 is a flowchart showing the control (processing procedure) when performing the lane number changing process in the data communication apparatus 10 according to the present embodiment.

  Referring to the link speed adjustment process shown in FIG. 6, when the data communication apparatus 10 is activated and the CPU 11 starts up, the state machine (not shown) that initializes the PCIe switch 12 is released from the reset state. At the same time, the microcontroller 101 included in the PCIe switch 12 is operated (step S_A0).

  The microcontroller 101 executes link training for establishing a physical layer connection in the PCIe bus in each lane of each port in the PCIe device connected to the PCIe switch 12.

  The PCIe switch 12 then links up (i.e., links up) with the maximum transfer rate (e.g., 8 Gbps) and the maximum number of links (e.g., 32) at which each lane in the UP and DP ports can operate. Is established) (step S_A1).

  Then, the microcontroller 101 executes the process after step S_A2 in the flowchart showing the link speed adjustment process shown in FIG.

  The microcontroller 101 measures the buffer usage rate and designates a port to be controlled based on the measured result (step S_A3).

  Here, in step S_A3, the following three port designations are sequentially performed with step S_A8. That is, PORT_NUM = 1_Upstream_Port 104, PORT_NUM = 2_Downstream_Port 107, and PORT_NUM = 3_Downstream_Port 110.

  Note that the order of the ports for measuring the buffer usage rate may be, for example, the upstream UP 104, the DP 110 to which the disk array device is connected, and the DP 107 to which the tape storage device is connected in descending order of load.

  Then, the microcontroller 101 measures the buffer usage rates in the transmission and reception buffers for the designated ports described above (step S_A4).

  Next, the microcontroller 101 disables the error detection circuit in the PCIe bus when the result measured in step S_A4 indicates that the buffer usage rate in the transmission and reception buffers is, for example, 30% or less (step S_A4). S_A51), the link speed is lowered by one step (slowed down), and the link is re-established (step S_A61).

  In this link speed change process, the microcontroller 101 issues a command for lowering the link speed, for example, by one step in the recovery state in which the link is temporarily set in the electrical idle state and then the link is restored. To re-establish the link. As an example, if a link is currently established at 8 Gbps, the link is changed to 5 Gbps. If the link is currently established at 5 Gbps, it is changed to 2.5 Gbps.

  Note that the reduction speed of the link speed is not limited to one level.

  As shown in FIG. 5, the UP 104, the DP 107, and the DP 110 have an error detection circuit. For example, when changing the link speed or the number of links at each port, the error detection circuit detects the transient state as an error by mistake and temporarily prevents the error from propagating to the upper layer. Is disabled, the link speed and the number of links are changed, and then the error detection circuit is controlled to be enabled again.

  Further, the microcontroller 101 determines that the buffer usage rate is, for example, 31% or more, and if any buffer usage rate in the transmission or reception buffer at that time exceeds 81%, for example, Once the link is idle, the error detection circuit is disabled (disabled, that is, not functioning, the same applies hereinafter) (step S_A52), and the link speed is increased by, for example, one level (increased) to reestablish the link. (Step S_A62).

  Similarly to the above-described speed reduction, the microcontroller 101 issues a command to increase the link speed by one step in the recovery state in which the link is temporarily set in the electrical idle state and then restored. To re-establish the link. As an example, if a link is currently established at 2.5 Gbps, the link is changed to 5 Gbps. If the link is currently established at 5 Gbps, the link is changed to 8 Gbps.

  Note that the link speed increase is not limited to one level.

  The buffer usage rate in the transmission and reception buffers can be a method of averaging the buffer usage rate described later, for example.

  After the link speed is changed (S_A61 and S_S62) and the link is established at the target port, the microcontroller 101 clears the information indicating the error in the error detection circuit, and then enables the error detection circuit. That is, it is made to function (the same applies hereinafter) (step S_A71, step S_A72).

  Then, the microcontroller 101 executes the above-described processing from the upstream port 104 by changing the port number as PORT_NUM = PORT_NUM + 1, and executes, for example, DP 107 and DP 110 in this order (step S_A8).

  Then, after performing the lane number changing process shown in FIG. 6, the microcontroller 101 puts, for example, a 10-second wait (step S_10), and again at the upstream port (that is, PORT_NUM = 1). The link speed adjustment processing is performed from S_A2, and thereafter, transmission and reception buffer usage rates are monitored and control based on the monitoring results is repeatedly performed.

  Note that the wait may be any number of seconds other than 10 seconds, as long as the buffer usage rate can be monitored at predetermined intervals.

  Further, for example, when the processing in the DP 110 is finished and the processing in all the ports is finished (that is, when PORT_NUM = 4), the microcontroller 101 continues the lane number changing process shown in FIG. 6 (step S_A9). .

  Here, the lane number changing process shown in FIG. 7 will be described. In the lane number changing process, the power consumption consumed by the PCIe switch in the data communication apparatus can be further reduced by executing the lane number changing process after the link speed adjusting process shown in FIG. 6 described above. is there.

  First, after the link speed adjustment process shown in FIG. 6 is completed for each port, step S_A9 in the link speed adjustment process is executed. That is, the lane number changing process in step S_A9 executes the control in the flowchart shown in FIG. 7 as a process following the link speed adjustment process.

  The microcontroller 101 executes the processes after step S_B2 in the flowchart representing the lane number changing process shown in FIG.

  Then, the microcontroller 101 measures the buffer usage rate and designates a port to be controlled based on the measured result (step S_B3).

  Here, in step S_B3, the following three port designations are sequentially performed with step S_B8. That is, PORT_NUM = 1_Upstream_Port 104, PORT_NUM = 2_Downstream_Port 107, and PORT_NUM = 3_Downstream_Port 110.

  Note that the order of the ports for measuring the buffer usage rate may be, for example, the upstream UP 104, the DP 110 to which the disk array device is connected, and the DP 107 to which the tape storage device is connected in descending order of load.

  Then, the microcontroller 101 measures the buffer usage rates in the transmission and reception buffers for the designated ports described above (step S_B4).

  Next, the microcontroller 101 disables the error detection circuit in the PCIe bus when the result of measurement in step S_B4 indicates that either of the buffer usage rates is 30% or less, for example (step S_B51). Then, the number of lanes is reduced by one level (for example, halved), and the link is reestablished (step S_B61).

  In this lane number changing process, the microcontroller 101 uses a command to reduce the number of lanes, for example, by one step in the recovery state in which the link is temporarily set in the electrical idle state and then restored. Re-establish the link by issuing As an example, if a link is currently established with 8 lanes, the link is changed to 4 lanes. If the link is currently established in 4 lanes, it is changed to 2 lanes.

  Note that the amount of lane reduction is not limited to one level.

  Further, the microcontroller 101 determines that the buffer usage rate is, for example, 31% or more, and if any buffer usage rate in the transmission or reception buffer at that time exceeds 81%, for example, The link is once idled, the error detection circuit is disabled (step S_B52), the number of lanes is increased by one level (for example, doubled), and the link is reestablished (step S_B62).

  Similarly to the above-described lane number reduction, the microcontroller 101 sets a command to increase the number of lanes by one step in the recovery state in which the link is temporarily set in the electrical idle state and then restored. Re-establish the link by issuing As an example, if a link is currently established in 2 lanes, the link is changed to 4 lanes. If the link is currently established with 4 lanes, the lane is changed to 8 lanes.

  Note that the increase in the number of lanes is not limited to one stage.

  Then, the microcontroller 101 changes the link speed (S_B61 and S_B62), and after the link is established in the target port, clears information indicating an error in the error detection circuit, and then enables the error detection circuit. (Step S_B71, Step S_B72).

  The microcontroller 101 executes the above-described process from UP 104 by changing the port number as PORT_NUM = PORT_NUM + 1, and executes, for example, DP 107 and DP 110 in this order (step S_B 8).

  Then, when the processing in the DP 110 is finished and the processing in all the ports is finished (that is, when PORT_NUM = 4), the microcontroller 101 continues the link speed adjustment processing shown in FIG. 6 (step S_A2).

  Further, the transmission and reception buffer usage rate in the PCIe switch 12 shown in FIG. 5 is, for example, that if the buffer usage rate is, for example, 30% or less, the buffer usage rate is low. In addition, if the buffer usage rate is 81% or more, for example, the buffer usage rate is high, and the link speed is increased or the number of lanes is increased.

  However, since the amount of data in the transmission and reception buffers changes dynamically, the buffer usage rate varies. Therefore, the buffer usage may be averaged, the buffer usage rate may be obtained based on the averaged buffer usage, and a determination may be made based on a predetermined threshold.

  More specifically, the microcontroller 101 in the PCIe switch 12 shown in FIG. 5 divides the sizes in the transmission and reception buffers of the UP 104, DP 107, and DP 110, which are buffers, into 10 equal parts, for example. .

  Then, the microcontroller 101, for example, every 100 ms (milli_second), for example, for 1 second (that is, 10 times), in the divided buffer, when data is accumulated from the one with less data, if the state of 3 or less continues, The buffer usage rate may be 30% or less.

  In addition, the microcontroller 101, for example, every 100 ms, for example, for 1 second (that is, 10 times), in the divided buffer, if data is accumulated from the one with the smallest amount, if the state of 8 or more continues, the buffer usage rate May be 81% or more.

  In this case, the link speed and the number of lanes are monitored so that the buffer usage rate is monitored, the buffer usage rate is monitored, the buffer usage rate is monitored, and the buffer usage rate is monitored (for example, In the size of the buffer divided into 10 equal parts, the capacity when data is stored from the smaller one (for example, the third and eighth thresholds from the bottom) is appropriately changed based on the rate of change in the buffer usage rate. do it.

  In addition, the rate of change in the buffer usage rate may be obtained by, for example, obtaining the rate of change when data is stored from the side with the smaller amount of data in the unit time, with the period for monitoring the buffer usage rate being a unit time.

  Note that the above-described monitoring interval, the number of times, and the threshold value for determining the buffer usage rate are examples, and are not limited to these numerical values.

  Here, FIG. 8 is a diagram illustrating a case where power consumption in the data input / output unit is reduced as a result of performing the link speed adjustment processing in the data communication apparatus 10 according to the present embodiment.

  As described above, the data communication apparatus 10 according to the present embodiment adjusts the link speed and the number of lanes according to the buffer usage rate (data communication amount) in each port, and thus consumes more power than necessary. Can be prevented.

  That is, as shown in FIG. 8, the effect of reducing the power consumption when the PCIe switch 12 in this embodiment is used is compared to the case where all the ports are operated with 8 Gbsp and 8 lanes, for example. By reducing the data rate in a circuit (not shown) that converts between parallel data and serial data for each lane at each port when the link speed is adjusted (decreased), the consumption in that circuit Since power can be reduced, total power consumption can be reduced by about 30%.

  Furthermore, if the number of lanes is reduced (not shown), the effect of reducing power consumption is the effect of changing the number of lanes compared to the case where all ports are operated at 8 Gbsp, for example, and 8 lanes. By suspending a circuit (not shown) that performs conversion between parallel data and serial data for each lane at each port in the case of (reduced), power consumption in the circuit can be further reduced. Therefore, the total power consumption can be reduced by about 60% including the case where the link speed is adjusted.

  The power consumption in each lane is calculated using, for example, the following values described in “Minimizing_PCI_Express_Power_Consumption” published by PCI_SIG as reference values.

  That is, the power consumption at 2.5 GT / s (Giga_Transfer_per_second) _Switecs is 100-150 mW / lane, the power consumption at 5 GT / s_Swithecs is 150-200 mW / lane, and the power consumption at 8 GT / s_Swithecs is _300 mW / Lane.

  In this embodiment, the link speed adjustment process is described with the link speed to be changed as one stage. However, the link speed adjustment process is changed in two or more stages including the minimum speed or the maximum speed based on the increase / decrease change amount of the buffer usage rate. It is also possible to adopt a configuration that allows this.

  Similarly, in the lane number changing process, the number of lanes to be changed has been described as one stage. However, based on the increase / decrease change amount of the buffer usage rate, it is possible to change the number of lanes in two or more stages including the minimum number or the maximum number. It is also possible to take

  As described above, according to the present embodiment, the power consumed by the data bus can be appropriately reduced according to the buffer usage rate in the data buffer.

  Note that the link speed adjustment process and the lane number change process can be applied between devices using the PCI_Express standard because a command conforming to the PCI_Express standard can be used.

  The link speed is, for example, an upper limit of 8 Gbps and a lower limit of 2.5 Gbps. Therefore, if the current link speed is 8 Gbps or 2.5 Gbps, the link speed may be increased to the upper limit or higher regardless of the buffer usage rate. In this case, the upper limit link speed or the lower limit link speed is maintained.

  Similarly, since the upper limit is 32 and the lower limit is 1, for example, if the current number of lanes is 32 or 1, the number of lanes can be increased to the upper limit or the lower limit regardless of the buffer usage rate. In this case, the upper limit number or the lower limit number is maintained.

  As described above, the configuration and operation described above have been described as examples of the third embodiment of the present invention. However, the present invention described by using this embodiment as an example is not necessarily limited to the configuration and operation.

(First example of the third embodiment)
Next, a first example of the third embodiment based on the third embodiment will be described with reference to FIGS. In the third embodiment, it has been described that the function for realizing the link speed adjustment process and the lane number changing process is implemented in the PCIe switch 12.

  In the first example of the present embodiment, the present invention can also be implemented for the PCI_Express bus (PCIe bus, not shown) in the RC built in the CPU 11 shown in FIG.

  Therefore, in the following description, the characteristic part according to the present embodiment will be mainly described, and the same configuration as that of the above-described third embodiment will be described by giving the same reference numerals to duplicate description. Omitted.

  In the first embodiment, instead of using the dedicated microcontroller 101 as shown in FIG. 5, the CPU itself has, for example, firmware (Firm_Ware (hereinafter abbreviated as “FW”) control executed by the CPU itself. The buffer usage rate in the PCIe bus is monitored, and link speed adjustment processing and lane number change processing are performed.

  Thereby, in the LAN card 15 shown in FIG. 3, for example, the link speed can be adjusted or the number of lanes can be changed based on the buffer usage rate in the PCIe bus of the RC in the CPU 11.

  This example is based on the first to third embodiments. Therefore, the present embodiment has the same effects as those of the first to third embodiments.

  That is, according to the present embodiment, in the RC built in the CPU or the PCIe switch connected to the RC via the PCIe bus, the power consumed by the data bus is appropriately set according to the buffer usage rate in the data buffer. Can be reduced.

  As mentioned above, as the first example of the third embodiment of the present invention, the above-described configuration and operation have been described as examples. However, the present invention described as an example of this example is not necessarily limited to such configurations and operations. It is not limited.

(Second example of the third embodiment)
Next, a second example of the third embodiment based on the third embodiment will be described with reference to FIGS.

  In the second example of the present embodiment, the host bus adapters (HBAs) 13 and 14 shown in FIG. 3 have a PCIe bus as an upstream and a LAN interface as a downstream, and a communicable LAN interface. The third embodiment is different from the first embodiment in that it is connected to an external device having, for example, a network storage device.

  In other words, even in a configuration having an HBA that controls peripheral devices via a LAN, the link speed and the number of lanes are changed according to the buffer usage rate in the PCIe bus in the upstream to which the PCIe bus in the HBA is connected. Is possible.

  As an example, it is also possible to apply an upstream device that conforms to the ExpEther (Express Ether) standard using the PCIe bus in the upstream and the LAN in the downstream. .

  Thus, the second embodiment can use a peripheral device corresponding to the ExpEther standard while reducing power consumption in a data communication apparatus in an office, for example.

  This example is based on the first to third embodiments. Therefore, the present embodiment has the same effects as those of the first to third embodiments.

  That is, according to the present embodiment, it is possible to appropriately reduce the power consumed by the data bus in accordance with the buffer usage rate in the data buffer.

  As described above, the configuration and operation described above are described as examples as the second example of the third embodiment of the present invention. However, the present invention described as an example of this example is not necessarily limited to the configuration and operation. It is not limited.

<Fourth Embodiment>
Next, a fourth embodiment based on the first to third embodiments will be described with reference to FIG. FIG. 9 is a block diagram illustrating a configuration when the information processing apparatus 300 realizes the function (FIG. 3) in the data communication apparatus 10 according to the third embodiment. That is, FIG. 9 is a diagram illustrating a configuration in which a program that performs link speed adjustment processing and lane number change processing operates in the information processing apparatus in the data communication apparatus according to the present embodiment.

  The data communication apparatus according to the present embodiment performs the functions and processes in the third embodiment with the CPU in the information processing apparatus 300, an operating system (hereinafter referred to as “OS”), and an application (hereinafter referred to as “AP”). And a software (Software: abbreviated as “SW”).

  Referring to FIG. 9, an information processing apparatus 300 according to the present embodiment includes a CPU 301, a memory 302, a PCIe switch processing program 303, a nonvolatile main storage device 304, and application software (AP_SW). A storage medium reader / writer 305, a data bus 306, a communication interface 307, an input / output controller and PCIe switch 308, a display 309, and a storage medium 310.

  In the present embodiment, the information processing apparatus 300 includes the CPU 301 included in the information processing apparatus 300 illustrated in FIG. 9 and the functions illustrated in the block diagram illustrated in FIG. 3 and the processes illustrated in the flowcharts illustrated in FIGS. This is realized by cooperation of an OS that is software operating in the CPU 301 and a PCIe switch processing program 303 that is a computer program developed in the memory 302.

  In this embodiment, as an example, a computer program for realizing a database device based on the data communication device 10 according to the third embodiment by the information processing device 300 will be described.

  However, the present invention is not limited to the above-described apparatus configuration. For the first and second application examples in the third embodiment, the above-described PCIe switch processing program 303 and a database program 318 described later are appropriately used. By modifying, various information processing apparatuses using the data communication apparatus 10 can be realized by the information processing apparatus 300 using a computer program.

  The database program 318 in the memory 302 is a program for causing the information processing apparatus 300 to operate as a database apparatus using a data communication apparatus. For example, the CPU 11 in the above-described third embodiment performs the data communication apparatus 10. Corresponds to the program that controls

  Next, the PCIe switch processing program 303 in the data communication apparatus by the information processing apparatus 300 will be described. The PCIe switch processing program 303 corresponds to, for example, processing performed by the microcontroller 101 illustrated in FIG. 5 in the third embodiment described above.

  The PCIe switch processing program 303 in the information processing apparatus 300 includes processing programs of a link speed adjustment process 311 and a lane number change process 312 as processing functions.

  The link speed adjustment process 311 and the lane number change process 312 in the PCIe switch process program 303 execute processes corresponding to the flowcharts illustrated in FIGS. 6 and 7 described in the third embodiment, respectively.

  Note that the description of the operation using the flowcharts for realizing the above-described processes has been described in the third embodiment, and thus the description in the present embodiment is omitted.

  In addition, the information processing apparatus 300 includes a storage medium reader / writer 305 that reads and writes the PCIe switch processing program 303 from the outside in the form of a file or data, and various input / outputs that the information processing apparatus 300 includes under the control of the OS in cooperation with the CPU 301. An input / output controller and PCIe switch 308 for controlling input / output of data, a data bus 306 capable of exchanging data with an external device (not shown, the same applies hereinafter), and also capable of data communication with the external device. A communication interface 307.

  Note that the host bus adapter (SAS) 313 uses SAS as an interface, and can be connected to, for example, a tape device device. Further, the host bus adapter (FC) 314 uses FC as an interface, and for example, can connect a disk array device or the like.

  The PCIe switch processing program 303 and the database program 318 are firmware (FW) for controlling the information processing apparatus 300 as a database apparatus in a Read_Only_Memory (hereinafter abbreviated as “ROM”) or the like (not shown). May be stored.

  An operator who operates the data communication apparatus is connected to the host bus adapter (SAS) 313 or the host bus adapter (FC) 314 connected to the input / output controller and the PCIe switch 308 using, for example, the display 309. For example, it is possible to monitor the operation of a tape device device, a disk array device, or the like.

  At that time, the operator combines the link speed and the number of lanes in the host bus adapter (SAS) 313 and the host bus adapter (FC) 314 connected to the input / output controller and the PCIe switch 308 on the display 309. It is possible to manage the operational status of the database device.

  In addition, the information processing apparatus 300 according to the present embodiment is a computer program that can implement the flowcharts (FIG. 6 and FIG. 7) representing the control in the PCIe switch 12 in the above-described data communication apparatus 10 (FIG. 3). , And supplied as a PCIe switch processing program 303).

  Then, the CPU 301 prepared as a control method as the database device by the information processing apparatus 300 and the cooperative OS, and the PCIe switch processing program 303 are read into the memory 302 and executed in the third embodiment. Operation | movement of the data communication apparatus 10 demonstrated by the form is achieved.

  In addition, the above-described computer program supply method to the information processing apparatus 300 includes a disk medium such as a floppy (registered trademark) disk or a CD-ROM (Compact_Disc-Read_Only_Memory) and a universal serial bus (Universal_Serial_Bus: hereinafter “USB”). A method of installing the information processing apparatus 300 using the storage medium reader / writer 305 through various computer-readable storage media 310 such as a memory medium such as a memory can be employed.

  In addition, the above-described computer program supply method to the information processing apparatus 300 can be installed from an external device via the data bus 306, or can be wired or wirelessly communicated using the communication interface 307. Currently, a general procedure can be employed, such as a method of downloading from an external device via a communication line.

  In such a case, the present embodiment can be considered to be configured by a computer-readable storage medium 310 in which the code constituting the computer program or the code is recorded.

  Further, the database apparatus using the general-purpose information processing apparatus 300 may be realized by a dedicated apparatus.

  This embodiment is based on the third embodiment. Therefore, this embodiment has the same effects as those of the third embodiment.

  That is, according to the present embodiment, the power consumed by the data bus can be appropriately reduced according to the buffer usage rate in the data buffer of the PCIe bus included in the input / output controller included in the information processing apparatus 300 and the PCIe switch 308. it can.

  As mentioned above, although the structure and operation | movement mentioned above were demonstrated as an example as 4th Embodiment of this invention, this invention demonstrated using this this embodiment as an example is not necessarily limited to the said structure and operation | movement.

  The present invention is not limited to the above-described embodiments. For example, the buffer usage rate is monitored in the data transmission buffer and the data reception buffer in each port constituting the high-speed serial communication bus such as a PCI_Express switch. Accordingly, the present invention can be applied to an information processing apparatus that controls to adjust the link speed and the number of lanes.

DESCRIPTION OF SYMBOLS 1 Data communication apparatus 2 Control part 3 Communication buffer 4 Data bus 5 External apparatus 10 Data communication apparatus 11 CPU
12 PCIe switch 13 Host Bus Adapter (SAS)
14 Host bus adapter (FC)
15 LAN card 16 Tape device 17 Disk array 18 Communication network 30 Communication buffer 50 Data bus switch 51 Upstream port 52 Transmission buffer 53 Reception buffer 61 Downstream port (# 1)
62 Transmission buffer 63 Reception buffer 71 Downstream port (# 2)
72 Transmission buffer 73 Reception buffer 80 Buffer monitoring unit 90 Link control unit 101 Microcontroller 102 Buffer monitoring unit 103 Link control unit 104 Upstream port 105 Transmission buffer 106 Reception buffer 107 Downstream port (# 1)
108 Transmission buffer 109 Reception buffer 110 Downstream port (# 2)
111 Transmission Buffer 112 Reception Buffer 300 Information Processing Device 301 CPU
302 Memory 303 PCIe switch processing program 304 Non-volatile main storage device 305 Storage medium reader / writer 306 Data bus 307 Communication interface 308 Input / output controller and PCIe switch 309 Display 310 Storage medium 311 Link speed adjustment process 312 Lane number change process 313 Host bus adapter (SAS)
314 Host bus adapter (FC)
318 Database program

Claims (10)

A communication buffer used when performing data communication through the data bus, and a control unit that controls data communication by the data bus to which the communication buffer is connected;
The controller is
If the buffer usage rate representing the proportion of data in the communication buffer does not exceed the first usage rate, reduce the data rate in the currently connected data bus and the number of lanes constituting the data bus,
The data communication apparatus according to claim 1, wherein when the buffer usage rate exceeds a second usage rate that is greater than the first usage rate, the data rate and the number of lanes in the currently connected data bus are increased.   In the communication buffer, the control unit includes an upstream port connected to the data bus connecting the communication buffer and the first data communication device, a communication buffer different from the communication buffer, and second data. 2. The data communication according to claim 1, wherein a buffer usage rate in the communication buffer of a downstream port connected to a data bus different from the data bus connected to the communication device is monitored. apparatus.   The control unit, according to a result of monitoring the buffer usage rate, a link speed, which is a data speed when transferring data between the upstream port and the downstream port, and the up rate 3. The data communication apparatus according to claim 1, wherein the number of lanes representing the number of links of 1 or more is changed between a stream port and a partner to which the downstream port is connected. The communication buffer includes a transmission buffer and a reception buffer,
The controller is
When the buffer usage rate in the communication buffer does not exceed the first usage rate for both the transmission buffer and the reception buffer, the data bus at the first data rate is slower than the data rate at the currently connected data bus. Establish data communication,
When the buffer usage rate of at least one of the communication buffers exceeds a second usage rate that is greater than the first usage rate, the second data rate is higher than the data rate of the currently connected data bus. Establish data communication on the data bus,
If both of the buffer usage rates in the communication buffer do not exceed the first usage rate even at the first data rate, the number of lanes is smaller than the number of lanes constituting the currently connected data bus. Establish data communication on the bus,
When the buffer usage rate of at least one of the communication buffers exceeds the second usage rate even at the second data rate, the number of lanes larger than the number of currently connected lanes is used. 4. The data communication apparatus according to claim 2, wherein data communication is established. The controller is
The time required for both the transmission buffer and the reception buffer to occupy the capacity corresponding to the first usage rate in a buffer area formed by the transmission buffer and the reception buffer respectively included in the upstream port and the downstream port to be monitored is predetermined. When monitoring at a time interval of a predetermined number of times, it is determined that the usage rate of the communication buffer in the upstream port and the downstream port is low,
A case in which at least one of the transmission buffer and the reception buffer occupies a capacity corresponding to a second usage rate larger than the first usage rate continues a predetermined number of times when monitored at the predetermined time interval The data communication apparatus according to any one of claims 2 to 4, wherein it is determined that a usage rate of a communication buffer in the upstream port and the downstream port is high. The controller is
The predetermined time interval for monitoring the buffer usage rate in the transmission buffer and the reception buffer of the upstream port and the downstream port to be monitored, the period for monitoring the buffer usage rate, the upstream port, and The capacity corresponding to the first usage rate and the capacity corresponding to the second usage rate larger than the first usage rate in the areas formed by the transmission buffer and the reception buffer respectively included in the downstream port are the buffer usage rate. The data communication device according to claim 2, wherein the data communication device is changed according to a change rate representing a change. The controller is
5. The data communication apparatus according to claim 3, wherein at least one of the predetermined link speed and the number of lanes is increased or decreased according to the buffer usage rate. 6.   The first data communication device is a route complex conforming to the PCI_Express standard or a central processing device incorporating the route complex, and the second data communication device is a PCI_Express bus and peripheral devices that are endpoints conforming to the PCI_Express standard The data communication apparatus according to claim 1, wherein the data communication apparatus is a host bus adapter that converts a data communication format with a peripheral bus that connects the two. When controlling the data bus to which the communication buffer used when performing data communication through the data bus is controlled by the control means for controlling the data communication,
By the control means,
If the buffer usage rate representing the proportion of data in the communication buffer does not exceed the first usage rate, reduce the data rate in the currently connected data bus and the number of lanes constituting the data bus,
When the buffer usage rate exceeds a second usage rate that is greater than the first usage rate, the data rate and the number of lanes in the currently connected data bus are increased. . A computer program for controlling a data communication apparatus having a data bus to which a communication buffer used when performing data communication through a data bus is connected, and the computer program
If the buffer usage rate representing the proportion of data in the communication buffer does not exceed the first usage rate, reduce the data rate in the currently connected data bus and the number of lanes constituting the data bus,
When the buffer usage rate exceeds a second usage rate that is greater than the first usage rate, a process of increasing the data speed and the number of lanes in the currently connected data bus,
A computer program to be realized by a computer.