JP2014077997A - Sequential circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose a display device which can achieve reduction of power consumption or improvement in reliability.SOLUTION: A plurality of transistors are used for a sequential circuit, the transistors having an S value of 0.7 V/decade or less, preferably 0.5 V/decade or less, and the same channel type. Reducing an S value to 0.7 V/decade or less, furthermore 0.5 V/decade or less makes it possible to secure normally-off characteristics while lowering a threshold voltage, so that the lowest driving voltage of the sequential circuit can fall within the range of 11 V or more and 16 V or less, furthermore 11 V or more and 13 V or less.

Description

The present invention relates to a semiconductor device such as a sequential circuit using a unipolar transistor and a display device using the sequential circuit.

Display devices such as liquid crystal display devices and EL display devices are preferably composed of unipolar transistors rather than CMOS in order to reduce the cost of the backplane (circuit board). The following Patent Document 1 and Patent Document 2 disclose a technique in which various circuits such as an inverter and a shift register, which are used in a driving circuit of a display device, are configured with unipolar transistors.

JP 2001-325798 A JP 2010-277852 A

Incidentally, low power consumption is an important point in evaluating the performance of a display device. In particular, in the case of a portable electronic device such as a mobile phone, the high power consumption of the display device leads to a demerit of shortening the continuous use time, and thus it is strongly required to reduce the power consumption. In addition, ensuring high reliability is also important in realizing commercialization of display devices.

In view of the above-described technical background, an object of the present invention is to propose a display device capable of reducing power consumption or improving reliability.

In order to achieve low power consumption and high reliability of the display device, the power supply voltage and signal voltage applied to the driver circuit are set to such an extent that a voltage necessary for operating a display element such as a liquid crystal element can be secured. It is considered desirable to keep it low. The voltage necessary for operating the display element depends on the liquid crystal material used for the liquid crystal element, the size of the capacitor of the pixel portion, the driving method of the liquid crystal, and the like. In order to realize low power consumption and high reliability, the voltage required for the operation of the drive circuit (hereinafter referred to as the minimum drive voltage) is in the range of 11V to 16V, preferably 11V to 13V. , It is required to lower.

In the case of a sequential circuit including unipolar transistors, the potentials of various nodes in the sequential circuit drop by the threshold voltage of the transistor. Therefore, it is necessary to add in advance a voltage comparable to the threshold voltage to the lowest drive voltage of the sequential circuit. Therefore, in the case of a sequential circuit composed of unipolar transistors, it is necessary to reduce the threshold voltage of the transistors in order to reduce the minimum drive voltage.

However, in the case of a transistor having a large S value (subthreshold swing value), if the threshold voltage is lowered, the off-state current that flows when the gate voltage is 0 V tends to be normally on. It becomes difficult to operate. Therefore, in order to reduce the minimum drive voltage while ensuring the normal operation of the sequential circuit, not only lowering the threshold voltage of the transistor but also reducing the S value to such an extent that the transistor is normally off. This is very important.

Thus, according to one embodiment of the present invention, a plurality of transistors having S values of 0.7 V / decade or less, preferably 0.5 V / decade or less and having the same channel type are used for sequential circuits. . By setting the S value to 0.7 V / decade or less, and further to 0.5 V / decade or less, the threshold voltage can be lowered while ensuring normally-off characteristics, and the minimum drive voltage of the sequential circuit is 11 V or more. It can be set to 16V or less, or more than 11V to 13V.

In addition, a transistor whose S value falls within the above range is quickly switched between a conductive state and a non-conductive state, and therefore has a period in which it is in a transitional state from a conductive state to a non-conductive state or from a non-conductive state to a conductive state. Therefore, power loss due to switching can be suppressed to a small value.

Since a transistor having a channel formation region in an oxide semiconductor film tends to have a lower S value than a transistor having a channel formation region in an amorphous silicon film or a polysilicon film, the S value can fall within the above range. . Thus, a transistor including a channel formation region in an oxide semiconductor film is suitable for use in the sequential circuit or the display device according to one embodiment of the present invention.

Specifically, a sequential circuit according to one embodiment of the present invention includes a first wiring to which a clock signal is supplied, a first transistor that controls electrical connection between the second wiring, a second wiring, and a low-level circuit. Controls electrical connection between the second transistor for controlling electrical connection with the third wiring to which the first potential is applied, the gate of the first transistor, and the fourth wiring to which the second electric potential at the high level is applied. And a fourth transistor for controlling electrical connection between the gate of the first transistor and the fifth wiring to which the first potential is applied. The first to fourth transistors are oxides. A semiconductor is included in the channel formation region, and the S value of the transistor is 0.7 V / decade or less.

In one embodiment of the present invention, a sequential circuit with reduced power consumption or a display device using the sequential circuit can be realized with the above structure.

FIG. 4 illustrates a sequential circuit of Embodiment 1. 4A and 4B illustrate a transistor of Embodiment 1; FIG. 6 illustrates a sequential circuit and a shift register in Embodiment 2. FIG. 6 illustrates an operation of a shift register circuit in Embodiment 2. The figure which shows the result of simulation. The figure which shows the structure of the sequential circuit used for simulation. The figure which shows the result of simulation. The figure which shows the result of simulation. The figure which shows the result of simulation. FIG. 6 illustrates a structure of a transistor used for simulation. 10A and 10B illustrate one embodiment of a transistor. The top view and sectional drawing of a liquid crystal display device. Illustration of electronic equipment. The figure which shows the value of the drain current with respect to gate voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that a display device in this specification includes a panel in which a display element such as a liquid crystal element or a light-emitting element is formed in each pixel, and a module in which an IC or the like including a controller is mounted on the panel. Included.

In this specification, connection means electrical connection and corresponds to a state where current, voltage, or a potential can be supplied or transmitted. Therefore, the connected state does not necessarily indicate a directly connected state, and a wiring, a resistor, a diode, a transistor, or the like is provided so that current, voltage, or potential can be supplied or transmitted. The state of being indirectly connected through a circuit element is also included in the category. In addition, even when independent components on the circuit diagram are connected to each other, in practice, for example, when a part of the wiring functions as an electrode, one conductive film has a plurality of components. In some cases, it also has the function of an element. In this specification, the term “connection” includes a case where one conductive film has functions of a plurality of components.

The source of the transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode connected to the semiconductor film. Similarly, a drain of a transistor means a drain region that is part of the semiconductor film or a drain electrode connected to the semiconductor film. The gate means a gate electrode.

The names of the source and the drain of a transistor interchange with each other depending on the polarity of the transistor and the level of potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source, and a terminal to which a high potential is applied is called a drain. In a p-channel transistor, a terminal to which a low potential is applied is called a drain, and a terminal to which a high potential is applied is called a source. In this specification, for the sake of convenience, the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .

In this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

(Embodiment 1)
In this embodiment, the basic principle of the present invention will be described.

In a sequential circuit for driving a display device, in the case where only a unipolar transistor is used, a bootstrap operation is performed so that the output voltage of a transistor functioning as a buffer does not decrease by the threshold voltage of the transistor. A transistor is used.

In order to realize this bootstrap operation, a transistor having a function of applying the first potential VDD by a first signal (set signal, represented by “S” in the figure), and a second signal (reset signal, in the figure) The transistor having a function of applying the second potential VSS is connected to the gate of the transistor functioning as a buffer. The bootstrap operation can be realized by setting the source potential in accordance with the amplitude of the clock signal by setting the transistor functioning as a buffer in a conductive state and then setting the gate of the transistor in a floating state.

As an example, as shown in FIG. 1A, a transistor FET1 functioning as a buffer, a transistor FET2 for fixing a wiring for outputting an output signal OUT to a low level (L), and a first potential at the gate of the transistor FET1 It can be expressed by a transistor FET3 having a function of supplying VDD and a transistor FET4 having a function of supplying the second potential VSS to the gate of the transistor FET1.

One of a source and a drain of the transistor FET1 illustrated in FIG. 1A is connected to a wiring to which a clock signal CLK is supplied, and the other of the source and the drain is connected to a wiring for outputting an output signal OUT. The gate of the transistor FET1 is connected to one electrode of the capacitor C1, and the other of the source and the drain is connected to the other electrode of the capacitor C1.

One of a source and a drain of the transistor FET2 illustrated in FIG. 1A is connected to a wiring for outputting the output signal OUT, and the other of the source and the drain is connected to a wiring to which a second potential VSS is applied. Further, the first potential VDD or the second potential VSS is applied to the gate of the transistor FET2, and the conduction state of the transistor FET2 is controlled.

One of the source and the drain of the transistor FET3 illustrated in FIG. 1A is connected to a wiring to which the first potential VDD is applied, and the other of the source and the drain is connected to the gate of the transistor FET1. The gate of the transistor FET3 is connected to a wiring to which the first signal S is applied. Note that the transistor FET3 illustrated in FIG. 1A may have a structure in which a potential corresponding to the first potential VDD is applied to the gate of the transistor FET1 as a diode-connected transistor.

One of a source and a drain of the transistor FET4 illustrated in FIG. 1A is connected to the gate of the transistor FET1, and the other of the source and the drain is connected to a wiring to which the second potential VSS is applied. The gate of the transistor FET4 is connected to a wiring to which the second signal R is applied.

Note that FIG. 1A illustrates a structure in which one of the source and the drain of the transistor FET1 is connected to a wiring to which the clock signal CLK is supplied; however, the structure is connected to a wiring to which the first potential VDD is applied. There may be. Further, the FET1 to FET4 may be provided in a single number, or a plurality of FET1 to FET4 may be provided in series or in parallel.

Note that as an example of a configuration for applying the first potential VDD or the second potential VSS to the gate of the transistor FET2 in FIG. 1A, as shown in FIG. 1B, the first potential VDD is applied to the gate of the transistor FET2. A configuration in which a transistor FET5 having a function of supplying VDD and a transistor FET6 having a function of supplying a second potential VSS to the gate of the transistor FET2 are provided.

One of the source and the drain of the transistor FET5 illustrated in FIG. 1B is connected to a wiring to which the first potential VDD is applied, and the other of the source and the drain is connected to the gate of the transistor FET2. The gate of the transistor FET5 is connected to a wiring to which the second signal R is applied. Note that the transistor FET5 illustrated in FIG. 1B may have a structure in which a potential corresponding to the first potential VDD is applied to the gate of the transistor FET2 as a diode-connected transistor.

One of the source and the drain of the transistor FET6 illustrated in FIG. 1B is connected to the gate of the transistor FET2, and the other of the source and the drain is connected to a wiring to which the second potential VSS is applied. The gate of the transistor FET6 is connected to a wiring to which the first signal S is applied.

FIG. 1C illustrates an example of a timing chart of the circuit illustrated in FIG.

First, in the timing chart shown in FIG. 1C, the first signal S is set to a high level (H), and the first potential VDD is applied to the gate of the transistor FET1. Then, the transistor FET1 becomes conductive.

Next, in the timing chart shown in FIG. 1C, the gate of the transistor FET1 is set in a floating state, and the clock signal CLK is changed from a low level (L) to a high level (H). Then, the voltage level of the output signal OUT rises, and with this rise, the voltage level of the gate of the transistor FET1 due to capacitive coupling rises in the capacitive element C1. When the voltage level of the gate of the transistor FET1 to which the increase in voltage level due to capacitive coupling by the capacitive element C1 is added exceeds the high level (H) of the clock signal CLK, the other of the source and drain of the transistor FET1 outputs A high level (H) voltage level is obtained as the signal OUT.

Next, in the timing chart shown in FIG. 1C, the second signal R is set to a high level (H), and the second potential VSS is applied to the gate of the transistor FET1. Then, the transistor FET1 is turned off.

Note that the high level (H) signal is, for example, a signal having the same voltage level as the first potential VDD. The low level (L) signal is, for example, a signal having the same voltage level as the second potential VSS.

Note that the timing chart of the circuit illustrated in FIG. 1B can be described in the same manner as in FIG. The difference between the circuit shown in FIG. 1A and the circuit shown in FIG. 1B is that the conduction state of the transistor FET2, which is a transistor for fixing the voltage level of the output signal OUT to the second potential VSS, It is in the point controlled by FET5 and transistor FET6. The conduction state of the transistor FET2 is controlled by switching the voltage level of the gate of the transistor FET2 by the first signal S and the second signal R applied to the transistor FET5 and the transistor FET6.

The operation of the timing chart shown in FIG. 1C applies a high level (H) or low level (L) signal across the threshold voltage of each transistor shown in FIGS. By controlling the current flowing through the transistor, a desired operation can be performed. On the other hand, the threshold voltage of the transistor shifts due to stress due to the voltage applied to the gate and deterioration of the transistor over time.

When the threshold voltage of this transistor shifts in the negative direction, the transistor is normally on. In particular, a transistor having a large S value is normally on even if the shift amount of the threshold voltage is small. In a sequential circuit composed of normally-on transistors, the amount of current flowing through the controlled transistor changes by applying a high-level (H) or low-level (L) signal, so that a desired output pulse is obtained. Therefore, it is necessary to set a minimum required drive voltage (minimum drive voltage) for driving in advance to be high.

Here, the shift of the threshold voltage in the above-described transistor having a large S value will be described with reference to a schematic diagram. In addition, a shift of the threshold voltage in a transistor having a large S value will be described with reference to a schematic diagram.

In FIG. 2A, the horizontal axis represents the gate voltage Vg, the vertical axis represents the drain current Id, the Vg-Id curve S_b for the transistor with a large S value is a solid line, and the Vg-Id curve S_s for a transistor with a small S value. Is indicated by a dotted line. FIG. 2A shows a Vg-Id curve before the threshold voltage is shifted. In FIG. 2B as well, the Vg-Id curve S_b for a transistor having a large S value is indicated by a solid line, and the Vg-Id curve S_s for a transistor having a small S value is indicated by a dotted line. FIG. 2B shows a Vg-Id curve after the threshold voltage has shifted.

As shown in FIGS. 2A and 2B, a transistor having a small S value can maintain a normally-off state even with the same threshold voltage shift amount, whereas a transistor having a large S value. Then, it turns out that it will be in the state of normally on. In other words, in a sequential circuit composed of transistors having a large S value, the amount of current flowing through the transistor changes due to stress due to the voltage applied to the gate and deterioration of the transistor over time. It needs to be set high.

On the other hand, a transistor having a small S value is provided for each transistor included in the sequential circuit, which is described in this embodiment. A transistor with a small S value is less likely to be normally on than a transistor with a large S value, even if the threshold voltage shifts in the negative direction. For this reason, in a sequential circuit composed of transistors having a small S value, the amount of current flowing through the transistor hardly changes due to stress due to the voltage applied to the gate or deterioration of the transistor over time. It can operate even when it is low.

The sequential circuit that can lower the minimum driving voltage by using a transistor having a small S value is based on the first potential VDD and the second potential VSS in the sequential circuits shown in FIGS. The supplied power supply voltage can be reduced. In addition, the amplitude voltage of the clock signal can be reduced. In addition, the amplitude voltage of the first signal (S) and the second signal (R) can be reduced. Therefore, a sequential circuit using a transistor having a small S value can reduce power consumption.

A transistor having a small S value preferably has a small S value, but it is preferable that the transistor has an optimum range according to the value of the amplitude voltage required for the load (wiring) that outputs a pulse. As a specific range of small S values, 0.7 V / decade or less, and further 0.5 V / decade or less are suitable.

In addition, a transistor having an S value of 0.7 V / decade or less, and further 0.5 V / decade or less is quickly switched between a conduction state and a non-conduction state. The period in the transition state from the conduction state to the conduction state is short, and therefore, power loss due to switching can be suppressed to a small level.

Note that the S value of the transistor can be reduced to some extent by thinning the gate insulating film in advance, but it is not preferable to form the gate insulating film extremely thin in consideration of the breakdown voltage of the transistor or the like. In this embodiment, for example, a transistor having a channel formation region including an oxide semiconductor having a wider band gap than silicon is preferably used as the transistor having a low S value.

By forming a transistor having a small S value using a transistor having an oxide semiconductor in a channel region, a gate insulating film is formed thicker than that of a transistor using silicon such as an amorphous silicon film or a polysilicon film. Also, the S value can be set in the above-described range.

Note that as the oxide semiconductor, for example, an In-based metal oxide, a Zn-based metal oxide, an In—Zn-based metal oxide, an In—Ga—Zn-based metal oxide, or the like can be used. Alternatively, a metal oxide containing another metal element instead of part or all of Ga contained in the In—Ga—Zn-based metal oxide may be used.

As described above, the sequential circuit described in this embodiment can reduce the minimum driving voltage and power consumption by using a transistor with a small S value.

(Embodiment 2)
In this embodiment, a sequential circuit using a transistor with a small S value described in the above embodiment and a shift register using the sequential circuit will be described.

First, a circuit configuration example of a pulse signal output circuit and a shift register including the pulse signal output circuit will be described with reference to FIGS.

Shift register includes a pulse signal output circuit _{10 _N} of the first pulse signal output circuit _{10 _1} to the N, and the signal line 11 to the signal line 14 for transmitting a clock signal CLK, and a (see FIG. 3 (A)) . The signal line 11 is supplied with a clock signal CLK1, the signal line 12 is supplied with a clock signal CLK2, the signal line 13 is supplied with a clock signal CLK3, and the signal line 14 is supplied with a clock signal CLK4.

The clock signal is a signal that repeats a high level (H) and a low level (L) at regular intervals. Here, the clock signals CLK1 to CLK4 are signals delayed by a quarter cycle. In the circuits shown in FIGS. 3A to 3C, the pulse signal output circuit is controlled by using the clock signal. Note that a plurality of clock signals may be further input to the sequential circuit.

The first pulse signal output circuit _{10_1 to} the Nth pulse signal output circuit _{10_N} include an input terminal 21, an input terminal 22, an input terminal 23, an input terminal 24, an input terminal 25, an output terminal 26, and an output terminal, respectively. 27 (see FIG. 3B).

The input terminal 21, the input terminal 22, and the input terminal 23 are connected to any one of the signal lines 11 to 14. For example, in the first pulse signal output circuit _{10_1} , the input terminal 21 is connected to the signal line 11, the input terminal 22 is connected to the signal line 12, and the input terminal 23 is connected to the signal line 13. In the second pulse signal output circuit _{10_2} , the input terminal 21 is connected to the signal line 12, the input terminal 22 is connected to the signal line 13, and the input terminal 23 is connected to the signal line 14. Note that here, the signal lines connected to the Nth pulse signal output circuit _{10_N} are the signal line 12, the signal line 13, and the signal line 14, but the Nth pulse signal output circuit 10_N is shown. _The signal line connected to _{_N} differs depending on the value of N.

In the k-th pulse signal output circuit (k is a natural number of 3 to N) of the shift register shown in this embodiment, the input terminal 24 is connected to the output terminal 26 of the (k−1) -th pulse signal output circuit. The input terminal 25 is connected to the output terminal 26 of the (k + 2) th pulse signal output circuit, the output terminal 26 is connected to the input terminal 24 of the (k + 1) th pulse signal output circuit, and the (k-2) th pulse signal output circuit. The output terminal 27 is connected to the input terminal 25 of the pulse signal output circuit, and outputs a signal to OUT_k.

In the first pulse signal output circuit _{10_1} , the start pulse (SP1) from the signal line 15 is input to the input terminal 24. In the (N−1) th pulse signal output circuit 10 _{_ (N−1)} , the start pulse (SP 2) is input to the input terminal 25. In the Nth pulse signal output circuit _{10_N} , the start pulse (SP3) is input to the input terminal 25. Note that the start pulse (SP2) and the start pulse (SP3) may be signals input from the outside or signals generated inside the circuit.

Next, specific structures of the first pulse signal output circuit _{10_1 to} the Nth pulse signal output circuit _{10_N} are described.

Each of the first pulse signal output circuit _{10_1 to} the Nth pulse signal output circuit _{10_N} includes a transistor 101 to a transistor 111 as illustrated in FIG. In the following description, the gate of a transistor is referred to as a gate terminal, one of the source and the drain is referred to as a first terminal, and the other of the source and the drain is referred to as a second terminal.

A structure of the pulse signal output circuit illustrated in FIG. 3C is described.

The transistor 101 has a first terminal connected to the input terminal 21, a second terminal connected to the output terminal 26, and a gate terminal connected to the second terminal of the transistor 107.

The transistor 102 has a first terminal connected to the output terminal 26, a second terminal connected to the power supply line 31, and a gate terminal connected to the second terminal of the transistor 108.

The transistor 103 has a first terminal connected to the input terminal 21, a second terminal connected to the output terminal 27, and a gate terminal connected to the second terminal of the transistor 107.

The transistor 104 has a first terminal connected to the output terminal 27, a second terminal connected to the power supply line 31, and a gate terminal connected to the second terminal of the transistor 108.

The transistor 105 has a first terminal connected to the power supply line 32, a second terminal connected to the first terminal of the transistor 106 and the first terminal of the transistor 107, and a gate terminal connected to the input terminal 24. Yes.

The transistor 106 has a first terminal connected to the second terminal of the transistor 105 and the first terminal of the transistor 107, a second terminal connected to the power supply line 31, and a gate terminal connected to the second terminal of the transistor 108. Connected with.

The transistor 107 has a first terminal connected to the second terminal of the transistor 105 and the first terminal of the transistor 106, a second terminal connected to the gate terminal of the transistor 101 and the gate terminal of the transistor 103, and a gate terminal. Is connected to the power line 32.

The transistor 108 has a first terminal connected to the second terminal of the transistor 110, and a second terminal connected to the gate terminal of the transistor 102, the gate terminal of the transistor 104, and the gate terminal of the transistor 106. Is connected to the input terminal 22.

The transistor 109 has a first terminal connected to the second terminal of the transistor 108, a second terminal connected to the power supply line 31, and a gate terminal connected to the input terminal 24.

The transistor 110 has a first terminal connected to the power supply line 32, a second terminal connected to the first terminal of the transistor 108, and a gate terminal connected to the input terminal 23.

The transistor 111 has a first terminal connected to the power supply line 32, a second terminal connected to the second terminal of the transistor 108, and a gate terminal connected to the input terminal 25.

Each configuration of the pulse signal output circuit described above is merely an example, and one embodiment of the present invention is not limited thereto.

When the pulse signal output circuit in FIG. 3C is the first pulse signal output circuit _{10_1} illustrated in FIG. 3A, the clock signal CLK1 is supplied to the input terminal 21, and the clock signal CLK2 is input to the input terminal 22. is given, the clock signal CLK3 is supplied to the input terminal 23 is given a start pulse SP1 to the input terminal 24, the input terminal 25, referred to as a third pulse signal output circuit _{10 _3} output signal (SROUT_3 ) Is entered. Further, from the output terminal 26 (referred to as SROUT_1) first pulse signal output circuit _{10 _1} output signal is output to the input terminal 24 of the second pulse signal output circuit _{10 _2,} the output signal OUT_1 is output from the output terminal 27 Is done.

The power supply line 31 is supplied with the second potential VSS, and the power supply line 32 is supplied with the first potential VDD.

Next, operation of the shift register illustrated in FIGS. 3A to 3C is described with reference to a timing chart in FIG. Note that in the timing chart shown in FIG. 4, the transistors 101 to 111 are all n-channel transistors.

During timing chart shown in FIG. 4, CLK1 to CLK4 each represent clock signal, SP1 indicates a start pulse, OUT_1 to OUT_N is a pulse signal output circuit _{10 _N} of the first pulse signal output circuit _{10 _1} through the N shows the output from the output terminal 27, OUT_1 to OUT_N shows the output signal from the first pulse signal output circuit _{10 _1} to the pulse signal output circuit _{10 _N} output terminal 26 of the first N.

As shown in FIG. 4, the shift register using the pulse signal output circuit in FIG. 3C includes a first potential VDD and a second potential VSS, CLK1 to CLK4, a start pulse SP, and output signals SROUT_1 to SROUT_N. Accordingly, desired pulses can be sequentially obtained as output signals OUT_1 to OUT_N.

The sequential circuits described in this embodiment and the transistors 101 to 111 used in the shift register are transistors with low S values as described in Embodiment 1. Therefore, the operation can be performed even if the minimum driving voltage for driving the sequential circuit is low.

A sequential circuit having a low minimum drive voltage using a transistor having a small S value is the power supply voltage given by the first potential VDD and the second potential VSS in the sequential circuits shown in FIGS. Can be reduced. Further, the amplitude voltage of CLK1 to CLK4 can be reduced. Further, the amplitude voltage of the start pulse SP can be reduced. In addition, the amplitude voltage of the output signals SROUT_1 to SROUT_N can be reduced. Therefore, a sequential circuit using a transistor having a small S value can reduce power consumption.

As the transistor having a low S value, for example, a transistor having a channel formation region including an oxide semiconductor having a wider band gap than silicon can be used.

Note that in one embodiment of the present invention, in the structure of the pulse signal output circuit illustrated in FIG. 3C, a back gate may be provided for all the transistors to control the threshold voltage. At this time, the voltage applied to the back gate may be the second potential VSS, the source potential of the transistor, or the gate potential of the transistor. In addition, in order to change the shift amount of the threshold voltage depending on the transistor, the potential applied to the back gate may be different for each transistor.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, the relationship between the S value of a transistor and the minimum drive voltage will be described using simulation results.

First, the relationship between the S value and the threshold voltage Vth for obtaining normally-on characteristics was examined using simulation. A structure of a transistor to be analyzed in the simulation is shown in FIG. A transistor 300 illustrated in FIG. 10 is provided over the gate insulating film 302 in a position overlapping with the conductive film 301 functioning as a gate over the insulating surface, the gate insulating film 302 provided over the conductive film 301, and the conductive film 301. A semiconductor film 303; a conductive film 304 provided over the semiconductor film 303 and functioning as a source electrode; and a conductive film 305 functioning as a drain electrode. In this embodiment, a region which overlaps with the conductive film 301 between the conductive film 304 and the conductive film 305 with the gate insulating film 302 interposed therebetween is defined as a channel formation region 306 in the transistor 300.

Note that the gate voltage Vgs means a voltage of the conductive film 301 functioning as a gate with reference to the potential of the conductive film 304 functioning as a source electrode.

In the transistor 300, the length Lov in the direction in which carriers move in a region where the conductive film 301 overlaps with the conductive film 304 or the conductive film 305 with the gate insulating film 302 and the semiconductor film 303 interposed therebetween is 2 μm. It was. The gate insulating film 302 is assumed to have a relative dielectric constant of 6.4 and a film thickness of 450 nm. Note that the length of the channel formation region in the carrier moving direction is the channel length L, and the length of the channel formation region 306 in the direction perpendicular to the carrier moving direction is the channel width W.

FIG. 5 is a graph showing the relationship between the gate voltage Vgs and the drain current Ids obtained when the S value is 0.3, 0.5, 0.7, 1.2 (V / decade), obtained by simulation. is there. In FIG. 5, the horizontal axis represents the gate voltage Vgs (V), and the vertical axis represents the drain current Ids (A). In FIG. 5, the value of the threshold voltage Vth is also changed in accordance with the value of the S value, and the drain current Ids is set so that the transistor 300 has a normally-off characteristic regardless of which value the S value has. The voltage Vf when rising is set to 0V.

Specifically, the voltage Vf is a point where the tangential line having the steepest change in the slope and the scale line corresponding to the lowest drain current Ids intersects in the graph showing the relationship of the drain current Ids to the gate voltage Vgs. Can be defined as the voltage at.

Then, the minimum driving voltage of the sequential circuit using the transistor 300 was obtained by simulation. A circuit diagram of the sequential circuit used in the simulation is shown in FIG. In the sequential circuit illustrated in FIG. 6, transistors M1 to M14 are used. The values of channel length L and channel width W of each transistor used in the simulation are shown in Table 1 below.

In the simulation, the power supply voltage at which an output signal OUT having a voltage corresponding to 99% of the power supply voltage as an amplitude is obtained is defined as the minimum drive voltage. The driving frequency of the sequential circuit was set to 32 kHz.

Table 1 below shows the relationship between the S value, the threshold voltage Vth, and the minimum drive voltage when the voltage Vf is adjusted to 0 V, obtained by simulation.

As shown in Table 2, it was found by simulation that the threshold voltage Vth can be lowered in accordance with the reduction of the S value. It has also been found that the minimum drive voltage can be lowered by lowering the threshold voltage Vth. Specifically, by setting the S value to 0.7 V / decade or lower, and further to 0.5 V / decade or lower, the threshold voltage can be lowered while ensuring the normally-off characteristics, and the minimum of the sequential circuit. It has been found that the drive voltage can be kept within the range of 11V to 16V, and further within the range of 11V to 13V.

FIG. 7 shows the relationship between the threshold voltage Vth and the minimum drive voltage obtained by simulation. FIG. 7 shows that the lower the threshold voltage of the transistor 300, the lower the minimum driving voltage can be. FIG. 8 shows the relationship between the S value and the threshold voltage Vth obtained by simulation. It has been found that when the value of the voltage Vf is constant, the threshold voltage Vth can be lowered as the S value decreases. FIG. 9 shows the relationship between the S value and the minimum drive voltage obtained by simulation. FIG. 9 shows that the minimum drive voltage can be lowered as the S value is smaller.

(Embodiment 4)
FIG. 11A illustrates a cross-sectional structure of the transistor 201 provided in the pixel, the conductive film 203 connected to the transistor 201, and the transistor 202 provided in the sequential circuit as an example.

A transistor 201 illustrated in FIG. 11A includes a conductive film 204 serving as a gate provided over an insulating surface, an insulating film 205 over the conductive film 204, and a position overlapping with the conductive film 204 over the insulating film 205. The semiconductor film 206 is provided, and the conductive film 207 and the conductive film 208 functioning as a source or a drain over the semiconductor film 206. In FIG. 11A, an insulating film 209 and an insulating film 210 are sequentially stacked over the semiconductor film 206, the conductive film 207, and the conductive film 208. The transistor 201 may include the insulating film 209 and the insulating film 210 as its components.

In addition, the transistor 202 illustrated in FIG. 11A overlaps with the conductive film 212 which is provided over the insulating surface and functions as a gate, the insulating film 205 over the conductive film 212, and the conductive film 212 over the insulating film 205. A semiconductor film 213 provided at a position; and a conductive film 214 and a conductive film 215 which function as a source or a drain over the semiconductor film 213. In FIG. 11A, an insulating film 209 and an insulating film 210 are sequentially stacked over the semiconductor film 213, the conductive film 214, and the conductive film 215. The transistor 202 may include the insulating film 209 and the insulating film 210 as its components.

Note that a display device tends to have a higher voltage required for operation than an integrated circuit. Thus, a transistor used for a display device is required to have higher withstand voltage than a transistor used for an integrated circuit. In order to secure a withstand voltage and secure a driving frequency in the pixel portion of about 60 Hz, when silicon oxide, silicon nitride oxide, silicon oxynitride, or the like is used for the insulating film 205, the film thickness is 150 nm to 500 nm. Furthermore, it is desirable that the thickness be 200 nm or more and 500 nm or less, and further 250 nm or more and 500 nm or less. Note that in a transistor having a channel formation region in an oxide semiconductor film, the S value is suppressed even when the gate insulating film is formed thicker than a transistor having a channel formation region in silicon such as an amorphous silicon film or a polysilicon film. be able to. Therefore, even when the thickness of the insulating film 205 functioning as a gate insulating film is within the above range, the S values of the transistors 201 and 202 are 0.7 V / decade or lower, and further 0.5 V / decade or lower. be able to.

An insulating film 211 using a resin is provided over the insulating film 209 and the insulating film 210. An opening is provided in the insulating film 209, the insulating film 210, and the insulating film 211, and the conductive film 203 connected to the conductive film 207 in the opening is provided over the insulating film 211. . The conductive film 203 functions as an electrode of the display element.

For example, the liquid crystal element includes a pair of electrodes and a liquid crystal layer to which an electric field is applied by the pair of electrodes. Therefore, in the case where the display element is a liquid crystal element, in addition to the conductive film 203 functioning as one of the pair of electrodes, the conductive film functioning as the other of the pair of electrodes and the liquid crystal layer may be provided over the insulating film 211. Good.

Note that the light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, such as an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode). For example, the OLED has at least an EL layer, an anode, and a cathode. The EL layer includes a single layer or a plurality of layers provided between the anode and the cathode, and includes at least a light-emitting layer containing a light-emitting substance in these layers. In the case where the display element is an OLED, a conductive film functioning as the other of the anode or the cathode and an EL layer may be provided over the insulating film 211 in addition to the conductive film 203 functioning as the anode or the cathode.

The EL layer is a layer in which electroluminescence can be obtained by a current supplied when the potential difference between the cathode and the anode becomes equal to or higher than the threshold voltage Vthe of the light emitting element. Electroluminescence includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state.

By using a resin for the insulating film 211, the formation surface of the conductive film 203 can be prevented from being uneven, that is, the flatness of the formation surface of the conductive film 203 can be improved.

Specifically, an organic material such as an acrylic resin, an epoxy resin, a benzocyclobutene resin, polyimide, or polyamide can be used for the insulating film 211. In addition to the organic material, a silicone resin or the like can be used. Note that the insulating film 211 with higher flatness can be formed by stacking a plurality of insulating films formed using these materials.

As the conductive film 203, indium oxide, indium oxide-tin oxide (ITO), indium oxide-tin oxide containing silicon or silicon oxide, indium zinc-oxide (indium zinc oxide), tungsten oxide, and the like are used. Indium oxide containing zinc oxide, Al—Zn-based oxide semiconductor containing nitrogen, Zn-containing oxide semiconductor containing nitrogen, Sn—Zn-based oxide semiconductor containing nitrogen, gold (Au), Platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), copper (Cu), palladium (Pd), titanium (Ti) Other elements belonging to Group 1 or Group 2 of the Periodic Table of Elements, that is, lithium (Li) or cesium (Cs) Alkali metals and alkaline earth metals such as magnesium (Mg), calcium (Ca), strontium (Sr), and alloys containing these (MgAg, AlLi), europium (Eu), ytterbium (Yb), and other rare earth metals And alloys containing these can be used. Note that the conductive film 203 is formed using the above-described material by, for example, a sputtering method or an evaporation method (including a vacuum evaporation method), and then the conductive film is formed into a desired shape by etching using a photolithography method. It can be formed by processing.

The insulating film 210 contains oxygen having a stoichiometric composition or higher, and is preferably an insulating film having a function of supplying part of the oxygen to the semiconductor film 206 and the semiconductor film 213 by heating. The insulating film 210 preferably has few defects. Typically, the ESR measurement indicates that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 1 × 10 ¹⁸ spins / cm. It is preferable that it is ³ or less. However, when the insulating film 210 is provided directly over the semiconductor film 206 and the semiconductor film 213, the semiconductor film 206 and the semiconductor film 213 are damaged when the insulating film 210 is formed, as illustrated in FIG. The film 209 is preferably provided between the semiconductor film 206 and the semiconductor film 213 and the insulating film 210. The insulating film 209 is desirably an insulating film that has a smaller damage to the semiconductor film 206 during formation than the insulating film 210 and has a function of transmitting oxygen. Note that the insulating film 209 is not necessarily provided as long as the insulating film 210 can be formed directly over the semiconductor film 206 and the semiconductor film 213 while suppressing damage to the semiconductor film 206 and the semiconductor film 213. .

The insulating film 209 preferably has few defects. Typically, a spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 3 × 10 ¹⁷ spins / cm ³ or less by ESR measurement. It is preferable that This is because when the density of defects included in the insulating film 209 is large, oxygen is bonded to the defects and the oxygen transmittance in the insulating film 209 is reduced.

In addition, the semiconductor film 206 and the semiconductor film 213 in the vicinity of the interface with the insulating film 209 preferably have few defects. Typically, the semiconductor film 206 and the semiconductor film 213 are typically formed by ESR measurement in which a magnetic field direction is applied in parallel to the film surface. The spin density of the signal appearing at g = 1.93 derived from oxygen vacancies in the oxide semiconductor used for the film 206 and the semiconductor film 213 is 1 × 10 ¹⁷ spins / cm ³ or less, and further, the detection limit or less. preferable.

By supplying oxygen from the insulating film 210 to the semiconductor film 206 or the semiconductor film 213, the amount of oxygen vacancies in the semiconductor film 206 or the semiconductor film 213 can be reduced.

Specifically, silicon oxide, silicon oxynitride, or the like with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm, preferably 10 nm to 30 nm can be used for the insulating film 209. As the insulating film 210, silicon oxide, silicon oxynitride, or the like with a thickness of 30 nm to 500 nm, preferably 150 nm to 400 nm can be used.

The silicon oxide film or the silicon oxynitride film used as the insulating film 209 is, for example, a substrate placed in a evacuated processing chamber of a plasma CVD apparatus at 180 ° C to 400 ° C, more preferably 200 ° C to 370 ° C. And the pressure in the processing chamber is set to 20 Pa or more and 250 Pa or less, more preferably 40 Pa or more and 200 Pa or less, and the high pressure power is supplied to the electrode provided in the processing chamber. Can do.

As a source gas for the insulating film 209, a deposition gas containing silicon and an oxidation gas are preferably used. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

By using the above conditions, an oxide insulating film that transmits oxygen can be formed as the insulating film 209. In addition, by providing the insulating film 209, damage to the semiconductor film 206 and the semiconductor film 213 can be reduced in a step of forming the insulating film 210 to be formed later.

Note that the hydrogen content in the insulating film 209 can be reduced and the dangling in the insulating film 209 can be reduced by increasing the amount of the oxidizing gas with respect to the deposition gas containing silicon by 100 times or more. Bonds can be reduced. Since oxygen transferred from the insulating film 210 may be trapped by dangling bonds included in the insulating film 209, oxygen contained in the insulating film 210 having more oxygen than the stoichiometric composition is efficiently converted into a semiconductor. It is possible to move to the film 206 and the semiconductor film 213 to fill oxygen vacancies contained in the semiconductor film 206 and the semiconductor film 213. As a result, the amount of hydrogen mixed in the semiconductor film 206 and the semiconductor film 213 can be reduced and oxygen vacancies in the oxide semiconductor film can be reduced. Therefore, the threshold voltages of the transistors 201 and 202 are negatively shifted. Can be suppressed.

Specifically, as the insulating film 209, silane having a flow rate of 20 sccm and dinitrogen monoxide having a flow rate of 3000 sccm are used as a source gas, the pressure in the processing chamber is set to 40 Pa, the substrate temperature is set to 220 ° C., and a high-frequency power source of 27.12 MHz is used. A silicon oxynitride film having a thickness of 50 nm is formed by a plasma CVD method in which high-frequency power is supplied to parallel plate electrodes. In the plasma CVD apparatus is a plasma CVD apparatus of a parallel plate type electrode area is 6000 cm ^2, is converted to electric power supplied per unit area (power ^{density) 1.6 × 10 -2 W / cm} 2 It is. Under such conditions, a silicon oxynitride film that transmits oxygen can be formed.

The silicon oxide film or the silicon oxynitride film used as the insulating film 210 is, for example, a substrate placed in a vacuum evacuated processing chamber of a plasma CVD apparatus at 180 ° C. to 260 ° C., more preferably 180 ° C. to 230 ° C. The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less by introducing the raw material gas into the processing chamber, and the electrode provided in the processing chamber is 0.17 W / cm ² or more and 0.00. 5W / cm ² or less, more preferably be the conditions for supplying high-frequency power of 0.25 W / cm ² or more 0.35 W / cm ² or less, it is formed.

As the conditions for forming the insulating film 210, by supplying high-frequency power with the above power density in the reaction chamber at the above pressure, the decomposition efficiency of the source gas in plasma is increased, the oxygen radicals are increased, and the oxidation of the source gas proceeds. Therefore, the oxygen content in the insulating film 210 is higher than the stoichiometric composition. However, when the substrate temperature is the above temperature, since the bonding force between silicon and oxygen is weak, part of oxygen is desorbed by heating. As a result, an oxide insulating film containing more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating can be formed. An insulating film 209 is provided over the semiconductor film 206 and the semiconductor film 213. Therefore, in the formation process of the insulating film 210, the insulating film 209 serves as a protective film for the semiconductor film 206 and the semiconductor film 213. As a result, the insulating film 210 can be formed using high-frequency power with high power density while reducing damage to the semiconductor film 206 and the semiconductor film 213.

Specifically, as the insulating film 210, silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm are used as the source gas, the pressure in the reaction chamber is 200 Pa, the substrate temperature is 220 ° C., and 1500 W using a 27.12 MHz high-frequency power source. A silicon oxynitride film having a thickness of 400 nm is formed by a plasma CVD method in which high-frequency power is supplied to parallel plate electrodes. In the plasma CVD apparatus is a plasma CVD apparatus of a parallel plate type electrode area is 6000 cm ^2, is converted to electric power supplied per unit area (power ^{density) 2.5 × 10 -1 W / cm} 2 It is.

Then, after the insulating film 209 and the insulating film 210 are formed, heat treatment is preferably performed. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the substrate strain point, preferably 200 ° C. or higher and 450 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower.

For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium). Note that it is preferable that hydrogen, water, and the like be not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas.

Specifically, for example, heat treatment may be performed at 350 ° C. for one hour in a nitrogen and oxygen atmosphere.

Through the above process, a transistor having excellent electrical characteristics in which a minus shift of the threshold voltage is suppressed can be manufactured. Further, a highly reliable transistor with little change in electrical characteristics due to a change with time or an optical BT stress test, typically a change in threshold voltage of 0 V to 2.5 V can be manufactured.

Next, in FIG. 11B, the transistor 201 is connected to the transistor 201 in the case where the insulating film 217 is provided between the insulating film 210 and the insulating film 211 in the cross-sectional structure illustrated in FIG. A cross-sectional structure of the conductive film 203 and the transistor 202 is shown as an example. The insulating film 217 desirably has a blocking effect that prevents diffusion of oxygen, hydrogen, and water. Alternatively, the insulating film 217 desirably has a blocking effect that prevents diffusion of hydrogen and water.

The insulating film exhibits a higher blocking effect as it is denser and denser, and as it is chemically stable with fewer dangling bonds. The insulating film showing the blocking effect of oxygen, hydrogen, and water is formed using, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like. be able to. For example, silicon nitride, silicon nitride oxide, or the like can be used as the insulating film exhibiting a blocking effect of hydrogen and water.

In the case where the insulating film 217 has a blocking effect on water, hydrogen, and the like, the insulating film 211 using a resin and impurities such as water and hydrogen existing outside the panel enter the semiconductor film 206 or the semiconductor film 213. Can be prevented. In the case where an oxide semiconductor is used for the semiconductor film 206 or the semiconductor film 213, part of water or hydrogen that has penetrated into the oxide semiconductor becomes an electron donor (donor); thus, the insulating film 217 having the blocking effect is used. The threshold voltages of the transistor 201 and the transistor 202 can be prevented from shifting due to generation of donors.

In the case where an oxide semiconductor is used for the semiconductor film 206 or the semiconductor film 213, the insulating film 217 has an oxygen blocking effect; thus, oxygen from the oxide semiconductor can be prevented from diffusing to the outside. Thus, oxygen vacancies serving as donors in the oxide semiconductor are reduced, so that the threshold voltages of the transistors 201 and 202 can be prevented from being shifted due to generation of donors.

In addition, when the adhesiveness between the insulating film 217 and the insulating film 211 is higher than the adhesiveness between the insulating film 210 and the insulating film 211, the insulating film 217 can be used to prevent the insulating film 211 from peeling.

As the insulating film 217 having a blocking effect of oxygen, hydrogen, water, or the like, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. . As the insulating film 217 having a blocking effect of hydrogen, water, or the like, silicon nitride, silicon nitride oxide, or the like can be used.

For example, in the case where a silicon nitride film is used as the insulating film 217, it is preferable that the silicon nitride film has a blocking effect of hydrogen, water, and the like, and that a release amount of hydrogen, ammonia, and the like from the silicon nitride film is small. A silicon nitride film having the above characteristics can be formed by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as a source gas.

Note that when ammonia is used as the source gas, the bond between silicon atoms and hydrogen atoms in silane and the triple bond between nitrogen atoms in nitrogen are easily cleaved by dissociated ammonia during film formation. Therefore, decomposition of silane and nitrogen is promoted during film formation, and a dense silicon nitride film can be formed. However, if the flow rate of ammonia in the source gas is too high, the amount of hydrogen and ammonia taken into the silicon nitride film will increase, and a silicon nitride film with a large amount of hydrogen and ammonia released will be formed. It becomes. Therefore, the flow rate of ammonia at the time of forming the silicon nitride film is such an amount that the decomposition of silane is promoted, and an amount that can suppress the release amount of hydrogen, ammonia, etc. It can be said that it is desirable to improve the reliability of the display device.

Specifically, when the flow rate ratio of nitrogen to the flow rate of ammonia is 5 or more and 50 or less, and more desirably 10 or more and 50 or less, silicon nitride has a high blocking effect for hydrogen, water, etc., and has a low release amount of hydrogen, ammonia, etc. A film can be formed.

In this embodiment mode, the insulating film 217 uses a silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm as a source gas, a processing chamber pressure of 200 Pa, a substrate temperature of 220 ° C., and a high frequency power source of 27.12 MHz. A silicon oxynitride film having a thickness of 50 nm is formed by a plasma CVD method in which high-frequency power of 1000 W is supplied to the parallel plate electrodes using Note that the plasma CVD apparatus has the same structure as the apparatus used when the insulating film 209 and the insulating film 209 are formed. Under such conditions, it is possible to form a silicon nitride film that has a blocking effect on hydrogen, water, and the like and that emits less hydrogen, ammonia, and the like from the silicon nitride film.

Note that an oxide semiconductor (purified OS) purified by reducing impurities such as moisture or hydrogen serving as an electron donor (donor) and reducing oxygen vacancies is an i-type (intrinsic semiconductor) or Close to i-type. Therefore, a transistor having a channel formation region in a highly purified oxide semiconductor film has extremely low off-state current. Therefore, by using a transistor having a channel formation region in the oxide semiconductor film for a sequential circuit of a driver circuit, power consumed by the off-state current of the transistor is reduced, and the sequential circuit and the display using the sequential circuit are used. Low power consumption of the device can be realized.

Specifically, it can be proved by various experiments that the off-state current of a transistor including a channel formation region in a highly purified oxide semiconductor film is small. For example, even in an element having a channel width of 1 × 10 ⁶ μm and a channel length of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, It is possible to obtain characteristics that are below the measurement limit, that is, 1 × 10 ⁻¹³ A or less. In this case, it can be seen that the off-current obtained by normalizing the off-current with the channel width of the transistor is 100 zA / μm or less. In addition, off-state current was measured using a circuit in which a capacitor and a transistor were connected and charge flowing into or out of the capacitor was controlled by the transistor. In this measurement, a highly purified oxide semiconductor film was used for a channel formation region of the transistor, and the off-state current of the transistor was measured from the change in charge amount per unit time of the capacitor. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even smaller off current of several tens of yA / μm can be obtained. Therefore, a transistor using a highly purified oxide semiconductor film for a channel formation region has significantly lower off-state current than a transistor using crystalline silicon.

Note that unless otherwise specified, off-state current in this specification refers to the gate potential when the drain potential is higher than that of the source and the gate in the n-channel transistor. It means a current that flows between the source and drain when is equal to or less than 0. Alternatively, the off-state current in this specification refers to a p-channel transistor in which the potential of the gate is 0 or more with respect to the source potential in a state where the drain is at a lower potential than the source and the gate. In addition, it means a current flowing between the source and the drain.

Note that an oxide semiconductor used for the semiconductor film 206 or the semiconductor film 213 preferably contains at least indium (In) or zinc (Zn). In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable that zirconium (Zr) is included as a stabilizer.

Among oxide semiconductors, In—Ga—Zn-based oxides, In—Sn—Zn-based oxides, and the like have excellent electrical characteristics by sputtering or a wet method, unlike silicon carbide, gallium nitride, or gallium oxide. There is an advantage that a transistor can be manufactured and the mass productivity is excellent. Further, unlike silicon carbide, gallium nitride, or gallium oxide, the In—Ga—Zn-based oxide can manufacture a transistor with excellent electrical characteristics even over a glass substrate. In addition, it is possible to cope with an increase in the size of the substrate.

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) may be included.

For example, as an oxide semiconductor, indium oxide, gallium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg Oxide, In—Mg oxide, In—Ga oxide, In—Ga—Zn oxide (also referred to as IGZO), In—Al—Zn oxide, In—Sn—Zn oxide Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Pr- Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-E -Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga- A Zn-based oxide, an In-Al-Ga-Zn-based oxide, an In-Sn-Al-Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or an In-Hf-Al-Zn-based oxide is used. be able to.

Note that for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be included. An In—Ga—Zn-based oxide has sufficiently high resistance when no electric field is applied, and can sufficiently reduce off-state current. In addition, the In—Ga—Zn-based oxide has high mobility.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1). / 5) atomic ratio In—Ga—Zn-based oxides and oxides in the vicinity of the composition can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or an oxide in the vicinity of the composition. Use it.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Hereinafter, the structure of the oxide semiconductor film is described.

An oxide semiconductor film is classified roughly into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, or the like.

An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal component. An oxide semiconductor film which has no crystal part even in a minute region and has a completely amorphous structure as a whole is typical.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Therefore, the microcrystalline oxide semiconductor film has higher regularity of atomic arrangement than the amorphous oxide semiconductor film. Therefore, a microcrystalline oxide semiconductor film has a feature that the density of defect states is lower than that of an amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts, and most of the crystal parts are large enough to fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. The CAAC-OS film is characterized by having a lower density of defect states than a microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film is described in detail.

When the CAAC-OS film is observed with a transmission electron microscope (TEM), a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When the CAAC-OS film is observed by TEM (cross-sectional TEM observation) from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when the CAAC-OS film is observed by TEM (planar TEM observation) from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS film crystal has c-axis orientation, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by the above-mentioned cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

Further, the crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface can have a higher degree of crystallinity than the region near the formation surface. is there. In addition, in the case where an impurity is added to the CAAC-OS film, the crystallinity of a region to which the impurity is added changes, and a region having a different degree of crystallinity may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

For example, the CAAC-OS film is formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the ab plane, and may be separated as flat or pellet-like sputtering particles having a plane parallel to the ab plane. is there. In this case, the flat-plate-like sputtered particle reaches the substrate while maintaining a crystalline state, whereby a CAAC-OS film can be formed.

In order to form the CAAC-OS film, the following conditions are preferably applied.

By reducing the mixing of impurities during film formation, the crystal state can be prevented from being broken by impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) existing in the deposition chamber may be reduced. Further, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used.

Further, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By increasing the substrate heating temperature at the time of film formation, when the flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

In addition, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing electric power. The oxygen ratio in the deposition gas is 30% by volume or more, preferably 100% by volume.

As an example of the sputtering target, an In—Ga—Zn-based oxide target is described below.

In-Ga-Zn system that is polycrystalline by mixing InO _X powder, GaO _Y powder and ZnO _Z powder in a predetermined number of moles, and after heat treatment at a temperature of 1000 ° C to 1500 ° C An oxide target is used. X, Y and Z are arbitrary positive numbers. Here, the predetermined mole number ratio is, for example, 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 for InO _X powder, GaO _Y powder, and ZnO _Z powder. : 2: 3 or 3: 1: 2. Note that the type of powder and the mol number ratio to be mixed may be changed as appropriate depending on the sputtering target to be manufactured.

The semiconductor film 206 or the semiconductor film 213 may have a structure in which a plurality of oxide semiconductor films formed using metal oxide targets having different metal atomic ratios are stacked. For example, the atomic ratio of the target is such that the first oxide semiconductor film is In: Ga: Zn = 1: 1: 1, and the second oxide semiconductor film is In: Ga: Zn = 3: 1: 2. You may form so that it may become. The atomic ratio of the target is such that the first oxide semiconductor film has In: Ga: Zn = 1: 3: 2, and the second oxide semiconductor film has In: Ga: Zn = 3: 1: 2. The third oxide semiconductor film may be formed so that In: Ga: Zn = 1: 1: 1.

Alternatively, the semiconductor film 206 or the semiconductor film 213 may have a structure in which a plurality of oxide semiconductor films formed using a metal oxide target containing different metals are stacked.

Next, an actual measurement value of the drain current Ids with respect to the gate voltage Vgs of the transistor 202 illustrated in FIG.

First, a specific structure of the transistor 202 used for measurement is described. The transistor 202 used for measurement has a channel formation region length (channel length L) in the carrier movement direction of 6 μm and a channel formation region length (channel width W) in a direction perpendicular to the carrier movement direction. ) Was 6 μm. As the semiconductor film 213, an In—Ga—Zn-based oxide semiconductor film with a thickness of 35 nm was used. As the insulating film 205 functioning as a gate insulating film, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm which are stacked in order from the bottom were used. As the conductive film 212, a 200-nm-thick tungsten film was used. As the conductive films 214 and 215, conductive films formed by sequentially stacking a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm were used, respectively.

Note that in this specification, oxynitride is a substance having a higher oxygen content than nitrogen in the composition, and nitride oxide has a nitrogen content higher than oxygen in the composition. Means a substance.

The measurement was performed when the drain voltage Vds was 3V. Note that the drain voltage Vds means the voltage of the conductive film 215 functioning as the drain with reference to the potential of the conductive film 214 functioning as the source. The measurement was performed in an environment where the substrate temperature was 27 ° C.

FIG. 14 shows the value of the drain current Ids (A) with respect to the gate voltage Vgs (V) of the transistor 202 obtained by the measurement. FIG. 14 shows that the threshold voltage Vth of the transistor 202 is 5.2 V and the S value is 0.47 V / decade. Thus, it is found that a transistor that is actually manufactured and includes a channel formation region in an oxide semiconductor film is within the range of the S value according to one embodiment of the present invention.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 5)
The appearance of a display device according to one embodiment of the present invention is described with reference to FIGS. FIG. 12A is a top view of a liquid crystal display device in which a substrate 4001 and a substrate 4006 are bonded to each other with a sealant 4005. 12B corresponds to a cross-sectional view taken along dashed line A1-A2 in FIG. 12A, and FIG. 12C corresponds to a cross-sectional view taken along broken line B1-B2 in FIG. Note that FIG. 12 illustrates a liquid crystal display device in FFS (Fringe Field Switching) mode.

A sealing material 4005 is provided so as to surround the pixel portion 4002 provided over the substrate 4001 and the pair of scan line driver circuits 4004. A substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed with the substrate 4001, the sealing material 4005, and the substrate 4006.

In addition, the signal line driver circuit 4003 is mounted in a region different from the region surrounded by the sealing material 4005 over the substrate 4001.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 provided over the substrate 4001 include a plurality of transistors. FIG. 12B illustrates a transistor 4010 included in the pixel portion 4002 and a transistor 4022 included in the scan line driver circuit 4004. FIG. 12C illustrates the transistor 4010 included in the pixel portion 4002.

In the pixel portion 4002 and the scan line driver circuit 4004, an insulating film 4020 using a resin is provided over the transistor 4010 and the transistor 4022. A first electrode 4021 of the liquid crystal element 4023 and a conductive film 4024 are provided over the insulating film 4020. The conductive film 4024 can function as a discharge path for charges accumulated in the insulating film 4020. Alternatively, the conductive film 4024 and the insulating film 4020 can serve as components of the transistor 4022, and the conductive film 4024 can function as a back gate.

An insulating film 4025 is provided over the insulating film 4020, the first electrode 4021, and the conductive film 4024. The insulating film 4025 preferably has a high blocking effect on water, hydrogen, and the like. As the insulating film 4025, a silicon nitride film, a silicon nitride oxide film, or the like can be used.

12B and 12C, in one embodiment of the present invention, the insulating film 4020 is removed at an end portion of the panel. The insulating film 4025 over the insulating film 4020 is in contact with the insulating film 4026 functioning as the gate insulating films of the transistor 4010 and the transistor 4022 between the sealant 4005 and the substrate 4001.

In the case where the insulating film 4025 and the insulating film 4026 have a high blocking effect such as water and hydrogen, the insulating film 4025 and the insulating film 4026 are in contact with each other at the edge of the panel, so that the insulating film 4025 and the insulating film 4026 come from the edge of the panel , Water, hydrogen, and the like can be prevented from entering a semiconductor film included in each of the transistor 4010 and the transistor 4022.

A second electrode 4027 of the liquid crystal element 4023 is provided over the insulating film 4025. A liquid crystal layer 4028 is provided between the second electrode 4027 and the insulating film 4025 and the substrate 4006. The liquid crystal element 4023 includes a first electrode 4021, a second electrode 4027, and a liquid crystal layer 4028.

Note that in one embodiment of the present invention, for example, a liquid crystal material classified into a thermotropic liquid crystal or a lyotropic liquid crystal can be used for a liquid crystal layer of a liquid crystal display device. Alternatively, for example, a liquid crystal material classified into a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or a discotic liquid crystal can be used for the liquid crystal layer. Alternatively, for example, a liquid crystal material classified into a ferroelectric liquid crystal or an antiferroelectric liquid crystal can be used for the liquid crystal layer. Alternatively, for the liquid crystal layer, for example, a liquid crystal material classified into a polymer liquid crystal such as a main chain polymer liquid crystal, a side chain polymer liquid crystal, a composite polymer liquid crystal, or a low molecular liquid crystal is used. it can. Alternatively, for the liquid crystal layer, for example, a liquid crystal material classified as a polymer dispersed liquid crystal (PDLC) can be used.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used for the liquid crystal layer. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, the temperature range is improved by adding a chiral agent or an ultraviolet curable resin. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is preferable because it has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency.

In the liquid crystal element 4023, the orientation of liquid crystal molecules included in the liquid crystal layer 4028 is changed in accordance with the value of voltage applied between the first electrode 4021 and the second electrode 4027, and the transmittance is changed. Therefore, the liquid crystal element 4023 can display gradation by controlling the transmittance according to the potential of the image signal supplied to the first electrode 4021.

Note that in one embodiment of the present invention, in a liquid crystal display device, a color image may be displayed by using a color filter, or a plurality of light sources that emit light of different hues are sequentially turned on, so that a color image is displayed. May be displayed.

In addition, an image signal from the signal line driver circuit 4003, various control signals from the FPC 4018, and a power supply potential are supplied to the scan line driver circuit 4004 or the pixel portion 4002 through lead wirings 4030 and 4031.

In this embodiment, the FFS (Fringe Field Switching) mode is used as the liquid crystal driving method. However, the liquid crystal driving method includes a TN (Twisted Nematic) mode, an STN (Super Twisted Nematic) mode, VA (Vertical Alignment) mode, MVA (Multi-domain Vertical Alignment) mode, IPS (In-Plane Switching) mode, OCB (Optically Compensated Birefringence) mode, Blue B mode A , ECB (Electrically Co ntrolled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, ASV (Advanced Super View) mode It is also possible to apply.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 6)
A display device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image. Device). In addition, as an electronic device that can use the display device of one embodiment of the present invention, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book, a video camera, a digital still camera, a goggle type display (head) Mount display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copying machine, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 13A illustrates a portable game machine including a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, and the like. The display device according to one embodiment of the present invention can be used for the display portion 5003, the display portion 5004, or another circuit. Note that although the portable game machine illustrated in FIG. 13A includes two display portions 5003 and 5004, the number of display portions included in the portable game device is not limited thereto.

FIG. 13B illustrates a display device, which includes a housing 5201, a display portion 5202, a support base 5203, and the like. The display device according to one embodiment of the present invention can be used for the display portion 5202 or another circuit. The display devices include all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 13C illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The display device according to one embodiment of the present invention can be used for the display portion 5402 or another circuit.

FIG. 13D illustrates a portable information terminal which includes a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by the connection portion 5605, and the angle between the first housing 5601 and the second housing 5602 is movable by the connection portion 5605. Yes. The video display on the first display portion 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 in the connection portion 5605. The display device according to one embodiment of the present invention can be used for the first display portion 5603, the second display portion 5604, or another circuit. Note that a display device to which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 13E illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 is movable by the connection portion 5806. Yes. The video switching in the display portion 5803 may be performed in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806. The display device according to one embodiment of the present invention can be used for the display portion 5803 or another circuit.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

FET 1 Transistor FET 2 Transistor FET 3 Transistor FET 4 Transistor FET 5 Transistor FET 6 Transistor 11 Signal line 12 Signal line 13 Signal line 14 Signal line 15 Signal line 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 31 Power supply Line 32 power supply line 101 transistor 102 transistor 103 transistor 104 transistor 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 111 transistor 201 transistor 202 transistor 203 conductive film 204 conductive film 205 insulating film 206 semiconductor film 207 conductive film 208 conductive film 209 insulating Film 210 Insulating film 211 Insulating film 212 Conductive film 213 Conductor film 214 Conductive film 215 Conductive film 217 Insulating film 300 Transistor 301 Conductive film 302 Gate insulating film 303 Semiconductor film 304 Conductive film 305 Conductive film 306 Channel formation region 4001 Substrate 4002 Pixel portion 4003 Signal line driver circuit 4004 Scan line driver circuit 4005 Sealing Stop material 4006 Substrate 4010 Transistor 4018 FPC
4020 Insulating film 4021 Electrode 4022 Transistor 4023 Liquid crystal element 4024 Conductive film 4025 Insulating film 4026 Insulating film 4027 Electrode 4028 Liquid crystal layer 4030 Wiring 5001 Housing 5002 Housing 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Housing 5202 Display unit 5203 Support base 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Housing 5602 Housing 5603 Display unit 5604 Display unit 5605 Connection unit 5606 Operation key 5801 Housing 5802 Housing 5803 Display unit 5804 Operation key 5805 Lens 5806 Connection

Claims (5)

A first transistor that controls electrical connection between a first wiring to which a clock signal is applied and a second wiring;
A second transistor that controls electrical connection between the second wiring and a third wiring to which a low-level first potential is applied;
A third transistor for controlling electrical connection between the gate of the first transistor and a fourth wiring to which a high-level second potential is applied;
A fourth transistor that controls electrical connection between a gate of the first transistor and a fifth wiring to which the first potential is applied;
The first to fourth transistors each include an oxide semiconductor in a channel formation region.
A sequential circuit in which the S value of the transistor is 0.7 V / decade or less. The sequential circuit according to claim 1, wherein the S value is 0.5 V / decade or less. 3. The sequential circuit according to claim 1, wherein the oxide semiconductor includes In, Ga, and Zn. In any one of Claims 1 thru | or 3,
In the first to fourth transistors, silicon oxide, silicon oxynitride, or silicon nitride oxide is used for a gate insulating film,
The sequential circuit in which the gate insulating film has a thickness of 150 nm to 500 nm. A display device using the sequential circuit according to claim 1.

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