JP2014072719A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a low-power-consumption and highly-reliable semiconductor device.SOLUTION: A semiconductor device comprises: a clock circuit part 30 which includes PMOS and NMOS transistors, and generates a clock signal; and a logic circuit part 20 which includes PMOS and NMOS transistors, and operates depending on a data signal, in which the clock circuit part and the logic circuit part are connected to a common low-potential side power source GND and a first power supply voltage Vdd(data) is supplied to the logic circuit part and a second power supply voltage Vdd(clock) lower than the first power supply voltage is supplied to the clock circuit part. The logic circuit part includes a gate to which the clock signal is input and clock logic gate parts TMG0-TMG4 which receives an input signal from another logic circuit part or outputs an output signal to another logic circuit part. A back gate voltage Vbg of the PMOS transistor included in the clock logic gate part is higher than a back gate voltage Vdd(data) of the PMOS transistor of the other logic circuit part.

Description

  The present invention relates to a semiconductor device that operates in response to a clock signal.

  In general, a large-scale semiconductor device (LSI) includes a clock circuit unit that generates and transmits a clock signal, and a logic circuit unit that operates according to a data signal. The logic circuit section is divided into a plurality of stages by flip-flop (FF) circuits, and each stage operates in synchronization with a clock signal supplied from the clock circuit section. The clock circuit unit includes an oscillation circuit and generates a clock signal in the semiconductor device, or generates an internal clock signal from a clock signal supplied from the outside of the semiconductor device.

  In recent years, semiconductor devices (LSIs) have been required to reduce power consumption, and the circuit uses a CMOS circuit in which a PMOS transistor and an NMOS transistor are connected in series between a high potential power source and a low potential power source. It is common. In a CMOS circuit, power consumption is mainly determined by two factors: (1) current consumption for charging / discharging a load capacity and (2) current consumption due to a minute leakage current of a transistor.

  The current for charging / discharging the load of (1) is proportional to the square of the operating voltage and the operating frequency, and the leakage current of (2) is determined by the transistor size regardless of the operating frequency. For this reason, it is effective to suppress the leakage current of (2) in an LSI having a low frequency or operation rate or having many standby states in general. The threshold voltage Vth of the transistor is increased and the leakage current is reduced. Reduce power consumption. On the other hand, in an LSI that always operates at a high frequency, it is effective to suppress current consumption for charging / discharging the load capacity of (1), and the threshold voltage Vth is reduced and the power supply voltage is lowered to reduce power consumption. suppress.

  As described above, since each element of the logic circuit section operates in synchronization with the clock signal, the data signal is switched only when the clock signal rises (or falls). That is, if the frequency of the clock signal is F [Hz], the data signal does not operate at F / 2 [Hz] or higher. Further, if the data signal is not switched in a certain cycle, the logic circuit does not operate, and therefore no charge / discharge current flows. In other words, the operating frequency of the logic circuit section is always less than or equal to ½ of the frequency of the clock signal, and is often about 1/10 in normal operation.

  For the reasons described above, in order to reduce the power consumption of an LSI, it is effective to increase the threshold voltage Vth of the CMOS circuit and suppress the leakage current in the logic circuit part, and to reduce the power supply voltage by reducing Vth in the clock circuit part. A technique for lowering is effective. When changing the power supply voltage, it is easy in terms of the circuit configuration that the high-potential-side power supply is the first and second power supplies with different voltages and the low-potential-side power supply is common, in other words, both are at the ground (GND) level. . For this reason, in the following description, when the power supply voltage is changed, the high-potential side power supply is assumed to be the first and second power supplies having different voltages, and the low-potential side power supply is assumed to be common.

JP 2001-068992 A JP 11-297969 A Japanese Patent Laid-Open No. 5-259844

  As described above, the logic circuit section operates in synchronization with the clock signal, and thus has a circuit that receives the clock signal. Here, such a circuit is referred to as a clock logic gate unit. The clock logic gate unit is included in the logic circuit unit and receives the clock signal generated by the clock circuit unit having a low power supply voltage, although the power supply voltage is not low. Specifically, a clock signal generated by a clock circuit unit having a low power supply voltage is input to the gates of a PMOS transistor and an NMOS transistor included in the clock logic gate unit. In this case, the PMOS transistor is not completely cut off even when a clock signal that is turned off to stop data is input, and the data is transmitted to the next stage, which may cause a malfunction. Can happen.

  According to the embodiment, even when the power supply voltage of the clock circuit unit is made lower than the power supply voltage of the logic circuit unit to reduce power consumption, a semiconductor device in which the occurrence of malfunction is reduced is realized.

  According to the embodiment, the semiconductor device includes a clock circuit unit and a logic circuit unit. The clock circuit unit includes a PMOS transistor and an NMOS transistor, and generates a clock signal. The logic circuit section includes a PMOS transistor and an NMOS transistor, and performs an operation according to the data signal. The clock circuit portion and the logic circuit portion are connected to a common low potential side power source. A first power supply voltage is supplied to the logic circuit section, and a second power supply voltage lower than the first power supply voltage is supplied to the clock circuit section. The logic circuit unit includes a clock logic gate unit that receives a clock signal from a gate and receives an input signal from another logic circuit unit or outputs an output signal to another logic circuit unit. The back gate voltage of the PMOS transistor included in the clock logic gate part is higher than the back gate voltage of the PMOS transistor in the other logic circuit part.

  According to the embodiment, a highly reliable semiconductor device with low power consumption is realized.

FIG. 1 is a diagram showing a basic configuration of a CMOS circuit and a change in current accompanying an on / off operation. FIG. 2 is a diagram illustrating a configuration of a logic circuit portion for one stage that operates in synchronization with a clock signal. FIG. 3 is a time chart showing the operation of the logic circuit section of FIG. FIG. 4 is a diagram illustrating a circuit example of a typical flip-flop (FF) circuit used in the logic circuit section, where (A) shows an FF circuit and (B) shows a clock circuit section. FIG. 5 is a diagram illustrating a schematic configuration of the semiconductor device of the first embodiment. FIG. 6 is a diagram illustrating a circuit example of a typical flip-flop (FF) circuit used in the logic circuit unit of the semiconductor device of the first embodiment, where (A) is an FF circuit and (B) is a clock. A circuit part is shown. FIG. 7 is a diagram showing the structure and wiring of the transmission gate of the clock logic gate portion of the semiconductor device of the first embodiment. FIG. 8 is a diagram illustrating a circuit example of a typical flip-flop (FF) circuit used in the logic circuit portion of the semiconductor device of the second embodiment, where (A) is an FF circuit and (B) is a clock. A circuit part is shown. FIG. 9 is a diagram illustrating a modification of the semiconductor device of the second embodiment. FIG. 10 is a diagram illustrating a circuit example of a typical JK flip-flop (JK-FF) circuit used in the logic circuit unit of the semiconductor device of the third embodiment. FIG. 10A illustrates the JK-FF circuit. (B) shows a circuit diagram of a clocked NAND gate.

  Before describing the embodiment, the occurrence of malfunction in a semiconductor device when the power supply voltage of the clock circuit portion is made lower than the power supply voltage of the logic circuit portion to reduce power consumption will be described.

FIG. 1 is a diagram showing a basic configuration of a CMOS circuit and a change in current accompanying an on / off operation. Here, an inverter circuit widely used is shown as an example.
As shown in FIG. 1, the inverter circuit using a CMOS circuit includes a PMOS transistor 1 and an NMOS transistor 2 connected in series between a high potential power source Vdd and a low potential power source GND. An input signal IN is input to the gates of the PMOS transistor 1 and the NMOS transistor 2, and an output signal OUT is output from a connection node (drain) between the PMOS transistor 1 and the NMOS transistor 2. Since the circuit in FIG. 1 is an inverter circuit, the output signal OUT is an inverted signal of the input signal IN. The inverter circuit of FIG. 1 drives an element connected to the output. In the driving operation, the element is regarded as the load capacitor 3, and the output signal of the inverter circuit performs an operation of charging or discharging the load capacitor 3.

  When the input signal IN is “low (L)”, the PMOS transistor 1 is turned on to conduct, the NMOS transistor 2 is turned off and cut off, and the charging current J flows from Vdd to the load capacitor 3. On the other hand, when the input signal IN is “high (H)”, the PMOS transistor 1 is turned off to be cut off, the NMOS transistor 2 is turned on to be conducted, and the discharge current D flows from the load capacitor 3 to GND. .

  In a CMOS circuit, power consumption is mainly determined by two factors: (1) current consumption for charging / discharging a load capacity, and (2) minute leakage current of a transistor.

  In the charge / discharge of the load capacity, the charge Q [C] required for one charge / discharge is Q = CV. Here, the capacitance value of the load capacitor 3 is C [F], and the power supply voltage is V [V]. In the following description, it is assumed that GND = 0V and the power supply voltage V [V] is a voltage value of Vdd.

In charging / discharging, if charge (= current) I [A] and power P [W] flowing per second is F [Hz],
I [A] = Q [C] × F [Hz] = C [F] × V [V] × F [Hz]
P [W] = I [A] × V [V] = C [F] × (V [V]) ² × F [Hz]
It is.

  Since the leakage current flows constantly, the operating frequency F [Hz] is not related, and the leakage current Ileak determined by the transistor size determines the power consumption Pleak, and Pleak = Ileak × V [V].

  For this reason, in general, in a CMOS circuit, it is effective to lower the power supply voltage VDD in order to reduce power consumption. For this purpose, it is necessary to lower the threshold voltage Vth of the transistor. At this time, Ileak increases exponentially (Ileak∝exp (−Vth)). For this reason, the component due to the leakage current becomes large in the power consumption, and if the value of the operating frequency F “Hz” is small, the power consumption may increase even if the power supply is lowered.

  For the above reasons, it is advantageous to suppress power consumption due to leakage current in an LSI having a low frequency and operating rate, in other words, a large number of standby states. The power consumption is suppressed by increasing Vth and reducing Ileak. Conversely, in an LSI that always operates at a high frequency, in order to suppress a component due to charge / discharge in power consumption, Vth is reduced and the power supply voltage is lowered to reduce power consumption.

  In general, a large-scale semiconductor device (LSI) includes a clock circuit unit that generates and transmits a clock signal, and a logic circuit unit that operates according to a data signal. The logic circuit section is divided into a plurality of stages by a flip-flop (FF) circuit, and each stage operates in synchronization with a clock signal supplied from the lock circuit section. Thereby, the influence of delay in each element in the logic circuit unit can be reduced, and a large-scale circuit can be operated normally.

FIG. 2 is a diagram illustrating a configuration of a logic circuit portion for one stage that operates in synchronization with a clock signal.
As shown in FIG. 2, the logic circuit section includes a flip-flop (FF) 11 that controls the timing of fetching the data signal Data from the previous stage, an FF 12 that controls the output timing of the data signal to the subsequent stage, and FFs 11 and 12. And a logic circuit 15 provided therebetween. The clock circuit unit includes buffers 12 and 14 that receive the clock signal Clock generated and transmitted by the clock generation unit. The clock signal output from the buffer 12 is applied to the FF 11, and the clock signal output from the buffer 12 is applied to the FF 12.

FIG. 3 is a time chart showing the operation of the logic circuit section of FIG.
The clock signal Clock always changes between “H” and “L” in a predetermined cycle. The data signal Data changes when it changes from the previous state when the clock signal Clock rises. The output X of the FF 11 changes from “H” to “L” when indicated by P because the data signal Data changes from “H” to “L” when the clock signal Clock rises. In the example of FIG. 3, the state of each part in the logic circuit 15 changes according to the change of the output X of the FF 11 from “H” to “L”, and the output Y of the logic circuit 15 becomes “ It changes from “H” to “L”. On the other hand, when the clock signal Clock rises next time, the data signal Data maintains the “L” state. Therefore, when indicated by Q, the output X of the FF 11 maintains “L” and does not change. The same applies to the output Y of the logic circuit 15.

  Thus, since the output X of the FF 11 changes only when the clock signal Clock rises, the minimum change period is twice that of the clock signal Clock. The same applies to the output Y of the logic circuit 15. In other words, if the operating frequency of the clock signal Clock is F [Hz], the operating frequency of the data signal Data in each part of the logic circuit unit is F / 2 [Hz] or less. Further, if the data signal Data does not change in a certain cycle, the logic circuit does not operate, so that no charge / discharge current flows in this case. That is, the operating frequency of the data signal Data is always less than or equal to the clock signal Clock1 / 2, and often becomes about 1/10.

  Considering what has been described above, in order to reduce the power consumption of the LSI, a method for suppressing the leakage current by increasing the threshold voltage Vth of the transistor is suitable for the logic circuit portion. It is effective to lower the power supply voltage by reducing the power supply voltage and suppress the charge / discharge current. However, simply lowering the power supply voltage of the clock circuit unit has a problem that malfunction is likely to occur in the FF of the logic circuit unit to which both the clock signal and the data signal are applied. Hereinafter, this problem will be described.

  FIG. 4 is a diagram illustrating a circuit example of a typical flip-flop (FF) circuit used in the logic circuit section, where (A) shows an FF circuit and (B) shows a clock circuit section.

  In FIG. 4A, an inverter Inv0 is a preceding output circuit and outputs a data signal Data in which “H” is Vdd and “L” is GND as shown in the figure. Two inverters Inv1 and Inv2 and two transmission gates TMG0 and TMG1 form the first half of the FF. Two inverters Inv3 and Inv4 and two transmission gates TMG12 and TMG3 form the second half of the FF. As shown in FIG. 4B, the clock circuit section includes inverters Inv11 and Inv12 connected in series, and outputs clock signals CLK and / CLK that are 180 degrees out of phase with the input clock signal Clock. .

  TMG0 to TMG3 are transmission gates which connect a PMOS transistor and an NMOS transistor in parallel, and CLK is applied to one gate of the PMOS transistor and NMOS transistor, and / CLK is applied to the other gate. In FIG. 4, in TMG0 and TMG3, CLK is applied to the gate of the PMOS transistor and / CLK is applied to the gate of the NMOS transistor. Therefore, TMG0 and TMG3 operate in phase with the clock signal (at the same timing). In TMG1 and TMG2, / CLK is applied to the gate of the PMOS transistor and CLK is applied to the gate of the NMOS transistor. Therefore, TMG1 and TMG2 operate in phase with the clock signal. Further, TMG0 and TMG3, and TMG1 and TMG2 operate in reverse phase with respect to the clock signal (at a timing shifted by 180 degrees). In TMG0 to TMG3, a clock signal CLK or / CLK is applied to the gate, and an input or an output is connected to an element of another logic circuit section. Here, such an element is referred to as a clock logic gate unit.

  In the flip-flop circuit of FIG. 4, TMG0 is in a passing state in the first half cycle of the clock signal, and the previous stage data signal Data is taken into the first half of the FF. At this time, the TMG 1 is in a cut-off state in order to make it easier to capture the previous stage data signal Data in the first half of the FF. Further, TMG2 is also in the cut-off state, the output of the first half of the FF is not transferred to the second half, and TMG3 is in the passing state, and the previously transferred data signal is held in the second half of the FF.

  In the second half cycle of the clock signal, TMG0 is cut off, TMG1 is passed, and the data signal Data captured in the first half of the FF is held. Further, TMG2 enters a passing state, and the data signal Data held in the first half of the FF is transferred to the second half of the FF. At this time, the TMG 3 is in a cut-off state in order to facilitate the transfer of the data signal Data in the first half of the FF to the second half. Since the operation of the flip-flop circuit of FIG. 4 is widely known, further explanation is omitted.

  Here, in order to reduce power consumption, consider a case where 1 V is supplied to the logic circuit portion as Vdd (data) and 0.7 V is supplied to the clock circuit portion as Vdd (clock). Note that GND is supplied in common to the logic circuit portion and the clock circuit portion. In other words, the power supply voltage of the logic circuit portion is Vdd (data) = 1V, and the power supply voltage of the clock circuit portion is Vdd (clock) = 0.7V. In this case, Vdd (data) = 1V is supplied to the well in which the PMOS transistor of the logic circuit portion is formed, and GND = 0V is supplied to the substrate on which the NMOS transistor is formed. In other words, the back gate voltage of the PMOS transistor in the logic circuit portion is Vdd (data) = 1V, and the back gate voltage of the NMOS transistor in the logic circuit portion is GND = 0V. Further, Vdd (clock) = 0.7 V is supplied to the well where the PMOS transistor of the clock circuit portion is formed, and GND = 0 V is supplied to the substrate where the NMOS transistor is formed. In other words, the back gate voltage of the PMOS transistor in the clock circuit portion is Vdd (clock) = 0.7V, and the back gate voltage of the NMOS transistor in the clock circuit portion is GND = 0V.

  CLK or / CLK is applied to the gates of the PMOS transistors TMG0 to TMG3 in a circuit in which the power supply voltage of the clock circuit unit is lowered. When the Data signal input to TMG0 to TMG3 is “H” (1 V) and CLK or / CLK is “H” (0.7 V), Vgs = Vd (clock) −Vdd (data) in these PMOS transistors. = -0.3V. For this reason, these PMOS transistors are not completely turned off, and TMG0 to TMG3 are not completely cut off from the data signal, so that the function as the FF cannot be sufficiently performed and a malfunction may occur. For example, when the power supply voltage of the clock circuit unit is not lowered and CLK or / CLK is “H” and 1.0 V, Vgs = 0 V, so that TMG0 to TMG3 block the data signal. In this way, since the power supply voltage of the clock circuit portion is lowered, the possibility of malfunctioning increases.

  In the semiconductor device of the embodiment described below, even if the power supply voltage of the clock circuit unit is lowered, the occurrence of malfunction is reduced.

FIG. 5 is a diagram illustrating a schematic configuration of the semiconductor device of the first embodiment.
As shown in FIG. 5, the semiconductor device according to the first embodiment includes a clock circuit unit 30, a logic circuit unit 20, a first power supply 41, a second power supply 42, and a back gate power supply 43. The clock circuit unit 30 includes a PMOS transistor and an NMOS transistor, and generates and transmits a clock signal. The clock circuit unit 30 includes a clock generation unit 31 that generates a clock signal, and a clock transmission unit 32 that distributes the clock signal in the semiconductor device. The clock generation unit 31 includes an oscillation circuit inside and may generate a clock signal, or may generate a clock signal used internally from a clock signal supplied from the outside of the semiconductor device.

  The logic circuit unit 20 includes a PMOS transistor and an NMOS transistor, and performs an operation according to the data signal. The first power supply 41 generates a power supply Vdd (Data) and supplies it to the logic circuit unit 20 as a high potential side power supply. The second power source 42 generates a power source Vdd (clock) and supplies it to the clock circuit unit 30 as a high potential side power source. Note that the low-potential side power supplies of the logic circuit unit 20 and the clock circuit unit 30 are both GND. The back gate power supply 43 generates the back gate power supply Vbg and supplies it to the well in which the PMOS transistor of the clock logic gate part of the logic circuit part 20 described later is formed. In the first embodiment, for example, the voltage of Vdd (Data) is 1 V, the voltage of Vdd (clock) is 0.7 V, and the voltage of Vbg is 2.0 V. Note that the voltage of the power supply Vdd (Data) may be expressed as Vdd (Data), the voltage of the power supply Vdd (clock) may be expressed as Vdd (clock), and the voltage of the back gate power supply Vbg may be expressed as Vbg. Therefore, Vdd (Data) = 1V, Vdd (clock) = 0.7V, and Vbg = 2.0V. It is desirable that the back gate power supply 43 can change the back gate power supply voltage Vbg.

  The logic circuit unit 20 includes a clock logic gate unit to which a clock signal is applied to a gate and receives an input signal from another logic circuit unit or outputs an output signal to another logic circuit unit. The back gate voltage of the PMOS transistor included in the clock logic gate unit is the back gate power supply Vbg supplied from the back gate power supply 43. The back gate voltage of the PMOS transistor in the other logic circuit section is 1V. Therefore, the back gate voltage Vbg = 2.0 V higher than the PMOS transistors of the other logic circuit units is supplied to the PMOS transistors included in the clock logic gate unit.

  By setting the power supply voltage and the back gate voltage as described above, the circuit element of the clock circuit unit 30 having a high operation rate operates at a low power supply voltage Vdd (clock) = 0.7 V. Power consumption can be effectively reduced by reducing consumption. On the other hand, since the high power supply voltage Vdd (Data) = 1 V is supplied to the circuit elements of the logic circuit unit 20 having a low operation rate, the leakage current can be reduced and the power consumption can be effectively reduced.

  Further, the back gate voltage of the PMOS transistor included in the clock logic gate part is higher than the back gate voltage of the PMOS transistor in the other part of the logic circuit part 20. Therefore, the threshold voltage Vth of the PMOS transistor included in the clock logic gate portion becomes high, and when the clock signal supplied from the clock circuit portion 30 is “H” = 0.7 V, that is, Vgs = −0.3 V ≠ Even at 0V, it will be cut off. As a result, the FF completely shuts off the data signal, so that the FF functions as an FF and prevents malfunction.

  FIG. 6 is a diagram illustrating a circuit example of a typical flip-flop (FF) circuit used in the logic circuit unit of the semiconductor device of the first embodiment, where (A) is an FF circuit and (B) is a clock. A circuit part is shown. In other words, FIG. 6 has a configuration in which the back gate voltage of the PMOS transistor included in the clock logic gate unit is changed from Vdd (data) to Vbg in the circuit of FIG.

  In the circuit of FIG. 6, in order to reduce power consumption, 1 V is supplied to the logic circuit portion as Vdd (data) and 0.7 V is supplied to the clock circuit portion as Vdd (clock). Commonly supplied to the circuit unit and the clock circuit unit. In other words, the power supply voltage of the logic circuit portion is Vdd (data) = 1V, and the power supply voltage of the clock circuit portion is Vdd (clock) = 0.7V. GND = 0V is supplied to the substrate on which the NMOS transistor of the logic circuit portion is formed, and Vdd (data) = 1V is supplied to the well in which the PMOS transistor other than the clock logic gate portion is formed. In other words, the back gate voltage of the PMOS transistors other than the clock logic gate portion of the logic circuit portion is Vdd (data) = 1V, and the back gate voltage of the NMOS transistor of the logic circuit portion is GND = 0V. Further, Vdd (clock) = 0.7 V is supplied to the well where the PMOS transistor of the clock circuit portion is formed, and GND = 0 V is supplied to the substrate where the NMOS transistor is formed. In other words, the back gate voltage of the PMOS transistor in the clock circuit portion is Vdd (clock) = 0.7V, and the back gate voltage of the NMOS transistor in the clock circuit portion is GND = 0V.

  In FIG. 6, transmission gates TMG0 to TMG3 are included in the clock logic gate unit. Similar to the other parts of the logic circuit part, the power supply voltage of the clock logic gate part is also Vdd (data) = 1V, and GND = 0V is supplied to the substrate on which the NMOS transistor of the clock logic gate part is formed. The However, Vbg = 2V is supplied to the well in which the PMOS transistor of the clock logic gate portion is formed. In other words, the clock logic gate portion is different from the other portions of the logic circuit portion in that the back gate voltage of the PMOS transistor is Vbg = 2V.

  Since the power supply voltage of the clock circuit section is Vdd (clock) = 0.7V, CLK and / CLK are signals of “H” = 0.7V and “L” = 0V. When the Data signal input to TMG0 to TMG3 is “H” (1 V) and CLK or / CLK is “H” (0.7 V), Vgs = Vd (clock) in these PMOS transistors in the clock logic gate section. −Vdd (data) = − 0.3V. However, in the first embodiment, since the back gate voltage of the PMOS transistor in the clock logic gate portion is Vbg = 2V, the PMOS transistor can be completely cut off even in this case. Thereby, TMG0 to TMG3 completely block the data signal and sufficiently function as the FF, so that no malfunction occurs. Note that the current supplied from the back gate power supply is only the PN junction leakage of the source / drain of the PMOS transistor in the clock logic gate section, and the power for that is very small. Further, since the loads of the clock signals CLK and / CLK do not change, the charge / discharge current of the load does not change.

FIG. 7 is a diagram showing the structure and wiring of the transmission gate of the clock logic gate portion of the semiconductor device of the first embodiment.
The PMOS transistor is formed in an N-well, and the NMOS transistor is formed in a P-sub. A clock signal / CLK that becomes a voltage Vdd (clock) when "H" is applied to the gate of the PMOS transistor, and a clock signal CLK that becomes a voltage Vdd (clock) when "H" is applied to the gate of the NMOS transistor. The sources and drains of the PMOS transistor and NMOS transistor are connected to each other and connected to other elements of the logic circuit section. A back gate voltage higher than 1V (here, 2V) is applied to the N-well in which the PMOS transistor is formed, and GND = 0V is applied to the P-sub in which the NMOS transistor is formed.

  FIG. 8 is a diagram illustrating a circuit example of a typical flip-flop (FF) circuit used in the logic circuit portion of the semiconductor device of the second embodiment, where (A) is an FF circuit and (B) is a clock. A circuit part is shown. In other words, the second embodiment has a configuration in which the transmission gate included in the clock logic gate unit is replaced with a clocked inverter in the first embodiment. Actually, the transmission gate and the inverter are replaced with a clocked inverter.

  As shown in FIG. 8, in the second embodiment, the back gate voltage of the PMOS transistor to which the clock signal CLK or / CLK of the clocked inverter is applied to the gate is set to Vbg = 2V. Thus, even when the Data signal input to these PMOS transistors is “H” (1 V) and CLK or / CLK is “H” (0.7 V), the PMOS transistors can be completely cut off. . As a result, the clocked inverter completely cuts off the data signal and sufficiently functions as the FF, so that no malfunction occurs.

  FIG. 9 is a diagram showing a modification of the semiconductor device of the second embodiment, and shows an example in which the arrangement order of transistors in the clocked inverter is changed. Also in this case, the back gate voltage of the PMOS transistor to which the clock signal CLK or / CLK of the clocked inverter is applied to the gate is set to Vbg = 2V.

  FIG. 10 is a diagram illustrating a circuit example of a typical JK flip-flop (JK-FF) circuit used in the logic circuit unit of the semiconductor device of the third embodiment. FIG. 10A illustrates the JK-FF circuit. (B) shows a circuit diagram of a clocked NAND gate.

  The JK-FF is well known and will not be described. However, by inputting the clock signal CLK to the NAND gate of the input stage, an FF that captures and holds the output of the previous stage according to the clock signal CLK can be realized. .

  In the third embodiment, the NAND gate in the input stage is a clocked NAND gate having the circuit configuration of FIG. The clocked NAND gate is widely known and will not be described in detail, but has a PMOS transistor and an NMOS transistor to which the clock signal CLK is applied to the gate. In the third embodiment, Vdd (data) is supplied as a power supply voltage to JK-FF. The back gate voltage of the NMOS transistor forming JK-FF is GND, and the back gate voltage of the PMOS transistors other than the PMOS transistor to which the clock signal CLK is applied to the gate is Vdd (data) = 1V. In contrast, the back gate voltage of the PMOS transistor to which the clock signal CLK is applied to the gate is Vbg = 2V. Thus, even when the Data signal input to these PMOS transistors is “H” (1 V) and CLK or / CLK is “H” (0.7 V), the PMOS transistors can be completely cut off. . As a result, the clocked NAND gate in the input stage completely cuts off the data signal, and the JK-FF functions sufficiently so that no malfunction occurs.

  As described above, according to the embodiment, even when the power supply voltage of the data system (logic circuit unit) and the clock system (clock circuit unit) of the LSI logic circuit is changed to reduce the power, a malfunction occurs. An LSI with reduced can be realized.

  Needless to say, various modifications are possible, and the power supply voltage and the back gate voltage should be appropriately set according to the process of the target semiconductor device.

  The embodiment has been described above, but all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and technology. In particular, the examples and conditions described are not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 1 PMOS transistor 2 NMOS transistor 3 Load capacity 20 Logic circuit part 30 Clock circuit part 41 1st power supply 42 2nd power supply 43 Back gate power supply Inv0-Inv4 Inverter TMG0-TMG4 Transmission gate

Claims (7)

A clock circuit unit that includes a PMOS transistor and an NMOS transistor and generates a clock signal;
A logic circuit unit including a PMOS transistor and an NMOS transistor, and performing an operation according to a data signal,
The clock circuit unit and the logic circuit unit are connected to a common low-potential side power supply,
A first power supply voltage is supplied to the logic circuit unit,
A second power supply voltage lower than the first power supply voltage is supplied to the clock circuit unit,
The logic circuit unit includes a clock logic gate unit that receives the input signal from another logic circuit unit or outputs an output signal to another logic circuit unit, with the clock signal being input to a gate.
A semiconductor device, wherein a back gate voltage of a PMOS transistor included in the clock logic gate portion is higher than a back gate voltage of a PMOS transistor of the other logic circuit portion.   The semiconductor device according to claim 1, wherein the clock logic gate unit is included in a flip-flop circuit.   The semiconductor device according to claim 2, wherein the clock logic gate unit is included in a JK flip-flop circuit.   The semiconductor device according to claim 1, wherein the clock logic gate unit includes a transmission gate.   The semiconductor device according to claim 1, wherein the clock logic gate unit includes a clocked inverter.   6. The semiconductor device according to claim 1, further comprising a back gate power supply that generates the back gate voltage of the PMOS transistor included in the clock logic gate unit.   The semiconductor device according to claim 6, wherein a voltage value of the back gate voltage is variable.

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