JP2014072680A - Amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compact, high performance amplification circuit with coupling capacitors.SOLUTION: The amplification circuit comprises: an amplifier; a first coupling capacitor; a second coupling capacitor; a non-inverting input side input series resistor; an inverting input side input series resistor; a non-inverting input side resistance circuit; and an inverting input side resistance circuit. The amplification circuit further includes adjustment means for adjusting at least one of four values consisting of a voltage value of a DC bias voltage applied to the non-inverting input side resistance circuit, a voltage value of a DC bias voltage applied to the inverting input side resistance circuit, a resistance value of a resistive element constituting the non-inverting input side resistance circuit, and a resistance value of a resistive element constituting the inverting input side resistance circuit.

Description

  The present invention relates to an amplifier circuit.

In electronic circuits, amplifier circuits are used for various purposes.
One purpose of use of the amplifier circuit is to remove common-mode noise (common mode noise) superimposed on an input signal and amplify a signal component. An amplifier circuit used for this type of purpose is called an isolation amplifier. Various systems have been proposed as isolation amplifiers. As shown in Patent Document 1, a pair of coupling capacitors are arranged in an input stage, and an input signal is input to the operational amplifier via the coupling capacitors. In many cases, a differential amplifying circuit configured to be supplied to is used. According to this differential amplifier circuit, the DC component of the input signal is cut by the coupling capacitor, and only the AC component is supplied to the operational amplifier and differentially amplified.

  The common-mode signal removal performance of the differential amplifier circuit having this configuration depends on the precision of the resistors and capacitors constituting the circuit, and the characteristics greatly vary due to slight errors. For this reason, it is necessary to use highly accurate parts.

JP 2001-7665 A

  With recent miniaturization and high density mounting of electronic devices, it is necessary to use smaller components in the amplifier circuit. The use of a high dielectric constant type multilayer ceramic capacitor as a large-capacitance capacitor is effective for miniaturization and high-density mounting.

  However, the multilayer ceramic capacitor has a specific electrical characteristic that the capacitance changes when a DC voltage is applied.

  For this reason, in the case of a differential amplifier circuit that uses a multilayer ceramic capacitor as the coupling capacitor and the voltage applied to the coupling capacitor on the Hot side and Cold side differs, the capacitance of the coupling capacitor deviates from the design value. Therefore, the in-phase signal removal performance may be deteriorated. Also, the capacitance may deviate from the design value due to aging.

  The same problem is common to an amplifier circuit that uses a capacitor whose capacitance varies according to the applied voltage as a coupling capacitor.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a small and high-performance amplifier circuit including a coupling capacitor.
Another object of the present invention is to provide an amplifier circuit that is small and has excellent common-mode signal removal performance.

In order to achieve the above object, an amplifier circuit according to the present invention includes:
An amplifier;
A first coupling capacitor having one end connected to the non-inverting input terminal of the amplifier and having a capacitance that varies according to an applied DC voltage;
A second coupling capacitor having one end connected to the inverting input terminal of the amplifier and having a capacitance that varies according to an applied DC voltage;
A non-inverting input side input series resistor connected to the other end of the first coupling capacitor and supplied with an input signal;
An inverting input side input series resistor connected to the other end of the second coupling capacitor and supplied with an input signal;
A non-inverting input-side resistor circuit connected to the first coupling capacitor and including a bias resistor to which a first DC bias voltage is applied;
An inverting input-side resistor circuit connected to the second coupling capacitor and including a bias resistor and a feedback resistor of the amplifier to which a second DC bias voltage is applied;
The voltage value of the first DC bias voltage, the voltage value of the second DC bias voltage, the resistance value of the resistance element constituting the non-inverting input side resistance circuit, and the resistance element constituting the inverting input side resistance circuit Adjusting means for adjusting at least one of the four values of the resistance value;
It is characterized by providing.

  For example, the adjusting means may be configured such that a ratio of a combined resistance value of the non-inverting input side resistance circuit to a resistance value of the non-inverting input side input series resistance is equal to the resistance value of the inverting input side input series resistance. A time constant of a circuit that is equal to the ratio of the combined resistance value of the circuit and that includes the non-inverting input side input series resistance, the non-inverting input side resistance circuit, and the first coupling capacitor is the inverting input. At least one of the four values may be adjusted so as to be equal to a time constant of a circuit including a side input series resistance, the inverting input side resistance circuit, and the second coupling capacitor. .

For example, further comprising an evaluation means for evaluating the signal processing of the amplifier circuit,
The adjusting means includes a voltage value of the first DC bias voltage, a voltage value of the second DC bias voltage, a combined resistance value of the non-inverting input side resistance circuit, and a combined resistance value of the inverting input side resistance circuit. At least one of the four values may be scanned and at least one of the four values may be adjusted based on the evaluation by the evaluation means.

For example, the non-inverting input side resistance circuit includes a first bias resistor and a second bias resistor connected to the non-inverting input terminal of the amplifier,
The inverting input side resistor circuit is connected between a third bias resistor connected to the second coupling capacitor and one end of the inverting input side input series resistor, and an inverting input end and an output end of the amplifier. Feedback resistors may be provided.

  For example, the adjusting means has a resistance value in which the non-inverting input side input series resistance, the inverting input side series resistance, the first bias resistance, and the feedback resistance are equal, and the second bias At least one of the four values may be adjusted so that the resistor and the third bias resistor have the same resistance value.

For example, the non-inverting input side resistance circuit is connected to a fourth bias resistor connected to the non-inverting input terminal of the amplifier, the first coupling capacitor, and one end of the non-inverting input side input series resistance. And a fifth bias resistor
The inverting input side resistor circuit is connected between a sixth bias resistor connected to the second coupling capacitor and one end of the inverting input side input series resistor, and an inverting input end and an output end of the amplifier. Feedback resistors may be provided.

  For example, the adjustment means has a resistance value in which the non-inverting input side input series resistance, the inverting input side input series resistance, the fourth bias resistance, and the feedback resistance are equal, At least one of the four values may be adjusted so that the bias resistor and the sixth bias resistor have the same resistance value.

  According to the present invention, it is possible to provide a small and high-performance amplifier circuit including a coupling capacitor.

1 is a circuit diagram of an isolation amplifier according to Embodiment 1 of the present invention. It is a figure explaining the characteristic of a high dielectric constant type multilayer ceramic capacitor. It is a figure explaining the specific example of the isolation amplifier shown in FIG. It is a figure explaining the specific example of the isolation amplifier shown in FIG.1 and FIG.3. It is a circuit diagram of the isolation amplifier which concerns on Embodiment 2 of this invention. It is a figure explaining the specific example of the isolation amplifier shown in FIG. It is a figure explaining the specific example of the isolation amplifier shown in FIG.5 and FIG.6. (A), (b) is a circuit diagram of the isolation amplifier which concerns on Embodiment 3 of this invention. It is a circuit diagram of the isolation amplifier which concerns on Embodiment 4 of this invention. (A), (b) is a circuit diagram of the isolation amplifier which concerns on Embodiment 5 of this invention. (A), (b) is a circuit diagram of the isolation amplifier which concerns on Embodiment 5 of this invention. (A), (b) is a circuit diagram of the isolation amplifier which concerns on Embodiment 6 of this invention. (A), (b) is a circuit diagram of the isolation amplifier which concerns on Embodiment 6 of this invention. It is a circuit diagram of the isolation amplifier which concerns on Embodiment 7 of this invention. It is a flowchart explaining operation | movement of the control part of the isolation amplifier shown in FIG.

Hereinafter, a signal processing circuit according to an embodiment of the present invention will be described using an isolation amplifier as an example.
(Embodiment 1)
The isolation amplifier 10 according to the first embodiment of the present invention is composed of a differential amplifier circuit, and as shown in FIG. 1, an operational amplifier (operational amplifier) 11, coupling capacitors C11 and C12, and an input series resistor R11. , R12, bias resistors R13, R15, R16, and a feedback resistor R14, and differentially amplifies two signals supplied from the signal source 21.

  One end of the input series resistor R11 is connected to one output end To1 of the signal source 21. The other end of the input series resistor R11 is connected to one end (one electrode) of the coupling capacitor C11. The other end (the other electrode) of the coupling capacitor C11 is connected to the non-inverting input terminal (positive input terminal) of the operational amplifier 11.

  One end of the input series resistor R12 is connected to the other output end To2 of the signal source 21. The other end of the input series resistor R12 is connected to one end of the coupling capacitor C12. The other end of the coupling capacitor C12 is connected to the inverting input terminal (negative input terminal) of the operational amplifier 11.

  One end of the bias resistor R13 is connected to the non-inverting input terminal of the operational amplifier 11, and the voltage V1 is applied to the other end.

  The feedback resistor R14 has one end connected to the inverting input terminal of the operational amplifier 11 and the other end connected to the output terminal of the operational amplifier 11 to constitute negative feedback.

  One end of the bias resistor R15 is connected to the non-inverting input terminal of the operational amplifier 11, and the voltage V2 is applied to the other end.

  The bias resistor R16 has one end connected to one end of the capacitor C12 and the other end to which the voltage V3 is applied.

  The coupling capacitors C11 and C12 are composed of high dielectric constant type multilayer ceramic capacitors having the same standard and the same rated capacity. As illustrated in FIG. 2, the multilayer ceramic capacitor has a characteristic that its capacitance gradually decreases from the rating as the DC applied voltage increases. In FIG. 2, the capacitance change rate is an index indicating how much the capacitance decreases from the rating (capacitance when the DC applied voltage is 0 V).

  The signal source 21 shown in FIG. 1 has a hot-side output terminal To1 and a cold-side output terminal To2, and generates a combined voltage Vhot + Sa of the DC bias voltage Vhot and the AC voltage signal component Sa from the hot-side output terminal To1. The output terminal To2 outputs a composite voltage Vcold-Sa of the direct current bias voltage Vcold and the inverted alternating voltage signal component -Sa.

  In the above configuration, the signals Vhot + Sa and Vcold-Sa output from the signal source 21 include DC bias voltages Vhot and Vcold, respectively. The DC bias voltages Vhot and Vcold are applied to the coupling capacitors C11 and C12, respectively. Due to this DC applied voltage, the capacitances of the coupling capacitors C11 and C12 deviate from the rated values and decrease in accordance with the characteristics shown in FIG. Further, the hot-side DC bias voltage Vhot and the cold-side DC bias voltage Vcold are different. For this reason, normally, although the same-capacitance coupling capacitors C11 and C12 are used, there is a difference in capacitance between the coupling capacitors C11 and C12, and the common-mode signal removal performance is reduced. End up.

  Therefore, in the present embodiment, circuit constants are set so that the voltages applied to both ends of the coupling capacitors C11 and C12 are equal, thereby suppressing deterioration of the common-mode signal removal performance.

First, the circuit constant of the input circuit including the feedback resistor R14 is set to a value satisfying the following expressions (1-1) and (1-2) so as to realize an isolation amplifier with the common-mode signal rejection ratio being maximized. And
R11: (R15 // R13) = R12: (R14 // R16) (1-1)
{R11 + (R15 // R13)} * C11 = {R14 + (R12 // R16)} * C12 (1-2)
“R // r” represents the combined resistance when the resistors R and r are connected in parallel.

  Formula (1-1) is the ratio of the resistance (R13 // R15) of the combined (parallel) resistor circuit of other resistors R13 and R15 to the input series resistor R11 in the non-inverting input (+) side circuit of the operational amplifier 11. This means that the ratio of the resistance (R14 // R16) of the combined (parallel) resistance circuit of the other resistances R14 and R16 to the input series resistance R12 in the circuit on the inverting input (−) side of the operational amplifier 11 is equal. In other words, it means that the voltage dividing ratio between the input series resistance on the non-inverting input side and the other resistance circuit is equal to the voltage dividing ratio between the input series resistance on the non-inverting input side and the other resistance circuit.

  Further, the expression (1-2) is obtained by the time constant {(R11 + (R15 // R13)) * C11} of the input circuit connected to the non-inverting input terminal (+) of the operational amplifier 11 and the inverting input terminal of the operational amplifier 11. This means that the time constant {(R14 + (R12 // R16)) * C12} of the input circuit connected to (−) is equal.

Further, the circuit constant is set to a value satisfying the expression (1-3) so that the DC applied voltage Vc11 of the coupling capacitor C11 and the DC applied voltage Vc12 of the coupling capacitor C12 are equal.
| Vc11 | = | R15 / (R13 + R15) * V1 + R13 / (R13 + R15) * V2-Vhot |
= | Vc12 | = | R15 / (R13 + R15) * V1 + R13 / (R13 + R15) * V2
-{R16 / (R12 + R16) * Vcold + R12 / (R12 + R16) * V3} | ... (1-3)

  There are an infinite number of combinations of circuit constants that satisfy the expressions (1-1) to (1-3). Accordingly, if a combination of arbitrary circuit constants (resistance value, voltage, etc.) satisfying the expressions (1-1) to (1-3) is specified and set to the isolation amplifier 10 shown in FIG. The purpose of is achieved.

  However, it is not easy to generate the three voltages V1 to V3 in one circuit, and usually the upper limit is about two including the ground voltage. Moreover, if the constants of the circuit elements are set to different values, the number of parts increases, which is undesirable in terms of circuit balance.

Therefore, here, for example, R11 = R12 = R13 = R14 = Ra, R15 = R16 = Rb are set as circuit constants that satisfy the above-described equations (1-1) and (1-2). Further, V1 = V3 = Vref and V2 = 0 = GND are set as voltages.
In this case, the circuit diagram of FIG. 1 is rewritten to the circuit diagram of FIG.

Under this condition, the DC applied voltages Vc11 and Vc12 of the coupling capacitors C11 and C12 are expressed by the following formulas (1-4) and (1-5), and the capacitances are the same. Needs to satisfy formula (1-6).
Vc11 = Rb / (Ra + Rb) * Vref-Vhot ... (1-4)
Vc12 = (Rb-Ra) / (Ra + Rb) * Vref- {Rb / (Ra + Rb) * Vcold} ... (1-5)
| Vc11 | = | Vc12 | ... (1-6)
Therefore, the values of Ra and Rb are selected so as to satisfy these expressions.

  As values satisfying the above equation, Ra = 10 kΩ, Rb = 20 kΩ, Vhot = 6 V, Vcold = 0 V, Vref = 6 V are selected, and C11 = C12 = 10 μF, and the circuit diagram of FIG. It is done.

In this case, equations (1-1) and (1-2) are established as follows.
R11: (R15 // R13) = R12: (R14 // R16) = 3: 2 ... (1-1)
{R11 + (R15 // R13)} * C11 = {R14 + (R12 // R16)} * C12 = 166.6 ... ms ... (1-2)

  In this case, the voltage of each part becomes the value shown in the figure, and the voltages applied to the coupling capacitors C11 and C12 are equal to 2V, respectively.

  Therefore, although the capacitances of the coupling capacitors C11 and C12 deviate from the rated values, they have the same value, and the common-mode signal removal performance does not deteriorate.

  As described above, according to the configuration of this embodiment, the same voltage is applied across the capacitors C11 and C12. For this reason, the coupling capacitors C11 and C12 have the same capacitance even though the multilayer ceramic capacitors having the characteristic that the capacitance varies according to the DC applied voltage are used as the coupling capacitors C11 and C12. Thus, the common-mode signal removal performance is excellent.

(Embodiment 2)
The circuit configuration of the isolation amplifier is not limited to the first embodiment, and can be changed as appropriate. For example, an isolation amplifier excellent in common-mode signal removal performance can also be realized by the differential amplifier circuit having the configuration shown in FIG.

  The isolation amplifier 10 shown in FIG. 5 includes an operational amplifier 11, coupling capacitors C21 and C22, input series resistors R21 and R22, bias resistors R23, R25, and R26, and a feedback resistor R24. The two signals supplied from are differentially amplified.

  One end of the input series resistor R21 is connected to the output end To1 of the signal source 21, and the other end is connected to one end of the coupling capacitor C21. The other end of the coupling capacitor C21 is connected to the non-inverting input terminal of the operational amplifier 11.

  One end of the input series resistor R22 is connected to the other output end To2 of the signal source 21, and the other end is connected to one end of the coupling capacitor C22. The other end of the coupling capacitor C22 is connected to the inverting input terminal of the operational amplifier 11.

  One end of the bias resistor R23 is connected to the non-inverting input terminal of the operational amplifier 11, and the voltage V21 is applied to the other end.

  The feedback resistor R24 has one end connected to the inverting input terminal of the operational amplifier 11 and the other end connected to the output terminal of the operational amplifier 21 to constitute negative feedback.

  The bias resistor R25 is connected to a connection node with one end of the coupling capacitor C21, and the voltage V22 is applied to the other end.

  One end of the bias resistor R26 is connected to one end of the coupling capacitor C22, and a voltage V23 is applied to the other end.

In the circuit of FIG. 5, in order to maximize the common-mode signal rejection ratio, the equations (2-1) and (2-2) must be satisfied.
R21: (R23 // R25) = R22: (R24 // R26) ... (2-1)
{R23 + (R21 // R25)} * C21 = {R24 + (R22 // R26)} * C22 ... (2-2)

  Expression (2-1) is the ratio of the resistance (R23 // R25) of the combined circuit of the other resistors R23 and R25 to the input series resistance R21 in the circuit on the non-inverting input (+) side of the operational amplifier 11 and the operational amplifier 11 This means that the ratio of the resistance (R24 // R26) of the combined (parallel) circuit of the other resistors R24 and R26 to the input series resistance R22 in the inverting input (-) side circuit is equal. In other words, it means that the voltage dividing ratio between the input series resistance on the non-inverting input side and the other circuit is equal to the voltage dividing ratio between the input series resistance on the non-inverting input side and the other circuit.

  Expression (2-2) is a time constant {(R23 + (R21 // R25)) * C21} of the input circuit connected to the non-inverting input terminal (+) of the operational amplifier 11 and the inverting input terminal of the operational amplifier 11. This means that the time constant {(R24 + (R22 // R26)) * C22} of the input circuit connected to (−) is equal.

Further, both-end voltages Vc21 and Vc22 across the coupling capacitors C21 and C22 are expressed by the following equations.
Vc21 = V21- {R25 / (R21 + R25) * Vhot + R21 / (R21 + R25) * V22}
Vc22 = V21- {R26 / (R22 + R26) * Vcold + R22 / (R22 + R26) * V23}

  In order to make the DC applied voltages of the coupling capacitors C21 and C22 coincide with each other, a circuit constant that satisfies | Vc21 | = | Vc22 | is set.

  If V21 = V23 = Vref, V22 = 0, R21 = R22 = R23 = R24 = Rc, and R25 = R26 = Rd, the circuit diagram of FIG. 5 can be rewritten to FIG.

Under this condition, suitable circuit constants are, for example, Vhot = 4V, Vcold = 0V, Vref = 6V, Rc = 20 kΩ, Rd = 30 kΩ, C11 = C12 = 10 μF. in this case,
R21: (R23 // R25) = R22: (R24 // R26) = 5: 3 ... (2-1)
{(R21 // R25) + R23} * C21 = {(R22 // R26) + R24} * C22
= {(20 // 30) +20} * 10 = 320ms ... (2-2)
Thus, the expressions (2-1) and (2-2) are satisfied.

  Further, the DC potential of each part is as shown in FIG. 7, and the DC voltage applied to the coupling capacitors C21 and C22 is equal to 3.6V. Even in this configuration, the DC applied voltages of the coupling capacitors C21 and C22 are the same, the capacitances of the coupling capacitors C21 and C22 are equal, and the common-mode signal removal performance of the isolation amplifier 10 is excellent. .

(Embodiment 3)
In the first and second embodiments, the example in which the capacitances of the hot and cold coupling capacitors C11 and C12 and C21 and C22 are made equal is shown. It is also possible to set the capacitance of the capacitor to a different value.

  For example, in the isolation amplifier 10 shown in FIG. 1, R11 = R12 = R13 = 10 kΩ, as shown in FIG. Assume that R14 = R15 = 20 kΩ and R16 = 10 kΩ are set.

  In this case, R11: (R15 // R13) = R12: (R14 // R16) = 3: 2, which satisfies the expression (1-1). That is, the voltage dividing ratio of the peripheral circuit to the input series resistance is the same in the Hot side input circuit and the Cold side input circuit.

Further, when the resistance value is substituted into the expression (1-2), the following expression is established.
{R11 + (R15 // R13)} * C11 = {R14 + (R12 // R16)} * C12
= {10+ (20 // 10)} * C11 = {20+ (10 // 10)} * C12
By transforming this equation, the following equation is derived.
2 * C11 = 3 * C12

  Therefore, Formula (1-2) is established when C11: C12 = 3: 2. That is, the time constant of the Hot side input circuit is equal to the time constant of the Cold side input circuit. Here, as an example, C11 = 9 μF and C12 = 6 μF.

  Assuming that the coupling capacitors C11 and C12 are of the same standard and the rated capacity is 10 μF, and the applied voltage-capacitance change rate has the characteristics shown in FIG. 2, the capacitance change rate is 10%. And 40%, the intended 9 μF and 6 μF are obtained.

  From the characteristics of FIG. 2, in order to set the capacitance change rate to 10% and 40%, 0.8 V and 1, 6 V must be applied to the coupling capacitors C11 and C12, respectively. Therefore, if Vcold = 0V, Vhot = 4V, V1 = 4.8V, V2 = 0V, V3 = 3.2V, 0.8V is applied to both ends of the coupling capacitor C11 and 1.6V is applied to both ends of C12. , C11 = 9 μF and C12 = 6 μF are obtained.

  Further, for example, as shown in FIG. 8B, R11 = 9 kΩ, R12 = 6 kΩ, R13 = 9 kΩ, R14 = 6 kΩ, R15 = 18 kΩ, R16 = 12 kΩ as resistance values satisfying the expression (1-1). Suppose that it is set.

  These values satisfy Expression (1-1). That is, the voltage dividing ratio requirement of the input circuit is satisfied.

  Furthermore, C11: C12 satisfying the expression (1-2) is 2: 3. Here, as an example, C11 = 6 μF and C12 = 9 μF. That is, the input circuit time constant requirement is satisfied.

  Assuming that the coupling capacitors C11 and C12 are of the same standard, the rated capacity is 10 μF, and the applied voltage-capacitance change rate has the characteristics shown in FIG. 2, the capacitance change rate is 40%. At 10%, the intended 6 μF and 9 μF are obtained.

  From the characteristics of FIG. 2, in order to set the capacitance change rate to 40% and 10%, voltages of 1.6 V and 0.8 V must be applied to each capacitor.

  When Vcol = 0V, Vhot = 4V, V1 = 3.6V, V2 = 0V, V3 = 4.8V, the DC applied voltage of C11 is 1.6V, the DC applied voltage of C12 is 0.8V, and C11 = 6 μF, C12 = 9 μF, and the characteristics of C11: C12 = 3: 2 are obtained.

  In addition, although the example in which the signal source 21 outputs the differential signals Vhot + Sa and Vcold−Sa has been shown, one of the output signals may output the signal Vhot or Vcold that does not include the AC signal component Sa. In this case, the gain of the circuits of FIGS. 8A and 8B is 6 dB.

(Embodiment 4)
The circuit configuration shown in the first to third embodiments is an exemplification, and the circuit configuration can be arbitrarily changed.

  That is, according to the present invention, as shown in FIG. 9, the input circuit is connected to i) coupling capacitors C1 and C2, ii) series input resistance circuits Z1 and Z2, and iii) coupling capacitors C1 and C2. Can be widely applied to a circuit that has a differential resistance of two input signals supplied via coupling capacitors C1 and C2 and includes a bias resistance circuit Z3 to Z6 to which a bias voltage of 1 is applied and a feedback resistance circuit Z7. It is.

In any circuit, the circuit constant is selected so as to satisfy Expression (3-1) and to obtain a necessary amplification factor.
Z1: (Z3 // Z4) = Z2: (Z5 // Z6 // Z7) ... (3-1)
{(Z1 // Z3) + Z4} * C1 = {(Z2 // Z5) + (Z6 // Z7)} * C2 ... (3-2)

  Further, based on the applied voltage-capacitance change rate characteristic, the coupling capacitors C1, C2 are obtained so that C1 and C2 satisfying the expression (3-2) are obtained (or the same voltage is applied). The rated capacitance and applied voltages V1 to Vq are set.

  That is, the resistance circuits Z1 to Z7 are the ratio (voltage division ratio) between the resistance value of the input series resistance circuit Z1 on the non-inverting input (+) side and the combined resistance value of the resistance circuit in which the bias resistance circuits Z3 and Z4 are connected in parallel. ) And the resistance value of the input series resistance circuit Z2 on the inverting input (−) side and the combined resistance value of the parallel connection circuit of the feedback resistance circuit Z7 and the resistance circuit in which the bias resistance circuits Z5 and Z6 are connected in parallel (Voltage division) is equal, the time constant of the non-inverting input (+) side circuit is equal to the time constant of the inverting input (−) side circuit, and a desired gain can be obtained. Set to a value.

  As described above, according to the present embodiment, while using a coupling capacitor composed of a multilayer ceramic capacitor having a characteristic in which the capacitance changes according to the applied voltage, the maximum common-mode component removal is achieved. An isolation amplifier having performance can be obtained.

  In the configuration of the isolation amplifier in FIG. 9, a part of the resistance circuits Z3 to Z6 may have a resistance value = ∞, that is, open. However, one of Z3 and Z4 and one of Z5 and Z6 are essential. For example, the circuit of FIG. 1 is an example of Z3 = Z6 = ∞, and the circuit of FIG. 5 is an example of Z6 = ∞.

(Embodiment 5)
In the above-described embodiment, an example in which coupling capacitors having the same characteristics and the same rating are used is shown. However, the characteristics of the elements are slightly different from each other. Furthermore, the characteristics fluctuate (deteriorate) due to aging.

  For this reason, there are slight variations in the rated value and DC applied voltage characteristics of the high dielectric constant type multilayer ceramic capacitor, and even when the same voltage is applied, the capacitances of both coupling capacitors are not equal, The common-mode signal removal performance may be lowered.

  In such a case, the DC voltage applied across the coupling capacitor is intentionally shifted so that the capacitances of the coupling capacitors are the same (or the desired capacitance ratio). The common-mode noise removal performance can be made the best.

  For example, in the case of the isolation amplifier 10 shown in FIG. 1, for example, as shown in FIG. 10A, if the resistors R15 and R16 are replaced with variable resistors VR15 and VR16 and appropriately adjusted, the above condition is satisfied. A potential difference satisfying the satisfying relationship can be given to the coupling capacitors C11 and C12.

  Further, as shown in FIG. 10B, the resistors VR15 and VR16 may be changed in conjunction with each other.

  In any circuit, VR15 and VR16 are changed so as to satisfy the above-described expressions (1-1) and (1-2).

  Similarly, in the case of the isolation amplifier 10 shown in FIG. 5, for example, as shown in FIG. 11A, if the resistors R25 and R26 are replaced with the variable resistors VR25 and VR26 and appropriately adjusted, the above-described conditions are satisfied. A potential difference satisfying the relationship satisfying can be applied to the coupling capacitors C21 and C22.

Further, as shown in FIG. 11B, the variable resistors VR25 and VR26 may be changed in conjunction with each other.
In any circuit, VR25 and VR26 are set so as to satisfy Expressions (2-1) and (2-2).

  Although the example in which the resistance values of the two bias resistors are variable is shown, a configuration in which the resistance value of one variable resistor is changed or a resistance value of three or more resistors may be changed. Furthermore, it is good also as a structure which changes the resistance value of three or more resistances interlockingly.

(Embodiment 6)
In the fifth embodiment, the capacitances of the coupling capacitors C11 to C22 are adjusted by adjusting the resistance value of the variable resistor. However, the coupling capacitors C11 to C11 are adjusted by adjusting the DC applied voltage to the bias circuit. It is also possible to adjust the capacitance of C22 to an optimum value.

For example, in the example of the circuit shown in FIG. 1, the voltage applied to the bias resistors R13 and R16 is adjusted by adjusting the voltage V1 or V3 by adjusting the volume as shown in FIG. What is necessary is just to obtain a sufficient electrostatic capacity.
Even in this circuit configuration, each circuit constant is set so as to satisfy the above-described equations (1-1) and (1-2).

  Further, as shown in FIG. 12B, the two voltages V1 and V3 may be adjusted in conjunction with each other.

  Similarly, for example, in the example of the circuit shown in FIG. 5, as shown in FIG. 13A, the DC applied voltage is adjusted by adjusting the voltage V <b> 21 or V <b> 23 using the volume, and the optimum capacitance is obtained. You can get it.

Further, as shown in FIG. 13B, V21 and V23 may be adjusted in conjunction with each other.
In addition, although the example which makes two application voltages variable was shown, it is good also as a structure which makes only one application voltage variable, or a structure which makes three or more application voltages variable. Furthermore, it is good also as a structure which changes 3 or more applied voltages interlockingly.

  Moreover, it is good also as a structure which can each change the resistance value of arbitrary numbers of variable resistance, and an arbitrary number of applied voltages.

(Embodiment 7)
In the fifth and sixth embodiments, it is necessary to operate the volume in order to adjust the circuit constant, but the adjustment work is not easy.
Therefore, for example, the volume may be composed of an electronic volume, and an optimum volume value may be automatically obtained while measuring circuit characteristics.

This embodiment will be described with reference to FIG.
In this configuration, the optimum circuit constant of the isolation amplifier 10 shown in FIG. 11B is automatically obtained and set. In addition to the configuration in FIG. A circuit 52 is added. The signal source 21 can output in-phase noise.

  In the following description, in order to facilitate understanding, R21 = R22 = R23 = R24 = Rc, VR25 = VR26 = VRd, and Equations (2-1) and (2-2) represent VRd values. Regardless, it shall be satisfied.

  Next, the operation of the isolation amplifier 10 having the configuration shown in FIG. 14 will be described with reference to FIG.

  When an instruction to adjust the capacitances of the coupling capacitors C21 and C22 is issued, the control unit 51 sets the resistance values of the variable resistors VR25 and VR26 (hereinafter referred to as the variable resistance value VRd) to the minimum value within the adjustment range. (Step S11).

  Next, the control unit 51 controls the signal source 21 to output in-phase noise. Further, the noise evaluation circuit 52 starts an operation for evaluating how much in-phase noise is removed from the level of the noise component included in the output signal of the operational amplifier 11 (step S12). A higher evaluation value is assigned as the in-phase noise component is removed.

  The control unit 51 stores the variable resistance value VRd and the evaluation result in association with each other (step S13).

Next, the control unit 51 determines whether or not the variable resistance value VRd has reached the maximum value within the adjustable range (step S14), and if not (step S14; No), the variable resistance value VRd is determined. The value is increased by a minute value ΔVR (step S15), and the process returns to step S12.
Thereafter, the same operation is repeated.

  On the other hand, when it is determined in step S14 that the variable resistance value VRd has reached the maximum value (step S14; Yes), the control unit 51 determines the variable resistance value in order from the highest evaluation value among the stored measurement results. N VRd are selected (step S16). Let the selected variable resistance values be VRd1 to VRdN.

Next, the control unit 51 sets the pointer i to 1 (step S17).
Next, the control unit 51 sets the resistance value of the variable resistor VRd to the minimum value VRdi−ΔVR of the adjustment range centered on the selected resistance value VRdi (step S18).

  Next, the control unit 51 controls the signal source 21 to output in-phase noise. Further, the noise evaluation circuit 52 is caused to perform an operation for evaluating how much in-phase noise has been removed from the output signal level of the operational amplifier 11 (step S19). The control unit 51 stores the variable resistance value VRd and the evaluation value in association with each other (step S20).

Next, the control unit 51 determines whether or not the variable resistance value VRd has reached VRdi + ΔVR that is the upper limit of the adjustment range centered on the selected resistance value VRdi (step S21). (S21; No), the variable resistance value VRd is increased by ΔΔVR (step S22), and the process returns to step S19. Note that ΔΔVR <ΔVR.
Thereafter, the same operation is repeated.

If it is determined in step S21 that the variable resistance value VRd has reached the upper limit VRdi + ΔVR of the adjustment range (step S21; Yes), the control unit 51 determines whether i = N (step S23).
If i is not N (step S23; No), i is set to i + 1 (step S24), the process returns to step S18, and the same operation is repeated.
On the other hand, if it is determined in step S23 that i = N (step S23; Yes), the maximum one of the evaluation values stored in steps S13 and S20 is specified, and the variable resistance value at that time is determined as the variable resistance. The resistance values of VR25 and VR26 are set (step S25).

With such a configuration, it is possible to automatically determine and set a circuit constant that maximizes the common-mode signal removal performance.
For example, by periodically executing the variable resistance setting process described above, the isolation amplifier can be operated in an optimum state even when the resistance value changes due to aging or the like.

  Although the embodiment in which the resistance value is automatically set has been described by taking the circuit of FIG. 11B as an example, when adjusting the variable resistance in FIGS. 11A, 12A, and 12B, etc. Is equally applicable. Moreover, it is also possible to apply to the example which adjusts the voltage illustrated to Fig.13 (a), (b).

  In the embodiment using the variable element, for example, in the embodiment of FIGS. 10 to 13, the variable range of the variable element, for example, the variable range of the resistance value of the variable resistors VR15, VR16, VR25, VR26, the variable voltage. The variable ranges of the voltage values of V1, V3, V21, and V23 are calculated based on the above formulas (1-1) and (1) over the entire capacitance variation range after predicting the capacitance variation range of the coupling capacitors C11 and C12. -2) is desirably set to a variable range that can be established.

  That is, the variable range of the physical quantity of the variable element is the ratio of the combined resistance value of the non-inverting input side resistance circuit to the resistance value of the non-inverting input side input series resistance at any value within the variable range. A circuit that is equal to the ratio of the combined resistance value of the inverting input side resistance circuit to the resistance value of the series resistance, and that includes the non-inverting input side input series resistance, the non-inverting input side resistance circuit, and the first coupling capacitor C11. Is preferably set in a variable range such that the time constant of the circuit composed of the inverting input side input series resistance, the inverting input side resistance circuit, and the second coupling capacitor C12 is equal.

  Further, the flowchart of FIG. 15 is an example, and the resistance value, the reference voltage, etc. when the common-mode signal rejection rate is the maximum are checked by gradually changing the resistance value, voltage, etc. Can be set in the circuit, the specific configuration is arbitrary.

  For example, in the flow of FIG. 15, first, the variable resistance VRd is scanned in a rough step ΔVR, and a two-step scan is performed in which the vicinity of the variable resistance value VRdi that obtained a relatively good result is scanned in a fine step ΔΔVR. Although an example of this is shown, only one-stage scanning may be performed. For example, VRd having the highest evaluation value may be selected in step S16, and it may be set as the final optimum value.

  In the above description, the present invention has been described by taking a multilayer ceramic capacitor of a high dielectric constant as an example. However, the present invention can be widely applied to a circuit using a capacitor whose capacitance changes according to an applied voltage, such as a varicap. It is.

  In the above embodiment, the present invention has been described by taking the isolation amplifier or the differential amplifier circuit as an example, but the present invention is not limited to this. The present invention is applicable to an analog signal processing circuit or a digital signal processing circuit that takes in and processes an AC signal using a coupling capacitor.

  In the above embodiment, the resistance circuit is represented as a lumped constant circuit, but may be a distributed constant circuit.

DESCRIPTION OF SYMBOLS 10 Isolation amplifier 11 Operational amplifier 21 Signal source 51 Control part 52 Noise evaluation circuit

Claims (7)

An amplifier;
A first coupling capacitor having one end connected to the non-inverting input terminal of the amplifier and having a capacitance that varies according to an applied DC voltage;
A second coupling capacitor having one end connected to the inverting input terminal of the amplifier and having a capacitance that varies according to an applied DC voltage;
A non-inverting input side input series resistor connected to the other end of the first coupling capacitor and supplied with an input signal;
An inverting input side input series resistor connected to the other end of the second coupling capacitor and supplied with an input signal;
A non-inverting input-side resistor circuit connected to the first coupling capacitor and including a bias resistor to which a first DC bias voltage is applied;
An inverting input-side resistor circuit connected to the second coupling capacitor and including a bias resistor and a feedback resistor of the amplifier to which a second DC bias voltage is applied;
The voltage value of the first DC bias voltage, the voltage value of the second DC bias voltage, the resistance value of the resistance element constituting the non-inverting input side resistance circuit, and the resistance element constituting the inverting input side resistance circuit Adjusting means for adjusting at least one of the four values of the resistance value;
An amplifier circuit comprising: The adjusting means is configured such that a ratio of a combined resistance value of the non-inverting input side resistance circuit to a resistance value of the non-inverting input side input series resistance is equal to a resistance value of the inverting input side input series resistance. The time constant of a circuit that is equal to the ratio of the combined resistance values and that includes the non-inverting input side input series resistance, the non-inverting input side resistance circuit, and the first coupling capacitor is the inverting input side input. Adjusting at least one of the four values to be equal to a time constant of a circuit composed of a series resistor, the inverting input-side resistor circuit, and the second coupling capacitor;
The amplifier circuit according to claim 1. An evaluation means for evaluating the signal processing of the amplifier circuit;
The adjusting means includes a voltage value of the first DC bias voltage, a voltage value of the second DC bias voltage, a combined resistance value of the non-inverting input side resistance circuit, and a combined resistance value of the inverting input side resistance circuit. And at least one value of the four values is adjusted based on the evaluation by the evaluation means.
The amplifier circuit according to claim 1 or 2. The non-inverting input side resistance circuit includes a first bias resistor and a second bias resistor connected to a non-inverting input terminal of the amplifier,
The inverting input side resistor circuit is connected between a third bias resistor connected to the second coupling capacitor and one end of the inverting input side input series resistor, and an inverting input end and an output end of the amplifier. Provided feedback resistor,
The amplifier circuit according to claim 1, 2, or 3. The adjusting means includes the non-inverting input side input series resistance, the inverting input side series resistance, the first bias resistance, and the feedback resistance having equal resistance values, and the second bias resistance. Adjusting at least one of the four values so that the third bias resistor has an equal resistance value;
The amplifier circuit according to claim 4. The non-inverting input side resistance circuit is connected to a fourth bias resistor connected to the non-inverting input terminal of the amplifier, the first coupling capacitor, and one end of the non-inverting input side input series resistance. A fifth bias resistor;
The inverting input side resistor circuit is connected between a sixth bias resistor connected to the second coupling capacitor and one end of the inverting input side input series resistor, and an inverting input end and an output end of the amplifier. Provided feedback resistor,
The amplifier circuit according to claim 1, 2, or 3. The adjusting means has the same resistance value as the non-inverting input side input series resistance, the inverting input side input series resistance, the fourth bias resistance, and the feedback resistance, and the fifth bias resistance. And at least one of the four values is adjusted so that the sixth bias resistor has a resistance value equal to the sixth bias resistor.
The amplifier circuit according to claim 6.

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