JP2014071485A - Recording device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recording device in which in a device performing communication in PCI Express, initial processing of each device can be performed without being restricted by a device which takes time in initial processing and which can be started in a short time.SOLUTION: In a device performing communication in PCI Express, control is performed so that, as to initial processing, processing is started for a device which takes time in link establishment processing, by using a processing start signal in advance, not by reset release. With this configuration, as to the initial processing in the device performing PCI Express communication, the processing is terminated to secure time for performing a link training sequence, so that linkup can be performed in a prescribed time.

Description

  The present invention relates to a recording apparatus, and more particularly, to a recording apparatus that performs recording using, for example, an inkjet recording head, which includes a device that establishes a link by performing communication according to PCI Express (registered trademark).

  In recent years, PCI Express (registered trademark), which is a broadband serial communication standard, has been widely used for networks and communications. The PCI Express Generation 1 standard has a data transfer rate of 2.5 Gbps, the Generation 2 standard is 5.0 Gbps, and the Generation 3 standard is 8.0 Gbps.

  The PCI Express structure is composed of a transaction layer, a data link layer, and a physical layer. Among these, the physical layer initializes the link of two devices on the link, and manages the low-level operation of the data transfer and power saving functions. The data link layer provides the transaction layer with a reliable data transfer service and a communication mechanism that can perform flow control and power link management with little overhead. The transaction layer generates and consumes data packets that are used to implement the load / store data transfer mechanism and also manages the flow control of these packets between the two components on the link.

  In the PCI Express standard, after the power is turned on to the device, the initialization process of the device itself is completed within 100 milliseconds after the reset is released, and the link training sequence is entered. Then, it is stipulated that the link establishment process must be completed and the link up must be made so that a configuration request can be accepted.

  However, in a configuration where there is a difference in the initialization processing time for each device that performs communication, the initialization processing of one device does not end, and the time required for the link training sequence is within the time specified by the PCI Express standard. Sometimes it cannot be secured. For this reason, there is a problem that communication devices cannot be linked up.

  In order to solve such a problem, as shown in FIG. 6, power is supplied from a relay unit (for example, PCIe switch) 13 and a power supply unit 15 between two PCIe communication devices 11 and 12 that perform link-up. A configuration is known in which a power supply control unit 14 for controlling the power supply is provided. With this configuration, in response to the power supply to the PCIe communication device 12 that takes a long time for the initialization process, the power supply to the relay unit 13 is performed after receiving the notification that the activation process of the PCIe communication device 12 has been completed. Control for delaying power supply is executed by the power supply controller 14. By delaying the power supply in this way, it becomes possible to delay the reset release performed by the relay unit 13 together, and control is performed so that the initialization process is completed and the link up is performed before entering the link training sequence. (For example, refer to Patent Document 1).

JP 2012-022477 A

  However, in the above conventional example, control is performed so that reset release is delayed and link-up is performed by controlling the power supply timing to the relay unit. There is a problem that becomes longer. In addition, since a relay unit is required between devices that communicate by PCI Express, there is a problem that the component cost and board area of the apparatus increase.

  The present invention has been made in view of the above-described conventional example, and an object of the present invention is to provide a recording apparatus that can perform initialization of a device that employs PCI Express at high speed and at low cost using a miniaturized configuration. And

  In order to achieve the above object, the recording apparatus of the present invention has the following configuration.

  That is, a recording apparatus including a first device and a second device configured to perform data communication in accordance with PCI Express, wherein the first device and the first device are configured in response to an activation instruction to the recording apparatus. A power supply control unit that starts supplying power to the second device and outputs an output stabilization signal indicating that the supply voltage is stabilized; receives the output stabilization signal from the power supply control unit; and responds to the reception Instructing the first device, which requires a longer time for the initialization process than the second device, to start the initialization process prior to the start of the link establishment process of the second device. And a control means.

  Therefore, according to the present invention, the device that takes time for the initialization process is instructed to start the initialization process prior to the start of the link establishment process of another device. There is an effect that it becomes possible. Further, since an intermediate apparatus is not required between devices that employ PCI Express as in the prior art, there is an effect that the apparatus can be further miniaturized and the apparatus cost can be reduced.

1 is an external perspective view of a recording apparatus that uses an A0 or B0 size recording medium that is a typical embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of the recording apparatus illustrated in FIG. 1. 2 is a block diagram illustrating a detailed configuration of a printer controller. FIG. 6 is a timing chart up to link-up using PCI Express according to an embodiment of the present invention. It is a timing chart as a comparative example in the case of not applying the PCI Express control method according to the embodiment of the present invention. It is a block diagram explaining the power control method of the communication device according to the conventional PCI Express.

  Hereinafter, preferred embodiments of the present invention will be described more specifically and in detail with reference to the accompanying drawings.

  In this specification, “recording” (sometimes referred to as “printing”) is not limited to the case of forming significant information such as characters and graphics, but may be significant. Furthermore, it also represents a case where an image, a pattern, a pattern, or the like is widely formed on a recording medium or a medium is processed regardless of whether or not it is manifested so that a human can perceive it visually.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Further, “ink” (sometimes referred to as “liquid”) should be interpreted widely as in the definition of “recording (printing)”. Therefore, by being applied on the recording medium, it is used for formation of images, patterns, patterns, etc., processing of the recording medium, or ink processing (for example, solidification or insolubilization of the colorant in the ink applied to the recording medium). It shall represent a liquid that can be made.

  Furthermore, unless otherwise specified, the “recording element” collectively refers to an ejection port or a liquid path communicating with the ejection port and an element that generates energy used for ink ejection.

<Overview of recording apparatus (FIGS. 1-2)>
FIG. 1 is an external perspective view of an ink jet recording apparatus using a recording medium having a large size such as A0 or B0, which is a typical embodiment of the present invention.

  An ink jet recording apparatus (hereinafter referred to as a recording apparatus) 100 shown in FIG. 1 can perform recording on roll paper having a size of 10 inches to 44 inches. The recording apparatus 100 includes a stand 101 on which a main body unit is placed, and a stacker 102 on which the discharged recording sheets are stacked. Further, the recording apparatus 100 is provided with a display panel 103 for displaying various recording information and setting results, and an operation panel 104 for setting a recording mode, recording paper, and the like. . An upper cover 106 that can be opened and closed is also provided.

  Further, on both sides of the recording apparatus 100, an ink tank accommodating portion 105 for accommodating ink tanks such as black, cyan, magenta, and yellow and supplying ink to the recording head is disposed.

  FIG. 2 is a block diagram showing a control configuration of the recording apparatus shown in FIG.

  As shown in FIG. 2, the recording apparatus 100 is connected to a host apparatus 150 via an external communication interface 140, receives image data transmitted from the host apparatus 150, and places an image on a recording medium such as recording paper. Form. The recording apparatus 100 includes a printer controller 110, a printer engine 120, a power control unit 130, and the like. Although the configuration and functions of the printer controller will be described in detail later, the printer controller receives image data from the host device and performs image processing, performs recording control of the printer engine, and records an image by the printer engine.

  The power control unit 130 controls power supply to each block such as the printer controller 110 and the printer engine 120, and notifies an output stability signal (Power-good) to the functional block of the printer controller when the output of the power supply is stabilized. .

<Configuration of printer controller (FIG. 3)>
FIG. 3 is a block diagram showing a detailed configuration of the printer controller 110.

  The printer controller 110 receives a print instruction and image data for printing from a host device such as a personal computer, converts the received image data into binary image data that can be printed by a printer engine (not shown), and To 120. As shown in FIG. 3, the printer controller 110 includes a main control unit 202 and a function expansion unit 301 that can expand the functions of the printing apparatus.

  The main control unit 202 includes an ASIC 203, an operation unit 216, a display unit 217, an RTC 219, an EEPROM 220, a RAM 221 and a ROM 222.

  The ASIC 203 includes a CPU 204, an image processing unit 205, an operation unit control circuit unit 206, a display unit control circuit unit 207, a network interface 208, an internal signal communication unit 209, and a PCI Express communication unit 218. The ASIC 203 further includes a serial communication control circuit unit 210, an EEPROM controller 211, a RAM controller 212, a ROM controller 213, and a printer engine interface 214.

  Each of these blocks is connected to the system bus bridge 215 via a bus line. These blocks are mounted as a system semiconductor device, that is, as an ASIC 203 sealed in one package.

  The CPU 204 governs overall control of the printer controller 110 and sequentially reads and executes control procedures stored in the RAM 221 or the ROM 222. Accordingly, the CPU 204 performs control / instruction to the PCI Express communication unit 218 to perform initialization processing, control of link establishment, and the like. In addition, the CPU 204 controls the operation unit 216 and the display unit 217 via the operation unit control circuit unit 206 and the display unit control circuit unit 207. Further, the CPU 204 controls the image processing unit 205 for converting the received image data into recording data for image formation, and controls the printer engine interface 214 for transferring the generated recording data to the printer engine 120. Etc.

  The image processing unit 205 converts the image data received from the host device 150 into binary image data that can be printed by the printer engine 120. The operation unit control circuit unit 206 notifies the state of the electrical signal output from the switch constituting the operation unit 216 as register information in response to a read command from the CPU 204. When a change occurs in the state of the electrical signal output from the switch, the operation unit control circuit unit 206 generates an interrupt signal and transmits the interrupt signal to the CPU 204. The display unit control circuit unit 207 outputs an electrical signal to the LCD and the LED lamp that constitute the display unit 217.

  The network interface 208 is a block that provides a transmission / reception function conforming to a network communication system such as 1000BASE-T. Further, the network interface 208 may include a display unit (not shown) such as an LED indicating the connected network communication speed. The network interface 208 transmits / receives data to / from a host device 150 such as a personal computer or a workstation connected via the network, and transmits a message to an SMTP server connected to the network.

  The serial communication control circuit unit 210 controls the RTC 219 connected to the ASIC 203 via the serial communication interface. On the other hand, the CPU 204 can read the information of the connected RTC 219 by reading the value of the register of the serial communication control circuit unit 210 and executing the writing, and also writes the information to the RTC 219. As a communication method of the serial communication interface, any one of I2C (registered trademark) of the 2-wire interface, SPI (registered trademark) of the 3-wire interface, and Microwire (registered trademark) may be adopted. Good.

  The EEPROM controller 211 controls the EEPROM 220 connected to the ASIC 203 via a serial communication interface. The EEPROM controller 211 generates a necessary control signal in response to a read request from the CPU 204, reads data stored in advance in the EEPROM 220, and sends the read contents back to the CPU 204 via the system bus bridge 215. The EEPROM controller 211 generates necessary control signals in response to a write request from the CPU 204 and rewrites the contents of the EEPROM 220 via the serial communication interface. Note that the communication method of the serial communication interface is any one of I2C (registered trademark), SPI (registered trademark), and Microwire (registered trademark), as is the case with the serial communication interface connecting the RTC 219. Also good.

  The RTC 219 and the EEPROM 220 are controlled by different control blocks, that is, the serial communication control circuit unit 210 and the EEPROM controller 211. However, an RTC device and an EEPROM device may be connected to one control block, and a device to be accessed may be specified according to device address information.

  The RAM controller 212 controls the RAM 221 connected to the ASIC 203 via the RAM bus. The RAM controller 212 relays data to be written or read between each block having the CPU 204 and the DMAC and the RAM 221. The RAM controller 212 generates necessary control signals in response to read requests and write requests from the CPU 204 and each block, and executes writing to the RAM 221 and reading from the RAM 221.

  The ROM controller 213 controls the ROM 222 connected to the ASIC 203 via the ROM bus. The ROM controller 213 generates necessary control signals in response to a read request from the CPU 204, reads control procedures and data stored in advance in the ROM 222, and sends the read contents to the CPU 204 via the system bus bridge 215. Forward. When the ROM 222 is configured by an electrically rewritable device such as a flash memory, the ROM controller 213 generates a necessary control signal and rewrites the contents of the ROM 222.

  The internal signal communication unit 209 performs control to transmit / receive data to / from the power supply control unit 130, the ASIC 302 included in the function expansion unit 301, the clock control unit 311, the reset control unit 313, and the like.

  The PCI Express communication unit 218 is controlled by the CPU 204, performs initialization processing and link establishment processing, and performs data communication by connecting to the PCI Express communication unit 305 of the ASIC 302 included in the function expansion unit 301. In addition, since the PCI Express communication unit 218 includes software processing such as execution of internal register setting processing in the initialization processing controlled and executed by the CPU 204, the processing time varies depending on changes in the conditions of the software processing load and the electrical time constant. . For this reason, it may not be possible to secure the time required for the link training sequence and the opposite device for performing link-up communication by PCI Express within 100 milliseconds defined by the standard. On the other hand, in the link training sequence, it is required that a time during which link establishment processing is simultaneously performed in each device that performs communication is secured for several tens of milliseconds or more. The PCI Express communication unit 218 is referred to as a first device, and the PCI Express communication unit 305 is referred to as a second device.

  The printer engine interface 214 is a block that transmits and receives data between the printer controller 110 and the printer engine 120. The printer engine interface 214 has a DMAC. The printer engine interface 214 sequentially reads binary image data generated by the image processing unit 205 and stored in the RAM 221 via the RAM controller 212 and transfers the binary image data to the printer engine 120.

  Similar to the printer engine interface 214, the image processing unit 205, the network interface 208, and the PCI Express communication unit 218 have a DMAC and issue a memory access request. The system bus bridge 215 connects blocks constituting the ASIC 203, and arbitrates bus rights when access requests are issued simultaneously from a plurality of blocks. When the CPU 204 and each block having the DMAC issue an access request to the RAM 221 almost simultaneously via the RAM controller 212, the system bus bridge 215 performs arbitration according to a priority designated in advance.

  The operation unit 216 includes switches that are linked to buttons for setting the operation of the recording apparatus 100, and outputs the state of these switches as an electrical signal. In addition, the operation unit 216 outputs a change in the switch state caused by operating the operation button as a change in the electrical signal. The operation unit 216 includes an online button for switching the operation mode, a menu button for instructing display of the menu screen, an up / down / left / right cross button for selecting an item from the menu screen, and an OK button for confirming the selection item. The operation unit 216 includes a stop button for instructing to stop printing and a paper feed selection button for selecting a recording paper feeding method.

  The display unit 217 includes an LCD and an LED lamp. The LCD displays an operating state of the recording apparatus 100 and displays a menu screen by operating a menu button or the like of the operation unit 216. The LED lamp displays the operation status of the recording apparatus 100 and a warning.

  The RTC (real-time controller) 219 includes an RTC device having a serial communication interface, a crystal resonator for generating a reference clock, and the like. The RTC 219 measures the time in units of year, month, day of the week, and second, and notifies the time information via the serial communication interface.

  The EEPROM 220 is configured by an EEPROM or the like having a serial communication interface, and stores parameters necessary for controlling the recording apparatus 100. The RAM 221 is configured by a synchronous DRAM or the like, and provides a storage of control procedures executed by the CPU 204, temporary storage of recording data for image formation generated by the image processing unit 205, a work area of the CPU 204, and the like.

  The RAM 221 is used by the network interface 208 for temporarily buffering image data received from the host device 150, temporarily storing data transferred to and from the function expansion unit, and the like.

  The ROM 222 is configured with a flash memory or the like, and stores a control procedure executed by the CPU 204. The flash memory is an electrically rewritable nonvolatile device, and the control procedure can be rewritten by following a predetermined sequence.

  In addition, each circuit block includes a register for setting an operation mode and the like, and the CPU 204 can set the operation mode and the like of each circuit block via a register access bus (not shown).

  The function expansion unit 301 is connected to the main control unit 202 via an internal signal communication unit or a PCI Express communication unit. The function expansion unit 301 includes an ASIC 302, a RAM 309, a ROM 310, a clock control unit 311, and a clock 312.

  The ASIC 302 includes a CPU 303, an internal signal communication unit 304, a PCI Express communication unit 305, a RAM controller 306, and a ROM controller 308. Each of these blocks is connected to the system bus bridge 307 via a bus line. These blocks are mounted as a system semiconductor device, that is, as an ASIC 302 sealed in one package.

  Each block of the ASIC 302 has the same function as each block of the ASIC 203, and the details of each function are omitted.

  The clock control unit 311 receives a notification of an output stability signal (Power-good) 401 indicating that the power supply is stable from the power control unit 130. Then, a reference clock output control signal (REFCLK-EN) 404 to the PCI Express communication unit 305 is notified to the clock 312. Also, a signal for starting processing (Delayed power-good) 405 is notified to the internal signal communication unit 209 of the ASIC 203.

  The clock 312 is composed of a crystal resonator or the like for generating a reference clock, and supplies the reference clock to the ASIC 302. Further, a reference clock (PCIe REFCLK) 403 is output to the PCI Express communication units 218 and 305 in accordance with an output control signal (REFCLK-EN) from the clock control unit 311.

  The reset control unit 313 controls the output of the reset signal (PLTRST-N) 402 in response to the notification of the output voltage stabilization signal (Power-good) 401 from the power supply control unit 130 and resets to the internal signal communication units 209 and 304. Output a signal. Thereby, the reset of the main control unit and the function expansion unit is released.

  In this embodiment, the function expansion unit 301 receives image data (hereinafter referred to as PDL data) described in PDL received from the host device 150 from the main control unit 202. Then, a display list that is intermediate data is generated and rendered, and the rendered data is sent to the main control unit 202.

  First, when PDL data is received from the host device 150 via the network interface 208, the CPU 204 stores the received PDL data in the RAM 309 of the function expansion unit 301 via the PCI Express communication unit 218. The CPU 303 executes a program stored in the ROM 310 to generate and render a display list that is intermediate data from the PDL data stored in the RAM 309. Then, the CPU 303 sends the rendered data again to the RAM 221 of the main control unit 202 via the PCI Express communication unit 305 and stores it.

  Therefore, the ROM 310 stores a control program for the function expansion unit 301 and a conversion program for processing PDL data. The RAM 309 can read and write data, expands the program in the ROM 310, and is used as a work area for execution of the control program of the function expansion unit and PDL data processing. The RAM 309 is also used as a buffer memory for temporarily storing various control data transmitted / received to / from the host device 150.

  Thus, from the viewpoint of processing of PDL data, the main control unit 202 and the function expansion unit 301 distribute the processing load, the main control unit 202 takes charge of part of the image processing, and the function expansion unit 301 He is in charge of the rest of the image processing.

  The printer engine 120 is a printing mechanism that prints an image on a recording medium based on the binary image data sent from the printer controller 110.

  Next, the timing of initialization processing and link establishment processing of the PCI Express communication unit will be described with reference to the drawings.

1. Description of Comparative Example (FIG. 4)
First, referring to a comparative example with respect to the embodiment of the present invention, it will be described how much time is required for link-up between communication devices when the PCI Express control method according to the embodiment of the present invention is not applied.

  FIG. 4 is a timing chart up to link-up between communication devices when the PCI Express control method according to the embodiment of the present invention is not applied.

  According to FIG. 4, the recording apparatus 100 is turned on and power supply is started by the power supply control unit 130. After a while, the output of the supply voltage is stabilized. When the output of the supply voltage becomes stable, the power supply control unit 130 notifies the clock control unit 311, the reset control unit 313, and the internal signal communication units 209 and 304 of the output stable signal (Power-good) 401 at time t = T3. . At time t = T4, the clock control unit 311 that has received the output stable signal (Power-good) 401 notifies the clock 312 of the output control signal (REFCLK-EN) 404 of the reference clock and controls the output of the reference clock. I do.

  In response to this, the clock 312 receives the output control signal (REFCLK-EN) 404 from the clock control unit 311 and outputs the reference clock (PCIe REFCLK) 403 at time t = T5.

  The reset control unit 313 controls the output of the reset signal (PLTRST-N) 402 upon receiving a notification of the output voltage stabilization signal (Power-good) 401 from the power supply control unit 130 at time t = T1. The internal signal communication units 209 and 304 are notified. The reset of the main control unit and the function expansion unit is released. After the reset is released, at time t = T11, the CPUs 204 and 303 start initialization of the PCI Express communication units 218 and 305 and link establishment processing.

  At time t = T12, the initialization process of the PCI Express communication unit 218 ends and the link establishment process is started. On the other hand, a certain time (time until time t = T13) is required to perform the link training sequence between the PCI Express communication units 218 and 305. However, as can be seen from FIG. 4, the time t = T13 is a time that has passed the specified time (T1 to T2), and the time required for link training is ensured by the time t = T2, which is the longest time of the specified time. Can not do it. When the specified time elapses, that is, when the time t = T2 is reached, the PCI Express communication unit 305 ends the link establishment process, and the link up is not established.

  As described above, when the PCI Express control method of the present invention is not applied, the time required for the link-up training sequence between the PCI Express communication units 218 and 305 is set within the specified time (T1 to T2: 100 ms). As a result, data cannot be transferred without being able to link up between PCI Express communication devices.

2. Description of the embodiment of the present invention (FIG. 5)
FIG. 5 is a timing chart up to PCI Express link-up.

  First, the power of the recording apparatus 100 is turned on, and power supply from the power control unit 130 is started. When the output of the supply voltage is stabilized, at time t = T3, the power supply control unit 130 notifies the output stabilization signal (Power-good) 401 of the clock control unit 311, the reset control unit 313, and the internal signal communication units 209, To 304. The clock control unit 311 that has received the output stable signal (Power-good) 401 notifies the reference clock output control signal (REFCLK-EN) 404 to the clock 312 at time t = T4 to control the output of the reference clock. I do. At the same time (t = T4), the clock control unit 311 notifies the internal signal communication unit 209 of a processing start signal (Delayed power-good) 405.

  At time t = T5, the clock 312 receives the output control signal (REFCLK-EN) 404 from the clock control unit 311 and outputs the reference clock (PCIe REFCLK) 403.

  Next, the internal signal communication unit 209 notifies the CPU 204 of reception of a processing start signal (Delayed power-good) 405. The CPU 204 that has received the notification from the internal signal communication unit 209 starts initialization and link establishment processing of the PCI Express communication unit 218 at time t = T6 after the output stabilization time (several ms) of the reference clock has elapsed.

  That is, the reset control unit 313 controls the reset signal (PLTRST-N) 402 in response to the notification of the output stable signal (Power-good) 401 of the supply voltage from the power supply control unit 130. At time t = T1, a reset signal (PLTRST-N) 402 is notified to the internal signal communication units 209 and 304, and the reset of the main control unit and the function expansion unit is released.

  After the reset is released, at time t = T7, the PCI Express communication unit 305 starts initialization and link establishment processing by hardware operation without intervention of software control. Further, at time t = T8, the initialization of the PCI Express communication unit 218 is completed and the link establishment process is started.

  In this way, at time t = T9, the link training sequence is performed between the PCI Express communication units 218 and 305, the link establishment process is completed, and the link is established. That is, at time t = T8, initialization and link establishment processing of the PCI Express communication unit 218 are completed, and at time t = T9, initialization and link establishment processing of the PCI Express communication unit 305 are completed and link up is performed.

  In this way, the processing of the PCI Express communication unit 218, which takes time for initialization and link establishment processing, is started by notification of the REFCLK-EN signal, so that the time necessary for the link training sequence is ensured within the specified time from reset release. can do. The specified time is 100 milliseconds between T1 and T2, as shown in FIG. Therefore, it is possible to link up between PCI Express communication units and perform data transfer.

  Therefore, according to the embodiment described above, in a system that performs PCI Express communication, processing is started for a device that takes time for initialization processing and link establishment processing using the processing start signal 405 prior to reset release instead of reset release. Can be controlled. By performing this control, the time required for the link training sequence can be secured within a specified time (100 milliseconds between T1 and T2). As a result, it is possible to guarantee link-up of the PCI Express communication unit and to suppress a delay in the startup time of the recording apparatus.

  In the embodiment described above, since the PCI Express communication unit can control communication by adding a signal line without requiring an intermediate device, the component cost of the entire device is reduced and the area of the ASIC board is reduced. Thus, the size of the apparatus can be reduced.

  In the embodiment described above, only the PCI Express communication unit 218 on the main control unit side is controlled to start the initialization process at the timing when the reference clock is stabilized. It is also possible to control. Further, both PCI Express communication units may be controlled in the same manner.

  In the embodiment described above, the CPU 204 controls the initialization processing of the PCI Express communication unit 218 such that the time for which the reference clock is stabilized is measured by the information from the RTC 219 and waits to start. However, the present invention is not limited to this, and the processing start signal 405 itself to be notified may be configured to be delayed for a predetermined time. At that time, the configuration for delaying the signal for a predetermined time can be easily realized by appropriately setting the time constant of the delay circuit with the resistor and the capacitor, which contributes to the suppression of the circuit scale and the cost of the circuit. It will be a thing.

  Furthermore, in the embodiment described above, the clock control unit 311, the clock 312, and the reset control unit 313 are mounted on the function expansion unit side. However, the configuration is not limited to this, and the configuration is mounted on the main control unit side. Also good. The power supply control unit 130 may also be configured in the printer controller 110.

  In the embodiment described above, the PCI Express control after power-on has been described. However, the present invention is not limited to this, and for example, the same as the above-described embodiment when returning from a hibernation state or returning from hibernation. Such control may be performed.

  In the above-described embodiment, the recording apparatus using the ink jet recording method for recording on a large-sized recording medium of A0 or B0 size has been described as an example. However, the present invention is limited to the above-described embodiment. Rather, various applications are possible. For example, the present invention can be applied to an office or personal use ink jet recording apparatus using a small size recording medium such as A4 or B5, a laser beam printer, or the like. Further, it is apparent that the present invention can be applied not only to a recording apparatus but also to other electronic devices that perform communication using PCI Express, such as a multifunction printer apparatus incorporating a scanner or a facsimile function.

  Further, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention at the stage of implementation. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When the effect is obtained, the constituent requirement is extracted as the deleted invention.

Claims (8)

A recording apparatus comprising a first device and a second device configured to perform data communication in accordance with PCI Express,
A power supply controller that starts supplying power to the first device and the second device in response to a start instruction to the recording apparatus and outputs an output stabilization signal indicating that the supply voltage is stable; ,
A link of the second device to the first device that receives the output stabilization signal from the power supply control unit and takes time for an initialization process compared to the second device in response to the reception. And a control unit that instructs to start the initialization process prior to the start of the establishment process. A clock for supplying a reference clock for operation to the first device and the second device;
The control means controls the clock to supply the reference clock to the first device and the second device in response to reception of the output stabilization signal. The recording apparatus according to 1.   The first device starts link establishment processing after completion of the initialization processing, and the second device starts link establishment processing after reset release in response to reception of the output stabilization signal. The recording apparatus according to claim 1 or 2.   The recording apparatus according to claim 3, wherein a longest time from the reset release to the end of the link establishment process is predetermined. The recording device comprises:
A printer engine for recording an image on a recording medium based on image data received from a host device;
A printer controller that receives the image data from the host device, executes image processing, supplies recording data to the printer engine, and controls recording of the printer engine;
The controller is
The first device performs reception of the image data, a part of the image processing, and recording control of the printer engine,
The recording apparatus according to claim 1, wherein the second device executes the remaining part of the image processing. The image data received from the host device is PDL data,
The recording apparatus according to claim 5, wherein the second device executes processing of the PDL data.   The PDL data and the rendered data obtained by processing the PDL data are transferred between the first device and the second device in accordance with PCI Express. 6. The recording device according to 6.   The recording apparatus according to claim 5, wherein the printer engine performs recording according to an inkjet recording method.

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