JP2014067994A - Nitride semiconductor wafer, nitride semiconductor element, and method of manufacturing nitride semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor wafer with suppressed cracks and low dislocation density, a nitride semiconductor element, and a method of manufacturing the nitride semiconductor wafer.SOLUTION: In a nitride semiconductor wafer 110 including a silicon substrate 40, a first buffer portion 51, a silicon-containing portion 55, and an upper layer portion 15, the first buffer portion 51 is provided on the silicon substrate 40 and includes first to n-th buffer layers BF1 to BFn containing a nitride semiconductor. The i-th buffer layer BFi of the first to n-th buffer layers BF1 to BFn has a lattice length Wi, the (i+1)-th buffer layer BF(i+1) on the i-th buffer layer BFi has a lattice length W(i+1), and the i-th buffer layer BFi and the (i+1)-th buffer layer BF(i+1) satisfy the relationship of 0.003≤(W(i+1)-Wi)/Wi≤0.008. The silicon-containing portion 55 is provided on the first buffer portion 51. The upper layer portion 15 contains a nitride semiconductor and is provided on the silicon-containing portion 55.

Description

  Embodiments described herein relate generally to a nitride semiconductor wafer, a nitride semiconductor element, and a method for manufacturing a nitride semiconductor wafer.

  There is a nitride semiconductor wafer in which a semiconductor layer containing a nitride semiconductor is formed on a silicon substrate. Nitride semiconductor wafers are used, for example, in the manufacture of light emitting diodes (LEDs), high speed electronic devices or power devices. The nitride semiconductor wafer has a problem that cracks are likely to occur in the semiconductor layer during manufacturing due to the difference between the thermal expansion coefficient of the silicon substrate and the thermal expansion coefficient of the semiconductor layer. There is a technique for suppressing the generation of cracks by applying compressive stress to the nitride semiconductor layer. However, when compressive stress is applied to the nitride semiconductor layer, it is difficult to reduce threading dislocations.

JP-T 2009-527913

  Embodiments of the present invention provide a nitride semiconductor wafer, a nitride semiconductor element, and a method for manufacturing a nitride semiconductor wafer that suppress cracks and have a low dislocation density.

  According to the embodiment of the present invention, a nitride semiconductor wafer including a silicon substrate, a first buffer unit, a silicon-containing unit, and an upper layer unit is provided. The first buffer unit is provided on the silicon substrate and includes first to nth buffer layers (n is an integer of 2 to 9) including a nitride semiconductor. The i-th buffer layer (i is an integer not less than 1 and less than n) among the first to n-th buffer layers has a lattice length Wi in a first direction parallel to the main surface of the first buffer layer. . The (i + 1) th buffer layer provided on the i-th buffer layer has a lattice length W (i + 1) in the first direction. In the first to n-th buffer layers, the i-th buffer layer and the (i + 1) -th buffer layer satisfy a relationship of 0.003 ≦ (W (i + 1) −Wi) /Wi≦0.008. The silicon-containing part is provided on the first buffer part and contains silicon. The upper layer portion is provided on the silicon-containing portion and includes a nitride semiconductor. The dislocation density of the upper layer part is less than the dislocation density of the first buffer part.

1 is a schematic cross-sectional view showing a nitride semiconductor wafer according to a first embodiment. It is a reciprocal lattice space mapping diagram showing the characteristics of the nitride semiconductor wafer according to the first embodiment. It is a reciprocal lattice space mapping figure which shows the characteristic of a reference example. FIG. 4A to FIG. 4D are electron micrographs showing a part of the nitride semiconductor wafer according to the first embodiment. It is a table | surface which shows the characteristic of the nitride semiconductor wafer which concerns on 1st Embodiment. It is a graph which shows the characteristic of the nitride semiconductor wafer which concerns on 1st Embodiment. It is a table | surface which shows the characteristic of the nitride semiconductor wafer which concerns on 1st Embodiment. It is a graph which shows the characteristic of the nitride semiconductor wafer which concerns on 1st Embodiment. It is a graph which shows the characteristic of the nitride semiconductor wafer which concerns on 1st Embodiment. It is a graph which shows the characteristic of the nitride semiconductor wafer which concerns on 1st Embodiment. It is a typical sectional view showing another nitride semiconductor wafer concerning a 1st embodiment. It is a typical sectional view showing another nitride semiconductor wafer concerning a 1st embodiment. 4 is a schematic cross-sectional view showing a part of another nitride semiconductor wafer according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing a part of another nitride semiconductor wafer according to the first embodiment. FIG. It is a graph which shows the characteristic of another nitride semiconductor wafer concerning a 1st embodiment. It is a typical sectional view showing another nitride semiconductor wafer concerning a 1st embodiment. 5 is a schematic cross-sectional view showing a nitride semiconductor device according to a second embodiment. FIG. FIG. 18A to FIG. 18E are schematic cross-sectional views in order of steps showing the method for manufacturing the nitride semiconductor wafer according to the third embodiment. It is a flowchart figure which shows the manufacturing method of the nitride semiconductor wafer which concerns on 3rd Embodiment.

Each embodiment will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
The nitride semiconductor wafer 110 according to the present embodiment is used for manufacturing a nitride semiconductor device such as a semiconductor light emitting device, a semiconductor light receiving device, or an electronic device, for example. The semiconductor light emitting element includes, for example, a light emitting diode (LED) and a laser diode (LD). The semiconductor light receiving element includes, for example, a photodiode (PD). The electronic device includes, for example, a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a field transistor (FET), a Schottky barrier diode (SBD), and the like.

FIG. 1 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor wafer according to the first embodiment.
As illustrated in FIG. 1, the nitride semiconductor wafer 110 according to this embodiment includes a silicon substrate 40, a first buffer unit 51, a silicon-containing unit 55, and an upper layer unit 15.
The first buffer unit 51 is provided on the silicon substrate 40. The silicon-containing part 55 is provided on the first buffer part 51. The silicon containing portion 55 contains silicon. The upper layer part 15 is provided on the silicon-containing part 55. The upper layer portion 15 includes a nitride semiconductor. The upper layer portion 15 includes at least one of the second buffer portion 52 and the functional layer 10s. The second buffer unit 52 is provided on the silicon-containing unit 55. The second buffer unit 52 includes a nitride semiconductor. The functional layer 10 s is provided on the second buffer unit 52. The functional layer 10s includes a nitride semiconductor. The functional layer 10s includes an impurity-containing layer IL containing impurities. The impurity concentration of the impurity-containing layer IL is higher than the impurity concentration of the second buffer unit 52.

Here, the stacking direction from the silicon substrate 40 toward the functional layer 10s is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is taken as an X-axis direction. A direction perpendicular to the Z-axis direction and the X-axis direction is taken as a Y-axis direction.
In the specification of the application, “stacking” includes not only the case of being stacked in contact with each other but also the case of being stacked with another layer inserted therebetween. Further, “provided on” includes not only the case of being provided in direct contact but also the case of being provided with another layer interposed therebetween.

  The first buffer unit 51 includes a plurality of buffer layers of a first buffer layer BF1 to an nth buffer layer BFn. However, n is an integer of 2-9. The i-th buffer layer BFi among the first buffer layer BF1 to the n-th buffer layer BFn has a lattice length Wi in the first direction parallel to the main surface BF1a of the first buffer layer BF1. However, i is an integer of 1 or more and less than n.

  The (i + 1) th buffer layer BF (i + 1) provided on the i-th buffer layer BFi has a lattice length W (i + 1) in the first direction. For example, the (i + 1) th buffer layer BF (i + 1) is in contact with the i-th buffer layer BFi.

  In the first buffer layer BF1 to the nth buffer layer BFn, two adjacent buffer layers (that is, the i-th buffer layer BFi and the (i + 1) th buffer layer BF (i + 1)) are all (W (i + 1) −Wi) / The relationship of Wi ≦ 0.008 is satisfied. As will be described later, (W (i + 1) −Wi) / Wi is preferably 0.003 or more.

  For example, when the main surface BF1a of the first buffer layer BF1 is a c-plane, the first direction is, for example, the a-axis direction. For example, the lattice length Wi is the lattice length in the a-axis direction in the i-th buffer layer BFi.

  Below, in order to demonstrate easily, it demonstrates as a case where a 1st direction is a-axis direction. However, in the embodiment, the first direction can be an arbitrary direction parallel to the main surface BF1a (XY plane). In the following description, the a-axis direction is the main surface BF1a (XY). The present invention can be applied to an arbitrary direction parallel to a plane.

The first buffer layer BF1 to the nth buffer layer BFn include a nitride semiconductor. The first buffer layer BF1 includes, for example, Al _x1 Ga _1-x1 N (0 <x1 ≦ 1). The n-th buffer layer BFn includes, for example, Al _xn Ga _1-xn N (0 ≦ xn <x1). The i-th buffer layer BFi between the first buffer layer BF1 and the n-th buffer layer BFn includes, for example, Al _xi Ga _1-xi N (xn <xi <x1). The first buffer layer BF1 is, for example, an AlN layer. The nth buffer layer BFn is, for example, an AlGaN layer or a GaN layer. The i-th buffer layer BFi between the first buffer layer BF1 and the n-th buffer layer BFn is, for example, an AlGaN layer. When the n-th buffer layer BFn is an AlGaN layer, the Al composition ratio of the AlGaN layer of the i-th buffer layer BFi between the first buffer layer BF1 and the n-th buffer layer BFn is equal to that of the AlGaN layer of the n-th buffer layer BFn. Higher than the Al composition ratio.

A lattice mismatch rate LM in the first direction (for example, the a-axis direction) between the i-th buffer layer BFi and the (i + 1) -th buffer layer BF (i + 1) is obtained by Expression (1).

[Equation 1]
LM = (W (i + 1) −Wi) / Wi × 100 (%) (1)

In the following, the lattice mismatch rate in the a-axis direction obtained from the physical property values of the AlN layer and the GaN layer is LMc, the lattice mismatch rate in the a-axis direction obtained from the experimental values of the AlN layer and the GaN layer is LMt, In the first buffer layer BF1 to the nth buffer layer BFn, the lattice mismatch rate in the a-axis direction of two adjacent buffer layers will be described as LMx.
For example, in the first buffer layer BF1 to the nth buffer layer BFn, the lattice mismatch ratio LMx in the a-axis direction of two adjacent buffer layers all satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%.

  The first buffer layer BF1 is an AlN layer, and the nth buffer layer BFn is a GaN layer. The lattice mismatch factor LMc in the a-axis direction obtained from the physical property values of the AlN layer and the GaN layer is 2.5%. The lattice mismatch factor LMt in the a-axis direction obtained from experimental values of the AlN layer and the GaN layer is, for example, 1.9% to 2.5%. That is, the lattice mismatch factor LMt in the first direction between the first buffer layer BF1 and the n-th buffer layer BFn is 1.9% to 2.5%.

  In the first buffer layer BF1 to the nth buffer layer BFn, the lattice mismatch rate LMx in the a-axis direction of two adjacent buffer layers is assumed to be constant. At this time, when the lattice mismatch ratio LMx is 0.3%, since 0.3 × 8 = 2.4, the first buffer layer BF1 that is an AlN layer and the nth buffer layer BFn that is a GaN layer The number of AlGaN layers provided between the two is seven.

  That is, the maximum value of the number n of buffer layers provided in the first buffer unit 51 is 9, which is obtained by adding the AlN layer and the GaN layer to the number 7 of the AlGaN layers. The minimum value of the number n is, for example, 2 for the AlN layer and the AlGaN layer thereon. For this reason, the number n is an integer of 2 to 9.

  When an AlN layer is formed on the silicon substrate 40, the lattice in the a-axis direction of the AlN layer is pulled by a lattice constant difference between AlN and silicon. When a GaN layer is formed on an AlGaN layer, the lattice in the a-axis direction of the GaN layer is compressed by the lattice constant difference between GaN and AlGaN. For this reason, the lattice mismatch ratio LMt in the a-axis direction between the AlN layer and the GaN layer tends to be smaller than 2.5%. According to an experiment in which a plurality of samples of the nitride semiconductor wafer were prepared and the lattice mismatch ratio LMt in the a-axis direction between the AlN layer and the GaN layer of the plurality of samples was measured, the average value of the lattice mismatch ratio LMt is About 2.1%. That is, the actual lattice mismatch ratio LMt between the AlN layer and the GaN layer in the a-axis direction is, for example, not less than 2.0% and not more than 2.2%.

  In the first buffer layer BF1 to the nth buffer layer BFn, the lattice mismatch factor LMx in the a-axis direction of two adjacent buffer layers is adjusted by changing the Al composition ratio. The Al composition ratio is gradually decreased from the first buffer layer BF1 toward the nth buffer layer BFn. That is, the Al composition ratio in the (i + 1) th buffer layer BF (i + 1) is lower than the Al composition ratio in the i-th buffer layer BFi.

In the following description, the number n of layers provided in the first buffer unit 51 is assumed to be 5.
That is, the first buffer unit 51 includes the first buffer layer BF1 to the fifth buffer layer BF5. The first buffer layer BF1 is provided on the silicon substrate 40. The second buffer layer BF2 is provided on the first buffer layer BF1. The third buffer layer BF3 is provided on the second buffer layer BF2. The fourth buffer layer BF4 is provided on the third buffer layer BF3. The fifth buffer layer BF5 is provided on the fourth buffer layer BF4. In this example, the fifth buffer layer BF5 is the nth buffer layer BFn.

The first buffer layer BF1 includes, for example, Al _x1 Ga _1-x1 N (0 <x1 ≦ 1). The second buffer layer BF2 includes, for example, Al _x2 Ga _1-x2 N (0 <x2 <x1). The third buffer layer BF3 includes, for example, Al _x3 Ga _1-x3 N (0 <x3 <x2). The fourth buffer layer BF4 includes, for example, Al _x4 Ga _1-x4 N (0 <x4 <x3). The fifth buffer layer BF5 includes, for example, Al _x5 Ga _1-x5 N (0 ≦ x5 <x4). The composition ratio x1 to the composition ratio x5 has a relationship of x1>x2>x3>x4> x5. In the nitride semiconductor wafer 110, for example, x1 = 1, x2 = 0.5, x3 = 0.3, x4 = 0.15, and x5 = 0.

  For example, the second buffer layer BF2 is in contact with the first buffer layer BF1. The third buffer layer BF3 is in contact with the second buffer layer BF2. The fourth buffer layer BF4 is in contact with the third buffer layer BF3. The fifth buffer layer BF5 is in contact with the fourth buffer layer BF4.

  The first to fifth buffer layers BF1 to BF5 have lattice lengths in the first direction (for example, the a-axis direction), that is, first to fifth lattice lengths W1 to W5, respectively.

  For example, the second buffer layer BF2 and the first buffer layer BF1 satisfy the relationship of 0.003 ≦ (W2−W1) /W1≦0.008. For example, the third buffer layer BF3 and the second buffer layer BF2 satisfy a relationship of 0.003 ≦ (W3−W2) /W2≦0.008. For example, the fourth buffer layer BF4 and the third buffer layer BF3 satisfy the relationship of 0.003 ≦ (W4−W3) /W3≦0.008. For example, the fifth buffer layer BF5 and the fourth buffer layer BF4 satisfy the relationship of 0.003 ≦ (W5−W4) /W4≦0.008.

The second buffer unit 52 includes, for example, Al _x0 Ga _x0 N (0 ≦ x0 <1). For the second buffer unit 52, for example, a non-doped GaN layer is used. The second buffer unit 52 is not limited to the GaN layer, and may be an AlGaN layer, for example. The second buffer unit 52 may be a stacked body including, for example, an AlGaN layer provided on the silicon-containing unit 55 and a GaN layer provided on the AlGaN layer. The second buffer unit 52 may be, for example, a stacked body in which a plurality of AlGaN layers having different Al composition ratios are stacked. Hereinafter, the case where the second buffer unit 52 is a GaN layer will be described. That is, in this example, the Al composition ratio x0 of the second buffer unit 52 is zero. The thickness of the second buffer unit 52 is, for example, not less than 250 nm and not more than 3000 nm.

FIG. 2 is a reciprocal space mapping diagram illustrating the characteristics of the nitride semiconductor wafer according to the first embodiment.
The horizontal axis of FIG. 2 is the reciprocal Qx of the lattice constant in the <11-20> direction, and the vertical axis is the reciprocal Qz of the lattice constant in the <0004> direction.
FIG. 2 shows a measurement result of reciprocal lattice space mapping of the nitride semiconductor wafer 110 (x0 = 0, x1 = 1, x2 = 0.5, x3 = 0.3, x4 = 0.15, and x5 = 0). Represents.
As shown in FIG. 2, in two adjacent buffer layers, the lattice mismatch ratio LMx in the a-axis direction is 0.46%, 0.66%, 0.34%, and 0.63%. Thus, in the nitride semiconductor wafer 110, the lattice mismatch rate LMx in the a-axis direction in the two adjacent buffer layers all satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%.

  Thus, in the nitride semiconductor wafer 110 according to the present embodiment, for example, the lattice mismatch ratio LMt between the AlN layer and the GaN layer is the lattice mismatch ratio LMx in the a-axis direction in the two adjacent buffer layers. The AlGaN layers are divided so as to satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%.

FIG. 3 is a reciprocal lattice space mapping diagram illustrating the characteristics of the reference example.
FIG. 3 shows the measurement results of reciprocal lattice mapping in the following reference example. In the reference example, a plurality of AlGaN layers are provided between the AlN layer and the GaN layer, and the Al composition ratio is equally divided in the plurality of AlGaN layers.

In the reference example illustrated in FIG. 3, x0 = 0, x1 = 1, x2 = 0.7, x3 = 0.5, x4 = 0.25, and x5 = 0.
As shown in FIG. 3, in the reference example, the lattice mismatch ratio LMx in the a-axis direction of two adjacent buffer layers is 0.12%, 0.55%, 0.47%, and 0.96%. is there. Thus, the lattice mismatch factor LMx in the a-axis direction between the first buffer layer BF1 and the second buffer layer BF2 is 0.12%, which is 0.3% or less. The lattice mismatch factor LMx in the a-axis direction between the fourth buffer layer BF4 and the fifth buffer layer BF5 is 0.96%, which is 0.8% or more.

  As in the reference example, in the configuration in which a plurality of AlGaN layers having an Al composition ratio equally divided are provided between the AlN layer and the GaN layer, the lattice mismatch rate in the a-axis direction in two adjacent buffer layers There are cases where LMx is excessively large and small.

  In the nitride semiconductor wafer 110 according to this embodiment, in the first buffer layer BF1 to the n-th buffer layer BFn, the lattice mismatch factor LMx in the a-axis direction of two adjacent buffer layers is prevented from becoming excessively large. Then, the lattice mismatch rate LMx is prevented from becoming excessively small. In this example, the Al composition ratio is set so that the lattice mismatch ratio LMx satisfies the relationship of 0.3% ≦ LMx ≦ 0.8%.

The thickness (length along the Z-axis direction) of the silicon-containing portion 55 is, for example, not less than 0.3 atomic layer and not more than 2.0 atomic layer, preferably not less than 0.5 atomic layer and not more than 1.4 atomic layer. It is. The silicon concentration in the silicon-containing portion 55 is, for example, 6.2 × 10 ¹⁹ atoms / cm ³ or more and 4.0 × 10 ²⁰ atoms / cm ³ or less, and preferably 1.0 × 10 ²⁰ atoms / cm ^3. The above is 2.8 × 10 ²⁰ atoms / cm ³ or less. For example, the silicon-containing portion 55 has an island shape. For example, the silicon-containing portion 55 is discontinuous on the upper surface 51 a of the first buffer portion 51. A part of the second buffer unit 52 is in contact with the first buffer unit 51 (n-th buffer unit BFn). The silicon-containing part 55 may include SiN, for example.

  The first buffer unit 51 may include a region having a high silicon concentration near the interface with the second buffer unit 52. A portion having a high silicon concentration in the first buffer portion 51 may be regarded as the silicon-containing portion 55, and a portion having a low silicon concentration may be regarded as the first buffer portion 51. The second buffer unit 52 may include a region having a high silicon concentration near the interface with the first buffer unit 51. A portion having a high silicon concentration in the second buffer portion 52 may be regarded as the silicon-containing portion 55, and a portion having a low silicon concentration may be regarded as the second buffer portion 52.

FIG. 4A to FIG. 4D are electron micrographs illustrating the configuration of part of the nitride semiconductor wafer according to the first embodiment.
4A to 4D, the silicon-containing layer 55 is formed on the first buffer portion 51, and then GaN that forms part of the second buffer portion 52 is formed on the silicon-containing layer 55. It is a SEM (Scanning Electron Microscope: scanning electron microscope) micrograph of the obtained sample.

In the sample of FIG. 4A, when the silicon-containing layer 55 is formed, SiH ₄ (monosilane) having a flow rate of 350 lm (liter / minute) is supplied at 1040 ° C. for 3 minutes. At the time of forming the second buffer portion 52, NH ₃ (ammonia) having a flow rate of 40 lm and TMGa (trimethylgallium) having a flow rate of 56.4 ccm (cc / minute) are supplied for 5 minutes at 1090 ° C. . It can be seen that the second buffer portion 52 is an island-like crystal having a height of 150 nm to 250 nm.
FIG. 4B is an enlarged photograph of the same sample as FIG. 4A taken at an enlarged magnification.

In the sample of FIG. 4C, when the silicon-containing layer 55 is formed, SiH ₄ having a flow rate of 350 lm is supplied at 1040 ° C. for 8 minutes. In forming the second buffer portion 52, NH ₃ having a flow rate of 40 lm and TMGa having a flow rate of 56.4 ccm are supplied at 1090 ° C. for 5 minutes. It can be seen that the second buffer portion 52 is an island-like crystal having a height of 200 nm to 600 nm.
That is, the thickness of the silicon-containing portion 55 of the sample of FIG. 4C is thicker than the thickness of the silicon-containing portion 55 of the sample of FIG.
FIG. 4D is an enlarged photograph of the same sample as that in FIG.

  4A to 4D show the silicon-containing portion 55 and the GaN layer of the second buffer portion 52 in the middle of growth provided on the silicon-containing portion 55 in an island shape. However, the thickness of the silicon-containing portion 55 is sufficiently small with respect to the resolution of the SEM, and it is difficult to observe the silicon-containing portion 55 with the SEM. For this reason, it can also be said that the portion shown as the background is the first buffer unit 51. In addition, when the silicon-containing portion 55 has an island shape, the portions shown as the base are both the first buffer portion 51 and the silicon-containing portion 55.

  As shown in FIGS. 4A to 4D, a GaN layer (nitride) formed on the first buffer unit 51 by providing the silicon-containing unit 55 on the first buffer unit 51. The degree of growth of the semiconductor layer changes. That is, the silicon-containing portion 55 affects the film quality of the nitride semiconductor layer (upper layer portion 15) formed thereon.

  The inventor of the present application suppresses cracks in the configuration of the nitride semiconductor wafer 110 according to the present embodiment by performing various experiments in which the growth conditions such as the first buffer unit 51 and the silicon-containing unit 55 are changed. It has been found that the dislocation density can be reduced.

  The presence or absence of the silicon-containing part 55 can be determined by, for example, SIMS (Secondary Ion Mass Spectrometry). For example, when silicon is detected in a region between the first buffer unit 51 and the second buffer unit 52 as a result of analysis using SIMS, it is determined that the silicon-containing unit 55 is provided. be able to.

Hereinafter, the experimental results regarding the nitride semiconductor wafer, which the inventor of the present application independently performed, will be described.
FIG. 5 is a table illustrating characteristics of the nitride semiconductor wafer according to the first embodiment.
FIG. 5 shows the growth conditions of the first buffer layer BF1 to the fifth buffer layer BF5 of the three samples of the first sample SP01 to the third sample SP03. In the experiment, the first sample SP01 to the third sample SP03 are produced based on the growth conditions shown in FIG. 5, and the characteristics of the first sample SP01 to the third sample SP03 are evaluated.

FIG. 5 shows the following experimental conditions.
The thickness t0 (μm) of the silicon substrate 40 and the thicknesses t1 (nm), t2 (nm), t3 (nm), t4 (nm), and t5 (nm) of the first to fifth buffer layers BF1 to BF5 ),
Each growth temperature GT1 (° C.), growth temperature GT2 (° C.), growth temperature GT3 (° C.), growth temperature GT4 (° C.) and growth temperature when forming the first to fifth buffer layers BF1 to BF5 GT5 (° C),
-Flow rate of each trimethylaluminum (TMA) gas TMA1 (ccm: cc / minute), TMA2 (ccm), TMA3 (ccm), TMA4 (ccm) when forming the first to fifth buffer layers BF1 to BF5 ) And TMA5 (ccm),
- when forming the first to fifth buffer layer BF1～BF5, respectively ammonia (NH ₃₎ gas flow rate N1 (lm: liter / minute) , flow rate N2 (lm), the flow rate N3 (lm), flow rate N4 (lm) and flow rate N5 (lm),
Growth rate GR1 (nm / minute), growth rate GR2 (nm / minute), growth rate GR3 (nm / minute), growth rate GR4 (nm / nm) when forming the first to fifth buffer layers BF1 to BF5 minute) and growth rate GR5 (nm / minute),
A composition ratio x2, x3, and x4 of Al in each of the second to fifth buffer layers BF2 to BF5.
In this experiment, the Al composition ratio x1 in the first buffer layer BF1 is 1, and the Al composition ratio x5 in the fifth buffer layer BF5 is 0.
The growth rate GR1 to the growth rate GR5 can be obtained by dividing the film thickness by the growth time.

  When the first buffer layer BF1 is formed on the silicon substrate 40, the silicon substrate 40 (nitride semiconductor wafer) warps due to the lattice constant difference in the first direction between the silicon and the first buffer layer BF1. Thus, when the (i + 1) th buffer layer BF (i + 1) is formed on the i-th buffer layer BFi, the lattice length in the first direction of the i-th buffer layer BFi and the (i + 1) th buffer layer BF (i + 1) Due to the difference, the silicon substrate 40 is warped. In the first sample SP01 to the third sample SP03, the change (warpage) of the curvature of the silicon substrate 40 when the first buffer layer BF1 to the fifth buffer layer BF5 are formed is measured by an optical monitor.

FIG. 6 is a graph illustrating characteristics of the nitride semiconductor wafer according to the first embodiment.
FIG. 6 shows a change in curvature of the silicon substrate 40 when the first buffer layer BF1 to the fifth buffer layer BF5 are sequentially formed in the first sample SP01 to the third sample SP03.
The vertical axis in FIG. 6 is the curvature CF (km ⁻¹ ) of the nitride semiconductor wafer, and the horizontal axis is the thickness T (nm) of the first buffer unit 51. The thickness T of 0 nm corresponds to the interface between the silicon substrate 40 and the first buffer layer BF1.

The thickness of the silicon substrate 40 of the third sample SP03 is different from the thickness of the silicon substrate 40 of the first sample SP01 and the thickness of the silicon substrate 40 of the second sample SP02. For example, when a plurality of samples having the same first buffer unit 51 are formed on a plurality of silicon substrates 40 having different thicknesses, the curvature of the silicon substrate 40 correlates with the thickness of the silicon substrate 40. This is because when the same first buffer part 51 is formed, the stress applied to the first buffer part 51 is substantially the same even if the thickness of the silicon substrate 40 is changed. The correlation between the curvature of the silicon substrate 40 and the thickness of the silicon substrate 40 is expressed by, for example, equation (2).


In the equation (2), the curvature K of the silicon substrate 40, the curvature radius R of the silicon substrate 40, the elastic modulus M _s of the silicon substrate 40, and the nitride semiconductor layers (for example, the first buffer layer BF1 to the fifth buffer layer). The thin film stress σ _{f of} BF5), the thin film thickness h _f of the nitride semiconductor layer, and the thickness h _s of the silicon substrate 40 are shown.

  In FIG. 6, the curvature of the silicon substrate 40 of the first sample SP01 and the thickness (525 μm) of the silicon substrate 40 of the second sample SP02 are used to change the curvature of the third sample SP03 using the equation (2). The conversion value converted into is used.

  When the curvature CF is negative, the position of the center of the silicon substrate 40 in the Z-axis direction is higher than the position of the end portion of the silicon substrate 40 in the Z-axis direction. When the curvature CF is negative, the silicon substrate 40 corresponds to a state in which the silicon substrate 40 warps upward. Conversely, when the curvature CF is positive, this corresponds to a state in which the silicon substrate 40 is warped in a downward convex shape.

As shown in FIG. 6, the curvature of the silicon substrate 40 is changed by forming the first buffer layer BF1 to the fifth buffer layer BF5. That is, the silicon substrate 40 is warped. For example, the thickness t1 of the first buffer layer BF1 of the third sample SP03 is 120 nm (see FIG. 5). Therefore, in FIG. 6, the amount of change in curvature CF in the range of thickness T from 0 nm to 120 nm is the amount of change CF1 in curvature of the silicon substrate 40 associated with the formation of the first buffer layer BF1. The amount of change in the curvature in the range of the thickness T from 0 nm to 120 nm includes the curvature of the silicon substrate 40 before forming the first buffer layer BF1, and the curvature of the silicon substrate 40 after forming the first buffer layer BF1. And the difference. For example, in the third sample SP03, the change amount CF1 of the curvature of the silicon substrate 40 accompanying the film formation of the first buffer layer BF1 is about 14.4 km ⁻¹ (converted value).

The thickness t2 of the second buffer layer BF2 of the third sample SP03 is 100 nm (see FIG. 5). The amount of change in curvature CF in the range of 120 nm to 220 nm in thickness T is the amount of change CF2 in curvature of the silicon substrate 40 accompanying the formation of the second buffer layer BF2. In the third sample SP03, the change amount CF2 of the curvature of the silicon substrate 40 accompanying the film formation of the second buffer layer BF2 is about −18.1 km ⁻¹ (converted value).

The thickness t3 of the third buffer layer BF3 of the third sample SP03 is 215 nm (see FIG. 5). The amount of change in curvature CF in the thickness T range of 220 nm to 435 nm is the amount of change CF3 in curvature of the silicon substrate 40 accompanying the formation of the third buffer layer BF3. In the third sample SP03, the amount of change CF3 in the curvature of the silicon substrate 40 accompanying the formation of the third buffer layer BF3 is about −38.6 km ⁻¹ (converted value).

The thickness t4 of the fourth buffer layer BF4 of the third sample SP03 is 250 nm (see FIG. 5). The amount of change in curvature CF in the thickness T range of 435 nm to 685 nm is the amount of change CF4 in curvature of the silicon substrate 40 accompanying the formation of the fourth buffer layer BF4. In the third sample SP03, the amount of change CF4 in the curvature of the silicon substrate 40 accompanying the formation of the fourth buffer layer BF4 is about −29.8 km ⁻¹ (converted value).

The thickness t5 of the fifth buffer layer BF5 of the third sample SP03 is 400 nm (see FIG. 5). The amount of change in curvature CF in the thickness T range of 685 nm to 1085 nm is the amount of change CF5 in curvature of the silicon substrate 40 accompanying the formation of the fifth buffer layer BF5. In the third sample SP03, the amount of change CF5 in the curvature of the silicon substrate 40 accompanying the formation of the fifth buffer layer BF5 is about −44.0 km ⁻¹ (converted value).

  Furthermore, in this evaluation, in order to compare the warpage of the silicon substrate 40 due to the formation of each buffer layer, the second buffer layer BF2 to the fifth buffer layer BF5 are made to a thickness of 100 nm based on the above measurement results. The amount of change in the curvature of the silicon substrate 40 when the film is formed is determined as follows.

As described above, since the thickness t2 of the second buffer layer BF2 of the third sample SP03 is 100 nm, the amount of change in the curvature of the silicon substrate 40 due to the second buffer layer BF2 being deposited to a thickness of 100 nm. CF2a is the same as the curvature variation CF2. In the third sample SP03, the curvature variation CF2a is approximately −18.1 km ⁻¹ (converted value).

In the third sample SP03, the amount of change in the curvature CF in the range of the thickness T from 220 nm to 320 nm is the amount of change CF3a in the curvature of the silicon substrate 40 as the third buffer layer BF3 is formed to a thickness of 100 nm. is there. In the third sample SP03, the curvature variation CF3a is about −25.8 km ⁻¹ (converted value).

In the third sample SP03, the amount of change in the curvature CF in the range of the thickness T from 435 nm to 535 nm is the amount of change CF4a in the curvature of the silicon substrate 40 resulting from the formation of the fourth buffer layer BF4 to a thickness of 100 nm. is there. In the third sample SP03, the curvature variation CF4a is about −13.3 km ⁻¹ (converted value).

In the third sample SP03, the change amount of the curvature CF in the thickness T range of 685 nm to 785 nm is the change amount CF5a of the curvature of the silicon substrate 40 when the fifth buffer layer BF5 is formed to a thickness of 100 nm. is there. In the third sample SP03, the curvature change amount CF5a is about −22.6 km ⁻¹ (converted value).

In the measurement apparatus used in the experiment, there is a limit to the measurement of the curvature CF, and at the measurement limit, the sum of the total curvature change CFt on the minus side and the plus curvature change CF1 on the plus side is calculated. The maximum is about -85 km- ¹ . In the first sample SP01, the measurement limit of the measuring apparatus is reached in the range of the thickness T after 700 nm. For this reason, the change amounts CF5 and CF5a of the curvature of the first sample SP01 cannot be measured.

  As shown in FIG. 6, when the first buffer layer BF1 is formed on the silicon substrate 40, the curvature of the silicon substrate 40 changes to the plus side. On the other hand, when the second buffer layer BF2 is formed on the first buffer layer BF1, when the third buffer layer BF3 is formed on the second buffer layer BF2, the fourth buffer layer is formed on the third buffer layer BF3. When the buffer layer BF4 is formed and when the fifth buffer layer BF5 is formed on the fourth buffer layer BF4, the curvature of the silicon substrate 40 changes to the negative side.

  When an AlN layer is formed on a silicon layer, a tensile stress is applied to the AlN layer due to a lattice constant difference in the first direction between silicon and AlN. When an AlGaN layer is formed on an AlN layer, compressive stress is applied to the AlGaN layer due to the difference in the lattice length in the a-axis direction between AlN and AlGaN. Furthermore, when a second AlGaN layer having an Al composition ratio lower than that of the first AlGaN layer is formed on the first AlGaN layer, the second AlGaN layer has a difference in lattice length in the a-axis direction between two AlGaN having different Al composition ratios. A compressive stress is applied. When a GaN layer is formed on the AlGaN layer, compressive stress is applied to the GaN layer due to the difference in the lattice length in the a-axis direction between AlGaN and GaN. The difference in the direction of change in curvature between the case where the first buffer layer BF1 is formed and the case where the second buffer layer BF2 to the fifth buffer layer BF5 are formed is caused by the difference in applied stress.

  When the curvature is negative, the silicon substrate 40 warps upward. That is, in the first sample SP01 to the third sample SP03, the silicon substrate 40 is warped upward by forming the second buffer layer BF2 to the fifth buffer layer BF5.

In the third sample SP03, the total curvature variation CFt of CF2, CF3, CF4, and CF5 is about −130.4 km ⁻¹ (converted value). The total curvature change amount CFt is the total change in curvature of the silicon substrate 40 due to compressive stress. In the third sample SP03, the total curvature change amount CFa of CF2a, CF3a, CF4a, and CF5a is about −79.8 km ⁻¹ (converted value). FIG. 6 illustrates t1 to t5, CF1 to CF5, CF2a to CF5a, and CFt of the third sample SP03.

FIG. 7 is a table illustrating characteristics of the nitride semiconductor wafer according to the first embodiment.
FIG. 7 shows the measurement results of the characteristics of the first sample SP01 to the third sample SP03 and the change in curvature of the silicon substrate 40.

  FIG. 7 shows the measurement results of the lattice mismatch rate and the amount of change in curvature. That is, FIG. 7 shows the lattice mismatch ratio LM2 (%) in the a-axis direction between the first buffer layer BF1 and the second buffer layer BF2, and the a-axis direction between the second buffer layer BF2 and the third buffer layer BF3. Lattice mismatch rate LM3 (%), lattice mismatch rate LM4 (%) in the a-axis direction between the third buffer layer BF3 and the fourth buffer layer BF4, a axis between the fourth buffer layer BF4 and the fifth buffer layer BF5 The lattice mismatch factor LM5 (%) in the direction is shown. FIG. 7 shows the lattice mismatch rate LMt (%) in the a-axis direction between the first buffer layer BF1 and the fifth buffer layer BF5. The lattice mismatch rates LM2 to LM5 and LMt are values obtained by reciprocal lattice space mapping.

In addition, FIG.
The relaxation rate SR2 in the a-axis direction of the second buffer layer BF2, the relaxation rate SR3 in the a-axis direction of the third buffer layer BF3, the relaxation rate SR4 in the a-axis direction of the fourth buffer layer BF4, and a of the fifth buffer layer BF5 Axial relaxation rate SR5,
The amount of change in curvature CF2a (km ⁻¹ ), CF3a (km ⁻¹ ), CF4a (km ⁻¹ ) of the silicon substrate 40 when the second to fifth buffer layers BF2 to BF5 are each formed to a thickness of 100 nm. ) And CF5a (km ⁻¹ ),
The amount of change in curvature CF2 (km ⁻¹ ), CF3 (km ⁻¹ ), CF4 (km ⁻¹ ), and CF5 (km ⁻¹ ) of the silicon substrate 40 as the second to fifth buffer layers BF2 to BF5 are formed. ),
A total curvature change amount CFa (km ⁻¹ ) of CF2a, CF3a, CF4a, and CF5a, and
A total curvature change amount CFt (km ⁻¹ ) of CF 2, CF 3, CF 4 and CF 5;
It is shown.

In the first sample SP01, the curvature variations CF5 and CF5a reach the measurement limit. Therefore, in FIG. 7, CF5, CF5a, CFa, and CFt of the first sample SP01 are blank. In the third sample SP03, the sum of the negative-side total curvature change CFt and the positive-side curvature change CF1 is −39.8 km ^−1, which is within the measurement range. The third sample SP03 is different from the first sample SP01 and the second sample SP02 in that the silicon substrate 40 has a thickness of 950 μm. Therefore, for the negative-side total curvature change CFt and the positive-side curvature change CF1 in the third sample SP03, the conversion value converted into the curvature of the substrate thickness of 525 μm using the equation (2) is parenthesized. It is shown as a number with a mark.

In the second sample SP02, the sum of the minus side total curvature variation CFt and the plus side curvature variation CF1 is −80.8 km ^−1, which is within the measurement range.

The relaxation rate SRi in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) provided on the i-th buffer layer BFi is obtained by, for example, Equation (3).


In the equation (3), the lattice length a1 in the a-axis direction of the i-th buffer layer BFi, the lattice length a2 in the a-axis direction of the (i + 1) th buffer layer BF (i + 1), and the (i + 1) th buffer layer BF ( i + 1) fully relaxed a-axis direction of the grating length a2 _R of is shown. When the lattice length a2 in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) matches the lattice length a1 in the a-axis direction of the i-th buffer layer BFi (when completely distorted), the (i + 1) th The relaxation rate SRi of the buffer layer BF (i + 1) in the a-axis direction is zero. Further, the (i + 1) the a-axis direction of the grating length a2 of the buffer layer BF (i + 1) is the (i + 1) -th buffer layer BF (i + 1) completely if it matches the lattice length a2 _R of relaxed a-axis direction (full of The relaxation rate SRi in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) is 1. The lattice mismatch rate in the a-axis direction between the lattice length a2 in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) and the lattice length a1 in the a-axis direction of the i-th buffer layer BFi is small, and the (i + 1) th buffer The thinner the layer BF (i + 1) is, the closer the relaxation rate SRi in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) approaches zero.

As shown in FIGS. 6 and 7, the total curvature change amount CFt is −97.2 km ⁻¹ for the second sample SP02 and −130.4 km ⁻¹ (converted value) for the third sample SP03. ). The curvature variation CFt of the third sample SP03 is larger than the curvature variation CFt of the second sample SP02. Further, as shown in FIG. 6, the curvature change amount CFt of the first sample SP01 is larger than the curvature change amount CFt of the second sample SP02.

  Therefore, the compressive stress applied to the first buffer unit 51 of the first sample SP01 is larger than the compressive stress applied to the first buffer unit 51 of the second sample SP02. The compressive stress applied to the first buffer unit 51 of the third sample SP03 is larger than the compressive stress applied to the first buffer unit 51 of the second sample SP02. In the first sample SP01 and the third sample SP03, compared with the second sample SP02, a larger compressive stress can be applied to the first buffer unit 51, and cracks can be further suppressed.

The first to third samples SP01 to SP03 are further analyzed.
FIG. 8 is a graph illustrating characteristics of the nitride semiconductor wafer according to the first embodiment.
FIG. 8 is a graph plotting the curvature variation CF2a, CF3a, CF4a, and CF5a of the first sample SP01 to the third sample SP03. The vertical axis in FIG. 8 is the curvature variation CF (km ⁻¹ ) of the silicon substrate 40, and the horizontal axis is the lattice mismatch ratio LMx (%) in the a-axis direction of two adjacent buffer layers. FIG. 8 shows an example of the relationship between the lattice mismatch factor LMx and the curvature variation CF when a nitride semiconductor layer having a thickness of 100 nm is formed.

  As described above, the CF 5a of the first sample SP01 has reached the measurement limit of the measurement apparatus. For this reason, the CF5a of the first sample SP01 cannot be plotted in FIG. In addition, for CF2a, CF3a, CF4a, and CF5a of the third sample SP03, the converted value obtained by the equation (2) is used.

  As shown in FIG. 8, in the region where LMx ≦ 0.8%, the absolute value of the curvature variation CF increases as the lattice mismatch factor LMx increases. On the other hand, in the region of 0.8% <LMx, the absolute value of the curvature variation CF decreases as the lattice mismatch factor LMx increases. In the region of 0.8% <LMx, the absolute value of the curvature variation CF decreases as the lattice mismatch factor LMx increases. The lattice mismatch factor LMx becomes too large and lattice relaxation occurs. It is thought that this is because. By setting LMx ≦ 0.8%, lattice relaxation can be suppressed. In addition, generation of dislocations accompanying lattice relaxation can be suppressed.

  As shown in FIG. 8, the absolute value of the curvature variation CF of the nitride semiconductor wafer in the region where LMx <0.3% is the nitride semiconductor wafer in the region where 0.3% ≦ LMx ≦ 0.8%. Is smaller than the absolute value of the curvature variation CF. In the nitride semiconductor wafer, when compressive stress is applied to the first buffer portion 51, the nitride semiconductor wafer warps upward. The magnitude of the curvature of the nitride semiconductor wafer that warps upward is in accordance with the magnitude of the compressive stress applied to the first buffer unit 51. Therefore, the compressive stress applied to the first buffer unit 51 when LMx <0.3% is applied to the first buffer unit 51 when 0.3% ≦ LMx ≦ 0.8%. Less than compressive stress.

  Further, by setting 0.3% ≦ LMx, the number of AlGaN layers between the AlN layer and the GaN layer can be suppressed. For example, the number of AlGaN layers can be suppressed to 7 or less. When the number of AlGaN layers increases, for example, the setting of growth conditions such as the flow rate of TMA gas and the flow rate of TMG gas becomes complicated, and it becomes difficult to manufacture a nitride semiconductor wafer. Therefore, the manufacture of the nitride semiconductor wafer can be facilitated by setting 0.3% ≦ LMx.

  Furthermore, in the range of LMx <0.3%, in order to obtain the amount of change in the curvature of the nitride semiconductor wafer equivalent to the range of 0.3% ≦ LMx ≦ 0.8%, the AlGaN layer becomes thick. A thick AlGaN layer tends to lose flatness. If the flatness of the AlGaN layer is lost, the compressive stress of the nitride semiconductor layer grown on the AlGaN layer may be reduced. Therefore, by setting 0.3% ≦ LMx, the nitride semiconductor wafer can be thinned and cracks can be suppressed.

  In the embodiment, the first buffer layer BF1 to the fifth buffer layer BF1 to the fifth buffer so that the lattice mismatch rate LMx in the a-axis direction in two adjacent buffer layers all satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%. By forming the buffer layer BF5, a larger compressive stress can be applied to the first buffer portion 51 than when the relationship of 0.3% ≦ LMx ≦ 0.8% is not satisfied.

  In the first sample SP01 of this experiment, the relationship of 0.3% ≦ LMx ≦ 0.8% is satisfied in the lattice mismatch rate LM2 to the lattice mismatch rate LM5 (see FIG. 7).

  On the other hand, in the second sample SP02, the lattice mismatch rate LM2 and the lattice mismatch rate LM5 do not satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%.

  In the third sample SP03, the lattice mismatch rate LM2 to the lattice mismatch rate LM5 satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%.

  As already described, the amount of change in the curvature of the first sample SP01 is larger than the amount of change in the curvature of the second sample SP02, and the compressive stress applied to the first buffer unit 51 of the first sample SP01 is the second amount. It is larger than the compressive stress applied to the first buffer part 51 of the sample SP02. The amount of change in curvature of the third sample SP03 is larger than the amount of change in curvature of the second sample SP02, and the compressive stress applied to the first buffer unit 51 of the third sample SP03 is the first buffer of the second sample SP02. It is larger than the compressive stress applied to the part 51. As described above, the first buffer layer BF1 to the fifth buffer so that the lattice mismatch rate LMx in the a-axis direction in two adjacent buffer layers all satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%. By forming the layer BF5, a larger compressive stress can be applied to the first buffer unit 51 than when the relationship of 0.3% ≦ LMx ≦ 0.8% is not satisfied.

  As expressed by equation (2), the curvature of the silicon substrate 40 correlates with the thickness of the silicon substrate 40. Therefore, even when the thickness of the silicon substrate 40 is changed, the relationship of 0.3% ≦ LMx ≦ 0.8% is satisfied, as in the case where the thickness of the silicon substrate 40 shown in FIG. 8 is 525 μm. In addition, by forming the first buffer layer BF1 to the fifth buffer layer BF5, a larger compressive stress is applied to the first buffer unit 51 than when the relationship of 0.3% ≦ LMx ≦ 0.8% is not satisfied. Can be applied.

  In the nitride semiconductor wafer 110, the thermal expansion coefficients of the functional layer 10 s including the nitride semiconductor, the second buffer unit 52, and the first buffer unit 51 are different from the thermal expansion coefficient of the silicon substrate 40. For this reason, in the nitride semiconductor wafer 110, tensile stress is applied to the functional layer 10s, the second buffer unit 52, and the first buffer unit 51 when the temperature of the functional layer 10s is returned to room temperature. In a conventional nitride semiconductor wafer, the nitride semiconductor wafer may be warped downward due to a tensile stress applied when the temperature is lowered, and a crack may occur in the functional layer 10s.

  In the nitride semiconductor wafer 110, the tensile stress applied to the functional layer 10 s when returning to room temperature can be balanced by the compressive stress of the first buffer unit 51. For example, warpage of nitride semiconductor wafer 110 when the temperature is returned to room temperature can be suppressed. Thereby, in the nitride semiconductor wafer 110, it can suppress that a crack generate | occur | produces in the functional layer 10s.

There is a semiconductor element in which a buffer layer containing Al _m Ga _1-m N (0 ≦ m ≦ 1) is provided between a substrate and a functional layer, and the Al composition ratio of the buffer layer decreases as the distance from the substrate to the functional layer increases. . In the semiconductor element of this reference example, for example, the Al composition ratio is decreased to 1.0, 0.8, 0.6, 0.4, 0.2, and 0. That is, the buffer layer of the semiconductor element of the reference example includes five buffer layers in which the Al composition ratio is equally divided. The lattice mismatch factor LMc in the a-axis direction obtained from the physical property values of AlN and GaN is 2.5%. The lattice mismatch factor LMt in the a-axis direction obtained from experimental values of AlN and GaN is, for example, 1.9% to 2.5%. When this is equally divided by five buffer layers with the Al composition ratio equally divided, the lattice mismatch rate LMx in the a-axis direction in the two adjacent buffer layers is 0.38% or more and 0.50% or less. .

However, when the lattice mismatch factor LMt of AlN and GaN in the a-axis direction is divided by five buffer layers obtained by equally dividing the Al composition ratio, the lattice mismatch factor in the a-axis direction in two adjacent buffer layers LMx does not necessarily fall within the range of 0.3% ≦ LMx ≦ 0.8%. For example, when Al _0.85 Ga _0.15 N having a _thickness of 100 nm is formed on AlN, Al _0.85 Ga _0.15 N is strain-grown, so that AlN and Al _0.85 Ga _0.15 N are grown. The lattice mismatch rate LMx is 0.0%, which is smaller than 0.3%.

When dividing the Al composition ratio equally is substantially the same as dividing the lattice mismatch ratio LMt between AlN and GaN in the a-axis direction, for example, Al _m Ga _1-m N Is completely relaxed.

When the buffer layer is formed by epitaxial growth or the like, the buffer layer is affected by the crystallinity of the underlying layer and the lattice length. Therefore, in order to obtain a fully relaxed _{Al m Ga 1-m} N varies depending on the composition ratio of Al, it is necessary to grow more very thick _{Al m Ga 1-m N 1000nm} .

However, the relaxation rate SRi in the a-axis direction of completely relaxed Al _m Ga _1-m N is 1, and since no compressive stress is applied, the effect of suppressing cracks is not exhibited. Therefore, the relaxation rate SRi in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) provided on the i-th buffer layer BFi needs to be smaller than 1. The relaxation rate SRi in the a-axis direction of the (i + 1) th buffer layer BF (i + 1) provided on the i-th buffer layer BFi is preferably, for example, 0.65 or less.

_Further, when the film thickness of Al _{m Ga 1-m} N and thickness on the order more than 50nm or less 1nm _is, Al _{m Ga 1-m} N is likely to grow strain, it is uniformly dividing the Al composition ratio, It does not correspond to equally dividing the lattice mismatch rate LMt between AlN and GaN in the a-axis direction.

  In the nitride semiconductor wafer 110 according to the present embodiment, for example, the lattice mismatch rate LMt of AlN and GaN is all 0.3% ≦ the lattice mismatch rate LMx in the a-axis direction in two adjacent buffer layers. Dividing with AlGaN so as to satisfy the relationship of LMx ≦ 0.8%. Thereby, compared with the case where the relationship of 0.3% ≦ LMx ≦ 0.8% is not satisfied, a large compressive stress can be applied to the first buffer unit 51.

FIG. 9 is a graph illustrating characteristics of the nitride semiconductor wafer according to the first embodiment.
The vertical axis in FIG. 9 is the edge dislocation density EDD (cm ⁻² ), and the horizontal axis is the growth time T _Si (minute) of the silicon-containing portion 55. FIG. 9 shows the results of an experiment in which a plurality of samples in which the growth time T _Si of the silicon-containing portion 55 was changed in the configuration of the nitride semiconductor wafer 110 and the edge dislocation density EDD of these samples were measured. Represent. In this experiment, SiH ₄ is used as a silicon source gas. In this experiment, the growth temperature of the silicon-containing portion 55 is 1040 ° C., and the flow rate of SiH ₄ is 350 lm. The growth temperature of the buffer unit 52 is 1090 ° C. Note that the edge dislocation density EDD (cm ⁻² ) can be obtained from, for example, the half width of the rocking curve of the X-ray diffraction method.

As shown in FIG. 9, the edge dislocation density EDD is 7.52 × 10 ⁹ (cm ⁻² ) in the sample having the growth time T _Si of 0 minute. A sample having a growth time T _Si of 0 minutes is a sample in which the silicon-containing portion 55 is not provided. In a sample having a growth time T _Si of 3 minutes, the edge dislocation density EDD is 1.12 × 10 ⁹ (cm ⁻² ). In the sample having a growth time T _Si of 4 minutes, the edge dislocation density EDD is 7.71 × 10 ⁸ (cm ⁻² ). In the sample having a growth time T _Si of 8 minutes, the edge dislocation density EDD is 6.01 × 10 ⁸ (cm ⁻² ). Thus, by providing the silicon-containing portion 55, the edge dislocation density EDD can be reduced.

The thickness of the silicon-containing portion 55 is not less than 0.3 atom layer and not more than 2.0 atom layer, and preferably not less than 0.5 atom layer and not more than 1.4 atom layer. If it is thinner than 0.3 atomic layer, the effect of reducing the edge dislocation density EDD is reduced, and if it is thicker than 2.0 atomic layer, crystal growth becomes difficult. The silicon concentration in the silicon-containing portion 55 is 6.2 × 10 ¹⁹ atoms / cm ³ or more and 4.0 × 10 ²⁰ atoms / cm ³ or less, preferably 1.0 × 10 ²⁰ atoms / cm ³ or more and 2 0.8 × 10 ²⁰ atoms / cm ³ or less. Thereby, a dislocation density can be reduced more appropriately.

FIG. 10 is a graph illustrating characteristics of the nitride semiconductor wafer according to the first embodiment.
The vertical axis in FIG. 10 is the edge dislocation density EDD (cm ⁻² ), and the horizontal axis is the NH ₃ gas flow rate FR _N (lm) for 5 minutes from the start of the growth of the second buffer unit 52. 10, in the configuration of the nitride semiconductor wafer 110, to produce a plurality of samples forming the second buffer unit 52 by changing the flow rate FR _N of NH ₃ gas, the edge dislocation density EDD of the plurality of samples Represents the result of the measured experiment. In this experiment, the growth time T _Si of the silicon-containing portion 55 is 3 minutes, and the growth temperature is 1040 ° C. Raw material gases of the silicon is SiH _4, the flow rate of SiH ₄ is 350Lm. The growth temperature of the second buffer unit 52 is 1090 ° C., and the flow rate of TMGa is 56.4 ccm. In the growth of the second buffer unit 52, the flow rate of NH ₃ gas is set to 40 lm after 5 minutes from the start of growth.

As shown in FIG. 10, in the sample flow rate FR _N is 1.0Lm, edge dislocation density EDD is a ^{8.05 × 10 8 (cm -2)} . In the sample of the flow rate FR _N is 2.5 lm, edge dislocation density EDD is a ^{4.44 × 10 8 (cm -2)} . In the sample of the flow rate FR _N is 10 lm, edge dislocation density EDD is a ^{5.11 × 10 8 (cm -2)} . In the sample of the flow rate FR _N is 40 lm, edge dislocation density EDD is a 1.12 × ¹⁰ 9 ^{cm -2.}

Thus, in the formation of the second buffer unit 52, the flow rate FR _N of 5 minutes of the NH ₃ gas from the growth start below 10lm than 2.5 lm. That is, the V / III ratio, which is the ratio of the group III element (for example, gallium) and the group V element (for example, nitrogen), is set to 490 or more and 1950 or less. Thereby, a dislocation density can be reduced more appropriately.

On the other hand, in the first buffer layer BF1 to the nth buffer layer BFn, the lattice mismatch factor LMx in the a-axis direction of two adjacent buffer layers satisfies the relationship of 0.3% ≦ LMx ≦ 0.8%. There is a reference example in which the silicon-containing part 55 is provided on the first buffer part 51 that is not present. More specifically, the reference example is an AlN layer (first buffer layer BF1), an Al _0.7 Ga _0.3 N layer provided on the AlN layer, and an Al _0.7 Ga _0.3 N. Al _0.5 Ga _0.5 N layer provided on the layer and Al _0.25 Ga _0.75 N layer (nth buffer layer provided on the Al _0.5 Ga _0.5 N layer) BFn), a SiN layer (silicon-containing portion 55) provided on the Al _0.25 Ga _0.75 N layer, and a GaN layer (second buffer portion 52) provided on the SiN layer, Including. In the structure of this reference example, a portion that does not satisfy the relationship of 0.3% ≦ LMx ≦ 0.8% occurs in the lattice mismatch ratio LMx in the a-axis direction between two adjacent buffer layers. In the reference example, the SiN layer is formed by setting the silicon source gas to SiH ₄ , the flow rate of SiH ₄ to 350 lm, and the growth time T _si to 6 minutes. In the reference example, the GaN layer is formed with the NH ₃ gas flow rate of 20 lm and the V / III ratio of 3900. In this reference example, the edge dislocation density EDD is 5.78 × 10 ⁹ (cm ⁻² ). Thus, even if the silicon-containing portion 55 is provided on the first buffer portion 51 that does not satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%, the effect of reducing the dislocation density is small. Thus, when the buffer layer is not appropriate, it is difficult to reduce the dislocation density even if the silicon-containing portion 55 is provided.

  The inventor of the present application has evaluated the dislocation density while conducting an experiment on the suppression of cracks, and found a configuration capable of reducing the dislocation density while suppressing cracks. That is, in two adjacent buffer layers, the first buffer layer BF1 to the n-th buffer layer BFn satisfying the relationship that the lattice mismatch rate LMx in the a-axis direction all satisfy 0.3% ≦ LMx ≦ 0.8% are provided. It was found that cracks can be suppressed. Then, the inventor of the present application has found that the dislocation density can be reduced by providing the silicon-containing portion 55 between the first buffer portion 51 and the second buffer portion 52 in the course of the experiment. The silicon-containing portion 55 formed on the first buffer portion 51 affects the film quality of the nitride semiconductor layer (upper layer portion 15) formed on the silicon-containing portion 55 (FIG. 4A to FIG. 4). 4 (d)). It is considered that the dislocation density is reduced because the film quality of the upper layer portion 15 (second buffer portion 52 in this example) is improved by providing the silicon-containing portion 55.

  Thus, in the nitride semiconductor wafer 110 according to this embodiment, cracks can be suppressed and the dislocation density can be reduced. This is an effect derived for the first time by the inventors' experiment.

  In the embodiment, the thickness t1 is, for example, 120 nm (80 to 180 nm), the thickness t2 is, for example, 100 nm (50 to 150 nm), and the thickness t3 is, for example, 200 nm (150 to 250 nm). The thickness t4 is, for example, 250 nm (200 nm or more and 300 nm or less), and the thickness t5 is, for example, 330 nm (300 nm or more and 350 nm or less).

  Alternatively, the thickness t1 is, for example, 240 nm (200 to 300 nm), the thickness t2 is, for example, 150 nm (100 to 200 nm), and the thickness t3 is, for example, 300 nm (250 to 350 nm). The thickness t4 is, for example, 400 nm (350 nm to 450 nm), and the thickness t5 is, for example, 500 nm (450 nm to 550 nm).

  Alternatively, the thickness t1 is, for example, 360 nm (300 to 400 nm), the thickness t2 is, for example, 200 nm (150 to 250 nm), and the thickness t3 is, for example, 400 nm (350 to 450 nm). The thickness t4 is, for example, 500 nm (450 nm or more and 550 nm or less), and the thickness t5 is, for example, 600 nm (550 nm or more and 650 nm or less).

  As described above, the thickness t2, the thickness t3, the thickness t4, and the thickness t5 may be changed corresponding to the thickness t1. The thickness t1 to the thickness t5 are not limited to the above. For example, the thickness t2, the thickness t3, the thickness t4, and the thickness t5 can be arbitrarily set, for example, within a range in which the curvature CF of the nitride semiconductor wafer 110 changes as the buffer layer grows. it can.

FIG. 11 is a schematic cross-sectional view illustrating the configuration of another nitride semiconductor wafer according to the first embodiment.
As shown in FIG. 11, in the nitride semiconductor wafer 111, the first buffer unit 51 includes four nitride semiconductor layers, a first buffer layer BF1 to a fourth buffer layer BF4.
In this example, the fourth buffer layer BF4 includes Al _x4 Ga _1-x4 N (0 ≦ x4 <x3). In this example, the fourth buffer layer BF4 includes, for example, AlGaN. The Al composition ratio x4 of the fourth buffer unit BF4 is, for example, 0.15.

  When x0 = 0 and x4 = 0.15, the lattice mismatch factor LMx in the a-axis direction between the fourth buffer layer BF4 (nth buffer layer BFn) and the second buffer unit 52 is also 0.3%. The relationship of ≦ LMx ≦ 0.8% is satisfied. As described above, the lattice mismatch rate LMx in the a-axis direction between the nth buffer layer BFn and the second buffer unit 52 may satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%.

  Also in this nitride semiconductor wafer 111, the first buffer unit 51 in which the lattice mismatch factor LMx in the a-axis direction in the two adjacent buffer layers satisfies the relationship of 0.3% ≦ LMx ≦ 0.8%, By providing the silicon-containing portion 55, cracks can be suppressed and the dislocation density can be reduced.

FIG. 12 is a schematic cross-sectional view illustrating the configuration of another nitride semiconductor wafer according to the first embodiment.
As illustrated in FIG. 12, in the nitride semiconductor wafer 112, the functional layer 10 s includes the first semiconductor layer 10, the second semiconductor layer 20, the light emitting layer 30, and the stacked unit 32. That is, the nitride semiconductor wafer 112 is a wafer for manufacturing a semiconductor light emitting element as a nitride semiconductor element.

  The first semiconductor layer 10 includes a nitride semiconductor. The first semiconductor layer 10 includes, for example, GaN of the first conductivity type. The first conductivity type is n-type, and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type. In the following description, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type. For example, the first semiconductor layer 10 is an n-type GaN layer. In this example, for example, the first semiconductor layer 10 is the impurity-containing layer IL. The impurity-containing layer IL may be the second semiconductor layer 20.

  The first semiconductor layer 10 is provided on the second buffer unit 52. The stacked unit 32 is provided on the first semiconductor layer 10. The light emitting layer 30 is provided on the stacked portion 32. That is, the light emitting layer 30 is provided on the first semiconductor layer 10, and the stacked portion 32 is provided between the first semiconductor layer 10 and the light emitting layer 30. The second semiconductor layer 20 is provided on the light emitting layer 30. The second semiconductor layer 20 includes a nitride semiconductor and has a second conductivity type. The second semiconductor layer 20 is, for example, a p-type GaN layer. Light is emitted from the light emitting layer 30 by causing a current to flow through the light emitting layer 30 through the first semiconductor layer 10 and the second semiconductor layer 20. The stacked portion 32 is appropriately provided in the functional layer 10s and can be omitted.

FIG. 13 is a schematic cross-sectional view illustrating the configuration of a part of another nitride semiconductor wafer according to the first embodiment.
As illustrated in FIG. 13, the light emitting layer 30 includes a plurality of barrier layers 33 and a well layer 34 provided between the plurality of barrier layers 33. For example, the plurality of barrier layers 33 and the plurality of well layers 34 are alternately stacked along the Z-axis direction.

  The number of well layers 34 may be one or two or more. That is, the light emitting layer 30 can have an SQW (Single-Quantum Well) structure or an MQW (Multi-Quantum Well) structure.

The band gap energy of the barrier layer 33 is larger than the band gap energy of the well layer 34. For example, In _α Ga _1-α N (0 <α <1) is used for the well layer 34. For the barrier layer 33, for example, GaN is used.

  The barrier layer 33 includes a nitride semiconductor containing a group III element and a group V element. The well layer 34 includes a nitride semiconductor containing a group III element and a group V element. The well layer 34 includes, for example, a nitride semiconductor containing indium (In) and gallium (Ga).

FIG. 14 is a schematic cross-sectional view illustrating the configuration of a part of another nitride semiconductor wafer according to the first embodiment.
As illustrated in FIG. 14, the stacked unit 32 includes a plurality of high band gap energy layers 35 and a plurality of low band gap energy layers 36 that are alternately stacked. The plurality of high band gap energy layers 35 include a nitride semiconductor. The plurality of low band gap energy layers 36 includes a nitride semiconductor. The band gap energy of each of the plurality of low band gap energy layers 36 is lower than the band gap energy of each of the plurality of high band gap energy layers 35. The band gap energy of each of the plurality of low band gap energy layers 36 is higher than the band gap energy of each of the plurality of well layers 34.
The stacked unit 32 is, for example, a superlattice layer.

  The high band gap energy layer 35 includes a nitride semiconductor containing a group III element and a group V element. The low band gap energy layer 36 includes a nitride semiconductor including a group III element and a group V element. The low band gap energy layer 36 includes, for example, a nitride semiconductor containing In and Ga.

In this example, the nitride semiconductor wafer 112 further includes an intermediate layer 60.
The intermediate layer 60 is provided between the second buffer unit 52 and the functional layer 10s. The intermediate layer 60 includes a first layer 61, a second layer 62, and a third layer 63. The second layer 62 is provided on the first layer 61. The third layer 63 is provided between the first layer 61 and the second layer 62 on the first layer 61. For example, a plurality of sets in which the first layer 61, the third layer 63, and the second layer 62 are stacked in this order are stacked along the Z-axis direction.

  The first layer 61 includes a nitride semiconductor containing Al. The second layer 62 includes a nitride semiconductor having an Al composition ratio lower than that of the first layer 61. The third layer 63 includes a nitride semiconductor containing Al. The Al composition ratio of the third layer 63 is lower than the Al composition ratio of the first layer 61 and higher than the Al composition ratio of the second layer 62. For the first layer 61, for example, an AlN layer is used. For the second layer 62, for example, a GaN layer is used. For the third layer 63, for example, an AlGaN layer is used.

  The thickness of the first layer 61 is, for example, 12 nm (for example, 10 nm or more and 14 nm or less). The thickness of the second layer 62 is, for example, 450 nm (for example, not less than 300 nm and not more than 600 nm). The thickness of the third layer 63 is, for example, 20 nm (for example, 15 nm or more and 25 nm or less).

  By providing the intermediate layer 60, for example, the propagation of defects such as threading dislocations due to lattice mismatch between the silicon substrate 40 and the functional layer 10s is suppressed. Thereby, for example, the performance of the nitride semiconductor device can be improved. In the intermediate layer 60, the third layer 63 is provided as necessary and can be omitted.

In this example, the nitride semiconductor wafer 112 further includes an underlayer 70.
The foundation layer 70 is provided between the second buffer unit 52 and the functional layer 10s. In this example, the foundation layer 70 is provided between the intermediate layer 60 and the functional layer 10s. The foundation layer 70 includes a nitride semiconductor. The concentration of impurities contained in the foundation layer 70 is lower than the concentration of impurities contained in the functional layer 10s. The concentration of impurities contained in the foundation layer 70 is lower than the concentration of impurities contained in the first semiconductor layer 10. For the underlayer 70, for example, a non-doped GaN layer (i-GaN layer) is used. The thickness of the foundation layer 70 is 1000 nm or more, for example.

FIG. 15 is a graph illustrating characteristics of another nitride semiconductor wafer according to the first embodiment.
The vertical axis in FIG. 15 is the edge dislocation density (cm ⁻² ), and the horizontal axis is the growth time T _Si (minute) of the silicon-containing portion 55. FIG. 15 shows a result of an experiment in which a plurality of samples in which the growth time T _Si of the silicon-containing portion 55 was changed in the configuration of the nitride semiconductor wafer 112 and the edge dislocation density of the plurality of samples were measured. . In this experiment, the growth temperature of the silicon-containing portion 55 is 1040 ° C. In this experiment, SiH ₄ is used as a silicon source gas, and the flow rate of SiH ₄ is 350 lm.

As shown in FIG. 15, the edge dislocation density is 1.6 × 10 ⁹ (cm ⁻² ) in the sample having a growth time T _Si of 0 minute. In the sample having a growth time T _Si of 11 minutes, the edge dislocation density is 5.77 × 10 ⁸ (cm ⁻² ).
Thus, also in the nitride semiconductor wafer 112, cracks can be suppressed and the dislocation density can be reduced.

FIG. 16 is a schematic cross-sectional view illustrating the configuration of another nitride semiconductor wafer according to the first embodiment.
As illustrated in FIG. 16, in the nitride semiconductor wafer 113, the functional layer 10 s is provided on the third semiconductor layer 83 provided on the second buffer unit 52, the third semiconductor layer 83, And a fourth semiconductor layer 84 having a larger band gap than the third semiconductor layer 83. The nitride semiconductor wafer 114 is, for example, a wafer for manufacturing a GaN-based HEMT as a nitride semiconductor element.

  The third semiconductor layer 83 is a channel layer, and the fourth semiconductor layer 84 is a barrier layer. The third semiconductor layer 83 and the fourth semiconductor layer 84 form a heterojunction. For the third semiconductor layer 83, for example, AlGaN or GaN is used. For the fourth semiconductor layer 84, for example, AlGaN or GaN is used. The third semiconductor layer 83 is, for example, non-doped. The third semiconductor layer 83 does not contain impurities, for example. The fourth semiconductor layer 84 is, for example, non-doped or n-type. For example, the fourth semiconductor layer 84 does not include impurities or includes n-type impurities. The third semiconductor layer 83 is, for example, a non-doped GaN layer. The fourth semiconductor layer 84 is, for example, a non-doped or n-type AlGaN layer.

  A source electrode 85 and a drain electrode 86 are provided on the fourth semiconductor layer 84 so as to be separated from each other. The source electrode 85 and the drain electrode 86 are in ohmic contact with the surface of the fourth semiconductor layer 84, respectively. A gate electrode 87 is provided on the fourth semiconductor layer 84 between the source electrode 85 and the drain electrode 86. The gate electrode 87 is in Schottky contact with the surface of the fourth semiconductor layer 84.

The lattice constant of the fourth semiconductor layer 84 is smaller than the lattice constant of the third semiconductor layer 83. As a result, distortion occurs in the fourth semiconductor layer 84, and piezoelectric polarization occurs in the fourth semiconductor layer 84 due to the piezoelectric effect. As a result, a two-dimensional electron gas 88 is formed near the interface between the third semiconductor layer 83 and the fourth semiconductor layer 84. By controlling the voltage applied to the gate electrode 87, the concentration of the two-dimensional electron gas 88 below the gate electrode 87 increases or decreases. Thereby, the current flowing between the source electrode 85 and the drain electrode 86 is controlled.
Also in this nitride semiconductor wafer 113, cracks can be suppressed and the dislocation density can be reduced.

(Second Embodiment)
FIG. 17 is a schematic cross-sectional view illustrating the configuration of a nitride semiconductor device according to the second embodiment.
As shown in FIG. 17, the nitride semiconductor device 210 according to this embodiment includes a first buffer unit 51, a silicon-containing unit 55, and an upper layer unit 15. The upper layer portion 15 includes a second buffer portion 52 and a functional layer 10s.
The nitride semiconductor element 210 is manufactured by the nitride semiconductor wafer 110. The first buffer unit 51 is formed on the silicon substrate 40. In the nitride semiconductor element 210, the silicon substrate 40 can be omitted. Regarding the first buffer unit 51, the silicon-containing unit 55, the second buffer unit 52, and the functional layer 10s, the configuration described in regard to the first embodiment can be applied.
Thereby, the nitride semiconductor device 210 in which cracks are suppressed and the dislocation density is reduced is provided.

(Third embodiment)
The present embodiment relates to a method for manufacturing a nitride semiconductor wafer. This embodiment corresponds to a part of the method for manufacturing a nitride semiconductor device.
FIG. 18A to FIG. 18E are schematic cross-sectional views in order of the processes, illustrating the method for manufacturing a nitride semiconductor wafer according to the third embodiment.
As shown in FIG. 18A, the first buffer layer BF1 is formed on the silicon substrate 40. For example, an AlN layer having a thickness of 120 nm is formed as the first buffer layer BF1. A second buffer layer BF2 is formed on the first buffer layer BF1. For example, an AlGaN layer having a thickness of 100 nm and an Al composition ratio of 50% is formed as the second buffer layer BF2. A third buffer layer BF3 is formed on the second buffer layer BF2. For example, an AlGaN layer having a thickness of 200 nm and an Al composition ratio of 30% is formed as the third buffer layer BF3. A fourth buffer layer BF4 is formed on the third buffer layer BF3. For example, an AlGaN layer having a thickness of 250 nm and an Al composition ratio of 15% is formed as the fourth buffer layer BF4. A fifth buffer layer BF5 is formed on the fourth buffer layer BF4. For example, a GaN layer having a thickness of 360 nm is formed as the fifth buffer layer BF5. Thereby, the first buffer part 51 is formed on the silicon substrate 40.

  In the first buffer unit 51, two adjacent buffers in the first buffer layer BF1 to the fifth buffer layer BF5 are adjusted by adjusting the Al composition ratio of the AlGaN layers of the second buffer layer BF2 to the fourth buffer layer BF4. All the lattice mismatch ratios LMx in the a-axis direction in the layer satisfy the relationship of 0.3% ≦ LMx ≦ 0.8%. As a result, a greater compressive stress is applied to the first buffer unit 51 than when the relationship of 0.3% ≦ LMx ≦ 0.8% is not satisfied. Thereby, generation | occurrence | production of a crack is suppressed in the functional layer 10s formed later.

As shown in FIG. 18B, the silicon-containing portion 55 is formed on the first buffer portion 51 (fifth buffer layer BF5). For example, the silicon-containing portion 55 is formed by supplying SiH ₄ for 8 minutes at a flow rate of 350 lm at 1040 ° C. to the silicon substrate 40 on which the first buffer portion 51 is formed.

  As illustrated in FIG. 18C, the second buffer unit 52 is formed on the silicon-containing unit 55 at 1090 ° C. For example, a GaN layer having a thickness of 2000 nm is formed as the second buffer unit 52.

  As illustrated in FIG. 18D, the first layer 61 is formed on the second buffer unit 52. For example, an AlN layer having a thickness of 12 nm is formed as the first layer 61. A third layer 63 is formed on the first layer 61. For example, an AlGaN layer having a thickness of 24 nm is formed as the third layer 63. A second layer 62 is formed on the third layer 63. For example, a GaN layer having a thickness of 350 nm is formed as the second layer 62. The formation of the first layer 61, the third layer 63, and the second layer 62 is repeated a plurality of times, and a plurality of sets of the first layer 61, the third layer 63, and the second layer 62 are stacked. Thereby, the intermediate layer 60 is formed on the second buffer unit 52.

  A base layer 70 is formed on the intermediate layer 60. For example, an i-GaN layer having a thickness of 1000 nm is formed as the base layer 70.

  As shown in FIG. 18E, the first semiconductor layer 10 is formed on the base layer 70. For example, an n-type GaN layer having a thickness of 1000 nm is formed as the first semiconductor layer 10.

  A plurality of high band gap energy layers 35 and low band gap energy layers 36 are alternately stacked on the first semiconductor layer 10. As the high band gap energy layer 35, for example, a GaN layer is used. For the low band gap energy layer 36, for example, an InGaN layer is used. Thereby, the stacked portion 32 is formed on the first semiconductor layer 10.

  A plurality of barrier layers 33 and well layers 34 are alternately stacked on the stacked portion 32. For the barrier layer 33, for example, a GaN layer is used. For the well layer 34, for example, an InGaN layer is used. Thereby, the light emitting layer 30 is formed on the stacked portion 32.

The second semiconductor layer 20 is formed on the light emitting layer 30. For example, a p-type GaN layer having a thickness of 100 nm is formed as the second semiconductor layer 20. Thereby, the functional layer 10 s is formed on the base layer 70. The upper layer portion 15 including the second buffer portion 52, the intermediate layer 60, the base layer 70, and the functional layer 10s is formed on the silicon-containing portion 55.
As described above, the nitride semiconductor wafer 113 is completed.

  In the embodiment, the semiconductor layer is grown by, for example, a metal-organic chemical vapor deposition (MOCVD) method, a metal-organic vapor phase epitaxy (MOVPE) method, or molecular beam epitaxy. (Molecular Beam Epitaxy: MBE) method, halide vapor phase epitaxy method (HVPE) method and the like can be used.

For example, when the MOCVD method or the MOVPE method is used, the following can be used as raw materials for forming each semiconductor layer. For example, TMGa (trimethyl gallium) and TEGa (triethyl gallium) can be used as the Ga raw material. As a source of In, for example, TMIn (trimethylindium), TEIn (triethylindium), or the like can be used. As a raw material for Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used. As a Si raw material, SiH ₄ (monosilane), Si ₂ H ₆ (disilane), or the like can be used.

FIG. 19 is a flowchart illustrating the method for manufacturing the nitride semiconductor wafer according to the third embodiment.
As shown in FIG. 19, in the method for manufacturing a nitride semiconductor wafer according to the embodiment, step S <b> 110 for forming the first buffer part 51, step S <b> 120 for forming the silicon-containing part 55, and the upper layer part 15 are formed. Step S130.

In step S110, for example, the process described with reference to FIG. In step S120, for example, the processing described with reference to FIG. In step S130, for example, the processing described with reference to FIGS. 18C to 18E is performed.
Thereby, the nitride semiconductor wafer which suppressed the crack and reduced the dislocation density is manufactured.

  According to the embodiment, a nitride semiconductor wafer, a nitride semiconductor element, and a method for manufacturing a nitride semiconductor wafer in which cracks are suppressed and dislocation density is reduced are provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. is good.

The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, a silicon substrate, a first buffer unit, a silicon-containing unit, an upper layer unit, a second buffer unit, a functional layer, an impurity-containing layer, and first to nth buffer layers included in a nitride semiconductor wafer and a nitride semiconductor element The specific configuration of each element is included in the scope of the present invention as long as those skilled in the art can implement the present invention in the same manner by appropriately selecting from the known ranges and obtain the same effects.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all nitride semiconductor wafers that can be implemented by those skilled in the art by appropriately modifying the design based on the nitride semiconductor wafer, nitride semiconductor element, and nitride semiconductor wafer manufacturing method described above as embodiments of the present invention. A nitride semiconductor device and a method for manufacturing a nitride semiconductor wafer also belong to the scope of the present invention as long as they include the gist of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 10s ... Functional layer, 15 ... Upper layer part, 20 ... 2nd semiconductor layer, 30 ... Light emitting layer, 32 ... Laminate part, 33 ... Barrier layer, 34 ... Well layer, 35 ... High band gap energy 36, low band gap energy layer, 40 ... silicon substrate, 51 ... first buffer part, 52 ... second buffer part, 55 ... silicon-containing part, 60 ... intermediate layer, 61 ... first layer, 62 ... second Layer 63, third layer 70, underlying layer, 83 third semiconductor layer, 84 fourth semiconductor layer, 85 source electrode, 86 drain electrode, 87 gate electrode, 88 two-dimensional electron gas, 110 , 111, 112, 113, 114 ... nitride semiconductor wafer, 210 ... nitride semiconductor element, BF1 ... first buffer layer, BF1a ... main surface, BF2 ... second buffer layer, B 3 ... 3rd buffer layer, BF4 ... 4th buffer layer, BF5 ... 5th buffer layer, BFi ... i-th buffer layer, BFn ... n-th buffer layer, BF (i + 1) ... (i + 1) th buffer layer, CF, CF2 ~ CF5, CF2a ~ CF5a, CFa, CFt ... variation, IL ... impurity-containing layer, LM, LMc, LMt, LMx, LM2-LM5 ... lattice mismatch rate, SRi, SR2-SR5 ... relaxation rate, t0-t5 ... Thickness, x2 to x4 ... Composition ratio

Claims (5)

A silicon substrate;
A first buffer unit provided on the silicon substrate and having first to nth buffer layers (n is an integer of 2 to 9) including a nitride semiconductor, wherein the first to nth buffer layers The i-th buffer layer (i is an integer of 1 or more and less than n) has a lattice length Wi in a first direction parallel to the main surface of the first buffer layer, and the i-th buffer layer The (i + 1) th buffer layer provided above has a lattice length W (i + 1) in the first direction, and in the first to nth buffer layers, the i-th buffer layer and the (i + 1) -th buffer. A first buffer section satisfying a relationship of 0.003 ≦ (W (i + 1) −Wi) /Wi≦0.008,
A silicon-containing part provided on the first buffer part and containing silicon;
An upper layer portion provided on the silicon-containing portion and including a nitride semiconductor;
With
A nitride semiconductor wafer in which a dislocation density in the upper layer portion is lower than a dislocation density in the first buffer portion.   In the first buffer unit, in all of the first to nth buffer layers, the i-th buffer layer and the (i + 1) th buffer layer are 0.003 ≦ (W (i + 1) −Wi) / Wi ≦ 0. The nitride semiconductor wafer according to claim 1 satisfying a relationship of .008. The upper layer part is
A second buffer portion provided on the silicon-containing portion and including a nitride semiconductor;
A functional layer provided on the second buffer portion and including a nitride semiconductor;
Including
The functional layer includes an impurity-containing layer containing impurities,
3. The nitride semiconductor wafer according to claim 1, wherein an impurity concentration of the impurity-containing layer is higher than an impurity concentration of the second buffer portion. A first buffer unit formed on a silicon substrate and having first to nth buffer layers (n is an integer of 2 to 9) including a nitride semiconductor, wherein the first to nth buffer layers Of these, the i-th buffer layer (i is an integer of 1 or more and less than n) has a lattice length Wi in a first direction parallel to the main surface of the first buffer layer, and is above the i-th buffer layer. The (i + 1) th buffer layer has a lattice length W (i + 1) in the first direction, and in the first to nth buffer layers, the i-th buffer layer and the (i + 1) -th buffer layer A first buffer unit satisfying a relationship of 0.003 ≦ (W (i + 1) −Wi) /Wi≦0.008;
A silicon-containing part provided on the first buffer part and containing silicon;
An upper layer portion provided on the silicon-containing portion and including a nitride semiconductor;
With
The upper layer part is
A second buffer portion provided on the silicon-containing portion and including a nitride semiconductor;
A functional layer provided on the second buffer portion and including a nitride semiconductor;
Including
A nitride semiconductor device in which a dislocation density in the upper layer portion is lower than a dislocation density in the first buffer portion. A first buffer unit including first to n-th buffer layers (n is an integer of 2 to 9) including a nitride semiconductor, wherein the i-th buffer layer (i Is an integer greater than or equal to 1 and less than n) and has a lattice length Wi in a first direction parallel to the main surface of the first buffer layer, and (i + 1) th provided on the i-th buffer layer. The buffer layer has a lattice length W (i + 1) in the first direction, and in the first to nth buffer layers, the i-th buffer layer and the (i + 1) -th buffer layer have 0.003 ≦ (W Forming a first buffer portion on the silicon substrate that satisfies a relationship of (i + 1) −Wi) /Wi≦0.008;
Forming a silicon-containing part containing silicon on the first buffer part;
Forming an upper layer portion including a nitride semiconductor and having a dislocation density lower than the dislocation density of the first buffer portion on the silicon-containing portion;
A method for manufacturing a nitride semiconductor wafer comprising: