JP2014063798A - Ceramics circuit board - Google Patents

Ceramics circuit board Download PDF

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JP2014063798A
JP2014063798A JP2012206712A JP2012206712A JP2014063798A JP 2014063798 A JP2014063798 A JP 2014063798A JP 2012206712 A JP2012206712 A JP 2012206712A JP 2012206712 A JP2012206712 A JP 2012206712A JP 2014063798 A JP2014063798 A JP 2014063798A
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circuit board
coating layer
metal plate
ceramic
thermal expansion
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Nobuhiko Chiwata
伸彦 千綿
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Proterial Ltd
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Hitachi Metals Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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Abstract

PROBLEM TO BE SOLVED: To provide a ceramics circuit board in which the increase of irregularities on the surface of a metal plate can be suppressed even if a thermal load acts thereon.SOLUTION: A ceramics circuit board includes a ceramic substrate composed of silicon nitride sintered compact, and a metal plate principally composed of copper and having one side bonded to one side of the ceramic substrate, and the other side on which a coating layer is formed. Thermal expansion coefficient of the ceramic substrate at -40°C through 250°C measured according to JIS Z2285 is 2-4×10/K, and thermal expansion coefficient of the metal layer excepting the coating layer is 16-18×10/K. The coating layer contains at least one kind selected from a group consisting of Mo, W, Cr, thermal expansion coefficient of the coating layer at -40°C through 250°C is 90-180 W mK, and when the average thickness of the metal plate is t2, t1/t2 is in a range of 0.005-0.1.

Description

本発明は、窒化珪素焼結体からなるセラミックス基板と、セラミックス基板に接合された銅を主成分とする金属板とを有するセラミックス回路基板に係る発明である。   The present invention relates to a ceramic circuit board having a ceramic substrate made of a silicon nitride sintered body and a metal plate mainly composed of copper bonded to the ceramic substrate.

上記セラミックス回路基板が組み込まれる半導体装置の側断面図を図１に示す。半導体装置１１は、ろう材層１０ｂを介してセラミックス基板１０ａの上面に接合された回路板（金属板）１０ｃと、ろう材層１０ｄを介してセラミックス基板１０ａの下面に接合された放熱板（金属板）１０ｅを有するセラミックス回路基板１０を備えている。そして、回路板１０ｃの上面には、半田層１１ａを介しＭＯＳＦＥＴやＩＧＢＴ等の半導体素子１１ｂが接合されている。   A side sectional view of a semiconductor device in which the ceramic circuit board is incorporated is shown in FIG. The semiconductor device 11 includes a circuit board (metal plate) 10c bonded to the upper surface of the ceramic substrate 10a via the brazing material layer 10b, and a heat dissipation plate (metal) bonded to the lower surface of the ceramic substrate 10a via the brazing material layer 10d. A ceramic circuit board 10 having a plate 10e is provided. A semiconductor element 11b such as MOSFET or IGBT is joined to the upper surface of the circuit board 10c via a solder layer 11a.

このように半導体素子を金属板に接合して半導体装置を形成する構成のセラミックス回路基板において、冷熱サイクル、具体的には半導体素子と金属板を接合する際の加熱・冷却に伴う熱負荷、または半導体装置の使用時の作動・停止に伴う熱負荷に起因し、金属板を構成する組織レベルにおける微小変形が生じ、金属板の表面の凹凸が大きくなる場合があった。そして、金属板の表面の凹凸は、特に、半田層１１ａと回路板１０ｃとの接合界面に剥離を発生させ、半導体装置の接合信頼性を低下させるため、当該凹凸の増大が低減可能な構成のセラミックス回路基板の実現が要請されていた。   In a ceramic circuit board configured to join a semiconductor element to a metal plate in this way to form a semiconductor device, a thermal cycle, specifically, a thermal load accompanying heating / cooling when joining the semiconductor element and the metal plate, or Due to the thermal load associated with the operation / stop when the semiconductor device is used, there is a case where micro deformation occurs at the structure level constituting the metal plate, and the surface of the metal plate becomes uneven. The unevenness on the surface of the metal plate generates peeling at the bonding interface between the solder layer 11a and the circuit board 10c and lowers the bonding reliability of the semiconductor device, so that the increase in the unevenness can be reduced. Realization of a ceramic circuit board has been demanded.

かかる要請に対応したセラミックス回路基板が組み込まれた半導体装置が、下記特許文献１に開示されている。特許文献１に開示された一つの態様の半導体装置は、半導体素子を搭載する金属板を備え、当該金属板の半導体素子を搭載する部分またはその近傍に、金属板よりも熱膨張係数が低い多孔質体からなる低熱膨張部を埋設した半導体装置である。また、特許文献１に開示された別の態様の半導体装置は、半導体素子を搭載する金属板を備え、当該金属板よりも熱膨張係数が低く、金属板の半導体素子を搭載する部分を取り囲む部分またはその近傍に環状体からなる、低熱膨張部が埋設されている半導体装置である。なお、上記２つの態様の半導体装置は、いずれも、セラミックス等からなる絶縁板と、絶縁板に接合された金属板とを有する絶縁回路基板を備えており、当該絶縁回路基板が、本発明におけるセラミックス回路基板に該当する。   A semiconductor device in which a ceramic circuit board corresponding to such a request is incorporated is disclosed in Patent Document 1 below. A semiconductor device according to one aspect disclosed in Patent Literature 1 includes a metal plate on which a semiconductor element is mounted, and a porous member having a lower thermal expansion coefficient than that of the metal plate at or near a portion of the metal plate on which the semiconductor element is mounted. This is a semiconductor device in which a low thermal expansion portion made of a material is embedded. A semiconductor device according to another aspect disclosed in Patent Document 1 includes a metal plate on which a semiconductor element is mounted, and has a lower coefficient of thermal expansion than the metal plate and surrounds a portion of the metal plate on which the semiconductor element is mounted. Alternatively, it is a semiconductor device in which a low thermal expansion portion made of an annular body is embedded in the vicinity thereof. Note that each of the semiconductor devices according to the above two aspects includes an insulating circuit board having an insulating plate made of ceramics or the like and a metal plate bonded to the insulating plate, and the insulating circuit board is used in the present invention. Corresponds to ceramic circuit board.

特開２００６−２９４８９０号公報JP 2006-294890 A

本発明は、上記特許文献１に例示された従来技術のセラミックス回路基板に対し、熱負荷が作用した場合でも金属板の表面の凹凸の増大が抑制されるセラミックス回路基板を提供することを目的としている。   An object of the present invention is to provide a ceramic circuit board in which an increase in unevenness on the surface of a metal plate is suppressed even when a thermal load is applied to the conventional ceramic circuit board exemplified in Patent Document 1. Yes.

上記目的を達成する本発明の一態様は、窒化珪素焼結体からなるセラミックス基板と、一方の面が前記セラミックス基板の一方の面に接合され、他方の面に形成された被覆層を有する銅を主成分とする金属板を備えたセラミックス回路基板であって、ＪＩＳ Ｚ２２８５に準拠して測定した、−４０〜２５０℃における前記セラミックス基板の熱膨張率が、２〜４×１０−６／Ｋであり、前記被覆層を除いた前記金属板の熱膨張率が、１６〜１８×１０−６／Ｋであり、前記被覆層は、Ｍｏ、Ｗ、Ｃｒからなる群のうち少なくとも一種を含み、−４０〜２５０℃における前記被覆層の熱伝導率は、９０〜１８０Ｗ・ｍ−１・Ｋ−１であり、前記被覆層の平均厚みをｔ１、前記金属板の平均厚みをｔ２としたとき、ｔ１／ｔ２が０．００５〜０．１の範囲であるセラミックス回路基板である。 One embodiment of the present invention that achieves the above object is a copper substrate having a ceramic substrate made of a silicon nitride sintered body, a coating layer formed on one surface of the ceramic substrate and bonded to the other surface. A ceramic circuit board provided with a metal plate containing as a main component, the coefficient of thermal expansion of the ceramic substrate at −40 to 250 ° C. measured according to JIS Z2285 is 2 to 4 × 10 −6 / K. The coefficient of thermal expansion of the metal plate excluding the coating layer is 16 to 18 × 10 −6 / K, and the coating layer includes at least one of the group consisting of Mo, W, and Cr, The thermal conductivity of the coating layer at −40 to 250 ° C. is 90 to 180 W · m −1 · K −1 , where the average thickness of the coating layer is t1 and the average thickness of the metal plate is t2. t1 / t2 is 0.005 A ceramic circuit board is in the range of .1.

かかるセラミックス回路基板によれば、ＪＩＳ Ｚ２２８５に準拠して測定した、−４０〜２５０℃における熱膨張率が２〜４×１０−６／Ｋであるセラミックス基板に、熱膨張率が１６〜１８×１０−６／Ｋの金属板が接合されている。このように熱膨張率の小さなセラミックス基板に金属板は接合されているので、冷熱サイクルに伴い熱負荷が作用した場合にも、金属板を構成する組織レベルの微小変形が抑制される。 According to such a ceramic circuit board, the thermal expansion coefficient is 16 to 18 × on a ceramic substrate having a thermal expansion coefficient of 2 to 4 × 10 −6 / K at −40 to 250 ° C. measured according to JIS Z2285. A metal plate of 10 −6 / K is joined. Since the metal plate is bonded to the ceramic substrate having a small coefficient of thermal expansion in this way, even when a thermal load is applied in association with the cooling / heating cycle, microdeformation at the tissue level constituting the metal plate is suppressed.

そして、上記金属板の表面には、Ｍｏ、Ｗ、Ｃｒからなる群のうち少なくとも一種を含む被覆層が形成されている。これらの元素は元来熱膨張率が低いので、金属板を構成する組織レベルの微小変形が抑制される。すなわち、本発明のセラミックス回路基板は、熱膨張率が低いセラミックス基板と被覆層との間に金属板を介在させる構成により、冷熱サイクルによる熱負荷が作用した場合における、金属板を構成する組織レベルの微小変形が抑制するものである。その結果、上記した冷熱サイクル試験に付した前後における、ＪＩＳ Ｂ０６０１−２００１に準拠して測定した被覆層の表面粗さ（Ｒｚ）の差が、２０μｍ以下となり、もって当該金属板に接合される半導体素子との接合信頼性が確保される。さらに、このような被覆層は、周知の成膜法、例えばメッキ、スパッタリング、化学蒸着、イオンプレーティング等の手段を利用し、比較的容易に形成することができ、上記特許文献１に記載のセラミックス回路基板に対し、低コストで被覆層を形成することが可能となる。なお、上記被覆層は、Ｍｏ、Ｗ、Ｃｒからなる群のうち少なくとも一種に替え、金属を主成分とする第１相と、セラミックスを主成分とする第２相とで構成してもよい。   And the coating layer containing at least 1 type in the group which consists of Mo, W, and Cr is formed in the surface of the said metal plate. Since these elements originally have a low coefficient of thermal expansion, microdeformation at the tissue level constituting the metal plate is suppressed. That is, the ceramic circuit board of the present invention has a structure in which a metal plate is interposed between a ceramic substrate having a low coefficient of thermal expansion and a coating layer, and a structure level that constitutes the metal plate when a thermal load is applied due to a cooling cycle. Slight deformation is suppressed. As a result, the difference in the surface roughness (Rz) of the coating layer measured in accordance with JIS B0601-2001 before and after being subjected to the above-described thermal cycle test is 20 μm or less, and the semiconductor is bonded to the metal plate. Bonding reliability with the element is ensured. Furthermore, such a coating layer can be formed relatively easily by using a known film forming method such as plating, sputtering, chemical vapor deposition, ion plating, and the like. A coating layer can be formed on the ceramic circuit board at a low cost. In addition, the said coating layer may replace with at least 1 type from the group which consists of Mo, W, and Cr, and may be comprised with the 1st phase which has a metal as a main component, and the 2nd phase which has a ceramic as a main component.

さらに、半導体素子が接合されるセラミックス回路基板としては、実用上、半導体素子の作動時に発生する熱を外部に放熱する必要があり、セラミックス回路基板の熱抵抗を低減せめる必要がある。このため、本発明に係るセラミックス回路基板では、銅を主成分とする金属板の低い熱抵抗を阻害しないよう、上記のとおり被覆層の熱伝導率を９０〜１８０Ｗ・ｍ−１・Ｋ−１とし、さらに当該被覆層の平均厚みをｔ１、金属板の平均厚みをｔ２としたとき、ｔ１／ｔ２が０．００５〜０．１の範囲としている。 Furthermore, as a ceramic circuit board to which a semiconductor element is bonded, it is practically necessary to dissipate heat generated during operation of the semiconductor element to the outside, and it is necessary to reduce the thermal resistance of the ceramic circuit board. For this reason, in the ceramic circuit board according to the present invention, the thermal conductivity of the coating layer is set to 90 to 180 W · m −1 · K −1 as described above so as not to inhibit the low thermal resistance of the metal plate mainly composed of copper. Furthermore, when the average thickness of the coating layer is t1 and the average thickness of the metal plate is t2, t1 / t2 is in the range of 0.005 to 0.1.

なお、上記態様のセラミックス回路基板において、−４０〜２５０℃における前記被覆層の熱膨張率をα１、前記金属板の熱膨張率をα２としたとき、α１／α２の範囲は０．１〜０．７となる。この態様および下記する態様のセラミックス回路基板の作用・効果については、発明を実施するための形態の欄で詳細に説明する。   In the ceramic circuit board of the above aspect, when the thermal expansion coefficient of the coating layer at −40 to 250 ° C. is α1, and the thermal expansion coefficient of the metal plate is α2, the range of α1 / α2 is 0.1 to 0. .7. The operation and effect of this embodiment and the ceramic circuit board of the embodiment described below will be described in detail in the section of the embodiment for carrying out the invention.

加えて、前記金属板は、半導体素子が接合される接合部を有し、前記被覆層は、前記接合部の周囲に設けられていることが望ましい。   In addition, it is preferable that the metal plate has a joint portion to which a semiconductor element is joined, and the covering layer is provided around the joint portion.

本発明によれば、上記したように、回路基板に熱負荷が作用した場合でも、金属板を構成する組織レベルの微小変形が抑制され、金属板の表面に設けられた被覆層の表面の凹凸の増大が抑制される。その結果、熱負荷が作用した後においても、被覆層の表面粗さ（Ｒｚ）の増大が抑制され、もって半導体素子の接合信頼性が確保できるとともに、熱抵抗の低いセラミックス回路基板を低コストで提供することができる。   According to the present invention, as described above, even when a thermal load is applied to the circuit board, minute deformation at the tissue level constituting the metal plate is suppressed, and the surface irregularities of the coating layer provided on the surface of the metal plate are suppressed. Increase is suppressed. As a result, even after a thermal load is applied, an increase in the surface roughness (Rz) of the coating layer is suppressed, so that it is possible to ensure the bonding reliability of the semiconductor element and to reduce the cost of the ceramic circuit board having a low thermal resistance. Can be provided.

半導体装置の側断面図である。It is a sectional side view of a semiconductor device. 本発明に係る第１態様のセラミックス回路基板の側断面図である。It is a sectional side view of the ceramic circuit board of the 1st mode concerning the present invention. 図２（ａ）のセラミックス回路基板に半導体素子を接合した状態の側断面図である。FIG. 3 is a side sectional view of a state in which a semiconductor element is bonded to the ceramic circuit board of FIG. 図２（ｂ）のセラミックス回路基板を上方から見た平面図である。It is the top view which looked at the ceramic circuit board of FIG.2 (b) from upper direction. 図２のセラミックス回路基板の第１変形例であるセラミックス回路基板の側断面図である。It is a sectional side view of the ceramic circuit board which is the 1st modification of the ceramic circuit board of FIG. 図２のセラミックス回路基板の第２変形例であるセラミックス回路基板の側断面図である。It is a sectional side view of the ceramic circuit board which is the 2nd modification of the ceramic circuit board of FIG. 図４（ａ）のセラミックス回路基板を上方から見た平面図である。It is the top view which looked at the ceramic circuit board of Fig.4 (a) from upper direction. 本発明に係る第２態様のセラミックス回路基板の側断面図である。It is a sectional side view of the ceramic circuit board of the 2nd mode concerning the present invention. 図５（ａ）のセラミックス回路基板を上方から見た平面図である。It is the top view which looked at the ceramic circuit board of Fig.5 (a) from upper direction. 図５（ａ）のＡ部拡大図である。It is the A section enlarged view of Fig.5 (a).

以下、本発明について、その第１実施形態およびその変形例、ならびに第２実施形態に基づき図面を参照しつつ具体的に説明する。なお、本発明は、上記実施形態に限定されることなく、本発明の作用・効果を奏することのできる範囲で、適宜変形して実施することができる。また、第１実施形態および第２実施形態の各構成要素は、適宜組み合わせて実施することができる。   Hereinafter, the present invention will be specifically described with reference to the drawings based on the first embodiment, its modification, and the second embodiment. In addition, this invention is not limited to the said embodiment, In the range which can show | play the effect | action and effect of this invention, it can deform | transform suitably and can be implemented. Moreover, each component of 1st Embodiment and 2nd Embodiment can be implemented in combination as appropriate.

［第１実施形態］
本発明に係る第１実施形態のセラミックス回路基板（以下、回路基板と言う場合がある。）について、その側断面図である図２（ａ）を参照しつつ説明する。本態様の回路基板１は、窒化珪素焼結体からなるセラミックス基板（以下、窒化珪素基板と言う場合がある。）１ａと、窒化珪素基板１ａの上面（一面）にろう材層１ｂを介し接合された金属板である回路板１ｃと、下面（他面）にろう材層１ｄを介し接合された金属板である放熱板１ｅとを有している。なお、ろう材層１ｂ・１ｄを構成するろう材としては、銅を主成分とする回路板１ｃ・放熱板１ｅと窒化珪素基板１ａとを接合する場合に常用される、例えばＴｉ等の活性金属を含むＡｇ−Ｃｕ系ろう材またはＡｇ−Ｃｕ−Ｉｎ系ろう材を使用すればよい。 [First Embodiment]
The ceramic circuit board of the first embodiment according to the present invention (hereinafter sometimes referred to as a circuit board) will be described with reference to FIG. The circuit board 1 of this embodiment is bonded to a ceramic substrate (hereinafter also referred to as a silicon nitride substrate) 1a made of a silicon nitride sintered body and an upper surface (one surface) of the silicon nitride substrate 1a via a brazing material layer 1b. A circuit board 1c that is a metal plate, and a heat radiating plate 1e that is a metal plate joined to the lower surface (other surface) via a brazing material layer 1d. As the brazing material constituting the brazing material layers 1b and 1d, an active metal such as Ti, which is commonly used when joining the circuit board 1c / heat radiating plate 1e mainly composed of copper and the silicon nitride substrate 1a, is used. An Ag—Cu based brazing material or an Ag—Cu—In based brazing material may be used.

窒化珪素基板１ａは、常用される製造方法で製造された、主相である窒化珪素粒子と焼結助剤を主成分とする粒界相を含む窒化珪素焼結体であり、そのＪＩＳ Ｃ００２５−１９８８に準拠して測定した、−４０〜２５０℃における熱膨張率は、２〜４×１０−６／Ｋである。 The silicon nitride substrate 1a is a silicon nitride sintered body including a grain boundary phase mainly composed of silicon nitride particles as a main phase and a sintering aid, which is manufactured by a commonly used manufacturing method, and the JIS C0025- The coefficient of thermal expansion at −40 to 250 ° C. measured in accordance with 1988 is 2 to 4 × 10 −6 / K.

回路板１ｃ・放熱板１ｅとはいずれも銅を主成分とする厚みが０．１〜１．０ｍｍの金属板であり、そのＪＩＳ Ｚ２２８５に準拠して測定した−４０〜２５０℃における熱膨張率は、１６〜１８×１０−６／Ｋである。ここで、本態様の回路基板１では、回路板１ｃ・放熱板１ｅは、ろう材層１ｂ・１ｄを介し窒化珪素基板１ａと接合しているが、直接接合法により窒化珪素基板１ａと直接接合してもよい。また、放熱板１ｅは、本発明において必須の構成要素ではなく、回路基板１は、少なくとも回路板１ｃが設けられていればよい。さらに、回路板１ｃは、単一の金属板に限定されず、複数の金属板からなる回路パターンであってもよい。 The circuit board 1c and the heat radiating board 1e are each a metal plate having a thickness of 0.1 to 1.0 mm mainly composed of copper, and a coefficient of thermal expansion at −40 to 250 ° C. measured in accordance with JIS Z2285. Is 16 to 18 × 10 −6 / K. Here, in the circuit board 1 of this embodiment, the circuit board 1c and the heat sink 1e are joined to the silicon nitride substrate 1a via the brazing filler metal layers 1b and 1d, but are directly joined to the silicon nitride substrate 1a by a direct joining method. May be. Moreover, the heat sink 1e is not an essential component in the present invention, and the circuit board 1 only needs to be provided with at least the circuit board 1c. Furthermore, the circuit board 1c is not limited to a single metal plate, and may be a circuit pattern composed of a plurality of metal plates.

上記回路板（金属板）１ｃの表面には被覆層１ｆが形成されている。本態様の被覆層１ｆは、常用される成膜法であるスパッタリング等で形成された、Ｍｏ（モリブデン）を主成分とする被覆層１ｆである。被覆層１ｆを構成する主成分は、Ｗ（タングステン）またはＣｒ（クロム）であってもよい。また、熱負荷が作用した場合に生じる回路基板１の反りを低減するため、上記被覆層１ｆは、放熱板１ｅの表面に設けておいてもよい。ここで、「主成分」とは、当該元素を５０％以上含むことを言う。そして、上記Ｗ、ＭｏまたはＣｒからなる群のうち少なくとも一種を主成分として含む被覆層１ｆの−４０〜２５０℃における熱膨張率をα１、回路板１ｃの熱膨張率をα２としたとき、α１／α２の範囲は０．１〜０．７となる。ここで、α１／α２が０．１未満の場合には、熱負荷が作用した場合に、被覆層１ｆと回路板１ｃとの接合界面、または回路板１ｃと窒化珪素基板１ａとの接合界面に過大な応力が生じ、被覆層１ｆまたは回路板１ｃが剥離する場合がある。一方で、α１／α２が０．７を超える場合には、本発明の作用・効果を発揮することができない。   A coating layer 1f is formed on the surface of the circuit board (metal plate) 1c. The covering layer 1f of this embodiment is a covering layer 1f mainly composed of Mo (molybdenum) formed by sputtering or the like, which is a commonly used film forming method. The main component constituting the coating layer 1f may be W (tungsten) or Cr (chromium). Further, the coating layer 1f may be provided on the surface of the heat radiating plate 1e in order to reduce the warp of the circuit board 1 that occurs when a thermal load is applied. Here, the “main component” means containing 50% or more of the element. When the thermal expansion coefficient at −40 to 250 ° C. of the coating layer 1f containing at least one of the groups consisting of W, Mo or Cr as a main component is α1, and the thermal expansion coefficient of the circuit board 1c is α2, α1 The range of / α2 is 0.1 to 0.7. Here, when α1 / α2 is less than 0.1, when a thermal load is applied, the bonding interface between the coating layer 1f and the circuit board 1c or the bonding interface between the circuit board 1c and the silicon nitride substrate 1a is applied. Excessive stress may occur and the covering layer 1f or the circuit board 1c may be peeled off. On the other hand, when α1 / α2 exceeds 0.7, the function and effect of the present invention cannot be exhibited.

さらに、本態様の回路基板１では、その熱抵抗を考慮し、被覆層１ｆの熱伝導率は、９０〜１８０Ｗ・ｍ−１・Ｋ−１としている。加えて、被覆層１ｆの平均厚みをｔ１、回路板１ｃの平均厚みをｔ２としたとき、ｔ１／ｔ２は０．００５〜０．１の範囲としている。すなわち、上記のように回路板１ｃの平均厚みが０．１〜１．０ｍｍである場合には、被覆層１ｆの平均厚みは０．５〜１００μｍとする。ここで、ｔ１／ｔ２が０．００５未満の場合には、本発明の作用・効果を発揮することができない。一方で、上記のように９０〜１８０Ｗ・ｍ−１・Ｋ−１の熱伝導率を有する被覆層１ｆであっても、ｔ１／ｔ２が０．１を超える場合には、回路基板１の熱抵抗が高くなる。なお、回路板１ｃおよび被覆層１ｆの平均厚みの定義は、実験例の項で説明する。 Furthermore, in the circuit board 1 of this aspect, the thermal conductivity of the coating layer 1f is set to 90 to 180 W · m −1 · K −1 in consideration of the thermal resistance. In addition, when the average thickness of the cover layer 1f is t1, and the average thickness of the circuit board 1c is t2, t1 / t2 is in the range of 0.005 to 0.1. That is, when the average thickness of the circuit board 1c is 0.1 to 1.0 mm as described above, the average thickness of the coating layer 1f is 0.5 to 100 μm. Here, when t1 / t2 is less than 0.005, the action and effect of the present invention cannot be exhibited. On the other hand, even when the coating layer 1f has a thermal conductivity of 90 to 180 W · m −1 · K −1 as described above, if t1 / t2 exceeds 0.1, the heat of the circuit board 1 Resistance increases. In addition, the definition of the average thickness of the circuit board 1c and the coating layer 1f will be described in the section of an experimental example.

上記した被覆層１ｆの熱伝導率および熱膨張率の測定方法は、実験例の項で詳細に説明する。   The method for measuring the thermal conductivity and the thermal expansion coefficient of the coating layer 1f described above will be described in detail in the experimental section.

上記構成の回路基板１を利用し半導体装置を形成する場合には、図２（ｂ）に示すように、金属板１ｃに被覆された被覆層１ｆの表面に形成された半田層９ａを介し半導体素子９ｂを接合する。なお、図２（ｂ）中、符号９ｃは半田層９ａと回路板１ｃとの接合界面である。ここで、Ｗ、ＭｏまたはＣｒを主成分とする被覆層１ｆは、その表面に厚い酸化膜が生成され易く、接合工程において溶融した半田の濡れ性が低い。そのため、当該被覆層１ｆの表面に直接半田層を形成する場合には、例えば半導体素子の接合工程の前に酸化膜を除去する工程を設けたり、当該接合工程を還元雰囲気下で行うとよい。   In the case of forming a semiconductor device using the circuit board 1 having the above configuration, as shown in FIG. 2B, the semiconductor is interposed via the solder layer 9a formed on the surface of the covering layer 1f covered with the metal plate 1c. The element 9b is joined. In FIG. 2B, reference numeral 9c denotes a bonding interface between the solder layer 9a and the circuit board 1c. Here, the coating layer 1f containing W, Mo, or Cr as a main component easily forms a thick oxide film on the surface thereof, and the wettability of the solder melted in the joining process is low. Therefore, when the solder layer is directly formed on the surface of the covering layer 1f, for example, a step of removing the oxide film may be provided before the semiconductor element bonding step, or the bonding step may be performed in a reducing atmosphere.

そして、本態様の回路基板１によれば、−４０℃での冷却を５分、２５０℃での加熱を５分とする昇温／降温サイクルを１サイクルとし、これを３００回繰り返してセラミックス回路基板に付与する冷熱サイクル試験に回路基板１を付した前後における、ＪＩＳ Ｂ０６０１−２００１に準拠して測定した被覆層１ｆの表面粗さ（Ｒｚ）の差が、２０μｍ以下となる。そのため、冷熱サイクルに起因した熱負荷が回路基板１に作用した場合でも、図２（ｂ）に示す接合界面９ｃにおいてクラックが生じ難く、回路板１ｃに接合された半導体素子９ｂとの接合信頼性が確保される。   And according to the circuit board 1 of this aspect, the temperature rising / falling cycle in which the cooling at −40 ° C. is 5 minutes and the heating at 250 ° C. is 5 minutes is one cycle, and this is repeated 300 times. The difference in the surface roughness (Rz) of the coating layer 1f measured in accordance with JIS B0601-2001 before and after the circuit board 1 is attached to the thermal cycle test applied to the substrate is 20 μm or less. Therefore, even when a thermal load resulting from the cooling / heating cycle acts on the circuit board 1, cracks are unlikely to occur at the bonding interface 9c shown in FIG. 2B, and the bonding reliability with the semiconductor element 9b bonded to the circuit board 1c. Is secured.

［第１変形例］
第１態様の回路基板１の第１変形例に係る回路基板２について、その側断面図である図３を参照しつつ説明する。なお、図３において、上記第１態様の回路基板１と同一の構成要素については、同一符号を付しており、詳細な説明を省略する（第１態様の回路基板の第２変形例および第２態様の回路基板についても同様）。 [First Modification]
A circuit board 2 according to a first modification of the circuit board 1 of the first aspect will be described with reference to FIG. 3 which is a side sectional view thereof. In FIG. 3, the same components as those of the circuit board 1 of the first aspect are denoted by the same reference numerals, and detailed description thereof is omitted (a second modification of the circuit board of the first aspect and the first embodiment). The same applies to the circuit board of the second embodiment).

第１変形例の回路基板２は、図３に示すように、Ｗを主成分とする被覆層（以下、第１変形例の説明において第１被覆層と言う。）１ｆの表面に、例えばメッキ法で形成されたＮｉを主成分とする第２被覆層２ｇが積層した状態で被覆されている点で、第１態様の回路基板１と相違している。なお、第２被覆層２ｇはＮｉに限定されず、硬度・耐腐食性その他最表面に求められる特性を考慮し、例えばＰｂ、Ｓｎ、Ａｕを主成分とする第２被覆層２ｇとしてもよい。かかる第２被覆層２ｇは溶融した半田との濡れ性が高いので、半導体素子との接合性を高めることができる。   As shown in FIG. 3, the circuit board 2 of the first modification has, for example, plating on the surface of a coating layer containing W as a main component (hereinafter referred to as a first coating layer in the description of the first modification). This is different from the circuit board 1 of the first aspect in that the second covering layer 2g mainly composed of Ni is coated in a laminated state. Note that the second coating layer 2g is not limited to Ni, and may be, for example, the second coating layer 2g mainly composed of Pb, Sn, and Au in consideration of hardness / corrosion resistance and other characteristics required for the outermost surface. Since the second coating layer 2g has high wettability with the molten solder, it is possible to improve the bondability with the semiconductor element.

［第２変形例］
第１態様の回路基板１の第２変形例に係る回路基板３について、その側断面図である図４（ａ）、図４（ａ）の平面図である図４（ｂ）を参照しつつ説明する。なお、図４（ａ）・（ｂ）は、いずれも半導体素子９ｂが搭載された状態を示している。第２変形例の回路基板３の回路板１ｃは、図４（ａ）・（ｂ）に示すように、平面方向においてその表面の中央部に半導体素子９ｂが接合される接合部３ｈを有し、当該接合部３ｈの周囲に被覆層３ｆが形成されている点で、第１態様の回路基板１と相違している。なお、被覆層３ｆは、図４（ｂ）に実線で示すように、接合部３ｈの周囲に形成されていればよいが、破線で示すように接合部３ｈを包囲するように略環状に形成しておくことが好ましい。また、ろう材層１ｂを介し回路板１ｃに半導体素子９ｂを接合してもよいが、回路板１ｃの表面に例えばＮｉ等を主成分とする被覆層を形成しておき、ろう材層を介し被覆層に半導体素子９ｂを接合してもよい。かかる第２変形例の回路基板３によれば、接合部３ｈを設けることにより半導体素子９ｂと回路板１ｃとの接合性を確保できる。加えて、接合部３ｈの周囲に設けた被覆層３ｆにより、熱負荷が作用した場合でも、回路板１ｃを構成する組織レベルの微小変形が抑制され、その結果、半導体素子の接続信頼性を阻害する、回路板１ｃの表面の凹凸の形成が低減される。 [Second Modification]
The circuit board 3 according to the second modification of the circuit board 1 of the first aspect is shown in FIG. 4A, which is a side sectional view thereof, and FIG. 4B, which is a plan view of FIG. explain. 4A and 4B show a state where the semiconductor element 9b is mounted. As shown in FIGS. 4A and 4B, the circuit board 1c of the circuit board 3 according to the second modification has a joint 3h to which the semiconductor element 9b is joined at the center of the surface in the plane direction. The circuit board 1 is different from the circuit board 1 of the first aspect in that a covering layer 3f is formed around the joint 3h. The coating layer 3f only needs to be formed around the joint 3h as shown by a solid line in FIG. 4B, but is formed in a substantially annular shape so as to surround the joint 3h as shown by a broken line. It is preferable to keep it. The semiconductor element 9b may be joined to the circuit board 1c via the brazing material layer 1b. However, a coating layer mainly composed of Ni or the like is formed on the surface of the circuit board 1c, and the brazing material layer is interposed therebetween. The semiconductor element 9b may be bonded to the covering layer. According to the circuit board 3 of the second modified example, it is possible to secure the bonding property between the semiconductor element 9b and the circuit board 1c by providing the bonding portion 3h. In addition, the coating layer 3f provided around the joint 3h suppresses microdeformation at the tissue level that constitutes the circuit board 1c even when a thermal load is applied, thereby inhibiting the connection reliability of the semiconductor element. The formation of irregularities on the surface of the circuit board 1c is reduced.

［第２実施形態］
本発明の第２実施形態に係る回路基板４について、その側断面図である図５（ａ）、図５（ａ）を上方から見た平面図である図５（ｂ）、図５（ａ）のＡ部拡大図である図５（Ｃ）を参照しつつ説明する。図５に示すように、第２態様の回路基板４は、第１態様のＷを主成分とする被覆層１ｆに替え、金属を主成分とする第１相４ｉと、セラミックスを主成分とする第２相４ｊとで構成された被覆層４ｆを有する点で、第１態様の回路基板１と相違している。以下、第２態様の被覆層４ｆについて詳細に説明する。 [Second Embodiment]
5 (a), which is a side sectional view of the circuit board 4 according to the second embodiment of the present invention, and FIG. 5 (b), FIG. ) Will be described with reference to FIG. As shown in FIG. 5, in the circuit board 4 of the second mode, the first phase 4i containing metal as the main component and ceramics as the main component are used instead of the coating layer 1f containing W as the main component. The circuit board 1 is different from the circuit board 1 of the first mode in that the coating layer 4f includes the second phase 4j. Hereinafter, the coating layer 4f of the second aspect will be described in detail.

本態様の被覆層４ｆは、図５に示すように、回路板１ｃの上面に規則的なパターンで配置された直径がＣの略円板形状の第２相４ｊと、平面方向において複数の第２相４ｊの周囲を埋めるように配置された第１相４ｉとを有している。ここで、金属を主成分とする第１相４ｉは、被覆層４ｆにおいて所望の熱伝導率を確保するために配置され、セラミックスを主成分とする第２相４ｊは所望の熱膨張率を得るために配置される要素である。したがって、第２相４ｊの形状は上記に限定されず、その平面視は略矩形状、略三角形状、略楕円形状その他各種の形状とすることができ、被覆層４ｆの面積に対する面積比は４０〜８０％であることが好ましい。さらに、第２相４ｊは規則的なパターンで配置しなくてもよいが、回路板１ｃを構成する組織レベルの熱負荷による微小変形の均一化のためには、例えば平面方向において中心間距離Ｐが等しくなるよう規則的に配置することが望ましい。   As shown in FIG. 5, the covering layer 4 f of this aspect includes a substantially disc-shaped second phase 4 j having a diameter C arranged on the upper surface of the circuit board 1 c, and a plurality of first layers in the planar direction. The first phase 4i is arranged so as to fill the periphery of the two-phase 4j. Here, the first phase 4i whose main component is a metal is arranged to ensure a desired thermal conductivity in the coating layer 4f, and the second phase 4j whose main component is a ceramic obtains a desired thermal expansion coefficient. It is an element that is arranged for. Therefore, the shape of the second phase 4j is not limited to the above, and the plan view thereof can be a substantially rectangular shape, a substantially triangular shape, a substantially elliptical shape, or other various shapes, and the area ratio to the area of the coating layer 4f is 40. It is preferable that it is -80%. Further, the second phase 4j may not be arranged in a regular pattern. However, in order to make the micro deformation uniform due to the thermal load at the tissue level constituting the circuit board 1c, for example, the center distance P in the plane direction is used. It is desirable to arrange regularly so that is equal.

第１相４ｉを構成する金属としては、各種の金属を使用することができる。例えば、被覆層１ｆの低熱膨張性を重視する場合には、Ｗ、Ｍｏ、Ｃｒからなる群のうちから少なくとも一種の金属で第１相４ｉを構成すればよい。また、半導体素子との接合時における溶融半田との濡れ性を重視する場合には、Ｎｉ、Ｐｂ、ＳｎおよびＡｕからなる群のうちから少なくとも一種の金属で第１相４ｉを構成すればよい。さらに、被覆層４ｆの高熱伝導性を重視する場合には、例えばＣｕ、Ａｌ等の熱伝導率の高い金属で第１相４ｉを構成すればよい。   Various metals can be used as the metal constituting the first phase 4i. For example, when importance is attached to the low thermal expansion property of the coating layer 1f, the first phase 4i may be made of at least one metal from the group consisting of W, Mo, and Cr. In the case where the wettability with the molten solder at the time of joining with the semiconductor element is regarded as important, the first phase 4i may be composed of at least one metal from the group consisting of Ni, Pb, Sn and Au. Furthermore, when importance is attached to the high thermal conductivity of the coating layer 4f, the first phase 4i may be made of a metal having high thermal conductivity such as Cu or Al.

また、第２相４ｊを構成するセラミックスとしては、例えばアルミナ、ジルコニアその他酸化物系セラミックス、炭化珪素、炭化硼素その他炭化物系セラミックス、窒化珪素、サイアロン、窒化アルミニウム、窒化硼素その他窒化物系セラミックスなど各種のセラミックスを使用することができる。   Examples of the ceramic constituting the second phase 4j include various types such as alumina, zirconia and other oxide ceramics, silicon carbide, boron carbide and other carbide ceramics, silicon nitride, sialon, aluminum nitride, boron nitride and other nitride ceramics. The ceramics can be used.

この第２態様の被覆層４ｆは、常用される成膜法を利用して形成することができる。すなわち、まず、窒化珪素基板１ａの上面にろう材層１ｂを介して接合された回路板１ｃの上面に、第２相４ｊの形状・配置に対応したマスクキングを行い、その後スパッタリングにより所定の厚みの第２相４ｊを形成する。次いで、ＮｉやＰｂ等で第１相４ｉを形成する場合には、第２相４ｊが形成された回路板１ｃの表面に、そのままメッキ法で第１相４ｉを形成すればよい。また、Ｗ、Ｍｏ等で第１相４ｉを形成する場合には、回路板１ｃの表面に形成された第２相４ｊを覆うようにマスキングを行い、スパッタリングにより第１相４ｉを形成すればよい。   The coating layer 4f of the second aspect can be formed using a commonly used film forming method. That is, first, masking corresponding to the shape and arrangement of the second phase 4j is performed on the upper surface of the circuit board 1c joined to the upper surface of the silicon nitride substrate 1a via the brazing filler metal layer 1b, and then a predetermined thickness is obtained by sputtering. The second phase 4j is formed. Next, when the first phase 4i is formed of Ni, Pb, or the like, the first phase 4i may be formed as it is by plating on the surface of the circuit board 1c on which the second phase 4j is formed. When the first phase 4i is formed of W, Mo or the like, masking is performed so as to cover the second phase 4j formed on the surface of the circuit board 1c, and the first phase 4i may be formed by sputtering. .

上記のように構成された被覆層４ｆを有する第２態様の回路基板１でも、第１相４ｉおおよび第２相４ｊの構成を調整することにより、被覆層４ｆの熱伝導率は、９０〜１８０Ｗ・ｍ−１・Ｋ−１となる。さらに、被覆層４ｆの厚みをｔ１、回路板１ｃの厚みをｔ２としたとき、ｔ１／ｔ２は０．００５〜０．１の範囲である。このように、被覆層４ｆの第１相４ｉおよび第２相４ｊの構成を調整することにより、上記冷熱サイクル試験に付した前後の、ＪＩＳ Ｂ０６０１−２００１に準拠して測定した前記被覆層の表面粗さ（Ｒｚ）の差が、２０μｍ以下となる。その結果、冷熱サイクルに起因した熱負荷が作用した場合でも、回路板１ｃに接合された半導体素子の接続信頼性が確保される。 Even in the circuit board 1 of the second aspect having the coating layer 4f configured as described above, the thermal conductivity of the coating layer 4f is 90 to 90 by adjusting the configuration of the first phase 4i and the second phase 4j. 180 W · m −1 · K −1 . Furthermore, when the thickness of the coating layer 4f is t1 and the thickness of the circuit board 1c is t2, t1 / t2 is in the range of 0.005 to 0.1. Thus, the surface of the said coating layer measured based on JISB0601-2001 before and after having attached | subjected the said thermal cycle test by adjusting the structure of the 1st phase 4i and the 2nd phase 4j of the coating layer 4f. The difference in roughness (Rz) is 20 μm or less. As a result, the connection reliability of the semiconductor element bonded to the circuit board 1c is ensured even when a thermal load caused by the cooling / heating cycle is applied.

［実験例］
以下、本発明について、その実験例１〜１６に基づき具体的に説明するが、本発明は、当該実験例に限定されない。 [Experimental example]
Hereinafter, although this invention is demonstrated concretely based on the experiment examples 1-16, this invention is not limited to the said experiment example.

表１に示す熱膨張率を有する窒化珪素基板ならびに回路板および放熱板を準備した。なお、窒化珪素基板の熱伝導率は８０Ｗ・ｍ−１・Ｋ−１、曲げ強度は７００ＭＰａ、破壊靱性値は６．５ＭＰａ１／２のものを使用した。また、回路板および放熱板としては、ＪＩＳ Ｈ３１００ Ｃ１０２０Ｈで規定される熱伝導率が４００Ｗ・ｍ−１・Ｋ−１の無酸素銅を使用した。 A silicon nitride substrate having a thermal expansion coefficient shown in Table 1, a circuit board, and a heat sink were prepared. The silicon nitride substrate used had a thermal conductivity of 80 W · m −1 · K −1 , a bending strength of 700 MPa, and a fracture toughness value of 6.5 MPa ½ . Further, as the circuit board and the heat sink, oxygen-free copper having a thermal conductivity of 400 W · m −1 · K −1 stipulated by JIS H3100 C1020H was used.

各実験例ともに、窒化珪素基板の平面方向の寸法Ｌ１・Ｌ２（図２参照）は、各々３７×４７ｍｍとし、その厚みｔ３は０．３２ｍｍとした。また、回路板および放熱板の平面方向の寸法Ｌ３・Ｌ４は、いずれも３５×４５ｍｍとした。表１に示す、回路板および放熱板の平均厚みｔ２は、任意の１０点の厚みをマイクロメータで測定した値の平均値である。なお、いずれの実験例でも、回路板および放熱板は、平面方向において窒化珪素基板の中央部に配置した。   In each experimental example, the planar dimensions L1 and L2 (see FIG. 2) of the silicon nitride substrate were each 37 × 47 mm, and the thickness t3 was 0.32 mm. Further, the dimensions L3 and L4 in the planar direction of the circuit board and the heat radiating plate were both 35 × 45 mm. The average thickness t2 of the circuit board and the heat radiating plate shown in Table 1 is an average value of values obtained by measuring thicknesses of arbitrary 10 points with a micrometer. In any experimental example, the circuit board and the heat radiating plate were arranged in the center of the silicon nitride substrate in the planar direction.

各実験例ともに、窒化珪素基板の両面の回路板および放熱板の接合される領域に、４５μｍの厚みとなるようスクリーン印刷でろう材ペーストで塗布した。なお、ろう材ペーストの組成は、Ａｇ：７０質量％、Ｉｎ：３質量％、残部Ｃｕ及び不可避不純物からなる５０％累積粒子径（ｄ５０）２０μｍの合金粉末と、前記合金粉末１００質量部に対し、５０％累積粒子径（ｄ５０）１０μｍのＡｇ粉末粒子を１０質量部、５０％累積粒子径（ｄ５０）が１５μｍの水素化チタン粉末を、１質量部を有するろう材粉末に対し、バインダーを５質量％、溶剤を１０質量％添加し、混練したろう材ペーストである。   In each experimental example, a solder paste was applied by screen printing to a region where the circuit board and the heat radiating plate on both sides of the silicon nitride substrate were bonded to each other to a thickness of 45 μm. The composition of the brazing material paste is as follows: Ag: 70% by mass, In: 3% by mass, 50% cumulative particle diameter (d50) 20 μm composed of the balance Cu and inevitable impurities, and 100 parts by mass of the alloy powder. 10 parts by weight of Ag powder particles having a 50% cumulative particle diameter (d50) of 10 μm, and 5 parts of binder for 5 parts of titanium hydride powder having a 50% cumulative particle diameter (d50) of 15 μm. It is a brazing material paste added with 10% by mass and 10% by mass of a solvent.

上記ろう材ペーストが印刷された窒化珪素基板に回路板および放熱板を載置し、接合炉に収納し、加熱・冷却し、窒化珪素基板と回路板・放熱板を接合した。なお、接合炉は、３８０℃の温度で１２時間保持し、１０℃／分の昇温速度で昇温し、炉内圧力が１Ｐａ以下となるよう制御しつつ５８０℃の温度で１０時間保持し、１０℃／分の昇温速度で昇温し、炉内圧力が５×１０−３Ｐａ以下となるよう制御しつつ８３５℃の温度で１時間保持し、その後、冷却速度３℃／分にて冷却するよう制御した。 The circuit board and the heat radiating plate were placed on the silicon nitride substrate on which the brazing paste was printed, housed in a joining furnace, heated and cooled, and the silicon nitride substrate and the circuit board / heat radiating plate were joined. The bonding furnace is held at a temperature of 380 ° C. for 12 hours, heated at a rate of temperature increase of 10 ° C./min, and maintained at a temperature of 580 ° C. for 10 hours while controlling the pressure in the furnace to be 1 Pa or less. The temperature is raised at a rate of 10 ° C./min, and the pressure inside the furnace is controlled to be 5 × 10 −3 Pa or less, and maintained at a temperature of 835 ° C. for 1 hour, and then the cooling rate is 3 ° C./min And controlled to cool.

窒化珪素基板の表面に接合された回路板・放熱板の表面を例えば化学研磨等により処理して、表面の異物等を除去した後、各実験例ごとに表１に示す組成および厚みの被覆層を有する回路基板を形成した。なお、表１において実施形態の欄には、上記説明した図２・４・５の回路基板のいずれに該当するかを示している。実験例１４の回路基板は、その回路板の表面に被覆層を設けなかった。   After the surface of the circuit board / heat sink bonded to the surface of the silicon nitride substrate is treated by, for example, chemical polishing to remove foreign matters on the surface, the coating layer having the composition and thickness shown in Table 1 for each experimental example A circuit board having was formed. In Table 1, the column of the embodiment indicates which of the above-described circuit boards of FIGS. The circuit board of Experimental Example 14 did not have a coating layer on the surface of the circuit board.

ここで、実験例１〜１１および実験例１５・１６の被覆層は、図２を参照して説明した第１態様の被覆層１ｆであり、回路板の表面の全てに設けた。そして、実験例１〜６、実験例８〜１２および実験例１５のＷまたはＭｏからなる被覆層１ｆはスパッタリングで形成し、実験例７のＣｒおよび実験例１６のニッケルリンからなる被覆層１ｆはメッキで形成した。また、実験例１２の被覆層は、図４を参照して説明した第１態様の第２変形例の被覆層３ｆであり、Ｗを主体とする被覆層３ｆを回路板１ｃの接合部３ｈの周囲に設けた。そして、実験例１２では、図４に示す被覆層３ｆの平面方向の寸法は、Ｌ７が３５ｍｍ、Ｌ８が３３ｍｍ、Ｌ９が２ｍｍ、Ｌ１０が５ｍｍ、Ｌ１１が３１ｍｍとした。   Here, the coating layers of Experimental Examples 1 to 11 and Experimental Examples 15 and 16 are the coating layers 1f of the first aspect described with reference to FIG. 2 and provided on the entire surface of the circuit board. And the coating layer 1f which consists of W or Mo of Experimental example 1-6, Experimental example 8-12 and Experimental example 15 is formed by sputtering, The coating layer 1f which consists of Cr of Experimental example 7 and nickel phosphorus of Experimental example 16 is It was formed by plating. Further, the coating layer of Experimental Example 12 is the coating layer 3f of the second modified example of the first mode described with reference to FIG. 4, and the coating layer 3f mainly composed of W is connected to the joint 3h of the circuit board 1c. Provided around. In Experimental Example 12, the dimensions in the planar direction of the covering layer 3f shown in FIG. 4 were L7: 35 mm, L8: 33 mm, L9: 2 mm, L10: 5 mm, and L11: 31 mm.

実験例１３の被覆層は、図５を参照して説明した第２態様の被覆層４ｆであり、回路板の表面の全てに設けた。この第１相４ｉおよび第２相４ｊを有する被覆層４ｆは、次のように形成した。すなわち、図５に示すように、回路板１ｃの表面積に対する第２相４ｊの面積率が５０％となるよう、平面方向において中心間距離Ｐが０．５ｍｍで配置された直径Ｃが０．４ｍｍの第２相４ｊに対応する開口部が形成されたステンレス製のマスクを回路板１ｃの表面に載置し、次いでスパッタリングでＡｌＮからなる第２相４ｊを形成した。第２相４ｉが形成された回路板１ｃの表面をＰｄ処理し、その後無電解Ａｕメッキを行うことにより、第２相４ｊの周囲を埋めるようにＡｕを主体とした第１相４ｉを形成した。なお、各実験例ともに形成された被覆層（実験例１４は回路板）のＪＩＳ Ｂ０６０１−２００１に準拠して測定した表面粗さの値は、いずれも８〜１５μｍの範囲であった。   The coating layer of Experimental Example 13 was the coating layer 4f according to the second embodiment described with reference to FIG. 5 and was provided on the entire surface of the circuit board. The covering layer 4f having the first phase 4i and the second phase 4j was formed as follows. That is, as shown in FIG. 5, the diameter C arranged at a center-to-center distance P of 0.5 mm in the plane direction is 0.4 mm so that the area ratio of the second phase 4j to the surface area of the circuit board 1c is 50%. A stainless steel mask having openings corresponding to the second phase 4j was placed on the surface of the circuit board 1c, and then the second phase 4j made of AlN was formed by sputtering. The surface of the circuit board 1c on which the second phase 4i is formed is Pd-treated, and then electroless Au plating is performed to form the first phase 4i mainly composed of Au so as to fill the periphery of the second phase 4j. . In addition, the value of the surface roughness measured based on JIS B0601-2001 of the coating layer (Experimental example 14 is a circuit board) formed with each experimental example was all in the range of 8 to 15 μm.

表１に示す被覆層の平均厚みｔ１ならびにその熱伝導率および熱膨張率α１は、次のようにして求めた。まず、被覆層の平均厚みｔ１は、各実験例毎に、上記説明した条件と同一の条件で試験片を作成し、当該試験片の任意の断面について光学顕微鏡で観察し、当該断面の任意の１０ヶ所の被覆層の厚みを求め、得られた値の平均値を被覆層の平均厚みとした。   The average thickness t1 of the coating layer shown in Table 1 and its thermal conductivity and thermal expansion coefficient α1 were determined as follows. First, the average thickness t1 of the coating layer is prepared for each experimental example under the same conditions as described above, and an arbitrary cross section of the test piece is observed with an optical microscope. The thicknesses of the 10 coating layers were determined, and the average value obtained was taken as the average thickness of the coating layer.

被覆層の熱伝導率は、厚さが０．２ｍｍ、幅３ｍｍ、長さが３０ｍｍのガラス基板の表面に被覆層を形成した試験片を作成し、当該試験片をスキャニングレーザー加熱法により測定することにより求めた。また、被覆層の熱膨張率は、上記試験片の被覆層に歪ゲージを設置し、−４０℃〜２５０℃の範囲で温度を変化させつつ求めた歪値より算出した。   The thermal conductivity of the coating layer is measured by preparing a test piece in which a coating layer is formed on the surface of a glass substrate having a thickness of 0.2 mm, a width of 3 mm, and a length of 30 mm, and scanning the heating test piece. Was determined by Moreover, the thermal expansion coefficient of the coating layer was calculated from the strain value obtained by installing a strain gauge on the coating layer of the test piece and changing the temperature in the range of −40 ° C. to 250 ° C.

Figure 2014063798
Figure 2014063798

各実験例で作成された回路基板の厚み方向の熱伝導率を、レーザフラッシュ法で確認した。その結果を表２に示す。   The thermal conductivity in the thickness direction of the circuit board prepared in each experimental example was confirmed by a laser flash method. The results are shown in Table 2.

各実験例で作成された回路基板を、−４０℃での冷却を５分、２５０℃での加熱を５分とする昇温／降温サイクルを１サイクルとし、これを３００回繰り返して付与する冷熱サイクル試験に付した。冷熱サイクル試験前および試験後における、ＪＩＳ Ｂ０６０１−２９９１に準拠して測定した前記被覆層の表面粗さ（Ｒｚ）の差の値を表２に示す。なお、被覆層を形成しなかった実験例１４の数値は、回路板の表面粗さである。   Cooling heat applied to the circuit board prepared in each experimental example by repeating it 300 times, with a temperature rising / falling cycle of cooling at −40 ° C. for 5 minutes and heating at 250 ° C. for 5 minutes as one cycle. It was subjected to a cycle test. Table 2 shows values of the difference in surface roughness (Rz) of the coating layer measured in accordance with JIS B0601-2991 before and after the thermal cycle test. In addition, the numerical value of the experiment example 14 which did not form a coating layer is the surface roughness of a circuit board.

次いで、各実験例で作成された回路基板であって、上記冷熱サイクル試験に付さない回路基板の平面方向において被覆層の中央部に、２００μｍの厚みの半田層を介し、半導体装置に擬したシリコン片を水素雰囲気下で接合した。使用した半田は、Ａｇ：５質量％、Ｃｕ：０．５質量％、残部Ｓｎおよび不純物からなる半田である。また、半導体装置に擬したシリコン片の熱膨張率は２．８×１０−６／Ｋであり、その平面方向の寸法Ｌ５・Ｌ６（図２参照）は、各々２５×２５ｍｍ、厚みｔ４は０．３ｍｍとした。なお、被覆層を形成しなかった実験例１４では、回路板１ｃの表面に半田層を介しシリコン片を接合した。 Next, a circuit board produced in each experimental example, which was simulated in a semiconductor device through a solder layer having a thickness of 200 μm at the center of the coating layer in the plane direction of the circuit board not subjected to the above-described thermal cycle test. Silicon pieces were joined in a hydrogen atmosphere. The used solder is a solder composed of Ag: 5% by mass, Cu: 0.5% by mass, the remainder Sn and impurities. Moreover, the thermal expansion coefficient of the silicon piece mimicking the semiconductor device is 2.8 × 10 −6 / K, the plane direction dimensions L5 and L6 (see FIG. 2) are each 25 × 25 mm, and the thickness t4 is 0. 3 mm. In Experimental Example 14 in which the coating layer was not formed, a silicon piece was bonded to the surface of the circuit board 1c via a solder layer.

上記シリコン片が接合された回路基板に、−４０℃での冷却を５分、２５０℃での加熱を５分とする昇温／降温サイクルを１サイクルとし、これを３００回繰り返して付与する冷熱サイクル試験に付した。冷熱サイクル試験に付した各実験例の回路基板を溶媒中に浸漬し、超音波探傷装置（日立建機製、Ｍｉ−ｓｃｏｐｅ、周波数：５０ＭＨｚ）で、半田層と被覆層（実験例１４では半田層と回路板）との接合界面に発生した剥離の有無を確認した。その結果を表２に示す。   Cooling heat applied to the circuit board to which the above silicon pieces are bonded by repeating the heating / cooling cycle of -40 ° C. for 5 minutes and heating at 250 ° C. for 5 minutes as one cycle. It was subjected to a cycle test. The circuit board of each experimental example subjected to the thermal cycle test was immersed in a solvent, and an ultrasonic flaw detector (manufactured by Hitachi Construction Machinery, Mi-scope, frequency: 50 MHz) was used to solder and cover layers (in the experimental example 14, the solder layer). The presence or absence of delamination that occurred at the bonding interface between the circuit board and the circuit board was confirmed. The results are shown in Table 2.

Figure 2014063798
Figure 2014063798

実験例１〜１６によれば、以下のことが確認された。本発明の範囲である実験例１〜１３の回路基板は、冷熱サイクル試験前後の被覆層の表面粗さの差が２０μｍ以下となり、その結果、半導体装置に擬したシリコン片を接合している半田層と被覆層との接合界面の剥離は発生しなかった。また、回路基板の熱伝導率も２００Ｗ・ｍ−１・Ｋ−１以上となり、回路基板の熱抵抗も適正な範囲であった。 According to Experimental Examples 1 to 16, the following was confirmed. In the circuit boards of Experimental Examples 1 to 13, which are within the scope of the present invention, the difference in the surface roughness of the coating layer before and after the thermal cycle test is 20 μm or less, and as a result, the solder joining the simulated silicon piece to the semiconductor device Separation of the bonding interface between the layer and the coating layer did not occur. Further, the thermal conductivity of the circuit board was 200 W · m −1 · K −1 or more, and the thermal resistance of the circuit board was in an appropriate range.

一方で、回路板の表面に被覆層を形成しなかった実験例１３の回路基板では、熱抵抗は低いものの、冷熱サイクル試験前後の被覆層の表面粗さの差が３５μｍとなり、その結果、半田層と被覆層との接合界面の剥離が生じた。また、被覆層の厚い実験例１４の回路基板では、冷熱サイクル試験前後の被覆層の表面粗さの差は９μｍであり、半田層と被覆層との接合界面の剥離は生じなかったものの、熱抵抗が大きかった。さらに、熱膨張率が大きいニッケルリンで形成した被覆膜を有する実験例１６の回路基板では、冷熱サイクル試験前後の被覆層の表面粗さの差が２５μｍとなり、その結果、半田層と被覆層との接合界面の剥離が生じた。さらに、この実験例１６の被覆膜は熱伝導率も低いため、熱抵抗も大きかった。   On the other hand, in the circuit board of Experimental Example 13 in which the coating layer was not formed on the surface of the circuit board, although the thermal resistance was low, the difference in the surface roughness of the coating layer before and after the thermal cycle test was 35 μm. Separation of the bonding interface between the layer and the coating layer occurred. Further, in the circuit board of Experimental Example 14 having a thick coating layer, the difference in the surface roughness of the coating layer before and after the thermal cycle test was 9 μm, and peeling of the bonding interface between the solder layer and the coating layer did not occur. The resistance was great. Furthermore, in the circuit board of Experimental Example 16 having the coating film formed of nickel phosphorus having a high coefficient of thermal expansion, the difference in surface roughness of the coating layer before and after the thermal cycle test was 25 μm, and as a result, the solder layer and the coating layer Separation of the bonding interface with. Furthermore, since the coating film of Experimental Example 16 had a low thermal conductivity, the thermal resistance was also large.

１（２〜４、１０） セラミックス回路基板
１ａ（１０ａ） 窒化珪素基板
１ｂ（１０ｂ） ろう材層
１ｃ（１０ｃ） 回路板（金属板）
１ｄ（１０ｄ） ろう材層
１ｅ（１０ｅ） 放熱板（金属板）
１ｆ（３ｆ、４ｆ） 被覆層
４ｉ 第１相
４ｊ 第２相
９ａ（１１ａ） 半田層
９ｂ（１１ｂ） 半導体装置
９ｃ 接合界面 1 (2-4, 10) Ceramic circuit board 1a (10a) Silicon nitride substrate 1b (10b) Brazing material layer 1c (10c) Circuit board (metal plate)
1d (10d) Brazing material layer 1e (10e) Heat sink (metal plate)
1f (3f, 4f) Cover layer 4i First phase 4j Second phase 9a (11a) Solder layer 9b (11b) Semiconductor device 9c Junction interface

Claims (4)

窒化珪素焼結体からなるセラミックス基板と、前記セラミックス基板に接合された銅を主成分とする金属板と、前記金属板の表面に設けられた被覆層とを有するセラミックス回路基板であって、
ＪＩＳ Ｚ２２８５準拠して測定した、−４０〜２５０℃における前記セラミックス基板の熱膨張率が、２〜４×１０−６／Ｋであり、前記被覆層を除いた前記金属板の熱膨張率が、１６〜１８×１０−６／Ｋであり、
前記被覆層は、Ｍｏ、Ｗ、Ｃｒからなる群のうち少なくとも一種を主体とし、
室温における前記被覆層の熱伝導率は、９０〜１８０Ｗ・ｍ−１・Ｋ−１であり、
前記被覆層の平均厚みをｔ１、前記金属板の平均厚みをｔ２としたとき、ｔ１／ｔ２が０．００５〜０．１の範囲であるセラミックス回路基板。 A ceramic circuit board having a ceramic substrate made of a silicon nitride sintered body, a metal plate mainly composed of copper bonded to the ceramic substrate, and a coating layer provided on the surface of the metal plate,
The thermal expansion coefficient of the ceramic substrate at −40 to 250 ° C. measured in accordance with JIS Z2285 is 2 to 4 × 10 −6 / K, and the thermal expansion coefficient of the metal plate excluding the coating layer is 16-18 × 10 −6 / K,
The coating layer is mainly composed of at least one of the group consisting of Mo, W, and Cr,
The thermal conductivity of the coating layer at room temperature is 90 to 180 W · m −1 · K −1 ,
A ceramic circuit board in which t1 / t2 is in the range of 0.005 to 0.1, where t1 is an average thickness of the coating layer and t2 is an average thickness of the metal plate. 前記被覆層は、Ｍｏ、Ｗ、Ｃｒからなる群のうち少なくとも一種に替え、金属を主成分とする第１相と、セラミックスを主成分とする第２相を有する請求項１に記載のセラミックス回路基板。   2. The ceramic circuit according to claim 1, wherein the coating layer has at least one kind selected from the group consisting of Mo, W, and Cr, and has a first phase mainly composed of metal and a second phase mainly composed of ceramic. substrate. −４０〜２５０℃における前記被覆層の熱膨張率をα１、前記金属板の熱膨張率をα２としたとき、α１／α２が０．１〜０．７である請求項１または２のいずれかに記載のセラミックス回路基板。   The α1 / α2 is 0.1 to 0.7, where α1 is the thermal expansion coefficient of the coating layer at −40 to 250 ° C., and α2 is the thermal expansion coefficient of the metal plate. The ceramic circuit board according to 1. 前記金属板は、半導体素子が接合される接合部を有し、前記被覆層は、前記接合部の周囲に設けられている請求項１乃至３のいずれかに記載のセラミックス回路基板。   The ceramic circuit board according to any one of claims 1 to 3, wherein the metal plate has a joint portion to which a semiconductor element is joined, and the covering layer is provided around the joint portion.
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