JP2014063278A - Synchronous processing circuit and synchronous processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous processing circuit capable of performing not only entire synchronous processing but also partial synchronous processing with a simple hardware mechanism.SOLUTION: The synchronous processing circuit performs a partial or entire synchronous processing of plural processing means using tree-structured plural nodes. The tree-structured nodes include: plural leaf nodes 3 positioned at the bottom each corresponding to the plural processing means; a root node 7 positioned at the top; and plural internal nodes 5 other than the root node 7 and the leaf nodes 3. The tree structure notifies a logical value not only from a child node to a parent node but also from the parent node to the child node. Each internal node 5 includes an internal node selection section that selects whether a logical value obtained by performing a logical operation on a logical value which is notified from a child node of the internal node 5 should be notified to the parent node, or a NOT logical value notified from the parent node should be notified.

Description

  The present invention relates to a synchronization processing circuit and a synchronization processing method, and more particularly, to a synchronization processing circuit that determines a synchronization state of some or all of a plurality of processing means by a tree structure.

  With advances in process technology, hardware technology, software technology, etc., multi-core processors having multiple processor cores (hereinafter abbreviated as “cores”) on a chip have become widespread. In addition, many-core processors with more cores are also being researched. For example, there are commercial chips with 100 cores.

  In many-core processors, etc., in order to achieve high effective performance, it is necessary to be able to utilize parallelism that is commensurate with the number of installed cores. For example, in the case where extremely high parallelism is inherent, such as in image processing and scientific and technological calculations, the operating rate of the core can be increased. However, there are many cases where sufficient parallelism cannot be extracted. Therefore, in order to expand the application range of the many-core processor and to spread it, not only in-program parallelism but also inter-program parallelism must be actively utilized. That is, in the many-core processor, it is extremely important to realize an efficient multithread / multiprogram execution environment. Specifically, an embedded system in which a plurality of software such as an OS, mail, a game, and a compiler operate simultaneously, and a data center server application in which a plurality of users submit different jobs can be considered.

  One of the challenges in simultaneously executing a plurality of parallel programs is to increase the efficiency of synchronization processing between cores. Synchronization is necessary to keep pace between cores. For example, it is executed when an access order is determined when a plurality of cores use a common resource such as a memory or a bus, or when a plurality of cores want to start operation simultaneously. Here, a set of cores participating in a certain synchronization is called a core group. In general, the number of cores used for execution of a parallelized program greatly depends on the degree of parallelism inherent in the program. In addition, in a situation where a plurality of programs are executed simultaneously, each of the plurality of core groups may issue a synchronization process. Therefore, in the many-core processor, it is necessary to realize a synchronization mechanism that can be executed independently and in parallel for a plurality of various core groups.

  One of the typical synchronization methods is barrier synchronization. This is a technique for realizing synchronization by embedding an instruction to stop until all target cores give permission in a program executed by each core to be synchronized. Barrier synchronization is implemented in many parallel computing environments such as MPI, OpenMP, and pthread. Barrier synchronization can generally be realized without the addition of dedicated hardware.

  In a large-scale system used in the HPC field, a hardware barrier mechanism is often implemented. For example, a large-scale system has a hardware barrier function that is smaller and faster than the system (see Non-Patent Documents 1 to 3). Patent Documents 1 and 2 implement synchronization and the like using a tree network structure.

  Research on on-chip multi-core and many-core processors has also been conducted (see Non-Patent Documents 4 to 6). Villa et al. (See Non-Patent Document 4) increase the barrier speed by adding a circuit to NoC for inter-core data communication. Ito et al. (See non-patent document 5) and Hoeer et al. (See non-patent document 6) perform barrier synchronization using a dedicated network. (

JP-T-2004-529414 JP-T-2004-536372

Gara, A., 13 others, Overview of the Blue Gene / L system architecture, IBM Journal of Research and Development, Vol. 49, No. 2, pp.195-212, 2005. Habata, S., 3 others, Hardware system of the Earth Simulator, Parallel Computing, Vol. 30, no. 12, pp.1287-1313, 2004. Ajima, Y., 2 others, Tofu: A 6d mesh / torus interconnect for exascale computers, Computer, Vol. 42, no. 11, pp.36-40, 2009. Villa, O., 2 others, Efficiency and scalability of barrier synchronization on NoC based many-core architectures, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems (Altman, E., ed.), Atlanta, GA, USA, ACM, ACM, pp.81-90, 2008. Ito, M., 16 others, An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler, 2008 IEEE International Solid-State Circuits Conference Digest of Technical Papers (Fujino, LC, ed. ), San Francisco, CA, IEEE, S Digital Publishing Inc, pp. 90-598, 2008. Hoefler, T., 3 others, Adding Low-Cost Hardware Barrier Support to Small Commodity Clusters, 19th International Conference on Architecture and Computing Systems -ARCS06, pp.343-350, 2006.

  However, barrier synchronization increases the time required for barrier synchronization when a large number of cores participate, and if it is frequently used, it causes a decrease in software execution performance. Furthermore, there is a problem that a large variation occurs in the barrier processing completion time of each core, and the prior tuning is not reflected as expected.

  Therefore, a hardware barrier mechanism is often implemented in a large-scale system used in the HPC field. However, the hardware barrier mechanism in a large-scale system (see Non-Patent Documents 1 to 3, Patent Documents 1 and 2) is premised on the existence of a multifunctional network controller that controls a long-distance network connecting between bodies and chips. Designed as Therefore, the circuit scale is large and it is difficult to use it as it is as a hardware barrier of a many-core processor. In a large-scale system, a network used for a hardware barrier is shared with other communication functions for the purpose of reducing wiring costs. For this reason, it is not always possible to expect barrier synchronization execution with the shortest latency.

  The method of Villa et al. (See Non-Patent Document 4) shares a network with data. Therefore, the latency of barrier synchronization is not fixed. None of the methods of Ito et al. (See Non-Patent Document 5) and Hoefler et al. (See Non-Patent Document 6) have a function of grouping cores in a network by a hardware circuit.

  Therefore, the present invention has an object of proposing a synchronization processing circuit and the like that can be realized by a simple hardware mechanism and that can realize synchronization processing not only as a whole but also partially.

  A first aspect of the present invention is a synchronization processing circuit that performs a synchronization process on a part or all of a plurality of processing means using a plurality of nodes in a tree structure, and the nodes in the tree structure are arranged at the lowest order. A plurality of leaf nodes that respectively correspond to the plurality of processing means, a root node that is positioned at the highest level, and a plurality of internal nodes other than the root node and the leaf node; In addition to notifying the logical value from the node to the parent node, the logical value is also notified from the parent node to the child node, and each internal node notifies the parent node of the internal node. Provided with an internal node selection means for selecting whether to notify a logical value obtained by performing a logical operation on a logical value notified from a child node or to notify a negative logical value notified from the parent node A.

  A second aspect of the present invention is the synchronous processing circuit according to the first aspect, wherein each leaf node is a parent node and whether or not the processing means corresponding to the leaf node has reached a synchronization point. Or a leaf node selection means for selecting whether to notify the negation of the logical value notified from the parent node.

  A third aspect of the present invention is a synchronous processing circuit according to the second aspect, wherein the synchronous processing circuit makes a state transition between a barrier completion waiting / acceptable state and a barrier completion notification waiting state. The leaf node for notifying the logical value indicating whether or not the corresponding processing means has reached the synchronization point is in response to the parent node in the barrier completion waiting / accepting state. The synchronous state logical value is notified as a logical value indicating that the synchronization point has been reached, the asynchronous state logical value different from the synchronous state logical value is notified as the logical value indicating that the synchronization point has not been reached, and the barrier completion When the synchronous processing logical value is notified from the parent node in the notification waiting state, the asynchronous logical state value is notified, and is notified from the root node and the parent node. The internal node that notifies the negation of the logical value is in the state of waiting for barrier completion / acceptance, and when all the child nodes notify the synchronous state logical value, Notifying, transitioning to the barrier completion notification waiting state, and transitioning to the barrier completion waiting / acceptable state when the asynchronous state logical value is notified from all the child nodes in the barrier completion notification waiting state Is.

  According to a fourth aspect of the present invention, there is provided a synchronization processing circuit according to the second or third aspect, wherein the return storage means stores information indicating whether or not the internal nodes are to be returned, and the leaf nodes. A mask storage means for storing information indicating whether or not to perform masking, and a process in which each leaf node corresponds to the leaf node according to the information stored in the mask storage means with respect to the parent node. Each of the internal nodes comprises a leaf node selecting means for selecting whether to notify a logical value indicating whether the means has reached a synchronization point, or to notify a negative logical value notified from the parent node. The internal node selecting means selects the information according to the information stored in the return storage means, and the root node performs a logical operation on the logical value notified from the child node of the internal node to the child node. Obtained and notifies the logical value.

  A fifth aspect of the present invention is a synchronization processing circuit according to any one of the first to fourth aspects, wherein there are a plurality of the tree structures, and each tree structure is synchronized independently of other tree structures. The processing is performed.

  A sixth aspect of the present invention is a synchronization processing circuit according to any one of the first to fifth aspects, wherein each internal node is configured to synchronize a configuration change process for dynamically changing the configuration of the tree structure. The configuration change processing synchronization mechanism sends a synchronization request to the parent node when the own node and all the child nodes are requesting synchronization to the parent node, and from any child node to the child node When a synchronization request is made to the parent node during the synchronization request and is not completed, a logical value indicating that the synchronization is not completed is sent, and otherwise a different logical value is sent.

  According to a seventh aspect of the present invention, there is provided a synchronization processing method in a synchronization processing circuit that performs a synchronization process for a part or all of a plurality of processing means using a plurality of nodes in a tree structure. Not only notifies the logical value from the parent node to the parent node, but also notifies the logical value from the parent node to the child node. An internal node in which a node and a child node exist notifies the parent node of a logical value obtained by performing a logical operation on the logical value notified from the child node of the internal node, or the parent node This includes a selection step for selecting whether to notify the negation of the logical value notified from.

  Note that the node is a hardware module, and the logical operations in the root node and the internal node are in the barrier completion waiting / acceptance state. For example, all the logical values notified from the child nodes have reached the synchronization point. If it is a value indicating a thing, it is a logical value indicating that the synchronization point has been reached, otherwise it is a different logical value. As a result, the internal node that is not set to return notifies the parent node that all the child nodes of the internal node in the core group have reached the synchronization point. Then, the internal node for which the root node and the loopback setting are set determines that the processing in the processing means in the core group has reached the synchronization point, sends a synchronization processing completion notification signal to each leaf node, and completes the barrier It is possible to transition to a notification waiting state. In the barrier completion notification waiting state, for example, if all the logical values notified from the leaf node are logical values indicating that the synchronous setting register of the leaf node has been reset, the synchronous setting register of the leaf node is reset. It is a logical value indicating that it has been performed, and otherwise a different logical value. As a result, the internal node for which the root node and the loopback setting are set can determine that all the synchronization setting registers of the processing means in the core group have been reset, and transition to the barrier completion waiting / acceptable state.

  In addition, the logical value obtained by the logical operation in the root node and the internal node is set as the state of the respective root node and internal node, and the state of the latest parent node is stored in the internal node and the leaf node. May be provided to notify the negation of the logical value stored in the parent node state storage means when performing folding or masking.

  In the synchronous processing circuit according to the third aspect, the internal node that notifies the logical value obtained by performing a logical operation on the logical value notified from the child node, waits for the barrier completion / In the acceptable state, when all the child nodes notify the synchronous state logical value, the synchronous state logical value is notified, and when any of the child nodes notifies the asynchronous state logical value, the asynchronous state A logical value is notified, and when all the child nodes notify the asynchronous state logical value in the barrier completion notification waiting state, the asynchronous state logical value is notified, and any one of the child nodes is notified. Notifies the synchronous state logical value when the synchronous state logical value is notified, and an internal node that notifies the negative of the logical value notified from the root node and the parent node. In the barrier completion waiting / acceptable state, when any of the child nodes notifies the asynchronous state logical value, the asynchronous state logical value is notified to the child node, and all the child nodes When notifying the synchronization state logical value, the child node is notified of the synchronization state logical value, transitioned to the barrier completion notification wait state, and any of the child nodes in the barrier completion notification wait state Notifies the synchronous state logical value to the child node, and notifies all the child nodes to the asynchronous state logical value when all the child nodes notify the asynchronous logical state value. An asynchronous state logical value may be notified, and the state may transition to the barrier completion wait / acceptable state.

  According to each aspect of the present invention, a simple structure in which a plurality of nodes are connected to a tree structure enables a hardware barrier free from small-scale, small latency, and variation. Furthermore, the barrier network can be divided by simple function addition (for example, folding or a mask from the third viewpoint). Furthermore, by implementing a plurality of barrier circuits (multiplexing from the fifth viewpoint), it becomes possible to give flexibility to combinations of cores participating in the barrier. Therefore, it is possible to realize a flexible hardware barrier mechanism that can be applied to a many-core processor that may operate various processes. Furthermore, as in the sixth aspect, the tree structure applies a synchronization mechanism, and each node is distributed to check whether the configuration change has been performed on all nodes, and the configuration is dynamically changed. Can be realized. Note that for a synchronized subtree network that does not require a configuration change, it is possible to continue the current barrier synchronization process by performing a new setting with the same setting. Therefore, a new barrier group can be dynamically generated in the barrier network by this function.

  For example, Patent Documents 1 and 2 describe that synchronization and the like are realized using a tree network structure. However, it can be evaluated that, for example, it uses a pulse signal or the like and does not return from above. In each aspect of the present invention, technical features are recognized by folding from above.

It is a block diagram which shows the outline | summary of an example of the synchronous processing circuit which concerns on this invention. It is a figure which shows an example of the hardware constitutions of the leaf node 3 of FIG. It is a figure which shows the state transition of the barrier mechanism proposed. It is a figure which shows an example of the hardware constitutions of the internal node 5 of FIG. Eight leaf nodes 41 _1, ..., is a diagram showing an example in which divided into four barrier network with 41 _8. It is a figure which shows an example of the state transition of a barrier mechanism. FIG. 5 is a diagram illustrating a hardware configuration that is an example of a synchronization circuit 31 in the internal node 5 of FIG. 4. It is a figure which shows the example divided into two groups using two barrier networks which consist of 8 nodes. It is a figure which shows an example of the structure change process synchronization mechanism of the leaf node for implement | achieving a dynamic structure change. It is a figure which shows an example of the structure change process synchronization mechanism of the internal node for implement | achieving a dynamic structure change. It is a figure which shows allocation of the core which performs a structure change of a node in experiment. It is a figure which shows the program for evaluation used in order to measure barrier synchronous time in experiment. It is a figure which shows the measuring object in experiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to this embodiment.

  FIG. 1 is a block diagram showing an outline of an example of a synchronization processing circuit according to the present invention. With reference to FIG. 1, the basic structure and operation of a hardware barrier mechanism (hereinafter abbreviated as “barrier mechanism”) according to the present invention will be described.

  In this embodiment, a fixed core group is targeted. In order to realize the barrier mechanism of this embodiment, the following hardware elements are required.

A two-way binary tree network dedicated to barriers is called a barrier network. FIG. 1 shows an example in which a core group is configured with four cores. Cores 1 ₁ ,..., 1 ₄ (hereinafter, the subscripts may be omitted when referring to plural (or any of plural ones)) are referred to as processor cores (abbreviated as “cores”). (An example of “processing means” in the claims of the present application). In FIG. 1, four cases are shown as examples.

The synchronization processing circuit includes a leaf node 3 (an example of “leaf node” in the claims), an internal node 5 (an example of “internal node” in the claims), and a root node 7 (“root node” in the claims). ), Folding storage units 9 ₁ , 9 ₂ (an example of “folding storage means” in claims of this application), and mask storage units 11 ₁ ,..., 11 ₄ (“mask storage means” in claims of this application). An example).

  The leaf node 3 is a hardware module added to each core. There are two types of 1-bit registers, a synchronization setting register and a synchronization status display register. The synchronization setting register is a register that indicates whether or not the core is in a barrier synchronization completion waiting state. When the program execution of the core reaches the synchronization point, it is set to '1'. When the synchronization status display register is reset, it is reset to “0”. The synchronization status display register is a register that holds a copy of the barrier mechanism status register managed by the root node 7.

  FIG. 2A is a diagram illustrating an example of a hardware configuration of the leaf node 3. Leaf node 3 supports a detach (mask) function. The mask function is a setting applied to the leaf node 3, and specifies whether or not the core 1 corresponding to the leaf node 3 participates in the barrier. In this embodiment, information indicating validity / invalidity of the mask function of each leaf node 3 is stored in the mask storage unit 11 of FIG. The leaf node 3 includes a synchronization setting register 21, a synchronization state display register 23, a negative operation unit 25, and a selector 27 (an example of “leaf node selection means” in the claims of the present application). The selector 27 selects whether the value of the synchronization setting register 21 or the value of the synchronization state display register 23 is negated by the negation operation unit 25 according to the mask valid / invalid setting in the mask storage unit 11. To notify the parent node. That is, if the mask is valid inside the barrier mechanism, the leaf node 3 transmits the value of the synchronization setting register 21 to the parent node (see FIG. 2B). On the other hand, when the node is invalid, the leaf node 3 outputs the inverted value of the synchronization state display register 23 to the parent node, thereby eliminating the influence on the upper node (see FIG. 2C).

The root node 7 is a hardware module that manages the synchronous processing execution state in the core group. The management target core group of the root node 7 is obtained by removing the leaf nodes whose mask function is invalid by the mask storage unit 11 from the descendant leaf nodes. In the example of FIG. 1, when the mask mechanism is valid (when the mask function is not used), the core groups managed by the root node 7 are the leaf nodes 3 _{1 to} 3 ₄ . The synchronization setting register values are counted from the leaf node 3 under management, and it is determined whether or not all the cores 1 have reached the synchronization point. There is a 1-bit synchronization status register inside.

  The proposed barrier mechanism has two states: a barrier completion wait / acceptable state and a barrier completion notification wait state, and the current state is indicated by a synchronization state register. The state transition is shown in FIG. The barrier completion waiting / acceptable state (W_SET in FIG. 3) is a state in which the core 1 belonging to the core group is executing the synchronization process or can execute the next barrier synchronization process. At this time, the synchronization state register is reset to “0”. The barrier completion notification waiting state (W_RST in FIG. 3) is a state in which barrier synchronization is completed and a completion notification is broadcast to all leaf nodes. At this time, the synchronization status register is set to “1”.

  The internal node 5 is a hardware module located between the root node 7 and the leaf node 3. In this embodiment, it is assumed that the internal structure is the same as that of the root node 7. When the internal node 5 divides the barrier network and realizes the synchronization processing of a plurality of core groups, the uppermost internal node 5 of each core group is enabled with the loopback function, and is used as the root node of the core group. Operate.

  FIG. 4A is a diagram illustrating an example of a hardware configuration of the internal node 5. The internal node 5 supports the return function. The loopback function is a setting applied to the internal node 5 and designates whether or not to participate in the barrier of the core group of the upper node. In this embodiment, information indicating validity / invalidity of the folding function of each internal node 5 is stored in the folding storage unit 9 of FIG. The internal node 5 includes a synchronization circuit 31, a synchronization state display register 33, a negative operation unit 35, a selector 37 (an example of “internal node selection means” in the claims of the present application), and a selector 39. For example, in the barrier completion waiting / acceptable state, the synchronization circuit 31 has reached the synchronization point when all the logical values notified from the child nodes are values indicating that the synchronization point has been reached. In other cases, a different logical value is used. For example, in the barrier completion notification waiting state, the synchronization circuit 31 sets the synchronization setting of the leaf node if all the logical values notified from the leaf node are logical values indicating that the synchronization setting register of the leaf node has been reset. It is a logical value indicating that the register has been reset, and a different logical value otherwise. Whether the selector 37 has negated the value of the synchronization state display register 33 by the negation calculation unit 35 (see FIG. 4B) or the synchronization circuit according to the setting of the loopback valid / invalid in the loopback storage unit 9 The logical value output from 31 (see FIG. 4C) is selected and notified to the parent node. The selector 39 determines whether the logical value output from the synchronization circuit 31 (see FIG. 4B) or the logical value notified from the parent node according to the setting of the loopback valid / invalid in the loopback storage unit 9 (See FIG. 4C) is selected and notified to the child node.

In this embodiment, the internal node 5 adopts the same hardware configuration as that of the root node 7. Therefore, the internal node 5 can have the same function as the root node 7. Therefore, the barrier network is divided into a plurality of subtrees by operating an internal node as a root node. FIG. 5 shows an example in which a barrier network having _eight leaf nodes 41 ₁ ,. The number of each leaf node 41 indicates the presence or absence of a mask. “0” indicates that the mask is valid, and “1” indicates that the mask is invalid. The numbers of the internal nodes 43 ₁ to 43 ₆ and the root node 45 indicate the presence or absence of folding. “0” indicates that the call is folded, and “1” indicates that the call is not folded. The leaf nodes 41 ₁ , 41 ₂ and 41 ₈ in FIG. The leaf nodes 41 ₃ and 41 ₄ in FIG. In the core group B, by applying the folding function to the internal node 41 ₂ as a parent node, to operate as a root node. The leaf nodes 41 ₅ and 41 ₆ in FIG. In the core group C, a loopback function is applied to the internal node 41 _{3 serving} as a parent node, thereby operating as a root node. Leaf nodes 41 ₇ of FIG. 5 constitutes the core group D.

  As shown in FIG. 4B, when the loopback function is applied to the internal node, the logical operation result of the signal (synchronization setting register value) forwarded from the child node cannot be forwarded to the parent node. It is transferred to the child node as a synchronization processing completion notification signal. For example, when both child nodes reach the synchronization point, the corresponding synchronization setting register is set to ‘1’ and the logical product of these is obtained. This result is fed back to the child node as a synchronization processing completion notification signal. Further, by transferring the inversion value of the synchronization processing completion notification signal forwarded from the parent node to the parent node, the influence on the upper (closer to the root node) node is eliminated. By configuring a plurality of small-scale barrier networks using partial trees in this way, each core group can perform barrier synchronization processing independently and in parallel.

  First, the operation of the barrier mechanism will be described with reference to FIGS. 6 and 7 when the folding function and the mask function are not used. FIG. 6 shows a state from when the state of the barrier mechanism is “barrier completion waiting / acceptable state” to when the state is changed to become “barrier completion waiting / acceptable state” again.

  In FIG. 6, the numbers in the internal node 53 and the root node 55 (circles in FIG. 6) indicate the value of the synchronization setting register on the left of the slash and the status output value on the right of the slash. The numbers in the leaf nodes 51 (squares in FIG. 6) indicate the value of the synchronization setting register on the left of the slash and the value of the status display register on the right of the slash.

  In FIG. 6A, the initial state of the barrier mechanism is “barrier completion waiting / acceptable state”, and the initial values of the synchronization setting registers of all the leaf nodes 51 are set to “0” (that is, the next barrier is changed). Ready to run).

In the synchronization process, a core corresponding to the leaf node 51 ₃ has reached the synchronization point. At this time, the synchronization setting register of the core is set to “1”. The value of the synchronization setting register of the core 2 is transmitted to the internal node 53 _2. At this time, if the value of the synchronization setting register of the other child node is not set, the synchronization waiting state is continued (FIG. 6B).

Reaches the core 51 ₄ synchronization point, synchronization setting register is set to '1'. Accordingly, the internal node 53 _2, the parent node 55 (where the root node), propagates the value of the synchronization setting register (Figure 6 (c)).

When the cores corresponding to the leaf nodes 51 ₁ and 51 ₂ reach the synchronization point, the internal node 531 propagates the value of the synchronization setting register to the root node 55. The root node 55 determines that all the cores have reached the synchronization point. As a result, a synchronization processing completion notification signal is sent to each leaf node, and a transition to a barrier completion notification waiting state is made (FIG. 6D).

  After receiving the barrier completion notification from the root node, each leaf node resets the synchronization setting register to “0” and propagates it to the root node (FIG. 6E).

  The root node 55 determines that the values of the synchronization setting registers of all the leaf nodes 51 have been reset, and sets the state of the barrier mechanism to a barrier completion waiting / acceptable state. As a result, the next new barrier synchronization can be accepted (FIG. 6A).

  FIG. 7 is a diagram illustrating an example of the synchronization circuit 31 in the internal node 5 of FIG. The synchronization circuit 31 includes an AND operation unit 61, an OR operation unit 63, a selector 65, and a synchronization storage unit 67. The logical product operation unit 61 calculates the logical product of the values of the synchronization setting register input from the child nodes. The logical sum operation unit 63 calculates the logical sum of the values of the synchronization setting register input from the child nodes. The selector 65 selects either the output of the logical product operation unit 61 or the output of the logical sum operation unit 63 based on the value stored in the synchronous storage unit 67. The synchronization storage unit 67 stores the output value of the selector 65. As shown in FIG. 7, when the internal node 5 is in the barrier completion waiting / acceptable state, the internal node 5 takes the logical product of the values of the synchronization setting registers input from the two child nodes. On the other hand, in the barrier completion notification waiting state, the logical sum of these values is forwarded to the parent node. By propagating these values toward the root, the root node can grasp the status of all leaf nodes.

  By using the loopback function and the mask function, it is possible to expand the configuration so that a plurality of barrier synchronizations can be executed within one barrier network by changing the subsequent setting information and logically dividing the barrier network.

  The operation of each node is the same as the root node in FIG. 6 for the child nodes for the internal nodes for which the loopback function is valid. The internal node with the invalid loopback function is the same as the internal node in FIG. The leaf nodes for which the mask function is valid are the same as the leaf nodes in FIG.

  An internal node with the loopback function enabled and a leaf node with the mask function disabled indicates to the parent node that the synchronization point has been reached if the core group of the parent node is “waiting for barrier completion / acceptable”. If the logical value is notified and “waiting for barrier completion notification”, the logical value indicating that the synchronization setting register has been reset is notified, and the influence on the upper (closer to the root node) node is eliminated.

  This makes it possible to support synchronous processing that can be executed independently and in parallel for a plurality of various core groups under a multi-program execution environment or the like.

Furthermore, as shown in FIG. 8, the flexibility can be expanded by multiplexing. In setting by masking / wrapping, only the group structure of subtree units can be performed. Therefore, other group configurations are handled by preparing a plurality of barrier networks (multiplexing). Figure 8 is to use two barrier network of eight nodes, and leaf nodes 61 _1, 61 _3, 61 ₅ and 61 ₇ were grouped leaf node 61 _2, 61 _4, 61 ₆ and 61 ₈ An example of division into two groups is shown. Nodes in each network operate independently.

  The barrier mechanism of the present invention makes it possible to execute a hardware barrier with a small latency and no variation by combining various nodes by combining a folding function, a mask function, and multiplexing. That is, it can be used in a many-core processor or the like, and a new hardware barrier method having flexibility can be realized. Specifically, it is a hardware barrier mechanism that can be realized with (1) low latency and small variation, (2) division of the barrier network, and (3) small circuit amount. Also, by preparing a plurality of small-scale barrier networks, it is possible to realize a flexible hardware barrier mechanism that can cope with a many-core processor in which various processes will operate.

  Next, an example of dynamic configuration change of the barrier mechanism will be described with reference to FIGS. FIG. 9 and FIG. 10 each show an example of a configuration change processing synchronization mechanism of a leaf node and an internal node for realizing a dynamic configuration change. 9 and 10 are examples in which no FF is inserted between nodes. When FF is included, the output is delayed from the parent node, so that it can be realized by appropriately adjusting the update register change timing.

  The barrier mechanism shown in FIGS. 9 and 10 is configured to be distributed to each node, thereby enabling parallel processing of configuration change and further speeding up the configuration change. Further, the barrier mechanism includes a configuration change processing synchronization mechanism for assisting confirmation of the configuration change. This configuration change processing synchronization mechanism is a mechanism for each node to confirm whether the configuration change has been performed on all nodes. This is realized by applying a barrier synchronization mechanism. That is, (1) each node has a configuration setting input for instructing a configuration change, and a configuration status output for confirming that the configuration change of all nodes has been performed, and (2) a configuration setting value is input. At the same time, input “1” to the configuration setting input, and (3) wait until the configuration status output becomes “0”. By performing such a series of processing, it can be confirmed that the configuration setting has been performed in all the nodes, and thereafter, the barrier synchronization by the new configuration setting and the configuration setting again can be performed.

  For a synchronous subtree network that does not require a configuration change, it is possible to continue the current barrier synchronization process by performing a new setting with the same setting. Therefore, a new barrier group can be dynamically generated in the barrier network by this function.

  Similar to the barrier synchronization mechanism, the dynamic configuration change mechanism confirms the configuration setting input of all the nodes and advertises the result using a combination of leaf nodes and internal nodes (root nodes). Unlike the barrier synchronization mechanism, it does not have hardware for folding or masking, and synchronizes all nodes in the network. Moreover, the state transition from the synchronization completion confirmation to the synchronization waiting is performed in the dynamic configuration change mechanism. Further, the synchronization request input signal is a pulse signal.

  The leaf node in FIG. 9 includes a logical sum operation unit 73, a logical product operation unit 75, and an update register 77. The leaf node in FIG. 9 sends “1” to the parent node while making a synchronization request (update request = “1” or update register = “1”). That is, the logical sum operation unit 73 calculates the logical sum of the value stored in the update register 77 and the update request. From the parent node, “1” is returned when synchronization is not completed, and “0” is returned when it is completed. The AND operation unit 75 calculates a logical product of the value notified to the parent node and the value notified from the parent node. The operation result of the logical product operation unit 75 becomes a status output. The status output is '1' if the leaf node is requesting synchronization and the parent node is performing synchronization processing, and '0' otherwise. The update register 77 stores the calculation result of the logical product calculation unit 75.

  The internal node of FIG. 10 includes a logical sum operation unit 81, logical product operation units 83, 85, 87, and 89, logical sum operation units 91 and 93, a negative operation unit 95, and an update register 97. The internal node in FIG. 10 returns '1' if a synchronization request is made to a parent node during a synchronization request from one of the child nodes and is not completed. Otherwise, it returns '1'. Returns '0'. When the own node and all child nodes are requesting synchronization, “1” is sent to the parent node for the synchronization request. The difference between the root node and the internal node is that there is no parent node to be synchronized in the case of the root node, so that “0” (synchronization completion) is always sent as a value from the parent node.

  That is, the logical sum operation unit 81 calculates the logical sum of the value stored in the update register 97 and the update request. The AND operation unit 83 calculates the logical product of the values notified from the child nodes. The logical product operation unit 85 calculates the logical product of the outputs of the logical sum operation unit 81 and the logical product operation unit 83 and notifies the parent node. The negation calculation unit 95 calculates negation of the value notified to the parent node. From the parent node, “1” is returned when synchronization is not completed, and “0” is returned when it is completed. The logical sum operation unit 93 calculates a logical sum of the value notified from the parent node and the operation result of the negative operation unit 95. The AND operation unit 87 calculates the logical product of the operation result of the OR operation unit 93 and the output of the OR operation unit 81. The update register 97 stores the calculation result of the logical product calculation unit 87. The logical sum operation unit 91 calculates the logical sum of the values notified from the child nodes. The logical product operation unit 89 calculates the logical product of the operation results of the logical sum operation units 91 and 93 and notifies the child node.

  Software processing for changing the configuration setting will be described. As for the dynamic configuration change mechanism, the interface with software is performed through a barrier control register (BRC). The BRC bits include RET, MSK, SYN, and STT. Here, RET, MSK, SYN, and STT include a plurality of bits. Each bit corresponds to a barrier network number. RET, MSK, and SYN are return information, mask information, and synchronization control, respectively. STT selects a writing destination at the time of writing, 1 writes configuration information (RET / MSK), and 0 writes synchronous control (SYN). At the time of reading, it indicates a synchronization state, 1 indicates synchronization completion, and 0 indicates synchronization reset completion.

  When changing the configuration setting, 1 is written in the STT bit and the configuration information is written in the RET / MSK. In the barrier network that performs configuration setting, writing must be performed even if there is no change in the setting of the own node. The STT bit is set to 1 during configuration setting. When the configuration is completed, the STT bit is set to 0, and thereafter, synchronous setting is possible. After the configuration is set, the barrier network is reset and enters a synchronization set waiting state.

  When operating another barrier network without waiting for the completion of configuration setting, synchronization control and synchronization reset must be set for the network being configured. Just reading the BRC register does not tell whether the configuration is in progress, so it must be stored in software. If SYN = 0 is set at the time of configuration, barrier synchronization is not started during configuration by read-modify-write.

  Subsequently, the barrier mechanism of the present invention is evaluated by measuring the barrier synchronization time and counting the circuit scale. In this evaluation, SMYLEref (Many-Coreonson, 4 others, construction of evaluation environment for Manycore architecture SMYLEref using FPGA, Information Processing Society of Japan, Vol.198, No.15, pp.1 -7, 2012.) RTL design. SMYLEref is an architecture in which multiple cores based on the MIPS R3000 architecture are clustered by bus connection, and many clusters are connected by a two-dimensional mesh on-chip network. In this experiment, a model of one cluster and 16 cores was created, and 8 barrier networks were implemented for 16 cores. In addition, a register is installed in each core for barrier control, and each core reads and writes the register to enable barrier synchronization. The register controls the configuration and synchronization of one of the leaf nodes used by the core and 15 internal nodes and root nodes (FIG. 11).

  First, the barrier synchronization time measurement will be described. FIG. 12 shows an evaluation program used to measure the barrier synchronization time. The evaluation program first writes the mask information and turn-back information of leaf nodes and internal nodes, which each core is in charge of, into a register (barrier cong function). Next, execute barrier synchronization (barrier function) twice. The reason why the barrier function is executed twice is that the function program is placed in the cache and that all cores simultaneously start executing the barrier function to be measured.

  The following processing is performed in the barrier function. That is, (1) reading of the register is repeated until the status display becomes “0” (check barrier reset). (2) Write synchronization setting = '1' to the register (barrier sync set). (3) Repeat reading of the register until the status display becomes “1” (check barrier set). (4) Write synchronization setting = '0' to the register (barrier sync reset).

  As the barrier synchronization time, the number of clock cycles required to execute the second barrier function was measured. The measurement was performed using an RTL simulator ISIM (0.40d version) manufactured by xilinx. For comparison, we also measured two test programs that do not use hardware barriers. In these tests, the hardware barrier function is executed twice before executing the second barrier function so that all cores can execute the barrier function simultaneously. Each of the two programs has a barrier synchronization method (Wilkinson, B., 1 other, Parallel Programming: Techniques and Applications Using Networked Workstations and Parallel Computers, Prentice Hall, Upper Saddle River, NJ, USA, 1999.) One is using the master-slave method for small nodes and the other is the buttery method for medium and higher nodes.

  Table 1 shows the measurement results when all 16 cores participate in barrier synchronization. The unit is a clock cycle. “Type” in the table indicates the type of measurement object, “HW” indicates a hardware barrier, “MS” indicates a Master-Slave method, and “BUT” indicates a buttery method. 'Starting fastest', 'Starting slowest', 'Completing fastest', and 'Completing slowest' respectively indicate the number of relative elapsed clock cycles starting from the starting fastest (FIG. 13). 'Starting fastest' is the relative elapsed clock cycle number of the core at which the execution of the barrier function was the earliest. Since this is the starting point in the table, the value is 0 for all types. 'Latest start' indicates the relative elapsed clock number of the core with the slowest start of execution of the barrier function, and 'Fastest completion' indicates the core with the fastest completion of the barrier function and the slowest completion of the core. Indicates the relative elapsed clock number. 'Completed-Completed' indicates the clock difference between the fastest completion and the slowest completion. Considering the value of 'latest late' as function execution latency and 'complete-completion' as inter-core variability, HW reduces latency to 1/87 for MS, 1/79 for variability and BUT. The latency has been improved to 1/66 and the variation to 1/30.

  Next, circuit scale evaluation will be described. The circuit scale was obtained using a logic synthesis tool xst (ISE 13.10.40 version) manufactured by Xilinx. Vertex-6 (ML605 evaluation board) is specified as the synthesis target FPGA.

  Table 2 shows the synthesis result of the SMYLEref model used for the barrier synchronization time measurement, and the synthesis result in which only the hardware barrier part is extracted therefrom. In the table, “Type” indicates a counted object, “LUT” indicates LUT, “Reg” indicates a register, and “RAM” indicates 36 Kbit RAM (block RAM). 'BAR' represents the barrier synchronization part, and 'SMYLE' represents the synthesis result of SMYLEref. 'BAR / S-MYLE' is the percentage of BAR to SMYLE for each LUT, Reg and RAM. BAR / SMYLE does not change as the number of cores increases, but decreases as the number of clusters increases. Considering the area required for a memory of about 32 KBytes per core, it is considered that the hardware circuit of the barrier is sufficiently small compared to the SMYREref many-core processor.

  As described above, in the present embodiment, a method for realizing high-speed, stable and flexible barrier synchronization by providing a small-scale hardware barrier circuit with a barrier network dividing function and further multiplexing the network has been described.

  In the experiment, in the barrier synchronization time evaluation, the latency was 1/66 and the variation was 1/30 when the hardware barrier mechanism was used, indicating the effectiveness of the proposed method. Also, in the circuit scale evaluation, the hardware barrier circuit is small, with 13% LUTs and 1.8% registers compared to the entire many-core processor.

  1 core, 3 leaf node, 5 internal node, 9 loopback storage unit, 11 mask storage unit, 21 synchronization setting register, 23 synchronization state display register, 25 negation operation unit, 27 selector, 31 synchronization circuit, 33 synchronization state display register, 35 negative operation unit, 37 selector, 41 leaf node, 43 internal node, 45 root node, 51 leaf node, 53 internal node, 55 root node, 61 logical product operation unit, 63 logical sum operation unit, 65 selector, 67 synchronous storage Unit, 71 leaf node, 73 logical sum operation unit, 75 logical product operation unit, 77 update register, 81 logical sum operation unit, 83, 85, 87, 89 logical product operation unit, 91 93 logical sum operation unit, 95 negative operation Part, 97 update register

Claims (7)

A synchronization processing circuit that performs a part or all of the synchronization processing of a plurality of processing means using a plurality of nodes in a tree structure,
The tree-structured nodes include a plurality of leaf nodes positioned at the lowest level and corresponding to the plurality of processing units, a root node positioned at the highest level, and a plurality of internal nodes other than the root node and the leaf nodes. Nodes included,
In the tree structure, not only the logical value is notified from the child node to the parent node, but also the logical value is notified from the parent node to the child node.
Each internal node notifies a parent node of a logical value obtained by performing a logical operation on a logical value notified from a child node of the internal node, or a logical value notified from the parent node A synchronization processing circuit comprising internal node selection means for selecting whether to notify the negative of   Each leaf node notifies the parent node of a logical value indicating whether the processing means corresponding to the leaf node has reached the synchronization point, or the logical value notified from the parent node The synchronization processing circuit according to claim 1, further comprising a leaf node selection unit that selects whether to notify a negative. The synchronous processing circuit performs a state transition between a barrier completion waiting / acceptable state and a barrier completion notification waiting state,
The leaf node that notifies the logical value indicating whether or not the corresponding processing means has reached the synchronization point,
In the barrier completion waiting / acceptable state, the corresponding processing means notifies the synchronization state logical value as a logical value indicating that the synchronization point has been reached, and indicates the synchronization as a logical value indicating that the synchronization point has not been reached. Notify asynchronous state logical value different from state logical value,
In the barrier completion notification waiting state, when the synchronous processing logical value is notified from a parent node, the asynchronous state logical value is notified,
An internal node that notifies the negation of the logical value notified from the root node and the parent node,
When all the child nodes notify the synchronous state logical value in the barrier completion waiting / acceptable state, the synchronous state logical value is notified to the child node, and the state transits to the barrier completion notification waiting state. And
The synchronous processing circuit according to claim 2, wherein when the asynchronous state logical value is notified from all the child nodes in the barrier completion notification waiting state, the state is shifted to the barrier completion waiting / acceptable state. A return storage means for storing information indicating whether or not to perform return at each internal node;
Mask storage means for storing information indicating whether or not to perform masking in each leaf node;
Whether each leaf node notifies the parent node of a logical value indicating whether or not the processing means corresponding to the leaf node has reached the synchronization point according to the information stored in the mask storage means Or a leaf node selection means for selecting whether to notify the negation of the logical value notified from the parent node,
The internal node selection means of each internal node selects according to the information stored in the loopback storage means,
The synchronous processing circuit according to claim 2, wherein the root node notifies a child node of a logical value obtained by performing a logical operation on the logical value notified from the child node of the internal node.   5. The synchronization processing circuit according to claim 1, wherein a plurality of tree structures exist, and synchronization processing is performed independently of other tree structures in each tree structure. Each of the internal nodes includes a configuration change processing synchronization mechanism for dynamically changing the configuration of the tree structure,
The configuration change processing synchronization mechanism is
When the own node and all child nodes are requesting synchronization to the parent node, send a synchronization request to the parent node.
If a synchronization request from one of the child nodes to the parent node is made to the child node and is not completed, a logical value indicating that the synchronization is not completed is sent to the child node. Otherwise, The synchronous processing circuit according to claim 1, which sends different logical values. A synchronization processing method in a synchronization processing circuit that performs a synchronization process of a part or all of a plurality of processing means using a plurality of nodes in a tree structure,
In the tree structure, not only the logical value is notified from the child node to the parent node, but also the logical value is notified from the parent node to the child node.
The internal node selection means included in the synchronous processing circuit performs logical operation on the logical value notified from the child node of the internal node to the parent node by the internal node where the parent node and the child node exist in the tree structure. A synchronization processing method including a selection step of selecting whether to notify the logical value obtained in this way or to notify the negative of the logical value notified from the parent node.

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