JP2014053061A - Semiconductor memory device and controller thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving use efficiency, and a controller thereof.SOLUTION: A semiconductor memory device 1 of an embodiment includes a memory cell array 111 and a control unit 140 that performs data access control. The memory cell array 111 includes a plurality of blocks; and any of the blocks holds information, BWL or BSG, on a word line or a first or second select gate line where a short failure has occurred.

Description

  Embodiments described herein relate generally to a semiconductor memory device and a controller thereof.

  A NAND flash memory in which memory cells are arranged three-dimensionally is known.

US Pat. No. 7,936,004

  Provided are a semiconductor memory device and a controller for the same, which can improve usage efficiency.

  The semiconductor memory device according to the embodiment includes a memory cell array capable of storing data in a nonvolatile manner and a control unit that performs data access control on the memory cell array. The memory cell array includes a plurality of blocks. The blocks include first and second selection transistors, each of which includes a charge storage layer and a control gate, and is stacked on a semiconductor substrate, and the first and second selection transistors. A plurality of memory cell transistors connected in series between the transistors, first and second select gate lines connected to the gates of the first and second select transistors, respectively, and connected to the gates of the memory cell transistors, respectively A word line. Any one of the blocks holds information regarding any word line in which a short circuit defect has occurred, or the first and second select gate lines.

1 is a block diagram of a memory system according to a first embodiment. 1 is a block diagram of a semiconductor memory device according to a first embodiment. 1 is a circuit diagram of a memory cell array according to a first embodiment. 1 is a perspective view of a memory cell array according to a first embodiment. 1 is a cross-sectional view of a memory cell array according to a first embodiment. 1 is a cross-sectional view of a memory cell array according to a first embodiment. 1 is a perspective view of a memory cell array according to a first embodiment. 1 is a block diagram of a row decoder and a driver circuit according to a first embodiment. The flowchart of the test method which concerns on 1st Embodiment. 1 is a schematic diagram of a memory cell array according to a first embodiment. FIG. The schematic diagram of the block which concerns on 1st Embodiment. The flowchart of operation | movement of the controller which concerns on 1st Embodiment. The diagram which shows the command which concerns on 1st Embodiment. 4 is a flowchart of the operation of the semiconductor memory device according to the first embodiment. 4 is a flowchart of the operation of the semiconductor memory device according to the first embodiment. 1 is a circuit diagram of a memory cell array according to a first embodiment. 1 is a circuit diagram of a memory cell array according to a first embodiment. 1 is a circuit diagram of a memory cell array according to a first embodiment. The circuit diagram of the memory cell array concerning a 2nd embodiment. The sequence diagram which shows the process of the memory system which concerns on 2nd Embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the second embodiment. The sequence diagram which shows the process of the memory system which concerns on 2nd Embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the second embodiment. The circuit diagram of the memory cell array concerning a 2nd embodiment. The sequence diagram which shows the process of the memory system which concerns on 2nd Embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the second embodiment. The sequence diagram which shows the process of the memory system which concerns on 2nd Embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the second embodiment. The circuit diagram of the memory cell array concerning a 2nd embodiment. The sequence diagram which shows the process of the memory system which concerns on 2nd Embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the second embodiment. The sequence diagram which shows the process of the memory system which concerns on 2nd Embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the second embodiment. The flowchart of operation | movement of the controller which concerns on 3rd Embodiment. The flowchart of operation | movement of the controller which concerns on 3rd Embodiment. FIG. 9 is a sequence diagram showing processing of a memory system according to a third embodiment. The flowchart of operation | movement of the controller which concerns on 3rd Embodiment. FIG. 9 is a sequence diagram showing processing of a memory system according to a third embodiment. The flowchart of operation | movement of the controller which concerns on 3rd Embodiment. FIG. 9 is a sequence diagram showing processing of a memory system according to a third embodiment. The block diagram of the register | resistor which concerns on 4th Embodiment. The timing chart of the signal at the time of SIN code storage concerning a 4th embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the fourth embodiment. FIG. 10 is a command sequence diagram of the semiconductor memory device according to the fourth embodiment. The conceptual diagram of the memory cell array concerning a 5th embodiment. The flowchart of operation | movement of the controller which concerns on 5th Embodiment. The graph which shows the relationship between the defect which concerns on 6th Embodiment, and its relief method. The perspective view of the memory cell array concerning a 6th embodiment. Sectional drawing of the memory cell array concerning 6th Embodiment. The top view of the word line which concerns on 6th Embodiment. The diagram of the memory cell array concerning the modification of the 1st thru / or a 6th embodiment. The diagram of the memory cell array concerning the modification of the 1st thru / or a 6th embodiment. FIG. 7 is a cross-sectional view of a memory cell array according to the first to sixth embodiments. The circuit diagram of the memory cell array concerning the modification of the 1st thru / or a 6th embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

1. First embodiment
The semiconductor memory device and its controller according to the first embodiment will be described. Hereinafter, as a semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cells are stacked on a semiconductor substrate will be described as an example.

1.1 Configuration
1.1.1 Memory system configuration
First, the configuration of a memory system including the semiconductor memory device according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram of a memory system according to this embodiment.

  As illustrated, the memory system includes a NAND flash memory 100, a controller 200, and a host device 300.

  The NAND flash memory 100 includes a plurality of memory cells and stores data in a nonvolatile manner. Details of the configuration of the NAND flash memory will be described later.

In response to a command from the host device 300, the controller 200 commands the NAND flash memory 100 to read, write, erase, and the like. The memory space of the NAND flash memory 100 is managed. The controller 200 and the NAND flash memory 100 may constitute the same semiconductor device, for example, and examples thereof include a memory card such as an SD ^TM card, an SSD (solid state drive), and the like.

  The controller 200 includes a host interface circuit 210, a built-in memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, and a NAND interface circuit 250.

  The host interface circuit 210 is connected to the host device 300 via the controller bus and manages communication with the host device 300. Then, the command and data received from the host device 300 are transferred to the CPU 230 and the buffer memory 240, respectively. In response to a command from the CPU 230, the data in the buffer memory 240 is transferred to the host device 300.

  The NAND interface circuit 250 is connected to the NAND flash memory 100 via the NAND bus and manages communication with the NAND flash memory 100. Then, the command received from the CPU 230 is transferred to the NAND flash memory 100, and the write data in the buffer memory 240 is transferred to the NAND flash memory 100 at the time of writing. Further, at the time of reading, the data read from the NAND flash memory 100 is transferred to the buffer memory 240.

  The CPU 230 controls the operation of the entire controller 200. For example, when a read command is received from the host device 300, a read command based on the NAND interface is issued in response thereto. The same applies to writing and erasing. The CPU 230 executes various processes for managing the NAND flash memory 1 such as wear leveling. Further, the CPU 230 executes various calculations. For example, data encryption processing, randomization processing, error checking (ECC) processing, and the like are executed.

  The built-in memory 220 is a semiconductor memory such as a DRAM, and is used as a work area for the CPU 230. The built-in memory 220 holds firmware for managing the NAND flash memory 100, various management tables, and the like.

1.1.2 Configuration of semiconductor memory device
Next, the configuration of the semiconductor memory device 100 will be described.

1.1.2.1 Overall configuration of semiconductor memory device
FIG. 2 is a block diagram of the NAND flash memory 100 according to the present embodiment. As illustrated, the NAND flash memory 100 includes a core unit 110, a page buffer 120, an input / output unit 130, and a peripheral circuit 140.

  The core unit 110 includes a memory cell array 111, a row decoder 112, and a sense amplifier 113.

  The memory cell array 111 includes a plurality of (four in the example of FIG. 2) blocks BLK (BLK0 to BLK3) that are a set of nonvolatile memory cells. The block BLK serves as a data erasing unit, and data in the same block BLK is erased collectively. Each of the blocks BLK includes a plurality (four in this example) of string groups GP (GP0 to GP3) that are sets of NAND strings 114 in which memory cells are connected in series. Of course, the number of blocks in the memory cell array 111 and the number of string groups in one block BLK are arbitrary.

  The row decoder 112 decodes the block address BA and selects the corresponding block BLK.

  The sense amplifier 113 senses and amplifies data read from the memory cell when reading data. When data is written, the write data is transferred to the memory cell. Data reading and writing to the memory cell array 111 are performed in units of a plurality of memory cells, and this unit becomes a page.

  The page buffer 120 holds data in units of pages. When reading data, the page buffer 120 temporarily holds the data transferred from the sense amplifier 113 in units of pages, and transfers the data serially to the input / output unit 130. On the other hand, when data is written, the data transferred serially from the input / output unit 130 is temporarily held and transferred to the sense amplifier 113 in units of pages.

  The input / output unit 130 controls transmission / reception of various commands and data to / from the controller 200 via the NAND bus.

  The peripheral circuit 140 includes a sequencer 141, a charge pump 142, a register 143, and a driver 144.

  The driver 144 supplies voltages necessary for writing, reading, and erasing data to the row decoder 112, the sense amplifier 113, and a source line driver (not shown). This voltage is applied to memory cells (a word line, a select gate line, a back gate line, a bit line, and a source line, which will be described later) by the row decoder 112, the sense amplifier 113, and the source line driver.

  The charge pump 142 boosts a power supply voltage supplied from the outside and supplies a necessary voltage to the driver 144.

  The register 143 holds various signals. For example, the status of the data writing or erasing operation is held, thereby notifying the controller whether or not the operation has been normally completed.

  The sequencer 141 controls the operation of the entire NAND flash memory 100.

1.1.2.2 Memory cell array 111
Next, details of the configuration of the memory cell array 111 will be described. FIG. 3 is a circuit diagram of the block BLK0. The blocks BLK1 to BLK3 have the same configuration.

  As illustrated, the block BLK0 includes, for example, four string groups GP. Each string group GP includes n (n is a natural number) NAND strings 114.

  Each of the NAND strings 114 includes, for example, eight memory cell transistors MT (MT0 to MT7), select transistors ST1 and ST2, and a back gate transistor BT. The memory cell transistor MT includes a stacked gate including a control gate and a charge storage layer, and holds data in a nonvolatile manner. The number of memory cell transistors MT is not limited to 8, and may be 16, 32, 64, 128, etc., and the number is not limited. Similar to the memory cell transistor MT, the back gate transistor BT also includes a stacked gate including a control gate and a charge storage layer. However, the back gate transistor BT is not for holding data but functions as a simple current path at the time of writing, reading and erasing data. Memory cell transistor MT and back gate transistor BT are arranged between select transistors ST1 and ST2 such that their current paths are connected in series. Note that the back gate transistor BT is provided between the memory cell transistors MT3 and MT4. The current path of the memory cell transistor MT7 on one end side of the series connection is connected to one end of the current path of the selection transistor ST1, and the current path of the memory cell transistor MT0 on the other end side is connected to one end of the current path of the selection transistor ST2. ing.

  The gates of the select transistors ST1 of the string groups GP0 to GP3 are commonly connected to select gate lines SGD0 to SGD3, respectively, and the gates of the select transistors ST2 are commonly connected to select gate lines SGS0 to SGS3, respectively. In contrast, the control gates of the memory cell transistors MT0 to MT7 in the same block BLK0 are commonly connected to the word lines WL0 to WL7, respectively, and the control gate of the back gate transistor BT is the back gate line BG (in the blocks BLK0 to BLK3). BG0 to BG3), respectively.

  That is, the word lines WL0 to WL7 and the back gate line BG are commonly connected between the plurality of string groups GP0 to GP3 in the same block BLK0, while the select gate lines SGD and SGS are connected to the same block BLK0. Even if it exists, it is independent for every string group GP0-GP3.

  In addition, among the NAND strings 114 arranged in a matrix in the memory cell array 111, the other end of the current path of the select transistor ST1 of the NAND string 114 in the same row is connected to any one of the bit lines BL (BL0 to BLn, n Are commonly connected to natural numbers). That is, the bit line BL commonly connects the NAND strings 114 between the plurality of blocks BLK. Further, the other end of the current path of the selection transistor ST2 is commonly connected to the source line SL. For example, the source line SL connects the NAND strings 114 in common between a plurality of blocks.

  As described above, the data of the memory cell transistors MT in the same block BLK are erased collectively. On the other hand, data reading and writing are performed collectively for a plurality of memory cell transistors MT connected in common to any word line WL in any string group GP in any block BLK. . This unit is called “page”.

  Next, a three-dimensional stacked structure of the memory cell array 111 will be described with reference to FIGS. 4 and 5 are a perspective view and a cross-sectional view of the memory cell array 111. FIG.

  As illustrated, the memory cell array 111 is provided on the semiconductor substrate 20. The memory cell array 111 includes a back gate transistor layer L1, a memory cell transistor layer L2, a selection transistor layer L3, and a wiring layer L4 that are sequentially formed on the semiconductor substrate 20.

  The back gate transistor layer L1 functions as the back gate transistor BT. The memory cell transistor layer L2 functions as the memory cell transistors MT0 to MT7 (NAND string 114). The selection transistor layer L3 functions as selection transistors ST1 and ST2. The wiring layer L4 functions as the source line SL and the bit line BL.

  The back gate transistor layer L1 includes a back gate conductive layer 21. The back gate conductive layer 21 is formed to expand two-dimensionally in a first direction D1 and a second direction D2 parallel to the semiconductor substrate 20 (that is, in the first direction and the second direction, memory cells are stacked). Is orthogonal to the third direction D3). The back gate conductive layer 21 is divided for each block BLK. The back gate conductive layer 21 is formed of, for example, polycrystalline silicon. The back gate conductive layer 21 functions as a back gate line BG.

  The back gate conductive layer 21 has a back gate hole 22 as shown in FIG. The back gate hole 22 is formed so as to dig the back gate conductive layer 21. The back gate hole 22 is formed in a substantially rectangular shape with the first direction as the longitudinal direction when viewed from the top.

  The memory cell transistor layer L2 is formed in the upper layer of the back gate conductive layer L1. The memory cell transistor layer L2 includes word line conductive layers 23a to 23d. The word line conductive layers 23a to 23d are stacked with an interlayer insulating layer (not shown) interposed therebetween. The word line conductive layers 23a to 23d are formed in stripes extending in the second direction with a predetermined pitch in the first direction. The word line conductive layers 23a to 23d are made of, for example, polycrystalline silicon. The word line conductive layer 23a functions as a control gate (word lines WL3, WL4) of the memory cell transistors MT3, MT4, and the word line conductive layer 23b functions as a control gate (word lines WL2, WL5) of the memory cell transistors MT2, MT5. The word line conductive layer 23c functions as control gates (word lines WL1, WL6) for the memory cell transistors MT1 and MT6, and the word line conductive layer 23d functions as control gates (word lines WL0, WL7) for the memory cell transistors MT0 and MT7. Function as.

  Further, the memory cell transistor layer L2 has a memory hole 24 as shown in FIG. The memory hole 24 is formed so as to penetrate the word line conductive layers 23a to 23d. The memory hole 24 is formed so as to align with the vicinity of the end portion of the back gate hole 22 in the first direction.

  Further, the back gate transistor layer L1 and the memory cell transistor layer L2 include a block insulating layer 25a, a charge storage layer 25b, a tunnel insulating layer 25c, and a semiconductor layer 26, as shown in FIG. The semiconductor layer 26 functions as the body of the NAND string 114 (back gate of each transistor).

  As shown in FIG. 5, the block insulating layer 25 a is formed with a predetermined thickness on the side wall facing the back gate hole 22 and the memory hole 25. The charge storage layer 25b is formed with a predetermined thickness on the side surface of the block insulating layer 25a. The tunnel insulating layer 25c is formed with a predetermined thickness on the side surface of the charge storage layer 25b. The semiconductor layer 26 is formed in contact with the side surface of the tunnel insulating layer 25c. The semiconductor layer 26 is formed so as to fill the back gate hole 22 and the memory hole 24.

  The semiconductor layer 26 is formed in a U shape when viewed from the second direction. That is, the semiconductor layer 26 includes a pair of columnar portions 26 a extending in a direction perpendicular to the surface of the semiconductor substrate 20, and a connecting portion 26 b connecting the lower ends of the pair of columnar portions 26 a.

The block insulating layer 25a and the tunnel insulating layer 25c are made of, for example, silicon oxide (SiO ₂ ). The charge storage layer 25b is made of, for example, silicon nitride (SiN). The semiconductor layer 26 is made of polycrystalline silicon. The block insulating layer 25a, the charge storage layer 25b, the tunnel insulating layer 25c, and the semiconductor layer 26 form a MONOS transistor that functions as the memory transistor MT.

  In other words, the configuration of the back gate transistor layer L1 is such that the tunnel insulating layer 25c is formed so as to surround the connecting portion 26b. The back gate conductive layer 21 is formed so as to surround the connecting portion 26b.

  In other words, the configuration of the memory transistor layer L2 is such that the tunnel insulating layer 25c is formed so as to surround the columnar portion 26a. The charge storage layer 25b is formed so as to surround the tunnel insulating layer 25c. The block insulating layer 25a is formed so as to surround the charge storage layer 25b. The word line conductive layers 23a-23d are formed so as to surround the block insulating layers 25a-25c and the columnar portion 26a.

  The select transistor layer L3 includes conductive layers 27a and 27b as shown in FIGS. The conductive layers 27a and 27b are formed in a stripe shape extending in the second direction so as to have a predetermined pitch in the first direction. The pair of conductive layers 27a and the pair of conductive layers 27b are alternately arranged in the first direction. The conductive layer 27a is formed in an upper layer of one columnar portion 26a, and the conductive layer 27b is formed in an upper layer of the other columnar portion 26a.

  Conductive layers 27a and 27b are formed of polycrystalline silicon. The conductive layer 27a functions as the gate (select gate line SGS) of the select transistor ST2, and the conductive layer 27b functions as the gate (select gate line SGD) of the select transistor ST1.

  As shown in FIG. 5, the select transistor layer L3 has holes 28a and 28b. The holes 28a and 28b penetrate through the conductive layers 27a and 27b, respectively. The holes 28a and 28b are aligned with the memory hole 24, respectively.

  As shown in FIG. 5, the select transistor layer L3 includes gate insulating layers 29a and 29b and semiconductor layers 30a and 30b. The gate insulating layers 29a and 29b are formed on the side walls facing the holes 28a and 28b, respectively. The semiconductor layers 30a and 30b are formed in a column shape extending in a direction perpendicular to the surface of the semiconductor substrate 20 so as to be in contact with the gate insulating layers 29a and 29b, respectively.

The gate insulating layers 29a and 29b are made of, for example, silicon oxide (SiO ₂ ). The semiconductor layers 30a and 30b are made of, for example, polycrystalline silicon.

  In other words, the configuration of the selection transistor layer L3 is such that the gate insulating layer 29a surrounds the columnar semiconductor layer 30a. The conductive layer 27a is formed so as to surround the gate insulating layer 29a and the semiconductor layer 30a. The gate insulating layer 29b is formed so as to surround the columnar semiconductor layer 30b. The conductive layer 27b is formed so as to surround the gate insulating layer 29b and the semiconductor layer 30b.

  As shown in FIGS. 4 and 5, the wiring layer L4 is formed in an upper layer of the selection transistor layer L3. The wiring layer L4 includes a source line layer 31, a plug layer 32, and a bit line layer 33.

  The source line layer 31 is formed in a plate shape extending in the second direction. The source line layer 31 is formed so as to be in contact with the upper surfaces of a pair of semiconductor layers 27a adjacent in the first direction. The plug layer 32 is formed so as to be in contact with the upper surface of the semiconductor layer 27 b and to extend in a direction perpendicular to the surface of the semiconductor substrate 20. The bit line layer 33 is formed in a stripe shape extending in the first direction with a predetermined pitch in the second direction. The bit line layer 33 is formed in contact with the upper surface of the plug layer 32. The source line layer 31, the plug layer 32, and the bit line layer 33 are formed of a metal such as tungsten (W), for example. The source line layer 31 functions as the source line SL described in FIG. 3, and the bit line layer 33 functions as the bit line BL.

  6 and 7 show another example of the memory cell array 111. FIG. 6 is a cross-sectional view along the bit line direction, and FIG. 7 is a perspective view.

  As shown in the drawing, the semiconductor layer 26 may have a single columnar shape instead of the U-shape as shown in FIGS. In this case, as shown in FIGS. 6 and 7, a source line layer 31 is formed above the semiconductor substrate, and a plurality of columnar semiconductor layers 30 are formed on the source line layer 31. Then, around the semiconductor layer 30, a selection transistor ST2, memory cell transistors MT0 to MT7, and a selection transistor ST1 are formed in order from the bottom, and a bit line layer 33 is further formed. In the case of this configuration, the back gate transistor BT is not necessary.

1.1.2.3 Row Decoder 112 Next, the configuration of the row decoder 112 will be described with reference to FIG. FIG. 8 is a block diagram of the row decoder 112 and the driver 144, and the row decoder 112 shows only the configuration associated with one of the blocks BLK. That is, the row decoder 112 shown in FIG. 8 is provided for each block BLK. The row decoder 112 selects or deselects the associated block BLK.

  As shown, the row decoder 112 includes a block decoder 41 and high breakdown voltage n-channel enhancement type (E type) MOS transistors 42 to 46 (42-0 to 42-7, 43-0 to 43-3, 44-0 to 44). -3, 45-0 to 45-3, 46-0 to 46-3), 47.

<About Block Decoder 41>
First, the block decoder 41 will be described. The block decoder 41 decodes the block address BA and outputs signals TG and / RDECA when data is written, read and erased. When the block address BA matches the corresponding block BLK, the signal TG is set to the “H” level. The voltage of the signal TG set to the “H” level is VPGMH at the time of writing, VREADH at the time of reading, and Vdda at the time of erasing. Further, the signal / RDECA is set to the “L” level (for example, 0 V).

  On the other hand, when the block address BA does not coincide with the block BLK, the signal TG is set to “L” level (eg, 0 V), and the signal / RDECA is set to “H” level.

  Note that VPGMH is a voltage for transferring the high voltage VPGM applied to the selected word line at the time of data writing, and VPGMH> VPGM. VREADH is a voltage for transferring the voltage VREAD applied to the non-selected word line at the time of reading data, and VREADH> VREAD. Vdda is a voltage for transferring a voltage Vdd (for example, 0 V) applied to the word line when erasing data, and Vdda> Vdd.

<Regarding Transistor 42>
Next, the transistor 42 will be described. The transistor 42 is for transferring a voltage to the word line WL of the selected block BLK. In each of the transistors 42-0 to 42-7, one end of the current path is connected to the word lines WL0 to WL7 of the corresponding block BLK, the other end is connected to the signal lines CG0 to CG7, and the gate is connected to the signal line TG. Connected in common.

  Therefore, for example, in the row decoder 112-0 corresponding to the selected block BLK0, the transistors 42-0 to 42-7 are turned on, and the word lines WL0 to WL7 are connected to the signal lines CG0 to CG7. On the other hand, in the row decoders 112-1 to 11-3 corresponding to the non-selected blocks BLK1 to BLK3, the transistors 42-0 to 42-7 are turned off, and the word lines WL0 to WL7 are separated from the signal lines CG0 to CG7. The

  The transistor 42 is commonly used for all string groups GP in the same block BLK.

<Regarding the transistors 43 and 44>
Next, the transistors 43 and 44 will be described. The transistors 43 and 44 are for transferring a voltage to the select gate line SGD. In each of the transistors 43-0 to 43-3, one end of the current path is connected to the select gate lines SGD0 to SGD3 of the corresponding block BLK, the other end is connected to the signal lines SGDD0 to SGDD3, and the gate is connected to the signal line TG. Connected in common. In each of the transistors 441 to 44-3, one end of the current path is connected to the select gate lines SGD0 to SGD3 of the corresponding block BLK0, the other end is connected to the node SGD_COM, and a signal / RDECA is applied to the gate. The node SGD_COM is a voltage for turning off the selection transistor ST1, such as 0V or a negative voltage VBB.

  Therefore, for example, in the row decoder 112-0 corresponding to the selected block BLK0, the transistors 43-0 to 43-3 are turned on and the transistors 441 to 44-3 are turned off. Therefore, the select gate lines SGD0 to SGD3 of the selected block BLK0 are connected to the signal lines SGDD0 to SGDD3.

  On the other hand, in the row decoders 112-1 to 11-3 corresponding to the unselected blocks BLK1 to BLK3, the transistors 43-0 to 43-3 are turned off and the transistors 44-1 to 44-3 are turned on. The Therefore, the select gate lines SGD0 to SGD3 of the non-selected blocks BLK1 to BLK3 are connected to the node SGD_COM.

<Regarding the transistors 45 and 46>
The transistors 45 and 46 are for transferring a voltage to the select gate line SGS, and their connection and operation are equivalent to the transistors 43 and 44 in which the select gate line SGD is replaced with the select gate line SGS.

  That is, in the row decoder 112-0 corresponding to the selected block BLK0, the transistors 45-0 to 45-3 are turned on and the transistors 46-0 to 44-4 are turned off. On the other hand, in the row decoders 112-1 to 11-3 corresponding to the unselected blocks BLK1 to BLK3, the transistors 43-0 to 43-3 are turned off and the transistors 44-1 to 44-3 are turned on. The

<Regarding Transistor 47>
Next, the transistor 47 will be described. The transistor 47 is for transferring a voltage to the back gate line BG. The transistor 47 has one end of the current path connected to the back gate line BG of the corresponding block BLK, the other end connected to the signal line BGD, and the gate connected to the signal line TG in common.

  Accordingly, in the row decoder 112 corresponding to the selected block BLK0, the transistor 47 is turned on, and in the row decoders 112-1 to 11-3 corresponding to the non-selected blocks BLK1 to BLK3, the transistor 47 is turned off.

  Of course, when the memory cell array 111 has the configuration of FIGS. 6 and 7, the transistor 47 is unnecessary.

1.1.2.4 About the driver 144
Next, the configuration of the driver 144, particularly the configuration for transferring the voltage to the row decoder 112, will be described with reference to FIG. The driver 144 transfers a voltage necessary for data writing, reading, and erasing to each of the signal lines CG0 to CG7, SGDD0 to SGDD3, SGSD0 to SGSD3, and BGD.

  As shown in FIG. 8, the driver 144 includes a CG driver 51 (51-0 to 51-7), an SGD driver 52 (52-0 to 52-3), an SGS driver 53 (53-0 to 53-3), and a BG. A driver 54 and a voltage driver 55 are provided.

  The voltage driver 55 receives the voltage from the charge pump 142 and transfers necessary voltages to the block decoder 41 and the CG driver 51 as voltages VRDEC and VCGSEL. The CG drivers 51-0 to 51-7 respectively transfer necessary voltages to the signal lines CG0 to CG7 (word lines WL0 to WL7) according to the page address. The SGD drivers 52-0 to 52-3 transfer necessary voltages to the signal lines SGDD0 to SGDD3 (select gate lines SGD0 to SGD3), respectively. The SGS drivers 53-0 to 53-3 transfer necessary voltages to the signal lines SGSD0 to SGSD3 (select gate lines SGS0 to SGS3), respectively. The BG driver 54 transfers a necessary voltage to the signal line BGD.

1.2 Test method of NAND flash memory 100
1.2.1 Test method
Next, a test method for the NAND flash memory 100 configured as described above will be described. In this method, when there is a defective block in the memory cell array 111, it is managed according to the degree of the defect.

  FIG. 9 is a flowchart of a test method performed on the NAND flash memory 100 before shipment. The test is performed by a tester of the NAND flash memory 100, and is roughly performed in the order of a block test, identification of a defective portion, and writing of management data.

  As shown in the figure, the tester performs a leak check for each block BLK for the memory cell array 111 (step S10).

  As a result of the leak check, if the leak amount is equal to or less than Ith1 (step S11, YES), the test is passed (step S12). Therefore, the tester registers the block BLK as a good block (step S13).

  As a result of the leak check, if the leak amount is larger than Ith1 (step S11, NO), the test is failed (step S14). In the case of failure, if the leak amount is further larger than Ith2 (step S15, NO), the tester registers the block BLK as a bad block (step S17). The block BLK registered in the bad block is prohibited from being used.

  In step S15, if the leak amount is equal to or less than Ith2 (step S15, YES), that is, if the leak amount is greater than Ith1 and equal to or less than Ith2, the tester registers the block BLK in the management block (step S16). . That is, the degree of failure can be estimated by the amount of leakage (for example, the amount of leakage current). Therefore, depending on the size of the leak, there is a certain amount of physical defects and the block must be treated as a bad block, or there is a defect in part, but it becomes a bad block. Therefore, it can be judged whether it can be handled as a management block. For this processing, for example, a leak check function in units of blocks prepared in a NAND flash memory can be used.

  The processes in steps S10 to S17 described above are performed for all blocks BLK in the memory cell array 111. Thereafter, the tester identifies the defective part.

  That is, the tester first selects a management block (step S18). Then, a defective part in the management block is specified (step S19). The defects assumed in the present embodiment are defects due to wiring shorts, for example, a short of the word line WL, a short of the select gate line SGD, and a short of the select gate line SGS. Examples of other defects will be described in the sixth embodiment.

  The processes in steps S18 and S19 described above are performed for all the blocks BLK registered as management blocks. Of course, if there is no management block in the memory cell array 111, the processes of steps S18 and S19 are omitted.

  Thereafter, the tester writes management data to the memory cell array 111 (step S20). The management data is information regarding the bad block and the block address of the management block obtained in the block test, and the defective part obtained in step S19. These pieces of information are written in the ROM fuse of the memory cell array 111.

1.2.2 Management data
Next, the management data obtained in FIG. 9 will be described. FIG. 10 is a schematic diagram of the memory cell array 111. As shown in the figure, for example, it is assumed that the block BLK2 is registered in the management block. Then, the management data including this management block information is written in, for example, the block BLK (m−1) (m is a natural number of 2 or more).

FIG. 11 is a schematic diagram of the block BLK (m−1). As shown in the figure, two pages PG in the block BLK (m−1) are used as ROM fuse areas. The management data includes the following information. That is,
(a) Bad column information BCOL
(b) Bad block information BBLK1
(c) Management block information BBLK2
(d) Management block information BBLK3
(e) Trimming information TRIM
(f) Bad word line information BWL
(g) Bad select gate line information BSG
BCOL is information relating to a defective column (defective bit line BL), for example, a column address of the defective column. BBLK1 is information related to a bad block, and is a block address of the bad block, for example. BBLK2 is information regarding the management block including the shorted word line WL, and is, for example, the block address of the management block. BBLK3 is information relating to the management block including the shorted select gate lines SGD and SGS, and is a block address of the management block, for example. The trimming information is trimming information related to the circuit operation of the NAND flash memory 100. BWL is information related to the shorted word line WL, for example, a word line address (page address). BSG is information relating to the shorted select gate lines SGD and SGS, and is, for example, a select gate line address (string address).

  In the example of FIG. 11, information BCOL, BBLK1, BBLK2, BBLK3, and TRIM are held in a certain page PG1, and information BWL and BSG are held in another page PG2.

1.3 Memory system operation
Next, operations of the controller 200 and the NAND flash memory 100 in the memory system configured as described above will be described.

1.3.1 Operation of controller 200
First, the operation of the controller 200 will be described with reference to FIG. FIG. 12 is a flowchart showing a rough flow of the control operation of the NAND flash memory 100 by the controller 200.

  As shown in the drawing, the controller 200 first turns on the NAND flash memory S10 (step S30). Then, the information (management data) in the ROM fuse is received from the NAND flash memory 100 (step S31). The information received in this step is information held in page PG1 in FIG. 11, and includes bad block information BBLK1 and management block information BBLK2 and BBLK3.

  Subsequently, the controller 200 receives the remaining management data from the NAND flash memory 100 (step S32). The information received in this step includes bad word line information BWL and bad select gate line information BSG.

  Steps S31 and S32 may be performed according to a request from the controller 200, or may be performed spontaneously by the NAND flash memory 100 without receiving a request from the controller 200 (POR: Power on Read). ).

  The controller 200 stores the received information in the RAM 220, for example. Then, in response to a request from the host device 300, the NAND flash memory 100 is accessed (step S33). The controller 200 accesses the good block and the management block based on the information BBLK1 to BBLK3 in the RAM 220, and does not access the bad block.

  FIG. 13 shows an example of instructions of the controller 200 for performing read access and write access to the NAND flash memory 100.

The command “Read (x)” is an instruction for reading data from the x address of the good block, and the management block cannot be accessed.
The command “ReadLBLKm (x)” is an instruction for reading data from address x of the management block. A command for controlling the same potential of at least two wirings that are short-circuited is included. However, the defective word line itself in the management block cannot be accessed.
The command “Program (x)” is an instruction for writing data to the x address of the good block, and the management block cannot be accessed.
The command “ProgramLBLKm (x)” is an instruction for writing data to the x address of the management block. A command for controlling the same potential of at least two wirings that are short-circuited is included. However, the defective word line itself in the management block cannot be accessed.

1.3.2 Operation of NAND flash memory 100
Next, the operation of the NAND flash memory 100 will be described with reference to FIG. FIG. 14 is a flowchart showing a rough flow of the operation of the NAND flash memory 100.

  As shown in the figure, when the NAND flash memory 100 is activated when power is turned on by the controller 200 (step S40), first, data is read from the ROM fuse. More specifically, first, data is read from the page PG1 in FIG. 11, and the read data is transferred to the controller 200 (step S41). In this step, information BBLK 1 to BBLK 3 is transferred to the controller 200.

  Subsequently, the NAND flash memory 100 reads data from the page PG2 in FIG. 11, and transfers the read data to the controller 200 (step S42). In this step, information BWL and BSG are transferred to the controller 200.

  The processes in steps S41 and S42 are performed immediately after activation. Thereafter, when an access command for the good block or the management block is received from the controller 200 (step S43), processing is performed according to the received command (step S44).

  FIG. 15 is a flowchart showing details of step S44. As shown in the figure, when the good block is accessed (step S50, NO), the NAND flash memory 100 performs normal control. That is, according to the page address, each of the drivers 52 to 54 applies a predetermined voltage to the selected word line, the non-selected word line, and the select gate line (step S52). As a result, data programming, reading, or erasing is executed (step S53). Then, the NAND flash memory 100 returns the processing status (pass or fail) to the controller 200 (step S54).

  When the management block (BBLK2 or BBLK3) is accessed (step S50, YES), the NAND flash memory 100 sets the two shorted wires to the same potential (step S51). For example, in the case of a management block in which a word line is shorted, the shorted word line is set to the same potential. The same applies to the select gate lines SGD and SGS. For other wirings, the same control as normal is performed (step S52).

  This state is shown in FIGS. 16 to 18 are circuit diagrams of the good block BLK0 and the management block BLK1.

  FIG. 16 shows a case where two word lines WL1 and WL2 are short-circuited in the management block BLK1. In this case, the two word lines WL1 and WL2 are always at the same potential. That is, the CG drivers 51-1 and 51-2 described with reference to FIG. 8 always output the same potential when the management block BLK1 is selected. Such control is not performed for the good block BLK0.

  FIG. 17 shows a case where two select gate lines SGS0 and SGS1 are short-circuited in the management block BLK1. In this case, the two select gate lines SGS0 and SGS1 are always at the same potential. That is, the SGS drivers 53-0 and 53-1 described with reference to FIG. 8 always output the same potential when the management block BLK1 is selected.

  FIG. 18 shows a case where two select gate lines SGD0 and SGD1 are short-circuited in the management block BLK1. In this case, the two select gate lines SGD0 and SGD1 are always at the same potential. That is, the SGD drivers 52-0 and 52-1 described with reference to FIG. 8 always output the same potential when the management block BLK1 is selected.

1.4 Effects of this embodiment
As described with reference to FIGS. 4 to 7, in the three-dimensional stacked NAND flash memory, the bit line BL and the source line SL are connected by the memory hole 24. In order to select each memory hole 24, there are select gate lines SGD and SGS. Further, a plurality of word lines WL are formed.

  As described above, the select gate lines SGD and SGS are individually separated, but the word line WL is common to each layer (see FIGS. 3, 6, and 7). The reason for this is that if each word line WL is divided for each string group GP, the number of word lines (the number of CG lines) increases as the number of stacked word lines WL increases, making it difficult to draw out CG lines and arrange decoders. Because it becomes.

  By sharing the word line WL, an increase in the area of the chip is suppressed. On the other hand, sharing the word line WL increases the block size. As is clear from FIG. 3, one string group GP corresponds to one block in a planar NAND flash memory in which memory cells are two-dimensionally formed. That is, one block size of the three-dimensional stacked NAND flash memory corresponds to several block sizes of the planar NAND flash memory.

  As the block size increases, the erase unit increases. As a result, there is a risk that the manufacturing yield may be reduced due to a decrease in performance or an increase in defective replacement units. Possible defects that may occur include a short circuit between adjacent word lines in the vertical direction, a short circuit between adjacent select gate lines SGS lines, and a short circuit between adjacent select gate lines SGD lines. Any of these defects becomes a block defect in the conventional treatment. That is, it is treated as a bad block and the entire block is prohibited. Therefore, there is a concern that the number of bad blocks increases and the manufacturing yield decreases.

  In this regard, in the present embodiment, appropriate voltage control is performed on a block in which a short circuit defect has occurred. As a result, it is possible to prevent the short-circuit failure from adversely affecting the operation and to prevent the block from being a bad block.

  That is, in addition to the conventional bad block information BBLK1, the ROM fuse has information BBLK2 and BBLK3 related to the block in which the short defect has occurred. More specifically, at the time of the test, a block leak check is performed, and if the leak amount exceeds the range considered as a good block, but is within a predetermined range, it is registered as a management block.

  The controller 200 accesses the NAND flash memory 100 based on the information BBLK1 to BBLK3. Then, based on the information BWL and / or BSG, the controller 200 determines the NAND flash memory 100 so that two or more short-circuited wirings have the same potential with respect to the block in which the short-circuit defect has occurred. To control. By setting the same potential, it is possible to suppress a short circuit failure from affecting the operation.

  As described above, since it is possible to avoid the block from being a bad block only due to the presence of a short circuit defect, the manufacturing yield of the NAND flash memory can be improved.

2. Second embodiment
Next, a semiconductor memory device and its controller according to the second embodiment will be described. In the present embodiment, the operation described in the first embodiment will be described more specifically. Below, only a different point from 1st Embodiment is demonstrated.

2.1 Read operation
First, the read operation will be described.

2.1.1 Bias relation at the time of reading
The bias relationship at the time of reading will be described with reference to FIG. FIG. 19 is a circuit diagram of a certain block BLK. FIG. 19 shows a case where two string groups GP0 and GP1 are included and data is read from the word line WL2 of the string group GP0.

  As shown in the drawing, the bit line BL is precharged to the voltage VPRE by the sense amplifier 113. The driver 144 applies a read voltage VCGR to the selected word line WL2. VCGR is a voltage corresponding to the level to be read. The voltage VREAD is applied to unselected word lines WL0, WL1, and WL3 to WL7. VREAD is a high voltage that turns on the memory cell transistor MT regardless of the retained data. A voltage VCG_BGV is applied to the back gate line BG. VCG_BGV is a voltage that turns on the back gate transistor BT. These voltages are commonly applied to the string groups GP0 and GP1.

  Further, the driver 144 applies a voltage VSG (for example, 5 V) to the select gate lines SGD0 and SGS0. VSG is a voltage that turns on the transistors ST1 and ST2. For example, 0 V is applied to the select gate lines SGD1, SGS1.

  As a result, in the selected string group GP0, the selection transistors ST1 and ST2 are turned on. Therefore, when the memory cell transistor MT of the read target page is turned on, a current flows from the bit line BL to the source line SL. On the other hand, no current flows in the off state.

  On the other hand, in the non-selected string group GP1, the selection transistors ST1 and ST2 are turned off. Therefore, data is not read from the non-selected string group GP1.

  Note that FIG. 19 is merely an example, and for example, a positive voltage VSRC (for example, 2.5 V) may be applied to the source line SL. In this case, the potentials of the bit line BL, the word line WL, the back gate line BG, and the select gate lines SGD, SGS are set to values obtained by further adding VSRC to the voltage described above.

2.1.2 Access to Good Block
Next, read access to the good block will be described with reference to FIG. FIG. 20 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when reading data from the good block. is there.

  As shown in the figure, upon receiving a read access from the host device 300, the controller 200 issues a read command “Read (x)”. In response to this, in the NAND flash memory 100, data is read into the page buffer 120 in units of pages under the control of the sequencer 141.

  Thereafter, the controller 200 reads data in the page buffer 120 serially. That is, for example, data is sequentially read by toggling a clock signal (signal / RE). Thereafter, the controller 200 transfers the read data to the host device 300.

  FIG. 21 is a timing chart of a command sequence on the NAND bus and a ready / busy signal when data is read from the good block. The ready / busy signal (R / B signal) is one of the signals indicating the state of the NAND flash memory 100. When R / B = “H”, the NAND flash memory 100 is in the ready state. Can accept commands. Conversely, when R / B = “L”, the NAND flash memory 100 is busy and does not accept commands.

  As shown in the figure, the controller 200 first issues a command “00h” defined by the NAND interface. “00h” is the first read command, and when “00h” is input, the NAND flash memory 100 can recognize the start of the read operation. Subsequently, the controller 200 issues an address ADD. Thereafter, the controller 200 issues “30h”. “30h” is a second read command. Upon receiving the second read command, the NAND flash memory 100 starts a read operation and enters a busy state. Thereafter, the data D read from the page corresponding to the address ADD is transferred from the page buffer 120 to the controller 200 serially.

  That is, “Read (x)” described with reference to FIG. 20 corresponds to a series of command sequences from “00h” to “30h” in FIG.

2.1.3 Access to management block
Next, read access to the management block will be described with reference to FIG. FIG. 22 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when reading data from the management block. is there.

  As shown in the figure, the difference from FIG. 20 described in the case of the good block is that the same potential control command is issued from the controller 200 to the NAND flash memory 100 together with the command “Read (x)”. That is, “Read_LBLKm (x)” described in FIG. 13 corresponds to a combination of “Read (x)” and the same potential control command. In addition, although the description “SIN” in the figure means rewriting of the SIN code, the details will be described in the fourth embodiment.

  FIG. 23 is a timing chart of a command sequence on the NAND bus and a ready / busy signal when data is read from the management block.

  As shown in the figure, the controller 200 first issues a command “00h” defined by the NAND interface, and then issues an address ADD. Thereafter, the controller 200 issues a new command “xxh”. “Xxh” is a second read command that replaces “30h” and includes, for example, the meaning of the same potential control command. By receiving “xxh”, the NAND flash memory 100 executes a read operation while controlling the shorted wiring at the same potential. Thereafter, the data D is serially transferred to the controller 200. The shorted wiring information can be transmitted to the NAND flash memory by various methods, and an example thereof will be described in the fourth embodiment.

2.2 Write operation
Next, the write operation will be described.

2.2.1 Bias relation at the time of writing
The bias relationship at the time of writing will be described with reference to FIG. FIG. 24 is a circuit diagram of a certain block BLK. FIG. 19 shows a case in which two string groups GP0 and GP1 are included, and data is written to the word line WL2 of the string group GP0.

  As shown in the figure, the sense amplifier 113 applies a voltage VDD or 0 V to the bit line BL according to the write data. A column to which data is to be written (injecting charge into the charge storage layer to increase the threshold) is given 0 V, and a column to which data is not to be written is given VDD. A write voltage VPGM (for example, 20 V, depending on the write level) is applied to the selected word line WL2 by the driver 144. VPGM is a high voltage for injecting charges into the charge storage layer. A voltage VPASS (10 V <VPASS <VPGM) is applied to unselected word lines WL0, WL1, and WL3 to WL7. VPASS is a high voltage that turns on the memory cell transistor MT regardless of the retained data. A voltage VCG_BGV is applied to the back gate line BG. VCG_BGV is a voltage that turns on the back gate transistor BT. These voltages are commonly applied to the string groups GP0 and GP1.

  Further, the driver 144 applies the voltage VSGD to the select gate lines SGD0 and SGS0. VSGD is a voltage that turns on the selection transistor ST1 to which 0 V is applied to the bit line BL (that is, the drain) and cuts off the selection transistor ST2 to which VDD is applied. 0V is applied to the select gate line SGS0, and the select transistor ST2 is turned off. Further, 0 V is also applied to the select gate lines SGD1, SGS1.

  As a result, in the string groups GP0 and GP1, channels are formed in the memory cell transistors MT0 to MT7. In the selected string group GP0, in the NAND string 114 in which 0 V is applied to the bit line BL, the selection transistor ST1 is turned on. Therefore, 0V is transferred to the channel of the memory cell transistor MT2, and charges are injected into the charge storage layer. On the other hand, in the NAND string 114 in which VDD is applied to the bit line BL, the selection transistor ST1 is cut off. As a result, the potential in the NAND string 114 becomes floating, and the potential rises due to coupling with the word line WL. As a result, no charge is injected into the charge storage layer of the memory cell transistor MT2, and no data is written.

  In the unselected string group GP1, the selection transistors ST1 and ST2 are in the off state. Therefore, data is not written to the non-selected string group GP2.

2.2.2 Access to Good Block
Next, write access to the good block will be described with reference to FIG. FIG. 25 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when writing data to the good block. is there.

  As shown in the figure, upon receiving a write access from the host device 300, the controller 200 issues a write command “Program (x)” and transfers the write data to the page buffer 120. In response to this, in the NAND flash memory 100, the data in the page buffer 120 is written in the memory cell array 111 in units of pages under the control of the sequencer 141.

  FIG. 26 is a timing chart of a command sequence on the NAND bus and a ready / busy signal when data is written to the good block.

  As illustrated, the controller 200 first issues a command “80h” defined by the NAND interface. “80h” is the first write command. When “80h” is input, the NAND flash memory 100 recognizes the start of the write operation. Subsequently, the controller 200 issues an address ADD. Further, the controller 200 serially transfers the write data D. Finally, the controller 200 issues “10h”. “10h” is a second write command, and upon receiving the second write command, the NAND flash memory 100 starts a write operation and enters a busy state. Then, the data D in the page buffer 120 is written in units of pages on the page corresponding to the address ADD.

  That is, “Program (x)” and “Data (x)” shown in FIG. 25 correspond to a series of command sequences from “80h” to “10h” in FIG.

2.2.3 Access to management block
Next, write access to the management block will be described with reference to FIG. FIG. 27 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when writing data to the management block. is there.

  As shown in the figure, the difference from FIG. 25 described in the case of the good block is that the controller 200 issues the same potential control command to the NAND flash memory 100 together with the command “Program (x)”. That is, “Program_LBLKm (x)” described in FIG. 13 corresponds to a combination of “Program (x)” and the same potential control command.

  FIG. 28 is a timing chart of a command sequence on the NAND bus and a ready / busy signal when data is written to the management block.

  As illustrated, the controller 200 issues a new command “yyh” instead of “10h” in the sequence described with reference to FIG. “Yyh” is a second write command that replaces “10h” and includes, for example, the meaning of the same potential control command. By receiving “yyh”, the NAND flash memory 100 executes the write operation while controlling the shorted wiring at the same potential.

2.3 Erase operation
Next, the erase operation will be described.

2.2.1 Bias relationship during erasure
The bias relationship at the time of erasing will be described with reference to FIG. FIG. 29 is a circuit diagram of a certain block BLK. FIG. 29 shows a case where data is erased collectively for two string groups GP0 and GP1 included in the block BLK.

  As shown in the figure, the erase voltage VERA (for example, 20 V) is applied to the bit line BL and the source line SL by the driver 144. Further, VERA_SG (for example, 12V) is applied to the select gate lines SGD0, SGD1, SGS0, and SGS1. This causes GIDL (gate induced drain leakage) at the select gate end. Of the hole-electron pairs generated by GIDL, holes enter the pillars 26 having a low voltage. For this reason, the potential of the pillar 26 rises to the erase voltage VERA.

  All word lines WL are applied with 0V, and holes are taken into the charge storage layer, and data is erased.

  Note that erasing can be performed in units of string groups GP. In this case, VERA may be applied to the select gate lines SGD and SGS of the non-selected string group or may be in a floating state.

2.3.2 Access to Good Block
Next, erase access to the good block will be described with reference to FIG. FIG. 30 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when erasing good block data. It is.

  As shown in the figure, upon receiving an erase access from the host device 300, the controller 200 issues an erase command “Erase (x)”. Then, in response to this, the NAND flash memory 100 executes an erase operation according to the control of the sequencer 141.

  FIG. 31 is a timing chart of a command sequence on the NAND bus and a ready / busy signal when erasing data of a good block.

  As shown in the figure, the controller 200 first issues a command “60h” defined by the NAND interface. “60h” is a first erase command. When “60h” is input, the NAND flash memory 100 recognizes the start of the erase operation. Subsequently, the controller 200 issues an address ADD. Finally, the controller 200 issues “D0h”. “D0h” is a second erase command. Upon receiving the second erase command, the NAND flash memory 100 starts an erase operation and enters a busy state. Then, the data in the block BLK (or string group GP) corresponding to the address ADD is erased collectively.

2.3.3 Access to management block
Next, erase access to the management block will be described with reference to FIG. FIG. 32 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when erasing the management block data. It is.

  As shown in the figure, the difference from FIG. 30 described in the case of the good block is that the same potential control command is issued from the controller 200 to the NAND flash memory 100 together with the command “Erase (x)”.

  FIG. 33 is a timing chart of a command sequence on the NAND bus and a ready / busy signal when erasing data in the management block.

  As illustrated, the controller 200 issues a new command “zzh” instead of “D0h” in the sequence described with reference to FIG. 31. “Zzh” is a second write command that replaces “D0h” and includes, for example, the meaning of the same potential control command. By receiving “zzh”, the NAND flash memory 100 executes a write operation while controlling the shorted wiring at the same potential.

2.4 Effects of this embodiment
The first embodiment can be realized by the method described in the present embodiment, for example.

3. Third embodiment
Next, a semiconductor memory device and its controller according to the third embodiment will be described. In the present embodiment, in the first and second embodiments, the bad word line information BWL and the bad select gate line information BSG are read at the time of data access to the NAND flash memory 100, not at power-on. Is. Hereinafter, only differences from the first and second embodiments will be described.

3.1 Operation
An operation of the memory system according to the present embodiment will be described. Since the test operation is the same as that in FIGS. 9 to 11 described in the first embodiment, the description thereof is omitted.

3.1.1 General operation of the controller
First, a rough operation of the controller will be described with reference to FIG. FIG. 34 is a flowchart of the operation of the controller 200, and corresponds to FIG. 12 described in the first embodiment.

  As shown in the drawing, the controller 200 receives the data in the page PG1 of FIG. 11 that has been read by POR (Power on Read) immediately after the power to the NAND flash memory 100 is turned on. That is, the bad block information BBLK1 and the management block information BBLK2 and BBLK3 are received. POR is a read operation spontaneously performed by the NAND flash memory 100 when the NAND flash memory 100 is powered on.

  This embodiment is different from the first embodiment in that the page PG2 is not read in POR.

  If there is an access request from the host device 300, the controller 200 determines whether it is an access to a good block or an access to a management block (step S60). If the access is for a good block (step S60, YES), a normal operation is executed (step S61). That is, it is the same as that of the first embodiment.

  On the other hand, when accessing the management block (step S60, NO), the controller 200 reads the bad word line information BWL or the bad select gate line information BSG corresponding to the management block (step S62). Then, similarly to the first embodiment, the management block is accessed (step S63).

3.1.2 Read operation
Next, a read operation for the management block in the present embodiment will be described with reference to FIG. FIG. 35 is a flowchart showing an operation when the controller 200 in the idle state receives a read access from the host device 300.

  As shown in the figure, when it is an access to a good block (step S70), the controller 200 issues a normal read command. This case is the same as FIGS. 20 to 21 described in the second embodiment.

  When the access is to the management block BBLK2 including the word line short defect (step S72), the controller 200 reads the BWL information (step S73). Thereafter, a read command for BBLK2 is issued (step S74). Step S74 is the same as FIG. 22 to FIG. 23 described in the second embodiment.

  When the access is to the management block BBLK3 including the select gate line short defect (step S75), the controller 200 reads the BSG information (step S76). Thereafter, a read command for BBLK3 is issued (step S77). Step S77 is the same as FIG. 22 to FIG. 23 described in the second embodiment.

  FIG. 36 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when reading data from the management block. is there.

  As shown in the figure, the difference from the example of FIG. 22 described in the second embodiment is that the process of reading management data is performed before the controller 200 issues the command “Read (x)”.

  That is, upon receiving a read access from the host device 300, the controller 200 issues a read command “Read (L)”. Then, in response to this, in the NAND flash memory 100, the management data (BWL and / or BSG) is read into the page buffer 120 in units of pages under the control of the sequencer 141.

  Thereafter, the controller 200 reads data in the page buffer 120 serially. As a result, the controller 200 can grasp where in the management block to be accessed there is a word line short defect or a select gate line defect.

  The subsequent processing is the same as in the case of FIG.

3.1.3 Write operation
Next, a write operation to the management block in this embodiment will be described with reference to FIG. FIG. 37 is a flowchart showing an operation when the controller 200 in the idle state receives a write access from the host device 300.

  As shown in the figure, when it is an access to a good block (step S80), the controller 200 issues a normal write command. This case is the same as FIGS. 25 to 26 described in the second embodiment.

  When the access is to the management block BBLK2 including the word line short defect (step S82), the controller 200 reads the BWL information (step S83). Thereafter, a write command for BBLK2 is issued (step S84). Step S84 is the same as FIG. 27 to FIG. 28 described in the second embodiment.

  When the access is to the management block BBLK3 including the select gate line short defect (step S85), the controller 200 reads the BSG information (step S86). Thereafter, a write command for BBLK3 is issued (step S87). Step S87 is the same as FIG. 27 to FIG. 28 described in the second embodiment.

  FIG. 38 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when writing data to the management block. is there.

  As shown in the figure, the difference from the example of FIG. 27 described in the second embodiment is that the process of reading the management data is performed before the controller 200 issues the command “Program (x)”.

  That is, upon receiving a write access from the host device 300, the controller 200 issues a read command “Read (L)”. Then, in response to this, in the NAND flash memory 100, the management data (BWL and / or BSG) is read into the page buffer 120 in units of pages under the control of the sequencer 141.

  Thereafter, the controller 200 reads data in the page buffer 120 serially. As a result, the controller 200 can grasp where in the management block to be accessed there is a word line short defect or a select gate line defect.

  The subsequent processing is the same as in the case of FIG.

3.1.4 Erase operation
Next, the erase operation for the management block in the present embodiment will be described with reference to FIG. FIG. 39 is a flowchart showing an operation when the controller 200 in the idle state receives an erase access from the host device 300.

  As shown in the figure, if the access is for a good block (step S90), the controller 200 issues a normal erase command. This case is the same as FIGS. 30 to 31 described in the second embodiment.

  When the access is to the management block BBLK2 including the word line short defect (step S92), the controller 200 reads the BWL information (step S93). Thereafter, an erase command for BBLK2 is issued (step S94). Step S94 is the same as that shown in FIGS. 32 to 33 described in the second embodiment.

  When the access is to the management block BBLK3 including the select gate line short defect (step S95), the controller 200 reads the BSG information (step S96). Thereafter, an erase command for BBLK3 is issued (step S97). Step S97 is the same as that shown in FIGS. 32 to 33 described in the second embodiment.

  FIG. 40 is a flowchart showing the flow of instructions among the host device 300, the controller 200, and the NAND flash memory (the input / output unit 130, the page buffer 120, and the core unit 110) when erasing the management block data. It is.

  As shown in the figure, the difference from the example of FIG. 32 described in the second embodiment is that the process of reading the management data is performed before the controller 200 issues the command “Erase (x)”. The method of reading the management data is the same as that at the time of reading and writing.

3.2 Effects of this embodiment
In the method according to the present embodiment, it is not necessary to read information BWL and BSG by POR when the NAND flash memory 100 is powered on. Therefore, the NAND flash memory can be started up at high speed.

  Note that after reading the information BWL and BSG for a certain management block and transferring them to the controller 200, it is not necessary to read the information BWL and BSG again when accessing the same management block.

4). Fourth embodiment
Next, a semiconductor memory device and its controller according to the fourth embodiment will be described. This embodiment shows an example of control for setting the shorted wiring to the same potential in the first to third embodiments. Hereinafter, only differences from the first to third embodiments will be described.

4.1 About the SIN code register
The NAND flash memory 100 includes a SIN code register in the register 143, for example. The SIN code is information regarding a voltage to be applied to each word line WL in data reading, writing, and erasing. The SIN code register holds such information, and the sequencer 141 and the driver 144 apply a desired voltage to each word line WL based on the information in the SIN code register.

  FIG. 41 is a circuit diagram of the SIN code register. As illustrated, the SIN code register 145 includes a latch circuit 60 (60-0 to 60-7), a buffer circuit 61, and a control unit (logic circuit) 62.

  The latch circuits 60-0 to 60-7 correspond to the word lines WL0 to WL7, respectively, and hold information to be applied to the word lines WL. The buffer circuit 61 temporarily holds the SIN code given from the control unit 62 and transfers it to each latch circuit 60.

  The control unit 62 includes a normal control unit 63, an interrupt control unit 64, and a selector 65. The normal control unit 63 issues a SIN code when the access target block is a good block. The interrupt control unit 64 holds the SIN code given from the controller 200 when the access target block is a management block. The selector 65 selects either the SIN code given from the normal control unit 63 or the SIN code given from the interrupt control unit 64 based on the selection signal SEL, and transfers it to the buffer circuit 61.

  The control unit 62 generates a clock CLK. In synchronization with the clock CLK, the buffer circuit 61 and the latch circuit 60 take in the signals.

4.2 How to set SIN code
Next, a method for setting the SIN code in the register 145 having the above configuration will be described. FIG. 42 is a timing chart showing the clock CLK and the SIN code set in each latch circuit 60.

  As shown in the figure, when the SIN code is transferred to the buffer circuit 61, voltage information to be applied to each word line WL is set in order from the latch circuit 60-0 in synchronization with the clock.

4.4 Rewriting operation of SIN code
Next, the SIN code rewriting operation will be described. In the present embodiment, the SIN code is rewritten to set the shorted wiring to the same potential. That is, for example, when the two word lines WL0 and WL1 are short-circuited, the SIN codes of the corresponding latch circuits 60-0 and 60-1 are rewritten so that the codes are the same.

  First, the reading operation will be described with reference to FIG. FIG. 43 shows a command sequence at the time of reading.

  As illustrated, after the command “00h”, the address ADD, and the command “xxh” are issued, the controller 200 issues a SIN code, and finally issues a second read command “30h”. When “xxh” is issued, the selector 65 selects the SIN code received from the controller 200 that is given from the interrupt control unit 64. As a result, the latch circuits 60-0 to 60-7 store a code such that the shorted word lines have the same potential.

  Next, the write operation will be described with reference to FIG. FIG. 44 shows a command sequence at the time of writing.

  As shown in the figure, after the command “80h”, the address ADD, the data D, and the command “yyh” are issued, the controller 200 issues a SIN code, and finally issues a second write command “10h”. When “yyh” is issued, the selector 65 selects the SIN code received from the controller 200 that is given from the interrupt control unit 64. As a result, the latch circuits 60-0 to 60-7 store a code such that the shorted word lines have the same potential.

4.5 Effects of this embodiment
The same potential control described in the first to third embodiments can be realized by the method according to the present embodiment, for example.

5. Fifth embodiment
Next, a semiconductor memory device and its controller according to a fifth embodiment will be described. The present embodiment is a measure against a short circuit defect that occurs after shipment of the NAND flash memory 100, that is, an acquired defect. Hereinafter, only differences from the first to fourth embodiments will be described.

5.1 About the first method
FIG. 45 is a schematic diagram of the memory cell array 111 according to the present embodiment. As illustrated, the memory cell array 111 includes an update management data holding unit in addition to the ROM fuse. The update management data holding unit is an area for holding acquired defect information (BBLK2, BBLK3, BWL, BSG). Accordingly, read and write access is possible by the controller 200, but erasure is prohibited. Access by the host device 300 is also prohibited. Further, it may be set to be read by POR.

  FIG. 46 is a flowchart showing an acquired defect inspection method. As shown in the figure, the controller 200 erases one of the blocks BLK (step S100). The status is checked (step S101). If there is a block that has failed status (erase failed), the block BLK is registered in the bad block or the management block according to the leak amount (step S102). This determination is the same as steps S11 to S17 described in the first embodiment.

  When any block BLK is registered as a management block, the controller specifies a defective part (step S103). After the identification, the defect information (BBLK2, BBLK3, BWL, BSG) is written in the update management data holding unit.

  The management data in the update management data holding unit may be voluntarily transmitted to the controller 200 by the NAND flash memory 100 at any timing, or may be transmitted in response to a request from the controller 200.

  In addition, the timing for performing the above inspection may be performed in response to a request from the controller 200, or the NAND flash memory 100 performs spontaneously at any timing when data access from the controller is not performed. May be.

  In the NAND interface, “Dfh” is defined as a leak check command between word lines. Therefore, this command may be used.

5.2 About the second method
Next, the second method will be described. As in the first method, the controller 200 may appropriately perform the operation of FIG. 9 described in the first embodiment, instead of the timing of the erase operation. Then, the defect found at that time is written in the update management data holding unit described with reference to FIG.

5.3 Effects of the present embodiment
In the method according to the present embodiment, even when a failure occurs during use, the block does not necessarily need to be a bad block, and may continue to be used as a management block. Therefore, user convenience can be improved.

6). Sixth embodiment
Next, a semiconductor memory device and its controller according to a sixth embodiment will be described. In the present embodiment, a failure that may occur in the three-dimensional stacked NAND flash memory, including the failure described in the first to fifth embodiments, and countermeasures against the failure will be described. Hereinafter, only differences from the first to fifth embodiments will be described.

  FIG. 47 is a diagram showing the types of defects and their remedies. 48 to 50 are a perspective view, a cross-sectional view, and a plan view of a word line, respectively, of the memory cell array, and illustrate possible defects.

6.1 CASE I
First, the defective CASE I is a short between adjacent memory holes MH in the direction along the select gate line SG (see FIG. 50). This defect is apparently observed as a short circuit between adjacent bit lines and is treated as a column defect. In this case, the defect is remedied by a column redundancy technique.

  The column redundancy is a technique for repairing a defective column by replacing the defective column with a redundancy column provided separately. In the case of CASE I, it is observed as a short defect of at least two bit lines, so at least two columns (columns including two bit lines) are replaced with redundancy columns.

6.2 CASE II
CASE II is a short between adjacent memory holes MH in the direction along the bit line BL (see FIGS. 48 to 50). This defect is apparently observed as a column defect. Also in this case, as in CASE I, the defect is remedied by the column redundancy technique.

  Unlike CASE I, in CASE II, a plurality of shorted memory holes MH exist in the same column. Therefore, if redundancy can be performed in units of one column (a column including one bit line), only that one column needs to be replaced.

6.3 CASE III
CASE III is a short circuit between the select gate lines SGD and SGS in the same NAND string 114 (see FIG. 49). This defect is apparently observed as a block defect, but only one memory group GP actually has a defect. Conventionally, such a block is registered in a bad block, and all the memory cells in the block cannot be used.

  However, the defect of CASE III is remedied by the method described in the first to fifth embodiments. That is, the controller 200 can recognize that the select gate lines SGD and SGS are short-circuited based on the management data. Therefore, when this block is accessed, the shorted select gate lines SGD and SGS are controlled to have the same potential. As a result, a block containing a CASE III defect can be relieved.

6.4 CASE IV
CASE IV is a short circuit of the select gate line SGD between the NAND strings 114 (see FIG. 48). This defect is also apparently observed as a block defect, but only two memory groups GP actually have a defect. Conventionally, such a block is also a bad block.

  However, the defect of CASE IV is also remedied by the method described in the first to fifth embodiments. That is, the controller 200 performs control so that at least two select gate lines SGD that are short-circuited have the same potential based on the management data. As a result, a block including a CASE IV defect can be relieved.

  When the select gate line is shorted between different strings, a plurality of strings including the shorted select gate line cannot be used. That is, these strings are always in a non-selected state. The controller 200 does not access these unselected strings. However, in the case of operations such as block batch data writing such as Flash Write, all the defective strings perform the same operation, so there is no particular problem. The same applies to CASE IV.

6.5 CASE V
CASE V is a short circuit of the select gate line SGS between the NAND strings 114 (see FIG. 49). This defect can be dealt with similarly to CASE IV. In other words, the controller 200 sets at least two shorted select gate lines SGS to the same potential based on the management data.

6.6 CASE VI
CASE VI is a short of the word line WL adjacent in the direction along the bit line BL (see FIGS. 49 and 50). This defect is also observed as a block defect apparently. As described above, in the three-dimensional stacked NAND flash memory, the word line WL is shared by a plurality of strings. Therefore, a short of the word line WL leads to a failure of the entire block. Therefore, conventionally, such a block is a bad block.

  However, the defect of CASE VI can be remedied by setting the shorted word line WL to the same potential as described in the first to fifth embodiments.

6.7 CASE VII
CASE VII is a short circuit between word lines WL adjacent in the direction along the memory hole MH (the vertical direction with respect to the surface of the semiconductor substrate) (see FIGS. 49 and 50). This defect can be remedied similarly to CASE VI.

6.8 CASE VIII
CASE VIII is a short circuit between the source line SL (D0) and the select gate line SGS (see FIG. 49). In the drawings of this specification, the symbol “D0” means a metal wiring layer provided at the lowest level on the NAND string, and the symbol “D1” is higher than “D0”. It means a metal wiring layer provided in the level.

  The source line SL may be different for each block or may be shared between the blocks. In the former case, the failure of CASE VIII is a block failure, and in the latter case, it is a failure of the entire memory cell array 111.

  In such a case, the controller 200 sets the shorted source line SL and the select gate line SGS to the same potential. In this example, the management data includes defective source line information, and this information is written to page PG1 or PG2 in FIG.

6.9 CASE IX
CASE IX is a short circuit between the contact plug C1 (D0) and the select gate line SGD (see FIG. 49). The contact plug C1 is formed at the D0 level, and connects the drain of the selection transistor ST1 and the bit line BL. This defect is remedied by the column redundancy technique as in CASE I and II.

6.10 CASE X
CASE X is a short circuit between the contact plug C1 (D0) and the source line SL (see FIG. 49). This defect can be dealt with in the same way as CASE IX.

7). Modifications etc.
As described above, the semiconductor memory device 1 according to the embodiment includes a memory cell array (111 @ FIG. 2) capable of storing data in a nonvolatile manner, and a control unit (140 @ FIG. 2) that performs data access control on the memory cell array. It comprises. The memory cell array includes a plurality of blocks. The blocks include first and second selection transistors, each of which includes a charge storage layer and a control gate, and is stacked on a semiconductor substrate, and the first and second selection transistors. A plurality of memory cell transistors connected in series between the transistors, first and second select gate lines connected to the gates of the first and second select transistors, respectively, and connected to the gates of the memory cell transistors, respectively A word line. Any one of the blocks holds information (BWL, BSG @ FIG. 11) regarding any word line in which a short circuit defect has occurred or the first and second select gate lines.

  With this configuration, it is possible to remedy a short circuit failure between wirings and improve the use efficiency of the memory space of the semiconductor memory device. The embodiments are not limited to those described above, and various modifications can be made.

  In the above embodiment, the case where only one defect of the word line short or the select gate line short is included in one block has been described as an example. However, a plurality of defects described in FIG. 47 may be included in the access target block (or string).

  In the above embodiment, the case where management data is written in the ROM fuse has been described as an example. However, if the configuration is such that the management data is held in the controller 200 when the test is performed, it is not necessary to write the management data to the ROM fuse. Such a method is suitable for a semiconductor device in which the NAND flash memory 100 and the controller 200 are integrated (a product sold in an integrated manner).

  Also, the page PG2 described with reference to FIG. 11 does not necessarily have to be handled as a ROM fuse, and may be an area secured as a management data dedicated area, which is separate from the ROM fuse. That is, the information BWL and BSG are not read by POR. However, this area is an area in which access by the user (host device 300) is prohibited, and only appending, for example, by the controller 200 is allowed (deletion is also prohibited). Of course, even in such a case, it may be read by POR by setting.

  In the second embodiment, the case where the information BWL and BSG is transferred to the controller 200 when accessing the NAND flash memory 100 has been described. In the present embodiment, the following two methods are conceivable. The first method is a method in which BOR and BSG are not read in the POR, but are read in accordance with an access command from the host device 300, as described above. In the second method, the NAND flash memory 100 reads BWL and BSG by POR, but does not transfer them to the controller 200 but holds them in the register 143, for example. Then, when there is an access request from the controller 200, the BWL and BSG in the register 143 are transferred to the controller 200. Of course, various other methods can be used.

  Furthermore, in the fourth embodiment, a case has been described in which the SIN code is rewritten so that the shorted wiring has the same potential. However, the method for setting the same potential is not limited to rewriting the SIN code, and the command sequence is not limited to the case of FIGS. For example, a new command for inputting a defective address may be prepared, and the controller 200 may input this command and the address of the location where a short circuit has occurred to the NAND flash memory 100. .

  Further, the threshold value of the memory cell transistor MT can be a negative value immediately after erasing data by extracting electrons from the charge storage layer. In the three-dimensional stacked NAND flash memory, a charge storage layer is connected between adjacent memory cell transistors MT. Therefore, when a transistor having a negative threshold and a transistor having a positive threshold are adjacent to each other, charge recombination may occur and data may be destroyed. Therefore, immediately after erasing, a program operation for shifting the threshold value within a certain range having a positive value may be performed.

  When the host device 300 accesses a defective word line, the following two methods are conceivable. One is that the controller 200 does not access the NAND flash memory 100. The other is a method in which the controller 200 converts a received logical address into a physical address of a word line having no defect when converting the logical address into a physical address. The difference between the above two methods is shown in FIG. FIG. 51 is a diagram showing the word lines and the write access order for each word line, and shows the case of a planar NAND flash memory.

  As shown in the figure, when there is no defective word line, data is written in the order of word lines WL (j−1) to WL (j + 3) (j is a natural number). When the word lines WLj and WL (j + 1) are short-circuited, when the controller 200 does not issue an access command to these word lines WL (when command issue is prohibited), the word line WL (j + 2) is accessed next. . On the other hand, when address conversion is performed, when an access command for the defective word line WLj is received, the logical address corresponding to WLj is converted to a physical address corresponding to WL (j + 2). Thereby, the word line WL (j + 2) is regarded as the word line WLj, and this WLj is accessed. FIG. 52 shows a case where each of the memory cell transistors MT holds 3-bit data. Data is written for each bit, and before lower bits of a word line WLk (k is a natural number) are written, lower bits of the word line WL (k−1) are written.

  In the case of a three-dimensional stacked NAND flash, the word line WL is shared between a plurality of strings in the same block. Therefore, as shown in the cross-sectional view of the memory cell array in FIG. 53, the word line WL controlled at the same potential is connected not only to the plurality of word lines WL in the selected string but also to the word line WL. The word lines in the unselected strings are also controlled at the same potential.

  The memory cell array shown in FIG. 2 may be configured as shown in FIG. FIG. 54 is a circuit diagram of the block BLK0, which corresponds to the block BLK0 using the word line pattern as shown in FIG. Other blocks BLK1 to BLK3 may have the same configuration. As illustrated, the word lines WL0 to WL3, the back gate line BG, the even-numbered select gate lines SGD0 and SGD2, and the odd-numbered select gate lines SGS1 and SGS3 are drawn to one end side of the memory cell array 111. In contrast, the word lines WL4 to WL7, the even-numbered select gate lines SGS0 and SGS2, and the odd-numbered select gate lines SGD1 and SGD3 are drawn to the other end side of the memory cell array opposite to the one end side. . Such a configuration may be adopted. In this configuration, for example, the row decoder 112 may be divided into two row decoders, and these may be arranged to face each other with the memory cell array 111 interposed therebetween. One row decoder selects select gate lines SGD0, SGD2, SGS1, SGS3, word lines WL0 to WL3, and back gate line BG, and the other row decoder selects select gate lines SGS0, SGS2, SGD1, SGD3, and The word lines WL4 to WL7 may be selected. According to this configuration, congestion of wiring such as select gate lines and word lines in a region (including the row decoder 112) between the first driver 16 and the memory cell array 111 can be reduced.

  In addition, the values used in the above description for data writing, reading, and erasing are only examples, and it goes without saying that they can be changed as appropriate. In the above embodiment, each memory cell transistor MT can hold data of 1 bit data (binary data) or 2 bits (quaternary data) or more. Further, the above embodiment is not limited to the wiring short of the word line, the select gate line, and the source line, and can be applied to a short circuit defect occurring in other wiring as much as possible.

  Furthermore, in the above-described embodiment, the three-dimensional stacked NAND flash memory has been described as an example of the semiconductor memory device. However, the three-dimensional stacked NAND flash memory is not limited to the configuration shown in FIGS. 3 to 7, and various modifications are possible. The above embodiment is not limited to the NAND flash memory, and can be applied to all semiconductor memory devices as much as possible.

  In addition, the order of the flowcharts described in the above embodiments can be changed as much as possible.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 41 ... Block decoder 51 ... CG driver 52 ... SGD driver 53 ... SGS driver 54 ... BG driver 55 ... Voltage driver 100 ... Semiconductor memory device 110 ... Core part 111 ... Memory cell array 112 ... Row decoder , 113 ... sense amplifier, 114 ... NAND string, 120 ... page buffer, 130 ... input / output unit, 140 ... peripheral circuit, 141 ... sequencer, 142 ... charge pump, 143 ... register, 144 ... driver, 200 ... controller, 210 ... Host interface circuit 220 ... Built-in memory 230 ... Processor 240 ... Buffer memory 250 ... NAND interface circuit 300 ... Host device

Claims (5)

A memory cell array capable of storing data in a nonvolatile manner;
A control unit that performs data access control on the memory cell array, the memory cell array includes a plurality of blocks, and the blocks include:
First and second selection transistors;
A plurality of memory cell transistors each including a charge storage layer and a control gate, stacked on a semiconductor substrate and connected in series between the first and second select transistors;
First and second select gate lines respectively connected to gates of the first and second select transistors;
A word line connected to each of the gates of the memory cell transistors, and any one of the blocks holds information relating to any word line in which a short circuit defect has occurred or the first and second select gate lines. A semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein when one of the blocks including the short-circuit defect is accessed, the control unit sets the wiring having the short-circuit defect to the same potential. A controller for controlling the semiconductor memory device according to claim 1, wherein the controller is
A processor that issues a command for accessing the semiconductor memory device;
And a memory unit capable of holding data, wherein the processor issues different commands when accessing a block including the short defect and when accessing a block not including the short defect. Controller. The controller according to claim 3, wherein the controller receives information on the short-circuit failure from the semiconductor memory device when the power to the semiconductor memory device is turned on, and holds the information in the memory unit. The controller receives bad block information from the semiconductor memory device when power is applied to the semiconductor memory device, and does not receive information regarding the short-circuit failure,
The said processor reads the information regarding the said short defect from the said semiconductor memory device, and hold | maintains it in the said memory part, when the access request to the block containing the said short defect is received from host equipment. 3. The controller according to 3.

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