JP2014050871A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2014050871A
JP2014050871A JP2012198270A JP2012198270A JP2014050871A JP 2014050871 A JP2014050871 A JP 2014050871A JP 2012198270 A JP2012198270 A JP 2012198270A JP 2012198270 A JP2012198270 A JP 2012198270A JP 2014050871 A JP2014050871 A JP 2014050871A
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solder
foil
layer
solder foil
semiconductor
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Yoshiharu Kaneda
芳晴 金田
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To raise reliability of a semiconductor device.SOLUTION: Two solder layers (a first solder layer 2a, a second solder layer 2b) with different melting points are bonded together to form two-layer solder foil (solder foil 2), a solder layer with a lower melting point of the two-layer solder foil is put on a wafer side, the two-layer solder foil is bonded to a semiconductor wafer, arranged on a stage, and the two-layer solder foil and the semiconductor wafer are heated and pressurized at temperature between the different melting points. Thus, since only the solder layer on the side of the wafer with the lower melting point is melted and becomes an adhesive material, the two-layer solder foil (solder foil 2) can be bonded to the semiconductor wafer, and die bonding of a semiconductor chip 1 with solder foil acquired by performing dicing can be performed via a semiconductor member constituted by melting the two solder layers by further performing the die bonding at temperature higher than the respective melting points of the two solder layers by using the semiconductor chip 1.

Description

本発明は、半導体装置の製造技術に関し、例えばダイボンド材として半田材を用いた半導体装置の組み立てに適用して有効な技術に関するものである。   The present invention relates to a semiconductor device manufacturing technique, for example, a technique effective when applied to the assembly of a semiconductor device using a solder material as a die bond material.

半導体素子と接合するサブマウント基板において、半田層に組成分布を設け、基板の表面側（半導体素子と接合する側）の融点を裏面側の融点よりも低くした構造が、例えば特開２００６−２８６９４５号公報（特許文献１）に開示されている。   In a submount substrate to be bonded to a semiconductor element, a structure in which a composition distribution is provided in the solder layer and the melting point on the front surface side (side to be bonded to the semiconductor element) is lower than the melting point on the back surface is disclosed, for example, in No. 1 (Patent Document 1).

また、半導体装置の製造方法において、半導体ウエハとこの半導体ウエハの裏面のメタル部側に配置されたはんだ材とを真空圧着装置のステージ上に用意し、さらに真空圧着装置の金型部を閉じて真空引きを行い、真空引きの終了後に前記はんだ材の融点以下の温度で圧着を行う工程が、例えば特開２００１−１７６８９０号公報（特許文献２）に開示されている。   Further, in the method of manufacturing a semiconductor device, a semiconductor wafer and a solder material disposed on the metal part side of the back surface of the semiconductor wafer are prepared on a stage of a vacuum pressure bonding apparatus, and a mold portion of the vacuum pressure bonding apparatus is closed. For example, Japanese Patent Application Laid-Open No. 2001-176890 (Patent Document 2) discloses a process of performing vacuuming and performing pressure bonding at a temperature equal to or lower than the melting point of the solder material after completion of vacuuming.

特開２００６−２８６９４５号公報JP 2006-286945 A 特開２００１−１７６８９０号公報JP 2001-176890 A

半導体装置において、半導体チップの裏面を電極として用いる場合、ダイボンド材として導電材である半田材が採用されるものがある。   In a semiconductor device, when a back surface of a semiconductor chip is used as an electrode, a solder material that is a conductive material is used as a die bond material.

例えばリードフレームを用いて組み立てられるフレームタイプの上記半導体装置において、半導体チップをダイパッドに接着させる際は、まず、ワイヤ状あるいはリボン状の半田を適量繰り出して、予め半田の融点より高い温度に加熱したダイパッド（板状部材）上に塗布し、塗り広げた半田の上に半導体チップを載せる手法が使われている。   For example, in the frame type semiconductor device assembled using a lead frame, when bonding a semiconductor chip to a die pad, first, an appropriate amount of wire-like or ribbon-like solder is fed out and heated to a temperature higher than the melting point of the solder in advance. A technique is used in which a semiconductor chip is placed on solder that has been applied onto a die pad (plate-shaped member) and spread.

しかしながらこの手法は、半田の塗布量や塗布位置のばらつき、半田内の気泡（ボイド）、半田がダイパッドからはみ出る、さらには半導体チップの四隅で半田厚がばらついて、ダイボンディング後の半導体チップが傾く等の不具合が発生しやすい。   However, this method involves variations in the amount and position of solder applied, bubbles in the solder, solder protruding from the die pad, and variations in the solder thickness at the four corners of the semiconductor chip, causing the semiconductor chip after die bonding to tilt. Such problems are likely to occur.

これらの不具合を解決する手段として、半導体ウエハの段階でその裏面に半田を事前にコーティングする手法が考案されている。   As means for solving these problems, a technique has been devised in which solder is pre-coated on the back surface of a semiconductor wafer.

この事前コーティング手法の一つに、半導体ウエハの裏面に半田箔を貼り付ける手法が知られている。   As one of the pre-coating methods, a method of attaching a solder foil to the back surface of a semiconductor wafer is known.

この手法を用いたのが、特許文献２（特開２００１−１７６８９０号公報）に開示された半導体装置の製造方法である。   This method is used in the semiconductor device manufacturing method disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 2001-176890).

しかしながら、特許文献２に記載された手法で、半田箔を半導体ウエハの裏面に均一に貼り付けることは困難であるとともに、貼り付け後剥れてしまったり、ダイシング時に剥れて半導体チップが飛び散ったり、さらにダイシングブレードが破損することが考えられる。   However, with the technique described in Patent Document 2, it is difficult to uniformly apply the solder foil to the back surface of the semiconductor wafer, and it may be peeled off after attaching, or may be peeled off during dicing and the semiconductor chip may be scattered. Further, it is conceivable that the dicing blade is damaged.

すなわち、特許文献２の手法は、半田材の融点以下の温度で半田材を半導体ウエハに圧着するものであり、この場合、半田箔の温度をその融点以上に上げると、半田が固形から液状となることで、半田の粘度が大幅に下がって半導体ウエハの外に流れ出たり、また流れ出なくとも半田箔全体が大きく軟化する。   That is, the technique of Patent Document 2 is to press the solder material onto the semiconductor wafer at a temperature below the melting point of the solder material. In this case, when the temperature of the solder foil is raised above the melting point, the solder changes from solid to liquid. As a result, the viscosity of the solder is greatly lowered and flows out of the semiconductor wafer, or the entire solder foil is greatly softened without flowing out.

その結果、半導体ウエハと半田箔を圧着させる熱板の平行度の精度が悪くなったりする。さらに、上記平行板と半導体ウエハの間に介在させる緩衝材の弾性により、半田箔の厚みがばらついてしまう現象が発生する。これらの現象の発生を、特許文献２は、半田材の融点以下の温度で半田材を半導体ウエハに圧着することで抑制するというものである。   As a result, the accuracy of the parallelism of the hot plate for pressing the semiconductor wafer and the solder foil is deteriorated. Furthermore, a phenomenon occurs in which the thickness of the solder foil varies due to the elasticity of the buffer material interposed between the parallel plate and the semiconductor wafer. Patent Document 2 discloses that these phenomena are suppressed by pressing the solder material onto the semiconductor wafer at a temperature lower than the melting point of the solder material.

ところが、融点以下で圧着させるためには、固体のままの半田箔を半導体ウエハの裏面に相当の圧力を掛けて圧着する必要があり、半導体ウエハの破損につながりやすい。   However, in order to perform the pressure bonding below the melting point, it is necessary to pressure-bond the solder foil that remains solid to the back surface of the semiconductor wafer by applying a considerable pressure, which is likely to damage the semiconductor wafer.

さらに、上下の熱板（平行板）の平行度、凹凸、また半導体ウエハの厚み、半田の厚みにばらつきがあると、半田箔と半導体ウエハとの面圧がウエハ内でばらつき、面圧が弱いところでは、うまく半田箔が圧着されずに剥れが発生する。逆に強すぎる部位では、半導体ウエハに局部的に大きな圧力が加わり、半導体ウエハの破損やパターンへダメージが発生してしまう。   Furthermore, if the parallelism of the upper and lower hot plates (parallel plates), unevenness, semiconductor wafer thickness, and solder thickness vary, the surface pressure between the solder foil and the semiconductor wafer varies within the wafer, and the surface pressure is weak. By the way, peeling occurs without the solder foil being successfully pressed. On the other hand, in a region that is too strong, a large pressure is locally applied to the semiconductor wafer, and the semiconductor wafer is damaged or the pattern is damaged.

また、半田が溶けてウエハ裏面のメタル層と合金層を形成するわけではなく、単なる圧着状態のため、接合力を上げる事は難しい。その結果、ダイシング等の外力が加わると半田箔が容易に剥れてしまい、チップ飛散やチップ飛散に起因するダイシングブレードの破損に繋がることがある。   In addition, the solder does not melt to form the metal layer and the alloy layer on the back surface of the wafer. As a result, when an external force such as dicing is applied, the solder foil is easily peeled off, which may lead to chip scattering and damage to the dicing blade due to chip scattering.

本願において開示される実施の形態の目的は、半導体装置の組み立てにおいて半導体ウエハに半田箔を均一に貼り付けることができる技術を提供することにある。   An object of an embodiment disclosed in the present application is to provide a technique capable of uniformly affixing a solder foil to a semiconductor wafer in assembling a semiconductor device.

その他の課題と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

一実施の形態の半導体装置の製造方法は、第１半田層と上記第１半田層に積層された第２半田層とから成る半田箔を、半導体ウエハの裏面側に重ね合わせてステージ上に配置し、上記第１半田層の融点と上記第２半田層の融点の間の温度で上記半田箔を加熱する。さらに、上記第２半田層の融点は上記第１半田層の融点より低く、上記第２半田層を上記半導体ウエハ側に配置して上記半田箔を加熱する。   According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device in which a solder foil including a first solder layer and a second solder layer stacked on the first solder layer is placed on a stage so as to overlap a back surface side of a semiconductor wafer. Then, the solder foil is heated at a temperature between the melting point of the first solder layer and the melting point of the second solder layer. Furthermore, the melting point of the second solder layer is lower than the melting point of the first solder layer, and the second solder layer is disposed on the semiconductor wafer side to heat the solder foil.

一実施の形態によれば、例えば半導体ウエハに半田箔を均一に貼り付けることができる。   According to one embodiment, for example, a solder foil can be uniformly attached to a semiconductor wafer.

実施の形態の半導体装置の構造の一例を示す平面図である。It is a top view which shows an example of the structure of the semiconductor device of embodiment. 図１のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure cut | disconnected along the AA line of FIG. 図１の半導体装置の組み立て手順の一例を示すフロー図である。FIG. 2 is a flowchart showing an example of an assembly procedure of the semiconductor device of FIG. 1. 図１の半導体装置の組み立てで用いられる２層半田箔の構造の一例を示す部分断面図である。It is a fragmentary sectional view which shows an example of the structure of the two-layer solder foil used by the assembly of the semiconductor device of FIG. 図４に示す２層半田箔の半導体チップとの接合状態の一例を示す部分断面図である。It is a fragmentary sectional view which shows an example of the joining state with the semiconductor chip of the two-layer solder foil shown in FIG. 図４に示す２層半田箔の組成の一例を示す組成図である。It is a composition diagram which shows an example of a composition of the two-layer solder foil shown in FIG. 図６の２層半田箔の貼り付け条件の一例を示すウエハ−半田箔温度相関図である。It is a wafer-solder foil temperature correlation diagram which shows an example of the bonding conditions of the 2 layer solder foil of FIG. 図４に示す２層半田箔の組成の変形例を示す組成図である。FIG. 5 is a composition diagram showing a modification of the composition of the two-layer solder foil shown in FIG. 4. 図８の２層半田箔の貼り付け条件の変形例を示すウエハ−半田箔温度相関図である。It is a wafer-solder foil temperature correlation diagram which shows the modification of the bonding conditions of the 2 layer solder foil of FIG. 実施の形態の２層半田箔の製造方法の一例を示す側面図である。It is a side view which shows an example of the manufacturing method of the two-layer solder foil of embodiment. 図３の組み立て手順（一部）の一例を示すプロセスフロー図である。FIG. 4 is a process flow diagram illustrating an example of the assembly procedure (part) of FIG. 3. 図３の組み立て手順（一部）の一例を示すプロセスフロー図である。FIG. 4 is a process flow diagram illustrating an example of the assembly procedure (part) of FIG. 3. 図３の組み立て手順（一部）の一例を示すプロセスフロー図である。FIG. 4 is a process flow diagram illustrating an example of the assembly procedure (part) of FIG. 3. 図３の組み立て手順（一部）の一例を示すプロセスフロー図である。FIG. 4 is a process flow diagram illustrating an example of the assembly procedure (part) of FIG. 3. 図３の組み立て手順におけるダイボンディング工程の一例を示す断面図である。It is sectional drawing which shows an example of the die bonding process in the assembly procedure of FIG. 図３の組み立て手順における半田箔貼り付け工程の一例を示すプロセスフロー図である。It is a process flow figure showing an example of a solder foil pasting process in the assembly procedure of FIG. 実施の形態の半田箔貼り付け工程における加熱・加圧方法の一例を示す斜視図である。It is a perspective view which shows an example of the heating and pressurizing method in the solder foil sticking process of embodiment. 図１７の加圧方法の一例を示す断面図である。It is sectional drawing which shows an example of the pressurization method of FIG. 実施の形態の半田箔貼り付け工程の一例を示す概念図である。It is a conceptual diagram which shows an example of the solder foil sticking process of embodiment. 実施の形態の半田箔貼り付け工程の一例を示す概念図である。It is a conceptual diagram which shows an example of the solder foil sticking process of embodiment. 実施の形態の半田箔貼り付け工程のタイムチャートの一例を示すチャート図である。It is a chart figure showing an example of a time chart of a solder foil pasting process of an embodiment.

以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

さらに、以下の実施の形態では便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。   Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

また、以下の実施の形態において、要素の数など（個数、数値、量、範囲などを含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良いものとする。   Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

また、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必ずしも必須のものではないことは言うまでもない。   Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

また、以下の実施の形態において、構成要素等について、「Ａからなる」、「Ａよりなる」、「Ａを有する」、「Ａを含む」と言うときは、特にその要素のみである旨明示した場合等を除き、それ以外の要素を排除するものでないことは言うまでもない。同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示した場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。このことは、上記数値および範囲等についても同様である。   Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

以下、実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、図面をわかりやすくするために平面図であってもハッチングを付す場合がある。   Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Further, even a plan view may be hatched for easy understanding of the drawing.

（実施の形態）
図１は実施の形態の半導体装置の構造の一例を示す平面図、図２は図１のＡ−Ａ線に沿って切断した構造の一例を示す断面図である。 (Embodiment)
FIG. 1 is a plan view showing an example of the structure of the semiconductor device of the embodiment, and FIG. 2 is a cross-sectional view showing an example of the structure cut along the line AA in FIG.

図１、図２に示す本実施の形態の半導体装置は、後述する図１２に示すリードフレーム３を用いて組み立てられるフレームタイプの半導体パッケージ（リード品）であり、本実施の形態では、上記半導体装置の一例として、樹脂封止型のＳＯＰ（Small Outline Package）８を取り上げ、このＳＯＰ８の構造とその製造方法について説明する。   The semiconductor device of the present embodiment shown in FIGS. 1 and 2 is a frame type semiconductor package (lead product) assembled by using a lead frame 3 shown in FIG. 12 to be described later. In the present embodiment, the semiconductor device described above is used. As an example of the apparatus, a resin-encapsulated SOP (Small Outline Package) 8 is taken up, and the structure of the SOP 8 and its manufacturing method will be described.

まず、図１、図２を用いてＳＯＰ８の構造について説明すると、半導体素子（半導体集積回路）１ｄが形成された半導体チップ１と、半導体チップ１の周囲に放射状に配置された複数のインナリード３ｂと、インナリード３ｂと一体に形成された複数のアウタリード３ｃと、半導体チップ１とインナリード３ｂとを電気的に接続する複数のワイヤ７とを有している。   First, the structure of the SOP 8 will be described with reference to FIGS. 1 and 2. The semiconductor chip 1 on which the semiconductor element (semiconductor integrated circuit) 1d is formed, and a plurality of inner leads 3b arranged radially around the semiconductor chip 1 are illustrated. And a plurality of outer leads 3c formed integrally with the inner leads 3b, and a plurality of wires 7 for electrically connecting the semiconductor chip 1 and the inner leads 3b.

すなわち、図２に示すように、半導体チップ１の表面（主面）１ａの周縁部に形成された複数の電極パッド１ｃと、これらの電極パッド１ｃに対応する複数のインナリード３ｂとが複数のワイヤ７によってそれぞれ電気的に接続されている。   That is, as shown in FIG. 2, a plurality of electrode pads 1c formed on the periphery of the surface (main surface) 1a of the semiconductor chip 1 and a plurality of inner leads 3b corresponding to these electrode pads 1c The wires 7 are electrically connected to each other.

さらに、ＳＯＰ８は、半田材からなるダイボンド材２ｃを介して半導体チップ１が固定されるチップ搭載部であるダイパッド（アイランド、タブともいう）３ａと、樹脂封止によって封止用樹脂等から形成され、かつ半導体チップ１とダイパッド３ａと複数のワイヤ７と複数のインナリード３ｂを封止する封止体４とを有している。   Further, the SOP 8 is formed from a die pad (also referred to as an island or a tab) 3a that is a chip mounting portion to which the semiconductor chip 1 is fixed via a die bond material 2c made of a solder material, and a sealing resin or the like by resin sealing. And a sealing body 4 that seals the semiconductor chip 1, the die pad 3a, the plurality of wires 7, and the plurality of inner leads 3b.

また、ＳＯＰ８であるため、複数のインナリード３ｂそれぞれと一体に形成された複数のアウタリード３ｃは、図１に示すように封止体４の側面から外部に向かって相反する２方向に突出しており、各アウタリード３ｃは、図２に示すようにガルウィング状に曲げ成形されている。   Further, since it is SOP8, the plurality of outer leads 3c formed integrally with each of the plurality of inner leads 3b protrude in two opposite directions from the side surface of the sealing body 4 as shown in FIG. Each outer lead 3c is bent into a gull wing shape as shown in FIG.

なお、ＳＯＰ８はワイヤボンディングタイプであるため、半導体チップ１は、その主面（表面）１ａを上方に向けた状態で、ダイパッド３ａの上面３ａａ上にフェイスアップ実装されている。   Since the SOP 8 is a wire bonding type, the semiconductor chip 1 is mounted face-up on the upper surface 3aa of the die pad 3a with the main surface (front surface) 1a facing upward.

すなわち、ダイパッド３ａの上面３ａａと半導体チップ１の裏面１ｂとがダイボンド材（半田材）２ｃを介して接合されている。なお、ＳＯＰ８では、半導体チップ１の裏面１ｂは電極１ｅ（例えば、グランドや電源等の電極）であるため、裏面１ｂと接続されるダイボンド材２ｃとして、導電材である半田材を採用している。   That is, the upper surface 3aa of the die pad 3a and the back surface 1b of the semiconductor chip 1 are joined via the die bond material (solder material) 2c. In SOP 8, since the back surface 1b of the semiconductor chip 1 is an electrode 1e (for example, an electrode such as a ground or a power supply), a solder material, which is a conductive material, is used as the die bond material 2c connected to the back surface 1b. .

また、半導体チップ１の表面１ａに形成された複数の電極パッド１ｃは、それぞれワイヤ７を介してインナリード３ｂと電気的に接続されており、これによって、半導体チップ１と、インナリード３ｂおよび外部端子となるアウタリード３ｃとが電気的に接続されている。   In addition, the plurality of electrode pads 1c formed on the surface 1a of the semiconductor chip 1 are electrically connected to the inner leads 3b through the wires 7, respectively, whereby the semiconductor chip 1, the inner leads 3b, and the external An outer lead 3c serving as a terminal is electrically connected.

つまり、複数のワイヤ７のそれぞれの一端は、半導体チップ１の電極パッド１ｃに電気的に接続されており、一方、複数のワイヤ７のそれぞれの他端は、それぞれのワイヤ７に対応するインナリード３ｂに電気的に接続されている。   That is, one end of each of the plurality of wires 7 is electrically connected to the electrode pad 1 c of the semiconductor chip 1, while the other end of each of the plurality of wires 7 is an inner lead corresponding to each wire 7. It is electrically connected to 3b.

なお、複数のワイヤ７は、例えば、金（Ａｕ）ワイヤや銅（Ｃｕ）ワイヤである。   The plurality of wires 7 are, for example, gold (Au) wires or copper (Cu) wires.

また、インナリード３ｂ、アウタリード３ｃおよびダイパッド３ａは、例えば銅合金や鉄−ニッケル合金等から成る薄板状の部材によって形成され、さらに封止体４は、例えば、熱硬化性のエポキシ系樹脂等から成り、樹脂封止工程で形成されたものである。したがって、封止体４は、インナリード３ｂやダイパッド３ａおよびダイボンド材２ｃ、さらに半導体チップ１および複数のワイヤ７を封止している。   The inner lead 3b, the outer lead 3c, and the die pad 3a are formed of a thin plate member made of, for example, a copper alloy or an iron-nickel alloy, and the sealing body 4 is made of, for example, a thermosetting epoxy resin or the like. Formed by a resin sealing process. Therefore, the sealing body 4 seals the inner lead 3b, the die pad 3a, the die bond material 2c, and the semiconductor chip 1 and the plurality of wires 7.

次に、本実施の形態の半導体装置（ＳＯＰ８）の組み立て手順を、図３に示す製造フロー図に沿って説明する。   Next, the assembly procedure of the semiconductor device (SOP 8) of the present embodiment will be described along the manufacturing flow diagram shown in FIG.

図３は図１の半導体装置の組み立て手順の一例を示すフロー図、図４は図１の半導体装置の組み立てで用いられる２層半田箔の構造の一例を示す部分断面図、図５は図４に示す２層半田箔の半導体チップとの接合状態の一例を示す部分断面図、図６は図４に示す２層半田箔の組成の一例を示す組成図、図７は図６の２層半田箔の貼り付け条件の一例を示すウエハ−半田箔温度相関図である。また、図８は図４に示す２層半田箔の組成の変形例を示す組成図、図９は図８の２層半田箔の貼り付け条件の変形例を示すウエハ−半田箔温度相関図、図１０は実施の形態の２層半田箔の製造方法の一例を示す側面図である。   3 is a flowchart showing an example of the assembly procedure of the semiconductor device of FIG. 1, FIG. 4 is a partial cross-sectional view showing an example of the structure of the two-layer solder foil used in the assembly of the semiconductor device of FIG. 1, and FIG. 6 is a partial cross-sectional view showing an example of a bonding state of the two-layer solder foil shown in FIG. 6 with a semiconductor chip, FIG. 6 is a composition diagram showing an example of the composition of the two-layer solder foil shown in FIG. 4, and FIG. It is a wafer-solder foil temperature correlation diagram which shows an example of the sticking conditions of foil. 8 is a composition diagram showing a modification of the composition of the two-layer solder foil shown in FIG. 4, and FIG. 9 is a wafer-solder foil temperature correlation diagram showing a modification of the bonding condition of the two-layer solder foil of FIG. FIG. 10 is a side view showing an example of the method for manufacturing the two-layer solder foil according to the embodiment.

まず、図３のステップＳ１に示す半田箔貼り付けを行う。ここで、本実施の形態の上記ＳＯＰ８は、ダイパッド３ａに半導体チップ１を固定するダイボンド材２ｃとして、半田材が用いられたものであり、溶融前（ダイボンディング前）の上記半田材（ダイボンド材２ｃ）が、図４に示すような２層構造の半田箔（２層半田箔）２となっている。   First, solder foil attachment shown in step S1 of FIG. 3 is performed. Here, the SOP 8 of the present embodiment uses a solder material as the die bond material 2c for fixing the semiconductor chip 1 to the die pad 3a, and the solder material (die bond material) before melting (before die bonding). 2c) is a two-layered solder foil (two-layer solder foil) 2 as shown in FIG.

すなわち、図５に示すような２層構造の半田箔２が裏面１ｂに貼り付けられた半導体チップ１を取得して（形成して）、この半導体チップ１をダイボンディングしてＳＯＰ８を組み立てるものである。   That is, the semiconductor chip 1 having the two-layered solder foil 2 as shown in FIG. 5 attached to the back surface 1b is obtained (formed), and the semiconductor chip 1 is die-bonded to assemble the SOP 8. is there.

さらに、本実施の形態のＳＯＰ８では、後述する図１１に示すように、半導体ウエハ１１の段階でその裏面１１ｂに２層構造の半田箔２を貼り付け、その後、ダイシングを行って、２層構造の半田箔２が裏面１ｂに貼り付けられた半導体チップ１を取得して組み立てを行うものである。   Further, in the SOP 8 of the present embodiment, as shown in FIG. 11 described later, a two-layer structure solder foil 2 is attached to the back surface 11b of the semiconductor wafer 11 and then dicing is performed to form a two-layer structure. The semiconductor chip 1 having the solder foil 2 attached to the back surface 1b is obtained and assembled.

ここで、本実施の形態でダイボンド材２ｃとして用いられる２層構造の半田箔２について説明する。   Here, the solder foil 2 having a two-layer structure used as the die bond material 2c in the present embodiment will be described.

図４に示すように２層構造の半田箔２は、メイン層となる第１半田層２ａと、コート層となる第２半田層２ｂとから構成される。第１半田層２ａは、図５に示す半導体チップ１を接着するダイボンディング用の半田であり、したがって、チップ接着用として要求される特性を有した半田層である。一方、第２半田層２ｂは、半導体ウエハ１１の裏面１１ｂに溶着可能な特性を有した半田層である。   As shown in FIG. 4, the solder foil 2 having a two-layer structure includes a first solder layer 2a serving as a main layer and a second solder layer 2b serving as a coat layer. The first solder layer 2a is die bonding solder for bonding the semiconductor chip 1 shown in FIG. 5, and is therefore a solder layer having characteristics required for chip bonding. On the other hand, the second solder layer 2 b is a solder layer having a characteristic capable of being welded to the back surface 11 b of the semiconductor wafer 11.

本実施の形態の半田箔２では、第２半田層２ｂの融点（固相点）は、第１半田層２ａの融点（固相点）より低く、第２半田層２ｂの融点（固相点）＜第１半田層２ａの融点（固相点）の関係となっている。   In the solder foil 2 of the present embodiment, the melting point (solid phase point) of the second solder layer 2b is lower than the melting point (solid phase point) of the first solder layer 2a, and the melting point (solid phase point) of the second solder layer 2b. ) <The melting point (solid phase point) of the first solder layer 2a.

そこで、２層構造の半田箔２を半導体ウエハ１１の裏面１１ｂに貼り付ける際には、半導体ウエハ１１側に融点が低い第２半田層２ｂを配置し、この状態で第２半田層２ｂの融点と第１半田層２ａの融点の間の高さの第１温度で加熱することで、この第１温度より融点が低い第２半田層２ｂのみが溶融し、この第２半田層２ｂを接着材として半田箔２を半導体ウエハ１１に貼り付けることができる。   Therefore, when the solder foil 2 having a two-layer structure is attached to the back surface 11b of the semiconductor wafer 11, the second solder layer 2b having a low melting point is disposed on the semiconductor wafer 11 side, and in this state, the melting point of the second solder layer 2b. And the first solder layer 2a are heated at a first temperature that is higher than the melting point of the first solder layer 2a, so that only the second solder layer 2b having a melting point lower than the first temperature is melted. The solder foil 2 can be attached to the semiconductor wafer 11 as follows.

すなわち、異なる融点（固相点）の２種類の半田箔材（第１半田層２ａと第２半田層２ｂ）を貼り合わせて圧延して形成した半田箔２を使用し、２層のうちの低融点側の第２半田層２ｂを半導体ウエハ１１の裏面１１ｂ側に配置し、第１半田層２ａの融点と第２半田層２ｂの融点の間の高さの温度（第１温度）で加圧することで半導体ウエハ１１に半田箔２を接着する。   That is, the solder foil 2 formed by bonding and rolling two kinds of solder foil materials (first solder layer 2a and second solder layer 2b) having different melting points (solid phase points) is used. The second solder layer 2b on the low melting point side is disposed on the back surface 11b side of the semiconductor wafer 11, and is applied at a temperature between the melting point of the first solder layer 2a and the melting point of the second solder layer 2b (first temperature). The solder foil 2 is bonded to the semiconductor wafer 11 by pressing.

これにより、融点が低い方の第２半田層２ｂが接着材となって、図５に示すように半田箔２を半導体チップ１（半導体ウエハ１１）に貼り付けることができる。さらに、後述するダイボンディング工程では、２層構造の半田箔２が貼り付けられた半導体ウエハ１１からダイシングを行って取得した半導体チップ１を用い、後述する図１５に示すように、ダイパッド３ａ上に２層構造の半田箔２を介して半導体チップ１を配置した後、第１半田層２ａの融点より高い第２温度で半田箔２を溶融することで、ダイパッド３ａに半導体チップ１を固定する。   Thus, the second solder layer 2b having the lower melting point becomes an adhesive, and the solder foil 2 can be attached to the semiconductor chip 1 (semiconductor wafer 11) as shown in FIG. Further, in a die bonding process described later, a semiconductor chip 1 obtained by performing dicing from a semiconductor wafer 11 to which a two-layered solder foil 2 is attached is used to form a die pad 3a on a die pad 3a as shown in FIG. After disposing the semiconductor chip 1 via the two-layered solder foil 2, the semiconductor chip 1 is fixed to the die pad 3a by melting the solder foil 2 at a second temperature higher than the melting point of the first solder layer 2a.

ここで、図６は、第１半田層２ａと第２半田層２ｂのそれぞれの組成と融点（固相点）の一例を示すものであり、この組み合わせの場合、第１半田層２ａの融点が２９９℃であり、第２半田層２ｂの融点が２５０℃である。   Here, FIG. 6 shows an example of the composition and melting point (solid phase point) of each of the first solder layer 2a and the second solder layer 2b. In this combination, the melting point of the first solder layer 2a is The second solder layer 2b has a melting point of 250 ° C.

図７は、図６のそれぞれの半田から成る半田箔２を半導体ウエハ１１に接着させた際の接着状態（○、△、×）を温度ごとに評価したものであり、２６０〜２９５℃の範囲で接着状態良好（○）という結果が得られた。したがって、図６に示す半田層の組み合わせから成る半田箔２の場合には、半導体ウエハ１１への接着条件の温度範囲を２６０〜２９５℃の範囲に設定すればよい。   FIG. 7 shows an evaluation of the adhesion state (◯, Δ, x) when the solder foil 2 made of each solder of FIG. 6 is adhered to the semiconductor wafer 11 for each temperature, and a range of 260 to 295 ° C. As a result, a good adhesion state (◯) was obtained. Therefore, in the case of the solder foil 2 composed of the combination of the solder layers shown in FIG. 6, the temperature range of the bonding condition to the semiconductor wafer 11 may be set to a range of 260 to 295 ° C.

つまり、第１半田層２ａと第２半田層２ｂの融点の差が大きければ半導体ウエハ１１への接着条件（加熱条件）の温度範囲の幅も大きくできる。   That is, if the difference between the melting points of the first solder layer 2a and the second solder layer 2b is large, the width of the temperature range of the bonding condition (heating condition) to the semiconductor wafer 11 can be increased.

ただし、第１半田層２ａと第２半田層２ｂの融点の温度差が大き過ぎる（組成の違いが大きい）と、ダイボンディング時に第１半田層２ａと第２半田層２ｂが再溶融して混ざり合った際に、組成の混合が均一になり難く、所謂偏析が起きたり、あるいは融点の変化が大きくなってしまうことがある。したがって、第１半田層２ａと第２半田層２ｂの融点の温度差は大き過ぎない方が好ましい。   However, if the temperature difference between the melting points of the first solder layer 2a and the second solder layer 2b is too large (the difference in composition is large), the first solder layer 2a and the second solder layer 2b are remelted and mixed during die bonding. When they are combined, it is difficult for the composition to be uniformly mixed, so-called segregation may occur, or the change in the melting point may increase. Therefore, it is preferable that the temperature difference between the melting points of the first solder layer 2a and the second solder layer 2b is not too large.

そこで、図８は、融点（固相点）２９９℃の第１半田層２ａと、融点（固相点）２７５℃の第２半田層２ｂとで、融点の温度差が２４℃の場合を取り上げた例であり、図９に示すように、２７５〜２９９℃の範囲において、半導体ウエハ１１への接着条件（加熱条件）の温度範囲として、マージンも含めて２９０±５℃（２８５〜２９５℃、Ａ部斜線領域）を設定することができる。なお、温度の条件幅として、±５℃を確保できていれば、量産性に対して問題なしと判断できる。   8 shows the case where the first solder layer 2a having a melting point (solid phase point) of 299 ° C. and the second solder layer 2b having a melting point (solid phase point) of 275 ° C. have a temperature difference of 24 ° C. As shown in FIG. 9, in the range of 275 to 299 ° C., the temperature range of the bonding condition (heating condition) to the semiconductor wafer 11 is 290 ± 5 ° C. (285 to 295 ° C., including the margin). (A shaded area) can be set. In addition, if ± 5 ° C. can be secured as the temperature condition range, it can be determined that there is no problem with mass productivity.

したがって、図８に示す第１半田層２ａと第２半田層２ｂから成る半田箔２の場合には、半導体ウエハ１１への接着条件の温度範囲を２９０±５℃とすることが好ましい。   Therefore, in the case of the solder foil 2 composed of the first solder layer 2a and the second solder layer 2b shown in FIG. 8, the temperature range of the bonding condition to the semiconductor wafer 11 is preferably 290 ± 5 ° C.

なお、半田箔２を半導体ウエハ１１に接着する際に用いられる熱圧着装置の熱板の温度ばらつき（±５℃程度）とマージンを考慮すると、第１半田層２ａと第２半田層２ｂの融点の差（温度差）は、少なくとも２０℃以上であることが望ましい。さらに本実施の形態の半田箔２では、図７および図９の結果より、第２半田層２ｂの融点が第１半田層２ａの融点より２４、２５℃程度低い組み合わせの場合が最適である。   Note that the melting points of the first solder layer 2a and the second solder layer 2b are considered in consideration of the temperature variation (about ± 5 ° C.) and the margin of the hot plate of the thermocompression bonding apparatus used when the solder foil 2 is bonded to the semiconductor wafer 11. The difference (temperature difference) is desirably at least 20 ° C. or more. Furthermore, in the case of the solder foil 2 of the present embodiment, the combination of the melting point of the second solder layer 2b being about 24 to 25 ° C. lower than the melting point of the first solder layer 2a is optimal from the results of FIGS.

また、図４に示す半田箔２の厚さ（Ｔ１）は、例えば５０μｍである。これは、第１半田層２ａと第２半田層２ｂを重ね合わせて圧延して半田箔２を形成する際に所望の厚さにするものであり、圧延時に５０μｍとするものである。本実施の形態では、チップダイボンド時の厚さと同じ５０μｍとしている。   Moreover, the thickness (T1) of the solder foil 2 shown in FIG. 4 is, for example, 50 μm. This is to make a desired thickness when forming the solder foil 2 by superposing and rolling the first solder layer 2a and the second solder layer 2b, and 50 μm at the time of rolling. In this embodiment, the thickness is 50 μm, which is the same as the thickness at the time of chip die bonding.

なお、２種類の半田箔材の厚さの割合は、重ね合わせ前の厚さの比率で確定される。本実施の形態の半田箔２では、その半田箔２の厚さ（Ｔ１）に対し、第２半田層２ｂの厚さ（Ｔ２）を１０〜６０％まで評価し、その結果、１０〜４０％程度が最適との結果を得た。例えば半田箔２の厚さ（Ｔ１）がＴ１＝５０μｍの場合、第２半田層２ｂの厚さ（Ｔ２）は、Ｔ２＝５〜２０μｍが最適となる。   Note that the ratio of the thicknesses of the two types of solder foil materials is determined by the ratio of the thickness before superposition. In the solder foil 2 of the present embodiment, the thickness (T2) of the second solder layer 2b is evaluated to 10 to 60% with respect to the thickness (T1) of the solder foil 2, and as a result, 10 to 40%. The result was optimal. For example, when the thickness (T1) of the solder foil 2 is T1 = 50 μm, the optimal thickness (T2) of the second solder layer 2b is T2 = 5 to 20 μm.

ただし、条件等によって２種類の半田の最適な厚さの比率は異なるため、圧着後の均一な厚さを確保するためには、第２半田層２ｂの厚さ（Ｔ２）が半田箔２の厚さ（Ｔ１）の５０％以下、好ましくは半田箔２の厚さ（Ｔ１）の１０〜４０％である。   However, since the optimum ratio of the thicknesses of the two types of solder differs depending on the conditions and the like, the thickness (T2) of the second solder layer 2b is set to that of the solder foil 2 in order to ensure a uniform thickness after the pressure bonding. It is 50% or less of the thickness (T1), preferably 10 to 40% of the thickness (T1) of the solder foil 2.

また、図１０は、２種類の半田箔材の貼り合わせ方法の一例を示すものであり、第１リール５から引き出した半田箔材である第１半田層２ａと、第２リール６から引き出した半田箔材である第２半田層２ｂとを複数のローラ１０によって貼り合わせ、および圧延して半田箔２を形成し、最後に巻き取りリール９に巻き取る。   FIG. 10 shows an example of a method for bonding two types of solder foil materials. The solder foil materials are drawn from the first reel 5 and the second reel 6. The second solder layer 2b, which is a solder foil material, is bonded and rolled by a plurality of rollers 10 to form the solder foil 2, and finally wound on the take-up reel 9.

これにより、半田箔２の形成完了となる。   Thereby, the formation of the solder foil 2 is completed.

その後、図１１のステップＳ１（図３のステップＳ１）の半田箔貼り付けを行う。すなわち、半導体ウエハ１１の裏面１１ｂへの半田箔２の貼り付けを行う。   Thereafter, the solder foil is affixed in step S1 of FIG. 11 (step S1 of FIG. 3). That is, the solder foil 2 is attached to the back surface 11 b of the semiconductor wafer 11.

ここでは、まず、主面１１ａおよびこの主面１１ａと反対側の裏面１１ｂを有し、かつ主面１１ａに複数の半導体素子１ｄ（図２参照）が形成された半導体ウエハ１１を準備する。本実施の形態で用いられる半導体ウエハ１１の裏面１１ｂは、例えばグランドや電源等の電極１ｅ（図５参照）となっている。   Here, first, a semiconductor wafer 11 having a main surface 11a and a back surface 11b opposite to the main surface 11a and having a plurality of semiconductor elements 1d (see FIG. 2) formed on the main surface 11a is prepared. The back surface 11b of the semiconductor wafer 11 used in the present embodiment is, for example, an electrode 1e (see FIG. 5) such as a ground or a power supply.

一方、第１半田層２ａと、この第１半田層２ａに積層された第２半田層２ｂとから成る半田箔２を準備する。その際、第２半田層２ｂの融点は第１半田層２ａの融点より低い。例えば、半導体ウエハ１１との接着材の役目を成す第２半田層２ｂの融点（固相点）は、２７５℃であり、ダイボンディング時に接着材となる第１半田層２ａの融点（固相点）は、２９９℃である。   On the other hand, a solder foil 2 comprising a first solder layer 2a and a second solder layer 2b laminated on the first solder layer 2a is prepared. At that time, the melting point of the second solder layer 2b is lower than the melting point of the first solder layer 2a. For example, the melting point (solid phase point) of the second solder layer 2b that serves as an adhesive to the semiconductor wafer 11 is 275 ° C., and the melting point (solid phase point) of the first solder layer 2a that becomes the adhesive during die bonding. ) Is 299 ° C.

その後、図１７および図１８に示すように、半導体ウエハ１１の裏面１１ｂ側に半田箔２を重ね合わせて、加熱可能な下熱板（第１ステージ）１７上に半導体ウエハ１１と半田箔２とを配置する。その際、図１８に示すように第２半田層２ｂを半導体ウエハ１１側に配置して半田箔２を下熱板１７上に搭載する。   Thereafter, as shown in FIGS. 17 and 18, the solder foil 2 is superposed on the back surface 11 b side of the semiconductor wafer 11, and the semiconductor wafer 11 and the solder foil 2 are placed on a heatable lower heat plate (first stage) 17. Place. At that time, as shown in FIG. 18, the second solder layer 2 b is disposed on the semiconductor wafer 11 side and the solder foil 2 is mounted on the lower heating plate 17.

なお、下熱板１７上に半導体ウエハ１１と半田箔２を重ねて配置する方法としては、図１７に示すように、予めウエハサイズと同サイズに円形に切断した半田箔２を準備し、この半田箔２と半導体ウエハ１１とを下熱板１７上に別々に重ねて配置してもよい。あるいは、図１６に示すように、半田箔２を予めウエハサイズより大きめにカットしておき、その後、半田箔２を半導体ウエハ１１に貼り合わせてから同サイズに切断し、この状態の半導体ウエハ１１を下熱板１７上に配置してもよい。   As a method for arranging the semiconductor wafer 11 and the solder foil 2 on the lower heating plate 17, as shown in FIG. 17, the solder foil 2 previously cut into a circle in the same size as the wafer size is prepared. The solder foil 2 and the semiconductor wafer 11 may be separately stacked on the lower heating plate 17. Alternatively, as shown in FIG. 16, the solder foil 2 is cut in advance to be larger than the wafer size, and then the solder foil 2 is bonded to the semiconductor wafer 11 and then cut to the same size. May be disposed on the lower heating plate 17.

ここで、図１６に示す予め半田箔２をウエハサイズより大きめにカットしておく方法について説明する。すなわち、予め半導体ウエハ１１の主面１１ａより広い面積で予備切断された半田箔２を準備し、半導体ウエハ１１の裏面１１ｂ（図１８参照）に上記予備切断された半田箔２を重ね合わせる。この時、まず、図１６のステップＳ１−１の半田箔引き出しに示すように、巻き取り治具（または図１０の巻き取りリール９）１２に巻き取られた半田箔２を引き出し、半導体ウエハ１１の主面１１ａより広い面積で予め半田箔２を予備切断（プリカット）する。すなわち、巻き取り治具１２から引き出した半田箔２を、予めウエハサイズより大きめにカット（切断）しておく。   Here, a method for cutting the solder foil 2 larger than the wafer size in advance as shown in FIG. 16 will be described. That is, the preliminarily cut solder foil 2 having a larger area than the main surface 11a of the semiconductor wafer 11 is prepared, and the preliminarily cut solder foil 2 is superposed on the back surface 11b of the semiconductor wafer 11 (see FIG. 18). At this time, first, as shown in the drawing of the solder foil in step S1-1 in FIG. 16, the solder foil 2 taken up by the winding jig (or the winding reel 9 in FIG. 10) 12 is drawn out, and the semiconductor wafer 11 is drawn. The solder foil 2 is preliminarily cut (precut) in advance in an area wider than the main surface 11a. That is, the solder foil 2 drawn out from the winding jig 12 is cut (cut) in advance to be larger than the wafer size.

その後、ステップＳ１−２の半田箔配置のように、上記予備切断された半田箔２上に半導体ウエハ１１を配置する。この時、図１８に示すように、第２半田層２ｂが半導体ウエハ１１側に位置するように半田箔２を配置する。   Thereafter, the semiconductor wafer 11 is placed on the preliminarily cut solder foil 2 as in the solder foil placement in step S1-2. At this time, as shown in FIG. 18, the solder foil 2 is arranged so that the second solder layer 2b is located on the semiconductor wafer 11 side.

その後、ステップＳ１−３の半田箔貼り合わせのように、表裏を反転させた後、半導体ウエハ１１に半田箔２を貼り合わせる。   Thereafter, the front and back surfaces are reversed as in the case of bonding the solder foil in step S1-3, and then the solder foil 2 is bonded to the semiconductor wafer 11.

その後、ステップＳ１−４の半田箔カットのように、ローラカッター１３等で半田箔２の不用部分を切断除去する。これにより、半導体ウエハ１１の裏面１１ｂ側に半田箔２が貼り合わされた状態となる。   Thereafter, the unnecessary portion of the solder foil 2 is cut and removed by the roller cutter 13 or the like as in the solder foil cutting in step S1-4. As a result, the solder foil 2 is bonded to the back surface 11 b side of the semiconductor wafer 11.

なお、ステップＳ１−３で半導体ウエハ１１の裏面１１ｂに半田箔２を配置した際に、半田箔２上から小さな圧力を印加する程度で、ローラカッター１３等を使用することなく、半田箔２の不用部分を容易に剥がして除去することも可能である。   Note that when the solder foil 2 is disposed on the back surface 11b of the semiconductor wafer 11 in step S1-3, the solder foil 2 can be applied to the solder foil 2 without using the roller cutter 13 or the like by applying a small pressure from the solder foil 2. It is also possible to easily peel off and remove unnecessary portions.

このように、半田箔２を予めウエハサイズより大きめに切断してから、半導体ウエハ１１に貼り合わせ、その後、ウエハと同サイズに切断することにより、貼り合わせ時の半田箔２と半導体ウエハ１１の位置決めを容易に行うことができる。また、ローラカッター１３等の切断用治具を用いることなく、半田箔２の切り代（不用部分）を容易に剥がし取ることもできる。ただし、ローラカッター１３等を用いて切断を行ってもよいことは言うまでもない。   In this way, the solder foil 2 is cut in advance to be larger than the wafer size, and then bonded to the semiconductor wafer 11, and then cut to the same size as the wafer, whereby the solder foil 2 and the semiconductor wafer 11 at the time of bonding are bonded. Positioning can be performed easily. Moreover, the cutting margin (unused part) of the solder foil 2 can be easily peeled off without using a cutting jig such as the roller cutter 13. However, it goes without saying that cutting may be performed using the roller cutter 13 or the like.

なお、図１７および図１８に示すように、下熱板（第１ステージ）１７と上熱板（第２ステージ）１８との間には、緩衝材１５や押し板１６が配置されている。本実施の形態においては、図１８に示すように、下熱板１７上にステンレス鋼等から成る押し板１６が配置され、その上（半田箔２の下方）に下側の緩衝材１５が配置され、一方、半導体ウエハ１１の上方に上側の緩衝材１５が配置されている。   As shown in FIGS. 17 and 18, a cushioning material 15 and a push plate 16 are disposed between the lower heating plate (first stage) 17 and the upper heating plate (second stage) 18. In the present embodiment, as shown in FIG. 18, a pressing plate 16 made of stainless steel or the like is disposed on the lower heating plate 17, and a lower cushioning material 15 is disposed thereon (below the solder foil 2). On the other hand, the upper cushioning material 15 is disposed above the semiconductor wafer 11.

すなわち、半導体ウエハ１１と半田箔２は、下側の緩衝材１５と上側の緩衝材１５によって挟まれた状態で上下から加圧される。なお、緩衝材１５は、例えばポリイミドテープ等である。   That is, the semiconductor wafer 11 and the solder foil 2 are pressed from above and below while being sandwiched between the lower cushioning material 15 and the upper cushioning material 15. The buffer material 15 is, for example, a polyimide tape.

このように、半導体ウエハ１１と半田箔２が緩衝材１５によって挟まれた状態で加圧されることにより、半導体ウエハ１１と半田箔２とに傷が付くことを低減または防止できる。   As described above, the semiconductor wafer 11 and the solder foil 2 are pressed in a state of being sandwiched between the buffer materials 15, so that the semiconductor wafer 11 and the solder foil 2 can be reduced or prevented from being damaged.

次に、半導体ウエハ１１と半田箔２に対して加熱・圧着を行う図１９に示す熱圧着装置１４について説明する。   Next, a thermocompression bonding apparatus 14 shown in FIG. 19 that performs heating and pressure bonding on the semiconductor wafer 11 and the solder foil 2 will be described.

熱圧着装置１４は、内部で熱圧着処理が行われるチャンバ１９と、チャンバ１９を支持する装置架台２１と、チャンバ１９に連通して設けられ、かつチャンバ１９内を真空排気する真空ポンプ２０と、チャンバ１９内に設けられ、かつワーク（例えば半導体ウエハ１１）が配置される下熱板１７および上熱板１８とを備えている。   The thermocompression bonding apparatus 14 includes a chamber 19 in which a thermocompression bonding process is performed, a device base 21 that supports the chamber 19, a vacuum pump 20 that is provided in communication with the chamber 19 and evacuates the chamber 19, A lower heating plate 17 and an upper heating plate 18 are provided in the chamber 19 and on which a workpiece (for example, the semiconductor wafer 11) is disposed.

また、チャンバ１９は、一対を成す下チャンバ１９ａおよび上チャンバ１９ｂから成り、下チャンバ１９ａと上チャンバ１９ｂが開閉自在に設けられている。これにより、ワークの搬入・取り出しを行う際には開いた状態とし、熱圧着処理を行う際には閉じて処理室を形成可能になっている。   The chamber 19 includes a pair of a lower chamber 19a and an upper chamber 19b, and the lower chamber 19a and the upper chamber 19b are provided to be openable and closable. Accordingly, the processing chamber can be formed in an open state when carrying in and taking out the workpiece and closed when performing the thermocompression treatment.

さらに、下チャンバ１９ａと上チャンバ１９ｂが閉じて密閉空間を形成した状態で、真空ポンプ２０によって真空排気を行うことでチャンバ１９内に真空雰囲気を形成することができる。   Further, a vacuum atmosphere can be formed in the chamber 19 by evacuating with the vacuum pump 20 in a state where the lower chamber 19a and the upper chamber 19b are closed to form a sealed space.

また、チャンバ１９内に対向して設けられた一対の下熱板１７および上熱板１８によって、下熱板１７上に配置されたワークを加熱および加圧（熱圧着）可能な構造となっている。   In addition, the work placed on the lower heating plate 17 can be heated and pressurized (thermocompression bonding) by a pair of the lower heating plate 17 and the upper heating plate 18 provided facing the inside of the chamber 19. Yes.

次に、熱圧着装置１４を用いた半田箔２の加熱・圧着方法について説明する。   Next, a method for heating / crimping the solder foil 2 using the thermocompression bonding apparatus 14 will be described.

まず、図１９のＳ１−５に示すワークセットを行う。ワークセット工程では、上チャンバ１９ｂを上昇させてチャンバ１９を開状態とする。   First, the work set shown in S1-5 of FIG. 19 is performed. In the work setting process, the upper chamber 19b is raised to open the chamber 19.

この状態で、重ね合わせた半導体ウエハ１１と半田箔２（図１８参照）を下チャンバ１９ａ内に設けられた下熱板１７上に配置する。本実施の形態では、図１８に示すように、下熱板１７上に設けられた押し板１６の上の緩衝材１５上に、半田箔２が貼り合わされた半導体ウエハ１１を配置する。   In this state, the superposed semiconductor wafer 11 and solder foil 2 (see FIG. 18) are placed on a lower heating plate 17 provided in the lower chamber 19a. In the present embodiment, as shown in FIG. 18, the semiconductor wafer 11 having the solder foil 2 bonded thereto is disposed on the cushioning material 15 on the pressing plate 16 provided on the lower heating plate 17.

その後、図１９および図２１に示すように、上チャンバ１９ｂを下降させ、これにより、下チャンバ１９ａと上チャンバ１９ｂを閉じてチャンバ１９の密閉状態を形成するとともに、真空ポンプ２０によってチャンバ１９内の減圧（脱気、真空排気）を開始する。すなわち、図１９のステップＳ１−６の脱気を開始する。   Thereafter, as shown in FIGS. 19 and 21, the upper chamber 19 b is lowered, thereby closing the lower chamber 19 a and the upper chamber 19 b to form a sealed state of the chamber 19. Start depressurization (deaeration, evacuation). That is, the deaeration in step S1-6 in FIG. 19 is started.

この減圧により、チャンバ１９内の圧力が１０００Ｐａ以下となるように減圧する。   By this pressure reduction, the pressure in the chamber 19 is reduced to 1000 Pa or less.

つまり、図２１に示すように減圧はチャンバ１９内の圧力（真空度）が１０００Ｐａより小さくなるまで続け、１０００Ｐａを完全に下回ったらその時点の圧力を維持してチャンバ１９内に真空雰囲気を形成し、この真空雰囲気で加圧および加熱を行う。   That is, as shown in FIG. 21, the pressure reduction is continued until the pressure (vacuum degree) in the chamber 19 becomes less than 1000 Pa. When the pressure is completely lower than 1000 Pa, the pressure at that time is maintained and a vacuum atmosphere is formed in the chamber 19. Then, pressurization and heating are performed in this vacuum atmosphere.

ここでは減圧によってチャンバ１９内の圧力が１０００Ｐａに到達した時点から所定の真空待機時間（Ｔ３）を経た後、加圧動作を行う。つまり、図１８および図２０のステップＳ１−７に示す加圧を行う。   Here, the pressurization operation is performed after a predetermined vacuum standby time (T3) from the time when the pressure in the chamber 19 reaches 1000 Pa due to decompression. That is, the pressurization shown in step S1-7 in FIGS. 18 and 20 is performed.

本加圧工程では、半導体ウエハ１１と半田箔２を、下熱板１７とこの下熱板１７に対向して配置された上熱板１８とによって加圧および加熱することで、半導体ウエハ１１の裏面１１ｂ側に半田箔２を貼り付ける（接着する）。   In this pressurizing step, the semiconductor wafer 11 and the solder foil 2 are pressed and heated by the lower heating plate 17 and the upper heating plate 18 disposed opposite to the lower heating plate 17, thereby The solder foil 2 is attached (adhered) to the back surface 11b side.

その際、図１８に示すように、上熱板１８の加圧面には緩衝材１５が配置されており、したがって、加圧時には半導体ウエハ１１上にも緩衝材１５が配置された状態となり、半導体ウエハ１１と半田箔２が、その上側と下側で緩衝材１５によって挟まれた状態で加圧が行われる。   At that time, as shown in FIG. 18, the buffer material 15 is disposed on the pressure surface of the upper heating plate 18. Therefore, the buffer material 15 is also disposed on the semiconductor wafer 11 at the time of pressurization, so that the semiconductor Pressurization is performed in a state where the wafer 11 and the solder foil 2 are sandwiched between the upper and lower sides of the buffer material 15.

これにより、加圧時に、半導体ウエハ１１と半田箔２とに傷が付くことを低減または防止できる。   Thereby, it is possible to reduce or prevent the semiconductor wafer 11 and the solder foil 2 from being damaged during pressurization.

また、本加圧工程では、第１半田層２ａと第２半田層２ｂとから成る半田箔２において、第１半田層２ａの融点と第２半田層２ｂの融点の間の高さの第１温度で半田箔２と半導体ウエハ１１を加熱する。   Further, in this pressurizing step, in the solder foil 2 composed of the first solder layer 2a and the second solder layer 2b, the height between the melting point of the first solder layer 2a and the melting point of the second solder layer 2b is the first. The solder foil 2 and the semiconductor wafer 11 are heated at a temperature.

例えば、図８に示す融点（固相点）２９９℃の第１半田層２ａと、融点（固相点）２７５℃の第２半田層２ｂからなる半田箔２を採用した場合、半田箔２の半導体ウエハ１１への接着条件の温度範囲を２９０±５℃とすることが好ましく、この範囲の温度（第１温度）で下熱板１７と上熱板１８とから加熱を行う。   For example, when the solder foil 2 including the first solder layer 2a having a melting point (solid phase point) of 299 ° C. and the second solder layer 2b having a melting point (solid phase point) of 275 ° C. shown in FIG. The temperature range of the bonding condition to the semiconductor wafer 11 is preferably 290 ± 5 ° C., and the lower heating plate 17 and the upper heating plate 18 are heated at a temperature within this range (first temperature).

これにより、２９０±５℃の範囲の第１温度で加熱すると、２９０±５℃より融点が低い第２半田層２ｂは溶融して接着材（半導体ウエハ１１に半田箔２を貼り付ける際の接着材）となるが、２９０±５℃より融点が高い第１半田層２ａは溶融することなくそのまま残る。   Thus, when heated at a first temperature in the range of 290 ± 5 ° C., the second solder layer 2b having a melting point lower than 290 ± 5 ° C. melts and adheres (adhesive when the solder foil 2 is attached to the semiconductor wafer 11) The first solder layer 2a having a melting point higher than 290 ± 5 ° C. remains as it is without melting.

この状態で図２１に示す所定の加圧時間（Ｔ４）の加圧を行い、さらに加熱を行う。   In this state, pressurization is performed for a predetermined pressurization time (T4) shown in FIG. 21, and further heating is performed.

所定の加圧時間（Ｔ４）の経過後、熱圧着装置１４において下熱板１７と上熱板１８による加圧を停止して減圧にするとともに、真空ポンプ２０によるチャンバ１９内の脱気（真空排気）を停止する（真空ブレイク、大気開放）。   After the elapse of a predetermined pressurization time (T4), the thermocompression bonding apparatus 14 stops the pressurization by the lower heat plate 17 and the upper heat plate 18 to reduce the pressure, and the vacuum pump 20 deaerates (vacuums) the chamber 19. Stop (exhaust) (vacuum break, release to atmosphere).

以上により、溶融した第２半田層２ｂを接着材として、図１１に示すように、半導体ウエハ１１の裏面１１ｂに第２半田層２ｂを介して第１半田層２ａ（半田箔２）を貼り付ける（接着する）ことができる。   As described above, the first solder layer 2a (solder foil 2) is attached to the back surface 11b of the semiconductor wafer 11 via the second solder layer 2b, using the melted second solder layer 2b as an adhesive, as shown in FIG. (Glue).

その後、図２１に示すように上チャンバ１９ｂを上昇させ、図２０のステップＳ１−８に示すワーク取り出しを行って、加圧・加熱工程を完了する。   Thereafter, as shown in FIG. 21, the upper chamber 19b is raised, and the workpiece is taken out as shown in step S1-8 in FIG. 20 to complete the pressurizing / heating process.

なお、本加圧工程では、熱圧着装置１４のチャンバ１９内の雰囲気を水素還元雰囲気として加圧および加熱を行ってもよい。すなわち、チャンバ１９内の脱気は行わず、その代わりとして、例えば窒素９０％＋水素１０％の雰囲気（水素還元雰囲気）をチャンバ１９内に形成し、この雰囲気で半田箔２の半導体ウエハ１１への接着（熱圧着）を行うものである。   In this pressurization process, pressurization and heating may be performed using the atmosphere in the chamber 19 of the thermocompression bonding apparatus 14 as a hydrogen reduction atmosphere. That is, the inside of the chamber 19 is not degassed. Instead, for example, an atmosphere of 90% nitrogen + 10% hydrogen (hydrogen reducing atmosphere) is formed in the chamber 19 and the solder foil 2 is transferred to the semiconductor wafer 11 in this atmosphere. Is bonded (thermocompression bonding).

このように水素還元雰囲気で半田箔２の加圧・加熱を行うことにより、半田層の酸化膜を除去することができ、第１半田層２ａと第２半田層２ｂのそれぞれの濡れ性を向上させることができる。   Thus, by pressurizing and heating the solder foil 2 in a hydrogen reducing atmosphere, the oxide film of the solder layer can be removed, and the wettability of each of the first solder layer 2a and the second solder layer 2b is improved. Can be made.

これにより、半田箔２と半導体ウエハ１１の接着の安定化を図ることができる。   As a result, the adhesion between the solder foil 2 and the semiconductor wafer 11 can be stabilized.

半田箔貼り付け工程終了後、図３のステップＳ２のダイシングテープ貼り付けを行う。ここでは、図１１のステップＳ２に示すダイシングテープ貼り付けを行う。つまり、半導体ウエハ１１の裏面１１ｂ側の半田箔２の下面にダイシングテープ２２を貼り付ける。   After completion of the solder foil attaching process, the dicing tape is attached in step S2 of FIG. Here, dicing tape attachment shown in step S2 of FIG. 11 is performed. That is, the dicing tape 22 is attached to the lower surface of the solder foil 2 on the back surface 11 b side of the semiconductor wafer 11.

その後、図３のステップＳ３および図１１のステップＳ３に示すダイシングを行う。ダイシング工程では、半導体ウエハ１１を複数の半導体チップ１に個片化する。その際、ダイシングテープ２２によって半導体ウエハ１１を支持した状態で、ダイシングブレード２３を走行させて半導体ウエハ１１を複数の半導体チップ１に個片化する。   Thereafter, dicing shown in step S3 in FIG. 3 and step S3 in FIG. 11 is performed. In the dicing process, the semiconductor wafer 11 is divided into a plurality of semiconductor chips 1. At that time, with the semiconductor wafer 11 supported by the dicing tape 22, the dicing blade 23 is run to separate the semiconductor wafer 11 into a plurality of semiconductor chips 1.

その後、図３のステップＳ２１および図１２のステップＳ２１に示すリードフレーム準備を行う。ここでは、図１２に示すようなダイパッド（板状部材）３ａや複数のインナリード３ｂおよびアウタリード３ｃを備えたリードフレーム３を準備する。   Thereafter, lead frame preparation shown in step S21 of FIG. 3 and step S21 of FIG. 12 is performed. Here, a lead frame 3 having a die pad (plate member) 3a, a plurality of inner leads 3b, and an outer lead 3c as shown in FIG. 12 is prepared.

その後、図３のステップＳ４および図１２のステップＳ４に示すダイボンディングを行う。本実施の形態のダイボンディング工程では、まず、ダイシング済み（図１１のステップＳ３）のダイシングテープ２２上の複数の半導体チップ１の中から１つの半導体チップ１をピックアップし、図１５のステップＳ４−１に示すダイボンディング用の半導体チップ１を準備する。なお、半導体チップ１の裏面１ｂは、例えばグランドや電源等の電極１ｅとなっている。   Thereafter, die bonding shown in step S4 in FIG. 3 and step S4 in FIG. 12 is performed. In the die bonding process of the present embodiment, first, one semiconductor chip 1 is picked up from the plurality of semiconductor chips 1 on the dicing tape 22 that has been diced (step S3 in FIG. 11), and step S4- in FIG. A semiconductor chip 1 for die bonding shown in FIG. The back surface 1b of the semiconductor chip 1 is an electrode 1e such as a ground or a power supply.

その後、図１５のステップＳ４−２に示すダイボンディング（チップ搭載）を行う。ここでは、半田箔２が裏面１ｂに貼り付けられた半導体チップ１を、半田箔２を介してダイパッド（薄い板状部材）３ａ上に配置する。   Thereafter, die bonding (chip mounting) shown in step S4-2 in FIG. 15 is performed. Here, the semiconductor chip 1 having the solder foil 2 attached to the back surface 1b is disposed on the die pad (thin plate member) 3a via the solder foil 2.

この時、ダイパッド３ａは第１半田層２ａの融点（２９９℃）より高い第２温度で加熱されている。この第２温度は、ダイボンディング温度であり、例えば３６０℃である。   At this time, the die pad 3a is heated at a second temperature higher than the melting point (299 ° C.) of the first solder layer 2a. This second temperature is a die bonding temperature, for example, 360 ° C.

これにより、図１５のステップ４−３の半田溶融に示すように、ダイパッド３ａ上の半田箔２（第１半田層２ａ）を加熱して、半田箔２が溶融されて成るダイボンド材（半田材）２ｃを介して半導体チップ１をダイパッド（板状部材）３ａに接合する。その際、半田箔２の第１半田層２ａの融点は２９９℃であり、第２半田層２ｂの融点は２７５℃であるため、ダイボンド温度（第２温度）３６０℃によって、両半田材（第１半田層２ａと第２半田層２ｂ）とも溶融し、両半田層が混ざり合う。   As a result, as shown in the solder melting in Step 4-3 of FIG. 15, the solder foil 2 (first solder layer 2a) on the die pad 3a is heated to melt the solder foil 2 (solder material). ) The semiconductor chip 1 is bonded to the die pad (plate member) 3a via 2c. At that time, since the melting point of the first solder layer 2a of the solder foil 2 is 299 ° C. and the melting point of the second solder layer 2b is 275 ° C., both the solder materials (first soldering temperature) (second temperature) are set to 360 ° C. Both the first solder layer 2a and the second solder layer 2b) are melted and the two solder layers are mixed.

その結果、組成も均一化され、混ざり合った後の半田材の融点は、第１半田層２ａの融点と第２半田層２ｂの融点の間の高さの温度となる。   As a result, the composition is made uniform, and the melting point of the solder material after mixing is a high temperature between the melting point of the first solder layer 2a and the melting point of the second solder layer 2b.

このようにダイボンディング温度（第２温度）：３６０℃で加熱することにより、第１半田層２ａと第２半田層２ｂが溶融して組成が混ざり合い、ダイボンド材２ｃとなって半導体チップ１をダイパッド３ａに接合することができる。なお、半導体チップ１の裏面１ｂが、グランドや電源等の電極１ｅとなっている場合であっても、ダイボンド材２ｃが導電性の半田材であるため、チップ裏面の電極１ｅとダイパッド３ａをダイボンド材２ｃを介して電気的に接続することができ、グランドや電源の安定化を図ることができる。   Thus, by heating at a die bonding temperature (second temperature) of 360 ° C., the first solder layer 2a and the second solder layer 2b are melted and the composition is mixed, and the semiconductor chip 1 is formed as a die bond material 2c. It can be joined to the die pad 3a. Even when the back surface 1b of the semiconductor chip 1 is an electrode 1e such as a ground or a power supply, the die bond material 2c is a conductive solder material, and therefore the electrode 1e on the back surface of the chip and the die pad 3a are die bonded. It can be electrically connected via the material 2c, and the ground and the power source can be stabilized.

なお、図６に示す組成の第１半田層２ａと第２半田層２ｂとからなる半田箔２を採用した場合であっても図８に示す半田材の場合と同様の効果を得ることができる。   Even when the solder foil 2 composed of the first solder layer 2a and the second solder layer 2b having the composition shown in FIG. 6 is employed, the same effect as that of the solder material shown in FIG. 8 can be obtained. .

ダイボンディング完了後、図３のステップＳ５および図１３のステップＳ５に示すワイヤボンディングを行う。ここでは、半導体チップ１の電極パッド１ｃ（図２参照）と、これに対応するインナリード３ｂとをワイヤ７によって電気的に接続する。   After completion of die bonding, wire bonding shown in step S5 in FIG. 3 and step S5 in FIG. 13 is performed. Here, the electrode pads 1c (see FIG. 2) of the semiconductor chip 1 and the inner leads 3b corresponding thereto are electrically connected by wires 7.

ワイヤボンディング完了後、図３のステップＳ６および図１３のステップＳ６に示す樹脂封入を行う。すなわち、半導体チップ１、ダイパッド３ａ、複数のインナリード３ｂおよびワイヤ７を封止用樹脂によって封入し、封止体４を形成する。   After completion of the wire bonding, resin sealing shown in step S6 in FIG. 3 and step S6 in FIG. 13 is performed. That is, the semiconductor chip 1, the die pad 3 a, the plurality of inner leads 3 b, and the wires 7 are sealed with a sealing resin to form the sealing body 4.

樹脂封入完了後、図３のステップＳ７に示すポストキュアを行う。すなわち、樹脂封入工程で形成した封止体４を熱処理して硬化させる。   After the resin encapsulation is completed, the post cure shown in step S7 in FIG. 3 is performed. That is, the sealing body 4 formed in the resin sealing step is heat-treated and cured.

ポストキュア完了後、図３のステップＳ８に示すバリ取り・外装めっきを行う。すなわち、樹脂封入工程等で形成されたレジンバリ等を除去するとともに、アウタリード３ｃ等に対して外装めっきを施す。   After completion of post cure, deburring / exterior plating shown in step S8 of FIG. 3 is performed. That is, the resin burrs and the like formed in the resin sealing step and the like are removed, and outer plating is applied to the outer leads 3c and the like.

バリ取り・外装めっき完了後、図３のステップＳ９および図１４のステップＳ９に示す個片分離を行う。すなわち、リードフレーム３から複数のアウタリード３ｃのそれぞれを切断・分離するとともに、各アウタリード３ｃの曲げ成形を行う。本実施の形態では、各アウタリード３ｃをガルウィング状に曲げ成形する。   After completion of the deburring / exterior plating, the individual separation shown in step S9 in FIG. 3 and step S9 in FIG. That is, each of the plurality of outer leads 3c is cut and separated from the lead frame 3, and each outer lead 3c is bent. In the present embodiment, each outer lead 3c is bent and formed into a gull wing shape.

個片分離後、図３のステップＳ１０に示す特性選別を行う。すなわち、組み立てられたＳＯＰ８に対して電気的特性検査を行い、良品・不良品の判別を行う。   After the individual separation, the characteristic selection shown in step S10 in FIG. 3 is performed. That is, an electrical characteristic inspection is performed on the assembled SOP 8 to determine whether the product is good or defective.

特性選別後、良品と判定されたＳＯＰ８に対してステップＳ１１の捺印を行う。ここでは、例えば封止体４の表面に製品の型番等の情報をマーク（捺印）する。   After the characteristic selection, the marking in step S11 is performed on the SOP 8 determined to be non-defective. Here, for example, information such as a product model number is marked on the surface of the sealing body 4.

捺印後、図３のステップＳ１２に示すテーピングを行い、さらにステップＳ１３に示す梱包・出荷を行う。   After the stamping, taping shown in step S12 in FIG. 3 is performed, and packing / shipping shown in step S13 is further performed.

本実施の形態の半導体装置の製造方法によれば、融点が異なる２つの半田層（第１半田層２ａ、第２半田層２ｂ）を貼り合わせて２層半田箔（半田箔２）を形成し、この２層半田箔のうち融点が低い第２半田層２ｂをウエハ側にして上記２層半田箔と半導体ウエハ１１を貼り合わせてステージ（下熱板１７、第１ステージ）上に配置し、２層半田箔（半田箔２）と半導体ウエハ１１を加圧する。そして、異なる上記融点の間の温度（第１温度）で加熱することで、融点が低いウエハ側の第２半田層２ｂのみが溶融して接着材となるため、２層半田箔（半田箔２）を半導体ウエハ１１に貼り付けることができる。   According to the method for manufacturing a semiconductor device of the present embodiment, two solder layers (first solder layer 2a and second solder layer 2b) having different melting points are bonded to form a two-layer solder foil (solder foil 2). The two-layer solder foil and the semiconductor wafer 11 are bonded to each other with the second solder layer 2b having a low melting point out of the two-layer solder foil and placed on the stage (the lower heating plate 17, the first stage). The two-layer solder foil (solder foil 2) and the semiconductor wafer 11 are pressurized. Then, by heating at a temperature between the different melting points (first temperature), only the second solder layer 2b on the wafer side having a low melting point is melted and becomes an adhesive, so that the two-layer solder foil (solder foil 2) ) Can be attached to the semiconductor wafer 11.

これにより、溶融していない融点が高い第１半田層２ａが半田形状を保持するため、半導体ウエハ１１の面全体に対して半田箔２を均一に貼り付けることができる。   As a result, the first solder layer 2 a having a high melting point that is not melted retains the solder shape, so that the solder foil 2 can be uniformly attached to the entire surface of the semiconductor wafer 11.

その結果、半田材（半田箔２から成る）を介してダイパッド（板状部材）３ａ上に半導体チップ１を搭載（ダイボンディング）した際に、半導体チップ１が傾いて搭載されることを抑制することができる。   As a result, when the semiconductor chip 1 is mounted (die bonding) on the die pad (plate-like member) 3a via the solder material (consisting of the solder foil 2), the semiconductor chip 1 is prevented from being mounted at an inclination. be able to.

また、溶融していない融点が高い第１半田層２ａが半田形状を保持して、半導体ウエハ１１の面全体に対して均一に半田箔２を貼り付けることができ、したがって、加圧時の半導体ウエハ１１と半田箔２の面圧のばらつきを抑制することができる。さらに、半導体ウエハ１１の損傷の抑制化を図ることができるとともに、ウエハパターンへのダメージの発生を抑制することができる。   In addition, the first solder layer 2a having a high melting point that is not melted retains the solder shape, so that the solder foil 2 can be uniformly applied to the entire surface of the semiconductor wafer 11, and thus the semiconductor during pressurization can be applied. Variation in surface pressure between the wafer 11 and the solder foil 2 can be suppressed. Further, it is possible to suppress damage to the semiconductor wafer 11 and to suppress occurrence of damage to the wafer pattern.

また、融点が低い第１半田層２ａを溶融して接着材として用いるため、半導体ウエハ１１に２層半田箔（半田箔２）を高い接合力で貼り付けることができる。   Further, since the first solder layer 2a having a low melting point is melted and used as an adhesive, the two-layer solder foil (solder foil 2) can be attached to the semiconductor wafer 11 with a high bonding force.

これにより、ダイシング等で外力が加わっても容易に剥がれることはなく、チップ飛散やチップ飛散に起因するダイシングブレード２３の破損を抑制することができる。   Thereby, even if an external force is applied by dicing or the like, it is not easily peeled off, and it is possible to suppress chip scattering and damage to the dicing blade 23 due to chip scattering.

また、ダイボンディング時にダイパッド３ａ上に半田材を塗布するのではなく、予め半導体ウエハ１１に半田箔２を貼り付け、その後、ダイシングによって半田箔２が貼り付けられた半導体チップ１を取得してからダイボンディングを行う方法であるため、ダイボンディング工程における半田の流れ出しおよび半田のボイドの発生等を抑制することができる。   Further, instead of applying a solder material on the die pad 3a at the time of die bonding, the solder foil 2 is attached in advance to the semiconductor wafer 11, and then the semiconductor chip 1 to which the solder foil 2 is attached is obtained by dicing. Since it is a method for performing die bonding, it is possible to suppress the flow of solder and the generation of solder voids in the die bonding process.

さらに、半田のマウント状態の安定化を図ることができるため、半導体装置の組み立ての品質のばらつきを低減することができ、半導体装置の品質の向上化を図ることができる。   Furthermore, since the mounting state of the solder can be stabilized, variation in the assembly quality of the semiconductor device can be reduced, and the quality of the semiconductor device can be improved.

また、ダイボンディング時には、第１半田層２ａの融点と第２半田層２ｂの融点より高い温度（第２温度）で加熱して２つの半田層を溶融させてダイボンド材（半田材）２ｃとすることにより、ダイボンド温度の設定・管理が容易であり、容易にダイボンディングの管理ができる工法を確立することができる。   Further, at the time of die bonding, the two solder layers are melted by heating at a temperature (second temperature) higher than the melting points of the first solder layer 2a and the second solder layer 2b to obtain a die bond material (solder material) 2c. Thus, it is easy to set and manage the die bonding temperature, and it is possible to establish a construction method that can easily manage die bonding.

また、ダイボンディングの品質を向上させることができるため、ダイボンディングの出来栄えのばらつきの少ない工法を確立することができる。   Moreover, since the quality of die bonding can be improved, a construction method with little variation in the quality of die bonding can be established.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

例えば、上記実施の形態では、半導体装置の一例としてＳＯＰを取り上げて説明したが、上記半導体装置は、ダイボンド材として、融点が異なる２種類の半田層から成る半田箔を用い、予めウエハ段階で半田箔を貼り付けてからダイシングして２層半田箔付きの半導体チップを取得し、かつダイボンディングを行って組み立てられる半導体装置であれば、他の半導体装置であってもよい。すなわち、ＳＯＰ以外のディスクリート品であってもよく、さらにＱＦＮ（Quad Flat Non-leaded Package) やＱＦＰ（Quad Flat Package）等の半導体装置であってもよい。   For example, in the embodiment described above, SOP is taken up as an example of the semiconductor device. However, the semiconductor device uses a solder foil made of two types of solder layers having different melting points as a die bonding material, and is previously soldered at the wafer stage. Another semiconductor device may be used as long as it is a semiconductor device that is assembled by performing die bonding after obtaining a semiconductor chip with a two-layer solder foil by dicing after the foil is pasted. That is, it may be a discrete product other than SOP, and may be a semiconductor device such as QFN (Quad Flat Non-leaded Package) or QFP (Quad Flat Package).

また、上記半導体装置は、リード品以外の基板品等であってもよく、例えばＢＧＡ（Ball Grid Array)やＬＧＡ（Land Grid Array)等であってもよい。   The semiconductor device may be a substrate product other than a lead product, for example, a BGA (Ball Grid Array), an LGA (Land Grid Array), or the like.

１ 半導体チップ
１ａ 表面（主面）
１ｂ 裏面
１ｃ 電極パッド
１ｄ 半導体素子
１ｅ 電極
２ 半田箔
２ａ 第１半田層
２ｂ 第２半田層
２ｃ ダイボンド材（半田材）
３ リードフレーム
３ａ ダイパッド（板状部材）
３ａａ 上面
３ｂ インナリード
３ｃ アウタリード
４ 封止体
５ 第１リール
６ 第２リール
７ ワイヤ
８ ＳＯＰ（半導体装置）
９ 巻き取りリール
１０ ローラ
１１ 半導体ウエハ
１１ａ 主面
１１ｂ 裏面
１２ 巻き取り治具（巻き取りリール）
１３ ローラカッター
１４ 熱圧着装置
１５ 緩衝材
１６ 押し板
１７ 下熱板（第１ステージ）
１８ 上熱板（第２ステージ）
１９ チャンバ
１９ａ 下チャンバ
１９ｂ 上チャンバ
２０ 真空ポンプ
２１ 装置架台
２２ ダイシングテープ
２３ ダイシングブレード 1 Semiconductor chip 1a Surface (main surface)
1b Back surface 1c Electrode pad 1d Semiconductor element 1e Electrode 2 Solder foil 2a First solder layer 2b Second solder layer 2c Die bond material (solder material)
3 Lead frame 3a Die pad (plate-like member)
3aa Upper surface 3b Inner lead 3c Outer lead 4 Sealing body 5 First reel 6 Second reel 7 Wire 8 SOP (semiconductor device)
9 Winding reel 10 Roller 11 Semiconductor wafer 11a Main surface 11b Back surface 12 Winding jig (winding reel)
13 Roller cutter 14 Thermocompression bonding equipment 15 Buffer material 16 Press plate 17 Lower heat plate (first stage)
18 Upper heat plate (second stage)
19 chamber 19a lower chamber 19b upper chamber 20 vacuum pump 21 device mount 22 dicing tape 23 dicing blade

Claims (9)

（ａ）主面および前記主面と反対側の裏面を有し、前記主面に複数の半導体素子が形成された半導体ウエハを準備する工程と、
（ｂ）第１半田層と、前記第１半田層に積層された第２半田層とから成る半田箔を準備する工程と、
（ｃ）前記半導体ウエハの前記裏面側に前記半田箔を重ね合わせて、加熱可能な第１ステージ上に配置する工程と、
（ｄ）重ね合わせた前記半導体ウエハと前記半田箔を、前記第１ステージと前記第１ステージに対向して配置された第２ステージとにより加圧および加熱して、前記半導体ウエハと前記半田箔を貼り付ける工程と、
を有し、
前記第２半田層の融点は前記第１半田層の融点より低く、前記（ｃ）工程では、前記第２半田層を前記半導体ウエハ側に配置して前記半導体ウエハと前記半田箔を前記第１ステージ上に配置し、
前記（ｄ）工程では、前記第１半田層の融点と前記第２半田層の融点の間の第１温度で前記半田箔を加熱する半導体装置の製造方法。 (A) preparing a semiconductor wafer having a main surface and a back surface opposite to the main surface, and a plurality of semiconductor elements formed on the main surface;
(B) preparing a solder foil comprising a first solder layer and a second solder layer laminated on the first solder layer;
(C) placing the solder foil on the back side of the semiconductor wafer and placing it on a heatable first stage;
(D) The semiconductor wafer and the solder foil that are superposed on each other are pressed and heated by the first stage and the second stage disposed opposite to the first stage. A process of pasting,
Have
The melting point of the second solder layer is lower than the melting point of the first solder layer. In the step (c), the second solder layer is disposed on the semiconductor wafer side so that the semiconductor wafer and the solder foil are connected to the first solder layer. On the stage,
In the step (d), the method of manufacturing a semiconductor device, wherein the solder foil is heated at a first temperature between the melting point of the first solder layer and the melting point of the second solder layer. 請求項１に記載の半導体装置の製造方法において、
前記半導体ウエハの前記裏面は電極である半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the back surface of the semiconductor wafer is an electrode. 請求項２に記載の半導体装置の製造方法において、
前記第２半田層の厚さは、前記半田箔の厚さの５０％以下である半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the thickness of the second solder layer is 50% or less of the thickness of the solder foil. 請求項３に記載の半導体装置の製造方法において、
前記第２半田層の厚さは、前記半田箔の厚さの１０〜４０％である半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the thickness of the second solder layer is 10 to 40% of the thickness of the solder foil. 請求項２に記載の半導体装置の製造方法において、
前記第１半田層と前記第２半田層の融点の差は、２０℃以上である半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 2,
A method of manufacturing a semiconductor device, wherein a difference in melting point between the first solder layer and the second solder layer is 20 ° C. or more. 請求項１に記載の半導体装置の製造方法において、
前記（ｄ）工程では、真空雰囲気で前記加圧および前記加熱を行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (d), a semiconductor device manufacturing method in which the pressurization and the heating are performed in a vacuum atmosphere. 請求項１に記載の半導体装置の製造方法において、
前記（ｄ）工程では、水素還元雰囲気で前記加圧および前記加熱を行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
In the step (d), a semiconductor device manufacturing method in which the pressurization and the heating are performed in a hydrogen reduction atmosphere. 請求項７に記載の半導体装置の製造方法において、
前記（ｃ）工程では、前記半導体ウエハの主面より広い面積で予備切断された前記半田箔を準備し、前記半導体ウエハの前記裏面側に前記予備切断された前記半田箔を重ね合わせる半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7,
In the step (c), the solder foil preliminarily cut in an area larger than the main surface of the semiconductor wafer is prepared, and the preliminarily cut solder foil is superposed on the back side of the semiconductor wafer. Production method. 請求項１に記載の半導体装置の製造方法において、
前記（ｄ）工程の後、さらに、
（ｅ）前記半導体ウエハを複数の半導体チップに個片化する工程と、
（ｆ）前記複数の半導体チップの中から１つの半導体チップをピックアップし、前記半導体チップを前記半田箔を介して薄い板状部材上に配置する工程と、
（ｇ）前記第１半田層の融点より高い第２温度で前記半田箔を加熱して、前記半田箔が溶融されて成る半田材を介して前記半導体チップを前記板状部材に接合する工程と、
を有する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
After the step (d),
(E) dividing the semiconductor wafer into a plurality of semiconductor chips;
(F) picking up one semiconductor chip from the plurality of semiconductor chips, and placing the semiconductor chip on a thin plate member via the solder foil;
(G) heating the solder foil at a second temperature higher than the melting point of the first solder layer, and bonding the semiconductor chip to the plate-like member via a solder material formed by melting the solder foil; ,
A method for manufacturing a semiconductor device comprising:
JP2012198270A 2012-09-10 2012-09-10 Method for manufacturing semiconductor device Pending JP2014050871A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017098554A1 (en) * 2015-12-07 2017-06-15 三菱電機株式会社 Laser light source device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017098554A1 (en) * 2015-12-07 2017-06-15 三菱電機株式会社 Laser light source device

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