JP2014045400A - Data transmission system, transmission device, reception device, and data transmission/reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transmission system in which tracking characteristics to jitter or frequency change are not deteriorated even when the number of data lanes is reduced.SOLUTION: The data transmission system comprises: a transmission device 20 having a parallel-serial conversion section 22 which converts a parallel data signal into a serial data signal; a data lane D1 which transmits the serial data signal to be outputted; a clock lane C1 which transmits a clock signal for converting the serial data signal into the parallel data signal; a reception device 30 having a serial-parallel conversion section 31 for the serial data signal to be transmitted into the parallel data signal on the basis of the clock signal to be transmitted through the clock lane; and a transmission data conversion section 21 which multiplies frequency of the clock signal with a predetermined multiplication number and adds an identification code to the serial data signal which identifies a break point in data strings according to the multiplication number.

Description

  The present invention relates to a data transmission system, a transmission device, a reception device, and a data transmission / reception method.

  When transmitting a pulse signal through an electric wire, a data transmission system (Low Voltage Differential Signaling: LVDS) (hereinafter referred to as LVDS) to which a differential signal transmission method is applied as a transmission method for preventing a signal error due to the influence of external noise on the electric wire. Also known as a system).

  In this LVDS system, a transmission side circuit transmits a pulse signal to be transmitted as two pulse signals (ie, differential signals) of a positive phase (+ side) and a negative phase (− side).

  As a transmission path, for example, a plurality of data lanes for transmitting converted serial data signals and a clock lane for transmitting clock signals for converting serial data signals into parallel data signals are paired. A transmission line is used.

  Various techniques related to the LVDS system have been proposed (see, for example, Patent Document 1).

JP 2000-78027 A

  Here, when the conventional LVDS system is applied to data transmission / reception in an image display device such as a display, for example, the clock transmitted in the clock lane is a dot clock (in order to display one dot of the display). The same frequency as the reciprocal of the time required for

  Accordingly, serial data having the number of bits determined by the frequency is assigned to each data lane in one period of the dot clock.

  However, when it is attempted to reduce the number of data lanes in the LVDS system due to a request for cost reduction or the like, the conventional LVDS system has a problem that the follow-up characteristics to jitter and frequency change deteriorate.

  An object of the present invention is to provide a data transmission system, a transmission apparatus, a reception apparatus, and a data transmission / reception method in which the tracking characteristics to jitter and frequency change do not deteriorate even if the number of data lanes is reduced.

  According to one aspect of the present invention for achieving the above object, a transmitter having parallel / serial conversion means for converting a plurality of types of parallel data signals into serial data signals, and a serial output from the transmitter One or more data lanes for transmitting data signals, a clock lane for transmitting clock signals for converting the serial data signals into parallel data signals, and the data lanes are transmitted. A receiving device having serial / parallel conversion means for converting the serial data signal into a parallel data signal based on the clock signal transmitted through the clock lane; The serial data signal is multiplied by the number and converted by the parallel-serial conversion means. The data transmission system and a transmission data conversion means for adding identifying identification code delimiter data sequence in response to said multiplication factor is provided.

  According to another aspect of the present invention, there is provided a transmission apparatus having parallel / serial conversion means for converting a plurality of types of parallel data signals into serial data signals, wherein the output serial data signal is transmitted 1 or Two or more data lanes are connected to a clock lane for transmitting a clock signal for converting the serial data signal into a parallel data signal, and the frequency of the clock signal is multiplied by a predetermined multiplication number. There is provided a transmission apparatus comprising transmission data conversion means for adding an identification code for identifying a delimiter of a data string to the serial data signal converted by the parallel / serial conversion means in accordance with the multiplication number.

  According to another aspect of the present invention, serial / parallel conversion means converts a serial data signal transmitted through a data lane into a parallel data signal based on a clock signal transmitted through the clock lane. The frequency of the clock signal is multiplied by a predetermined multiplication number, and the serial data signal is added with an identification code for identifying a data string delimiter according to the multiplication number A receiving device is provided.

  According to another aspect of the present invention, the frequency of the clock signal for transmission is multiplied by a predetermined multiplication number, and the serial data signal converted by the predetermined parallel-serial conversion means is changed according to the multiplication number. A data transmission / reception method is provided in which an identification code for identifying a data string delimiter is added and transmitted / received.

  According to the present invention, it is possible to provide a data transmission system, a transmission device, a reception device, and a data transmission / reception method in which the tracking characteristics to jitter and frequency change do not deteriorate even if the number of data lanes is reduced.

The functional block diagram which shows the function structure of the data transmission system which concerns on embodiment. The block block diagram which shows schematic structure of the data transmission system which concerns on 1st Example. The time chart of the low voltage differential signal of 1 dot clock period in the data transmission system which concerns on 1st Example. It is a time chart in the data transmission system which concerns on 1st Example, (a) Time chart concerning parallel input, (b) Time chart inside transmission, (c) Time chart concerning serial data, (d) Inside reception (E) Time chart concerning parallel output. The block block diagram which shows schematic structure of the data transmission system which concerns on 2nd Example. The time chart of the low voltage differential signal of 1 dot clock period in the data transmission system which concerns on 2nd Example. The block block diagram which shows schematic structure of the data transmission system which concerns on a comparative example. The time chart of the low voltage differential signal of 1 dot clock period in the data transmission system which concerns on a comparative example. The time chart of the low voltage differential signal of 1 dot clock period at the time of reducing a data lane in a comparative example.

  Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[Embodiment]
As shown in the functional block diagram of FIG. 1, the data transmission system 1 according to the present embodiment includes a transmission apparatus 20 having parallel / serial conversion means 120 that converts a plurality of types of parallel data signals into serial data signals. One or more data lanes D1 for transmitting a serial data signal output from the transmission device 20, and a clock lane C1 for transmitting a clock signal for converting the serial data signal into a parallel data signal A receiving device 30 having serial / parallel conversion means 130 for converting a serial data signal transmitted via the data lane D1 into a parallel data signal based on the clock signal transmitted via the clock lane C1; In addition to multiplying the frequency of the clock signal by a predetermined multiplication factor, The serial data signal is converted by means 120, and a transmission data conversion means for adding identifying identification code delimiter data sequence in accordance with the multiplication factor (transmission data converting unit 21).

  The predetermined multiplication number can be an integer of 2 or more.

(LVDS)
Here, LVDS is a transmission method in which the amplitude is reduced to about several hundred mV in order to realize high-speed signal transmission of, for example, several hundred megabits / second or more.

  LVDS has features such as high-speed signal transmission, low noise generation, less influence from external noise, and low power consumption. It is used in various fields such as communication equipment, network devices, and liquid crystal monitors. Has been.

  Further, according to LVDS, for example, the number of signal lines necessary for transmitting a video signal having 6 to 10 bits of RGB gradations is about 20 to 40 in the conventional CMOS / TTL system. In comparison, for example, there is an advantage that it can be reduced to about 4 pairs (3 pairs of data lanes, 1 pair of clock lanes) to 6 pairs (5 pairs of data lanes, 1 pair of clock lanes).

(Comparative example)
Before describing an embodiment of the present invention, a data transmission system 200 according to a comparative example will be described with reference to FIGS.

  As shown in the block configuration diagram of FIG. 7, the data transmission system 200 according to the comparative example includes a parallel / serial conversion unit (PS conversion unit) 222 that converts a plurality of types of parallel data signals into serial data signals. A transmission device 220 having a plurality of (N: N is an integer of 2 or more) data lanes D1 to DN for transmitting a serial data signal output from the transmission device 220, and a serial data signal as a parallel data signal A clock lane C1 for transmitting a clock signal for conversion into a serial data signal transmitted via the data lanes D1 to DN and a parallel signal based on the clock signal transmitted via the clock lane C1. And a receiving device 230 having a serial / parallel conversion unit (SP conversion unit) 231 for converting into a data signal.

  The transmission device 220 is connected to an information processing device 210 that inputs, for example, 2N = 14 parallel data (PDI) and a 10 MHz dot clock (DCKI). In the example shown in FIG. 7, the parallel data is branched by N = 7 at the node n <b> 20 and input to the parallel / serial conversion unit 222.

  Further, the dot clock is branched at the node n21, and part of the dot clock is input to the PLL circuit 223 and input to the PS converter 222 as a 70 MHz clock signal.

  The PS converter 222 of the transmission device 220 is connected to the data lanes D1 to DN via channel differential drivers 224a to 224n corresponding to the number of channels.

  Transmission data (TD) d1 to dn (+/−) converted into serial data is transmitted via the data lanes D1 to DN.

  Further, the PS converter 222 of the transmission device 220 is connected to a clock lane C1 that transmits a transmission clock (TCCK +/−) via a clock differential driver 225.

  On the other hand, the SP converter 231 of the receiving device 230 is connected to the data lanes D1 to DN via the channel differential receivers 235a to 235n corresponding to the number of channels.

  The DLL circuit 233 of the receiving device 230 is connected to the clock lane C1 via the clock differential receiver 236.

  The DLL circuit 233 performs predetermined delay processing on the received 10 MHz transmission clock. Then, for example, it is input to the SP converter 231 as a sampling clock (N = 7) of 10 MHz.

  The serial data received by the receiving device 230 is converted into parallel data and output to the information processing device 240. In this case, in the example illustrated in FIG. 7, the data converted by the SP conversion unit 231 is output to the information processing apparatus 240 as 2N = 14 parallel data (PDO), for example.

  Further, for example, a 10 MHz dot clock (DCKO) is output from the DLL circuit 233 of the receiving device 230 to the information processing device 240.

  The clock transmitted in the clock lane C1 has the same frequency as the dot clock (the reciprocal of the time required to display one dot of the display).

  Therefore, in one period of the dot clock, serial data having the number of bits determined by the frequency is assigned to each of the data lanes D1 to DN.

  That is, as shown in FIG. 8, in the period t10 to t11 of one dot clock (CK +/−), the differential signals S11 to 17 in the data lane D1, the differential signals S21 to 27 in the data lane D2, and so on. Is transmitted. The transmitted differential signal is N = 7-bit serial data.

  Here, in the receiving device 230, in order to accurately capture the serial data, the DLL circuit 233 performs phase comparison on the basis of the change timing of the transmission clock, thereby generating a sampling clock.

  In addition, the transmission clock may be subjected to frequency modulation in order to reduce frequency fluctuation due to a jitter component from the information processing apparatus 210 and to reduce EMI (Electromagnetic Interference). For this reason, the sampling clock is as responsive as possible and needs to follow the frequency change.

  By the way, there is a demand to reduce the number of data lanes in order to reduce the cost.

  However, in the data transmission system 200 according to the comparative example, when an attempt is made to reduce the number of data lanes D1 to DN, if the number of bits allocated in one cycle (t20 to t21) is increased as shown in FIG. The interval for performing the phase comparison on the clock also becomes longer.

  Thereby, in the data transmission system 200 according to the comparative example, when the number of the data lanes D1 to DN is reduced, the followability to the frequency change is deteriorated.

(First embodiment)
The data transmission system 1 according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 2, the data transmission system 1 according to the first embodiment includes a parallel / serial conversion unit (PS conversion unit) 22 that converts a plurality of types of parallel data signals (PDI) into serial data signals. And the frequency of the clock signal is multiplied by a predetermined multiplication number, and the serial data signal converted by the PS converter 22 is added with an identification code for identifying a data string delimiter according to the multiplication number A transmission device 20 having a data converter 21, a single data lane D1 for transmitting a serial data signal (TDd1 +/−) output from the transmission device 20, and a serial data signal as a parallel data signal A clock lane C1 for transmitting a clock signal (TCCK +/−) for conversion, and a serial data signal transmitted via the data lane D1 And a receiving device 30 having a serial-parallel conversion unit (S-P conversion section) 31 for converting the parallel data signals based on the clock signal transmitted through the clock lanes C1.

  The transmission device 20 is connected to an information processing device 10 that inputs, for example, 2N = 14 parallel data (PDI) and a 10 MHz dot clock (DCKI).

  The dot clock is branched at the node n1, and part of the dot clock is input to the PLL circuit 23. The generated 20 MHz clock signal is input to the transmission data converter 21 and the 160 MHz clock signal is input to the PS converter 22. Is done.

  In addition, the PS conversion unit 22 of the transmission device 220 is connected to the data lane D1 via the channel differential driver 24.

  Transmission data TDd1 +/− converted to serial data is transmitted via the data lane D1.

  Further, the PS conversion unit 22 of the transmission device 20 is connected to the clock lane C1 via the clock differential driver 25.

  On the other hand, the SP converter 31 of the receiving device 30 is connected to the data lane D1 via the differential receiver 35.

  The DLL circuit 33 of the receiving device 30 is connected to the clock lane C1 via the clock differential receiver 36.

  The DLL circuit 33 performs predetermined delay processing on the received 20 MHz transmission clock. Then, for example, the 20 MHz sampling clock (N = 8) is input to the SP converter 31.

  The serial data received by the receiving device 30 is converted into parallel data (PDO) and output to the information processing device 40. In this case, in the example illustrated in FIG. 7, the data converted by the SP conversion unit 31 is output to the information processing apparatus 40 as 2N = 14 parallel data, for example.

  Further, for example, a 10 MHz dot clock (DCKO) is output from the clock generation unit 34 of the receiving device 30 to the information processing device 40.

  Further, as will be described later, for example, N + 1 = 8-bit data is input from the transmission data conversion unit 21 to the PS conversion unit 22 with a recognition bit added.

  Here, in the data transmission system 1 according to the present embodiment, a predetermined multiplication factor (M) is used for a period of one dot clock so that the interval at which the phase of the transmission clock is compared in the receiving device 30 does not become long. Times: M is an integer greater than or equal to 2).

  Further, in the data transmission system 1 according to the present embodiment, the data string delimiter is identified according to the multiplication number in order to determine the number of M transmission clocks corresponding to the data string delimiter position. Identification codes (recognition bits) for M bits are added.

  The identification code is arranged at a fixed bit position with respect to the clock signal in the serial data signal.

  That is, the addition position of the recognition bit to the serial data can be a bit position fixed with respect to the transmission clock.

  In the example shown in FIG. 3, the recognition bits I1 and I2 are added to the head positions of the data strings S11 to S17 and S21 to 27, respectively, in one dot clock period (t1 to t2).

  The positions of the recognition bits I1, I2, etc. are not limited to the head position, but may be the Pth (P is an integer) from the end or the head of the data string, for example.

  In FIG. 3, transmission data d1 +/− is serial data of M × N + 2 (= 16, where M = 2, N = 7) bits.

  Here, M corresponds to the number of changes of the transmission clock in one dot clock period, and N corresponds to the number of bits of serial data excluding the recognition bit in one transmission clock period.

  The number of bits of parallel data is a value M × N × L obtained by multiplying the product M × N of M and N by the number L of data lanes.

  Further, the identification codes (recognition bits) I1, I2, etc. can be constituted by a 1-bit data string.

  Further, the transmission data converter 21 and the PS converter 22 can be connected to a PLL circuit 23 having a number of PLL elements corresponding to a predetermined multiplication number.

  In addition, the receiving device 30 includes an output data conversion unit 32 that decodes the signal converted by the SP conversion unit 31 into the original parallel data signal.

  The S-P converter 31 is connected to a DLL circuit 33 having a number of DLL elements corresponding to a predetermined multiplication number, and the output data converter 32 is connected to the DLL circuit 33 to generate a predetermined clock. The clock generator 34 is connected.

  FIG. 4 is a time chart in the data transmission system 1 according to the first embodiment, where (a) is a time chart related to parallel input, (b) is a time chart inside transmission, and (c) is related to serial data. A time chart, (d) is a time chart inside the reception, and (e) is a time chart related to parallel output.

  As shown in FIG. 4C, in the serial data, the recognition bits I1 and I2 are added to the head positions of the data strings S11 to S17 and S21 to 27, respectively.

  Also, as shown in FIG. 4 (d), within the receiving apparatus 30, the separation of the data string is determined based on the recognition bits I1 and I2, and the serial data is accurately decoded into the original parallel data signal. (See FIG. 4E).

  Here, the operation of the data transmission system 1 according to this embodiment having the above-described configuration will be described.

  The transmission device 20 transmits, for example, 14 (M × N: where M is a predetermined multiplication number M = 2, N = 7) bits of the parallel data input (see FIG. 4A), the transmission data conversion unit 21. Transmission data d1 +/− generated by performing PS conversion M times (M = 2 in this embodiment) in the form of adding identification codes (recognition bits) I1 and I2 to 8 (= N + 1) bits in FIG. The data is transmitted to the receiving device 30 via the data lane D1 (see FIGS. 4B and 4C).

  Similarly, the transmission clock is transmitted to the receiving device 30 via the clock lane C1 as a clock signal CK +/− that repeats in units of 8 (= N + 1, N = 7) bits (FIG. 4B). ) And (c)).

  On the other hand, in the receiving device 30, a sampling clock is generated by the DLL circuit 33 based on the clock signal CK +/−.

  Then, the captured transmission data d1 +/− is subjected to SP conversion into data of 8 (= N + 1, where N = 7) bits (see FIG. 4D).

  Next, the output data converter 32 determines the delimiter position based on the identification codes (recognition bits) I1 and I2, and 14 (M × N: where M is a predetermined multiplication number M = 2, N = 7) Bit parallel data (for example, S11 to S17 and S21 to 27 shown in FIG. 4E) is restored.

  As described above, according to the data transmission system 1 according to the present embodiment, since the transmission clock is multiplied by a predetermined multiplication number, the number of times of phase comparison is also multiplied, so that the follow-up to jitter and frequency change can be accelerated. Can do.

  In addition, since the follow-up characteristic to jitter is improved, stable data transmission is possible, and the transmission efficiency can be increased by increasing the transmission frequency.

  In addition, since the number of serial data corresponding to one cycle of the transmission clock is reduced, the number of sampling clocks and the circuit scale of the PLL circuit 23 or DLL circuit 33 that generates the sampling clock can be reduced to reduce costs. it can.

(Second embodiment)
The data transmission system 1a according to the second embodiment will be described with reference to FIGS.

  In FIG. 5, the same components as those of the data transmission system 1 according to the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The difference in configuration between the data transmission system 1a according to the second embodiment and the data transmission system 1 according to the first embodiment is that a data lane D2 is provided in addition to the data lane D1.

  In the data transmission system 1a according to the present embodiment, the parallel data input from the information processing apparatus 10 is, for example, 28 (4 × N, where N = 7) bits.

  In this case, the identification code (recognition bit) to be added is, for example, 4 bits I1 to I4 as shown in FIG.

  For this reason, the identification codes (recognition bits) I1 to I4 and the like can also serve as predetermined significant information.

  For example, the predetermined significant information may be format information related to a parallel data signal, or timing information of encryption processing (such as scramble processing of broadcast data or image data) related to a parallel data signal.

  In FIG. 6, transmission data TDd1 +/− and TDd2 +/− are serial data of M × N + 2 (= 16, where M = 2, N = 7) bits.

  Here, the operation of the data transmission system 1a according to the present embodiment will be described.

  The transmission apparatus 20 identifies, for example, 28 (M × N × L: where M is a predetermined multiplication number M = 2, N = 7, L = 2) bits of parallel data input in the transmission data conversion unit 21. Transmission data TDd1 + generated by performing PS conversion M times (in this embodiment, M = 2) in the form of 8 (= N + 1) bits by adding codes (recognition bits) I1 and I2 and I3 and I4, respectively. / − And TDd2 +/− are transmitted to the receiving apparatus 30 via the data lanes D1 and D2 (see FIG. 6).

  Similarly, the transmission clock is transmitted to the receiving device 30 via the clock lane C1 as a clock signal CK +/− that repeats in units of 8 (= N + 1, N = 7) bits (see FIG. 6). .

  The identification code is arranged at a fixed bit position with respect to the clock signal in the serial data signal.

  That is, the addition position of the recognition bit to the serial data can be a bit position fixed with respect to the transmission clock.

  In the example shown in FIG. 6, the recognition bits I1 and I2 are added to the head positions of the data strings S11 to S17 and S21 to 27, respectively, in one dot clock period (t3 to t4), and the recognition bits I3 and I4 are These are added to the head positions of the data strings S31 to S37 and S41 to 47, respectively.

  On the other hand, in the receiving device 30, a sampling clock is generated by the DLL circuit 33 based on the clock signal CK +/−.

  Then, the captured transmission data TDd1 +/− and TDd2 +/− are subjected to SP conversion into 8 (= N + 1, where N = 7) bit data.

  Next, the output data conversion unit 32 determines the delimiter position based on the identification codes (recognition bits) I1 to I4, and 28 (M × N × L: where M is a predetermined multiplication number M = 2, N = 7, L = 2) Restore to bit parallel data output.

  Thus, according to the data transmission system 1a according to the present embodiment, since the transmission clock is multiplied by a predetermined multiplication number, the number of times of phase comparison is also multiplied, so that the follow-up to the jitter and the frequency change can be accelerated. Can do.

  In addition, since the follow-up characteristic to jitter is improved, stable data transmission is possible, and the transmission efficiency can be increased by increasing the transmission frequency.

  In addition, since the number of serial data corresponding to one cycle of the transmission clock is reduced, the number of sampling clocks and the circuit scale of the PLL circuit 23 or DLL circuit 33 that generates the sampling clock can be reduced to reduce costs. it can.

  Further, the data transmission system according to the present embodiment is, for example, a transmission device having parallel-serial conversion means for converting a plurality of types of parallel data signals into serial data signals, and outputs serial data signals. Are connected to one or more data lanes that transmit the clock signal and a clock lane that transmits a clock signal for converting the serial data signal into a parallel data signal, and the frequency of the clock signal is multiplied by a predetermined multiplication factor. It can be applied to a transmission apparatus provided with transmission data conversion means for multiplying serial data signals converted by parallel-serial conversion means and adding an identification code for identifying a data string delimiter according to the multiplication number. .

  Also, the data transmission system according to the present embodiment converts, for example, a serial data signal transmitted via a data lane into a parallel data signal based on a clock signal transmitted via a clock lane. A receiving device having serial / parallel conversion means, wherein a frequency of a clock signal is multiplied by a predetermined multiplication number, and an identification code for identifying a data string delimiter is added to the serial data signal according to the multiplication number The present invention can be applied to a receiving apparatus.

  Further, the present invention can be realized as various electrical devices such as a communication device, a network device, and a liquid crystal monitor including the data transmission system, the transmission device, or the reception device according to the above embodiment.

  Also, an identification code for multiplying the frequency of the clock signal for transmission by a predetermined multiplication number and identifying a data string delimiter according to the multiplication number in a serial data signal converted by a predetermined parallel-serial conversion means It can be applied to a data transmission / reception method for transmitting / receiving data.

[Other embodiments]
As described above, the embodiments have been described. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are illustrative and do not limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments not described herein.

  The data transmission system and the like of the present invention can be applied to various electrical devices such as communication devices, network devices, and liquid crystal monitors.

DESCRIPTION OF SYMBOLS 1, 1a ... Data transmission system 10 ... Information processing apparatus 20 ... Transmission apparatus 21 ... Transmission data conversion part 22 ... Parallel / serial conversion part (PS conversion part)
23 ... PLL circuit 24 ... Channel differential driver 30 ... Receiving device 31 ... Serial / parallel converter (SP converter)
32 ... Output data conversion unit 33 ... DLL circuit 34 ... Clock generation unit 35 ... Differential receiver 36 ... Differential receiver for clock 40 ... Information processing device 200 ... Data transmission system 210 ... Information processing device 220 ... Transmission device 222 ... Parallel Serial converter 223... PLL circuit 224a to 224n... Channel differential driver 225... Clock differential driver 230... Receiver 233... DLL circuit 235a to 235n ... Channel differential receiver 236. Processing unit C1 ... Clock lane D1-DN ... Data lane I1-I4 ... Recognition bits n1, n20, n21 ... Node

Claims (20)

A transmitter having parallel-serial conversion means for converting a plurality of types of parallel data signals into serial data signals;
One or more data lanes for transmitting serial data signals output from the transmitter;
A clock lane for transmitting a clock signal for converting the serial data signal into a parallel data signal;
A receiving apparatus having serial-parallel conversion means for converting the serial data signal transmitted through the data lane into a parallel data signal based on the clock signal transmitted through the clock lane;
A transmission for multiplying the frequency of the clock signal by a predetermined multiplication number and adding an identification code for identifying a data string delimiter according to the multiplication number to the serial data signal converted by the parallel-serial conversion means A data transmission system comprising: data conversion means.   The data transmission system according to claim 1, wherein the predetermined multiplication number is an integer of 2 or more.   A receiving device having serial / parallel conversion means for converting a serial data signal transmitted through the data lane into a parallel data signal based on a clock signal transmitted through the clock lane; The data transmission system according to claim 1, wherein the data transmission system is a data transmission system.   The data transmission system according to any one of claims 1 to 3, wherein the identification code is arranged at a bit position fixed to the clock signal in the serial data signal.   The data transmission system according to any one of claims 1 to 4, wherein the identification code is composed of a 1-bit data string.   The data transmission system according to claim 1, wherein the identification code also serves as predetermined significant information.   The data transmission system according to claim 6, wherein the predetermined significant information is format information related to the parallel data signal.   7. The data transmission system according to claim 6, wherein the predetermined significant information is encryption processing timing information regarding the parallel data signal.   9. The parallel-serial conversion unit and the transmission data conversion unit are connected to a PLL circuit having a number of PLL elements corresponding to the predetermined multiplication number. The data transmission system described in 1.   The said receiving apparatus is provided with the output data conversion means which decodes the signal converted by the said serial / parallel conversion means to the original parallel data signal, The any one of Claims 1-9 characterized by the above-mentioned. Data transmission system.   The serial / parallel converter is connected to a DLL circuit having a number of DLL elements corresponding to the predetermined multiplication number, and the output data converter is connected to the DLL circuit to generate a predetermined clock. The data transmission system according to claim 10, wherein the data transmission system is connected to the means. A transmitter having parallel-serial conversion means for converting a plurality of types of parallel data signals into serial data signals,
Connected to one or more data lanes for transmitting an output serial data signal and a clock lane for transmitting a clock signal for converting the serial data signal into a parallel data signal;
A transmission for multiplying the frequency of the clock signal by a predetermined multiplication number and adding an identification code for identifying a data string delimiter according to the multiplication number to the serial data signal converted by the parallel-serial conversion means A transmission apparatus comprising data conversion means.   The transmission apparatus according to claim 12, wherein the predetermined multiplication number is an integer of 2 or more. A receiving device having serial / parallel conversion means for converting a serial data signal transmitted through a data lane into a parallel data signal based on a clock signal transmitted through the clock lane,
The frequency of the clock signal is multiplied by a predetermined multiplication number, and the serial data signal is added with an identification code for identifying a delimiter of a data string according to the multiplication number.   The receiving apparatus according to claim 14, wherein the predetermined multiplication number is an integer of 2 or more.   An electrical apparatus comprising the data transmission system according to any one of claims 1 to 11.   An electric apparatus comprising the transmission device according to claim 12.   An electric apparatus comprising the receiving device according to claim 14.   An identification code for multiplying the frequency of the clock signal for transmission by a predetermined multiplication number and identifying a data string delimiter according to the multiplication number is added to the serial data signal converted by a predetermined parallel-serial conversion means. A data transmitting / receiving method characterized by additionally transmitting / receiving.   The data transmission / reception method according to claim 19, wherein the predetermined multiplication number is an integer of 2 or more.

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