JP2014045080A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises a process of supplying a resin (underfill material) 4a between a mounted semiconductor chip 10 and a wiring board by a flip chip interconnection method as below. A surface of the semiconductor chip 10 includes a region NR1 in which a plurality of bumps (projection electrodes) are regularly arranged with a first arrangement density and a region NR2 in which a plurality of bumps are arranged with a second arrangement density lower than the first arrangement density. Here, in the process of supplying the resin 4a, the resin 4a is supplied to the region NR2 of lower arrangement density of the plurality of bumps before the region NR1 is filled with the resin 4a.

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a manufacturing method of a semiconductor device that is mounted so that an electrode formation surface of a semiconductor chip faces a connection terminal formation surface of a wiring board. .

  There is a technique in which a semiconductor chip is mounted on a substrate by a flip-chip connection method, and an underfill resin is injected between the semiconductor chip and the substrate (for example, Patent Document 1 (Japanese Patent Laid-Open No. 2010-232671) and Patent Document 2) No. 2007-157800).

JP 2010-232671 A JP 2007-157800 A

  In the flip-chip connection method, a plurality of protruding electrodes (bump electrodes, bumps) are formed on the formation surface of a plurality of electrode pads of a semiconductor chip. Then, the semiconductor chip and the wiring board are electrically connected by connecting the protruding electrode to the terminal on the wiring board side. Further, from the viewpoint of relaxing the stress applied to the plurality of protruding electrodes and improving the reliability of the semiconductor device, it is preferable to dispose, for example, a resin material as an underfill between the semiconductor chip and the wiring substrate.

  However, in the semiconductor device as described above, bubbles (voids) may remain inside the underfill material disposed between the semiconductor chip and the wiring board. If air bubbles remain inside the underfill material, the stress relaxation function may not be sufficiently exhibited.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The outline of typical ones disclosed in the present application will be briefly described as follows.

  In other words, the semiconductor device manufacturing method according to one aspect includes a step of electrically connecting the semiconductor chip and the wiring board by a flip chip connection method. Further, after electrically connecting the plurality of protruding electrodes formed on the surface side of the semiconductor chip and the plurality of terminals formed on the chip mounting surface of the wiring board, between the semiconductor chip and the wiring board A step of supplying an underfill material. The surface of the semiconductor chip has a first region in which the plurality of protruding electrodes are regularly arranged at a first arrangement density, and the plurality of protrusions at a second arrangement density lower than the first arrangement density. It includes a second region in which the electrode is disposed. Here, in the step of supplying the underfill material, the underfill material is supplied to the second region where the arrangement density of the plurality of protruding electrodes is low before the first region is filled with the underfill material. Is.

  The effects obtained by the representative embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the exemplary embodiment disclosed in the present application, the reliability of the semiconductor device can be improved.

1 is a perspective view illustrating an overall structure of a semiconductor device according to an embodiment. FIG. 2 is a plan view showing a mounting surface side of the semiconductor device shown in FIG. 1. FIG. 2 is a plan view showing a chip mounting surface side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line of FIG. It is a top view which shows the surface side of the semiconductor chip shown in FIG. FIG. 6 is an enlarged sectional view showing a part of the semiconductor chip shown in FIG. 5 in an enlarged manner. It is a top view shown in the state where the semiconductor chip and underfill shown in FIG. 3 were removed. It is an expanded sectional view of the B section of FIG. FIG. 2 is an explanatory diagram illustrating an outline of a manufacturing process of the semiconductor device illustrated in FIG. 1. It is a top view which shows the whole structure of the wiring board prepared by the board | substrate preparation process shown in FIG. It is an enlarged plan view of the B section in FIG. It is a partial expanded sectional view of FIG. FIG. 10 is a plan view showing a wafer prepared in the integrated circuit formation step shown in FIG. 9. It is an expanded sectional view which expands and shows a part of wafer shown in FIG. It is an expanded sectional view which shows the state which cut | disconnected the fuse shown in FIG. FIG. 16 is an enlarged cross-sectional view illustrating a state in which bumps are bonded on the land portion illustrated in FIG. 15. FIG. 12 is an enlarged plan view showing a state where a semiconductor chip is mounted on the chip mounting area shown in FIG. 11. It is an expanded sectional view along the AA line of FIG. FIG. 18 is an enlarged plan view showing a state after an underfill material is supplied between the semiconductor chip and the wiring board shown in FIG. 17. It is an expanded sectional view which shows the state which supplies an underfill material from a nozzle by the sealing process shown in FIG. FIG. 10 is an enlarged cross-sectional view showing a state in which solder balls are bonded onto a plurality of lands in the ball mounting step shown in FIG. 9. FIG. 20 is an explanatory diagram schematically showing a state where a resin (underfill material) is filled with a model obtained by simplifying the embodiment shown in FIG. 19. It is explanatory drawing which showed typically a mode that resin (underfill material) was filled from the side different from FIG. FIG. 24 is an explanatory view schematically showing a state in which a resin (underfill material) is filled in a semiconductor chip which is a modification to FIG. 23. FIG. 24 is an explanatory view schematically showing a state where a resin (underfill material) is filled in a semiconductor chip which is another modified example with respect to FIG. 23. It is explanatory drawing which showed typically an example of the supply method of resin (underfill material) in the embodiment shown in FIG. It is explanatory drawing which showed typically the example of the supply method different from FIG. It is explanatory drawing which shows the detailed flow of the sealing process shown in FIG. It is explanatory drawing which showed typically the supply method of resin (underfill material) corresponding to the flow of FIG. It is explanatory drawing which shows typically the example when the planar shape of the area | region where the arrangement | positioning density of a protruding electrode is low is long. It is explanatory drawing which showed typically the supply method of resin (underfill material) in the example shown in FIG. It is explanatory drawing which showed typically the supply method of resin (underfill material) which is a modification with respect to FIG. FIG. 32 is an explanatory diagram showing a resin supply method in a modification of the semiconductor chip shown in FIG. 31. FIG. 32 is an explanatory diagram illustrating a resin supply method according to another modification of the semiconductor chip illustrated in FIG. 31. FIG. 35 is an explanatory diagram showing a resin supply method in a modification to the semiconductor chip shown in FIG. 34. It is explanatory drawing which shows the supply method of the resin in the modification with respect to the semiconductor chip shown in FIG. It is explanatory drawing which shows the modification with respect to the resin supply method shown in FIG. FIG. 4 is a plan view showing an upper surface side of a semiconductor device which is a modified example with respect to FIG. 3.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

<Semiconductor device>
FIG. 1 is a perspective view showing the overall structure of the semiconductor device of this embodiment. FIG. 2 is a plan view showing the mounting surface side of the semiconductor device shown in FIG. 3 is a plan view showing the chip mounting surface side of the semiconductor device shown in FIG. 1, and FIG. 4 is a cross-sectional view taken along the line AA in FIG.

  As shown in FIG. 1, a semiconductor device 1 according to the present embodiment includes a semiconductor chip 10 and a substrate on which the semiconductor chip 10 is mounted, and a wiring board (base material, electrically connected to the semiconductor chip 10). Interposer) 3 is provided. As shown in FIGS. 1 and 3, an underfill (underfill resin, resin material, stress relaxation member) 4 made of, for example, a resin is disposed between the semiconductor chip 10 and the wiring board 3.

  Further, as shown in FIG. 2, a plurality of solder balls 5 serving as a plurality of external terminals are arranged on the lower surface (surface) 3 b that is a mounting surface of the wiring board 3. Specifically, the solder balls 5 are arranged in a matrix (array or matrix) in plan view. A package in which solder balls 5 as external terminals are arranged in a matrix on the mounting surface like the semiconductor device 1 is called an area array type semiconductor device. The area array type semiconductor device 1 can effectively use the lower surface 3b of the wiring board 3 serving as a mounting surface as a space for arranging external terminals, so that the increase in the mounting area and the number of terminals can be increased. Can be made.

<Details of semiconductor chip>
Next, details of the semiconductor chip 10 shown in FIG. 1 will be described. FIG. 5 is a plan view showing the surface side of the semiconductor chip shown in FIG. 3, and FIG. 6 is an enlarged sectional view showing a part of the semiconductor chip shown in FIG.

  As shown in FIG. 4, the semiconductor chip 10 includes a front surface 10a and a back surface 10b located on the opposite side of the front surface 10a. As shown in FIG. 3 or 5, the front surface 10a (see FIG. 5) and the back surface 10b (see FIG. 3) each form a quadrangle in plan view. In other words, the front surface 10a and the back surface 10b of the semiconductor chip 10 are, as shown in FIGS. 3 and 5, the side H1, the side H2 crossing the side H1, the side H1 crossing the side H1, and the side H3 facing the side H2. , A side H4 facing the side H1 is provided. Further, the front surface 10a and the back surface 10b of the semiconductor chip 10 are a corner K1 that is an intersection of the sides H1 and H2, a corner K2 that is an intersection of the sides H1 and H3, and a corner that is an intersection of the sides H2 and H4. K3 and a corner K4 that is an intersection of the side H3 and the side H4. In the example shown in FIGS. 3 and 5, the front surface 10a and the back surface 10b are each a rectangle having a short side (sides H1, H4) of about 6 mm and a long side (sides H2, H3) of about 8 mm. Make it.

  Further, as shown in FIG. 5, a plurality of bumps (projection electrodes) which are external electrodes (electrodes for inputting / outputting signals and potentials with external devices) of the semiconductor chip 10 are provided on the surface 10a of the semiconductor chip 10. 11 is formed. The plurality of bumps 11 are made of a conductive material (metal material) such as solder, gold, and copper, for example, and the plurality of bumps 11 are regularly arranged on the surface 10 a of the semiconductor chip 10. In other words, the external electrode arrangement of the semiconductor chip 10 is an area array type external electrode arrangement in which a plurality of bumps 11 are arranged in a lattice pattern on the surface 10a. In the example shown in FIG. 5, the plurality of bumps 11 are arranged in a staggered pattern.

  In general, the external electrodes of the semiconductor chip are arranged along the peripheral edge of the external electrode formation surface, and are not arranged at the center of the external electrode formation surface. However, as in the semiconductor chip 10 of the present embodiment, in addition to the peripheral portion of the surface 10a, a plurality of bumps 11 that are external electrodes are arranged in the central portion (region NR1). The number of external electrodes per unit area can be increased. In other words, the planar size of the semiconductor chip 10 can be reduced by effectively utilizing the surface 10a of the semiconductor chip 10 as a space for arranging external electrodes.

  However, the arrangement density of the plurality of bumps 11 is not uniform over the entire surface 10a, and there are regions having different arrangement densities. That is, the surface 10a of the semiconductor chip 10 includes a region NR1 in which the plurality of bumps 11 are regularly arranged at the first arrangement density. In the region NR1, a plurality of bumps 11 are arranged in a staggered pattern, and the distance between the centers of adjacent bumps 11 is, for example, about 280 μm. In addition, the surface 10a of the semiconductor chip 10 includes a region NR2 in which the plurality of bumps 11 are arranged at a second arrangement density lower than the first arrangement density. In the region NR2, the bump 11 is not arranged at the place where the bump 11 is to be arranged according to the arrangement rule applied to the region NR1. For this reason, in the region NR2, the arrangement density of the plurality of bumps 11 is lower than that in the region NR1, and for example, the distance between the adjacent bumps 11 is 560 to 840 μm.

  Further, the surface 10a of the semiconductor chip 10 includes a region NR3 in which the plurality of bumps 11 are arranged at a third arrangement density lower than the first arrangement density. In the region NR3, according to the arrangement rule applied to the region NR1, the bump 11 is not disposed at the place where the bump 11 is to be disposed. For this reason, in the region NR3, the arrangement density of the plurality of bumps 11 is lower than that in the region NR1, and for example, the distance between the adjacent bumps 11 is 560 to 840 μm. In the example shown in FIG. 5, the region NR <b> 2 and the region NR <b> 3 are examples in which a plurality of bumps 11 are arranged with the same arrangement density. However, the semiconductor device manufacturing technique of the present embodiment described below can be applied to an example in which the arrangement density of the region NR2 and the region NR3 is different.

  In addition, the surface 10a of the semiconductor chip 10 includes a region NR4 in which the plurality of bumps 11 are arranged with a fourth arrangement density lower than the first arrangement density. In addition, the surface 10a of the semiconductor chip 10 includes a region NR5 in which the plurality of bumps 11 are arranged at a fifth arrangement density lower than the first arrangement density. In the regions NR4 and NR5, the bumps 11 are not arranged at the positions where the bumps 11 are to be arranged according to the arrangement rule applied to the region NR1. For this reason, in the regions NR4 and NR5, the arrangement density of the plurality of bumps 11 is lower than that in the region NR1, and for example, the distance between the adjacent bumps 11 is 560 to 840 μm. In the example shown in FIG. 5, each of the regions NR2, NR3, NR4, and NR5 shows an example in which a plurality of bumps 11 are arranged with the same arrangement density. However, the semiconductor device manufacturing technique of the present embodiment described below can be applied to an example in which the arrangement densities of the regions NR2, NR3, NR4, and NR5 are different.

  In the example shown in FIG. 5, the regions NR2, NR3, NR4, and NR5 having a lower arrangement density than the region NR1 are arranged as follows. That is, the region NR2 is disposed at a position closest to the corner K3 among the four corners of the semiconductor chip 10. The region NR3 is disposed at a position closest to the corner K4 among the four corners of the semiconductor chip 10. The region NR4 is disposed at a position closest to the corner K1 among the four corners of the semiconductor chip 10. The region NR5 is disposed at a position closest to the corner K2 among the four corners of the semiconductor chip 10.

  As shown in FIG. 6, the semiconductor chip 10 includes a main surface (semiconductor element formation surface, front surface) 12a and a main surface (back surface) 12b located on the opposite side of the main surface 12a, and is made of, for example, silicon (Si). The semiconductor substrate 12 is a base material to be formed. The main surface 12 b of the semiconductor substrate 12 constitutes the back surface 10 b of the semiconductor chip 10. A semiconductor element formation region 12c is disposed on the main surface 12a of the semiconductor substrate 12, and a plurality of semiconductor elements (not shown) such as transistors and diodes are formed in the semiconductor element formation region 12c.

  These semiconductor elements are electrically connected to a pad (electrode pad) PD formed on the uppermost layer of the wiring layer 13 through a wiring layer (first wiring layer, chip wiring layer) 13 formed on the main surface 12a. It is connected to the. Specifically, the semiconductor element has a plurality of internal wirings (wirings) 13a formed in the wiring layer 13 and a plurality of surface wirings (wirings, uppermost layer wirings) 13b formed in the uppermost layer of the wiring layer. It is electrically connected to the PD. In FIG. 6, only one pad PD is shown, but a plurality of pads PD are formed on the uppermost layer of the wiring layer 13. Further, the pad PD is formed integrally with the surface wiring 13b.

  The internal wiring 13a is an embedded wiring made of, for example, copper (Cu), and a groove or hole is formed in the insulating layer 13c formed in the wiring layer 13, and a conductive metal material such as copper is embedded in the groove or hole. Thereafter, the surface is polished to form wiring, so-called damascene technology. The insulating layer 13c is an inorganic insulating layer made of a semiconductor compound such as silicon oxide (SiOC) containing carbon. In addition, the wiring layer 13 forms an integrated circuit by electrically connecting a plurality of semiconductor elements, but has a laminated structure in order to secure a routing space for the wiring path.

  The uppermost layer of the wiring layer 13 is formed with a pad PD and a surface wiring 13b that are integrally formed with the pad PD and electrically connect the plurality of pads PD and the semiconductor elements via the internal wiring 13a. The pad PD and the surface wiring 13b are made of, for example, aluminum (Al), and are covered with an insulating layer 13d serving as a passivation film that protects the wiring layer 13. The insulating layer 13d is an inorganic insulating layer made of a semiconductor compound such as silicon oxide (SiO) or silicon nitride (SiN), as with the insulating layer 13c, from the viewpoint of improving the adhesion with the insulating layer 13c. is there. Further, in the surface 10a of the pad PD, an opening is formed in the insulating layer 13d, and the pad PD is exposed from the insulating layer 13d in the opening.

  Further, the semiconductor chip 10 of the present embodiment is called a so-called WPP (Wafer Process Package), and a rewiring layer (wiring layer, second wiring layer) 14 is further formed on the wiring layer 13. The rewiring layer 14 has a lower surface (main surface, back surface) 14 b facing the wiring layer 13 and an upper surface (main surface, surface) 14 a opposite to the lower surface 14 b, and the upper surface 14 a is connected to the surface 10 a of the semiconductor chip 10. It has become. A plurality of land portions (bump lands) 14c are formed on the upper surface 14a of the rewiring layer 14, and the pads PD are electrically connected to the pads PD via the plurality of wirings (rewiring) 14d formed in the rewiring layer 14, respectively. Connected to. A bump 11 is bonded to each land portion 14c.

  Specifically, for example, an insulating film (organic insulating film) 14e made of an organic compound such as polyimide resin is formed on the insulating layer 13d, and the wiring 14d is formed on the insulating film 14e. The insulating film 14e is formed with an opening for exposing the pad PD on the pad PD, and the pad PD and the wiring 14d are bonded to each other in the opening. The wiring 14d and the insulating film 14e are covered with an insulating film (organic insulating film) 14f made of an organic compound such as polyimide resin. An opening is formed in a part of the region of the insulating film 14f overlapping the wiring 14d, and the land portion 14c is exposed from the insulating film 14f in the opening. Bumps 11 serving as external electrodes of the semiconductor chip 10 are joined to the land portions 14c.

  As described above, the WPP-type semiconductor chip 10 has the rewiring layer 14 formed on the pad PD to change the planar position of the bump 11 serving as the external electrode to a position different from the pad PD. For this reason, for example, even if a plurality of bumps are formed along the peripheral edge of the surface 10a in accordance with the rules of a general semiconductor chip, by providing the rewiring layer 14, as shown in FIG. In addition, bumps 11 that are external electrodes can be arranged in a staggered pattern.

  However, for reasons of the manufacturing process of the semiconductor chip 10, the bumps 11 are located at the positions where the bumps 11 are to be disposed in the arrangement rule applied to the region NR1, such as the regions NR2, NR3, NR4, and NR5 shown in FIG. An area that cannot be placed may occur. For example, in the manufacturing process of the WPP type semiconductor chip 10, after forming the rewiring layer 14, a fuse blow process is performed in which the fuse 15 is cut as shown in FIG. 6. In the fuse blow process, the fuse 15 is cut by irradiating laser from the surface 10a side. For this reason, the bump 11 cannot be disposed at a position where the fuse 15 is cut. Regions NR2, NR3, NR4, and NR5 shown in FIG. 5 are regions in which the bumps 11 cannot be disposed for the reasons described above, for example.

  The bumps 11 (and the solder balls 5 shown in FIG. 2) of the present embodiment are made of so-called lead-free solder that does not substantially contain lead (Pb), for example, only tin (Sn), tin-bis film. (Sn-Bi), tin-silver (Sn-Ag), tin-silver-copper (Sn-Ag-Cu), or the like. Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHs (Restriction of Hazardous Substances) directive.

<Details of wiring board>
Next, details of the wiring board 3 shown in FIG. 1 will be described. FIG. 7 is a plan view showing the semiconductor chip and the underfill shown in FIG. 3 removed. FIG. 8 is an enlarged cross-sectional view of a portion B in FIG.

  As shown in FIG. 4, the semiconductor chip 10 is mounted on the wiring board 3. The wiring board 3 includes an upper surface (chip mounting surface, front surface) 3a that forms a quadrangle in plan view, and a lower surface (mounting surface, rear surface) 3b that is located on the opposite side of the upper surface 3a. For example, in the example shown in FIG. 3, the planar shape of the wiring board 3 is a square having a side length of about 15 mm to 30 mm. The wiring board 3 includes a side surface 3c located between the upper surface 3a and the lower surface 3b.

  As shown in FIG. 7, a plurality of terminals (lands, bonding leads) 6 are arranged on the upper surface 3 a of the wiring board 3. The wiring board 3 is a so-called multilayer wiring board in which a plurality of wiring layers 3d (see FIG. 8) are stacked, and the upper surface of the wiring layer 3d disposed on the uppermost layer is a solder resist film (insulating film, protective film). ) Covered with 3f. An opening is formed in the solder resist film 3f at a position where the terminal 6 is disposed, and the plurality of terminals 6 are exposed from the solder resist film 3f in the opening. The plurality of terminals 6 are arranged similarly to the arrangement of the plurality of bumps 11 of the semiconductor chip 10 shown in FIG. That is, as shown in FIG. 8, when the semiconductor chip 10 is mounted on the wiring substrate 3, the plurality of bumps 11 and the plurality of terminals 6 are arranged to face each other.

  As shown in FIG. 8, the wiring board 3 has a plurality of insulating layers 3z, and a plurality of wirings 3h are formed in the insulating layer 3z. The wiring 3h includes a conductor pattern formed on the upper surface or the lower surface of the insulating layer 3z and a buried conductor pattern (interlayer conductive path) formed so as to penetrate the insulating layer 3z. Further, a land (external terminal) 7 that is an external terminal of the semiconductor device 1 is formed in the wiring layer 3 d of the lowermost layer (the lower surface 3 b side that is the mounting surface) among the plurality of wiring layers 3 d. The plurality of lands 7 are electrically connected to the plurality of terminals 6 formed on the upper surface 3a side via the plurality of wirings 3h.

  The wiring layer 3d on which the lands 7 are formed is covered with a solder resist film (insulating film, protective film) 3g. An opening is formed in the solder resist film 3g at a position where the land 7 is disposed, and the plurality of lands 7 are exposed from the solder resist film 3g in the opening. Further, in the example shown in FIG. 8, solder balls 5 are bonded to the lands 7 so as to be exposed from the solder resist film 3g.

  As described above, the wiring board 3 includes a plurality of terminals 6 formed on the upper surface 3a side and a plurality of terminals formed on the lower surface 3b side via the wiring 3h formed on the plurality of wiring layers 3d included in the wiring board 3. The lands 7 are electrically connected to each other. Then, by electrically connecting the semiconductor chip 10 and the plurality of terminals 6 of the wiring board 3 via the plurality of bumps 11, the semiconductor elements formed on the semiconductor chip 10 and the plurality of lands 7 of the wiring board 3 are arranged. (And solder ball 5) can be electrically connected.

  Further, as can be seen by comparing the layout of the plurality of terminals 6 shown in FIG. 7 with the layout of the plurality of solder balls 5 shown in FIG. 2, the plurality of terminals 6 are different from the plurality of solder balls 5 in plan view. Placed in position. Specifically, in a plan view, the plurality of solder balls 5 are arranged to be distributed over a wider range than the plurality of terminals 6. Further, the plurality of solder balls 5 are arranged at a wider arrangement interval (pitch) than the plurality of terminals 6. That is, in the wiring substrate 3, the terminals 6 are arranged on the upper surface 3a side corresponding to the electrode layout of the semiconductor chip 10, and a plurality of solders are arranged on the lower surface 3b side corresponding to the terminal layout of the mounting substrate (not shown). A ball 5 is arranged. Accordingly, the wiring board 3 functions as an interposer that adjusts and relays the layout of the terminals when the semiconductor device 1 is mounted on a mounting board (not shown).

  As shown in FIG. 8, the semiconductor chip 10 is bonded to the terminals 6 and the bumps 11 with the surface 10a on which the plurality of bumps 11 are formed and the upper surface 3a that is the chip mounting surface of the wiring board 3 facing each other. It is mounted by a so-called flip-chip connection method (face-down mounting method).

  As another method of electrically connecting the semiconductor chip 10 and the wiring substrate 3, a wire connection method of connecting using a wire that is a thin metal wire is conceivable. The flip chip connection method applied in the present embodiment can shorten the path distance (transmission distance) for electrically connecting the semiconductor chip 10 and the wiring board 3 as compared with the wire connection method. Characteristics can be improved. Moreover, since the external electrode of the semiconductor chip 10 can be widely arranged on the surface 10a as described above, the number of terminals can be increased. Further, in the case of the wire connection method, it is necessary to form a sealing body so as to cover the entire semiconductor chip in order to protect the wire, but in the case of the flip chip connection method, the back surface 10b is exposed as shown in FIG. be able to. Therefore, the semiconductor device 1 can be thinned.

  However, as shown in FIG. 8, in the flip chip connection method, the distance for electrically connecting the semiconductor chip 10 and the wiring board 3 is short. For this reason, when an external force is applied to the semiconductor device 1, stress tends to concentrate on the bumps 11. For example, after the semiconductor device 1 is mounted on a mounting board (not shown), when a temperature cycle load (repeatedly exposed to a high temperature environment during operation and a low temperature environment when stopped) is applied, Stress is generated due to the difference in the coefficient of linear expansion of the constituent materials. This stress may concentrate on some of the plurality of bumps, and if the stress concentrates on some of the bumps 11, the bumps 11 may be damaged. The damaged bump 11 is liable to cause deterioration in electrical characteristics and electrical connection reliability, which causes a decrease in the reliability of the semiconductor device 1.

  Therefore, in the case of the flip chip connection method, as shown in FIGS. 1, 4, and 8, embedding the underfill 4 that is a stress relaxation material around the bump 11 improves the reliability of the semiconductor device 1. It is effective from the viewpoint of The underfill 4 is made of, for example, resin and has a function of dispersing and relaxing stress transmitted to the vicinity of the bumps 11. For this reason, the stress applied to each bump 11 can be reduced, and damage to the bump 11 can be prevented or suppressed.

  Further, in order to sufficiently exert the stress relaxation function of the underfill 4, it is preferable that the underfill 4 is brought into close contact with the bumps 11 to eliminate as much as possible gaps and bubbles remaining in the underfill 4. When gaps or bubbles remain in the underfill 4, the solder of the bumps 11 is remelted by high-temperature reflow (about 280 ° C.) when the semiconductor device is solder-mounted on the mounting substrate, and flows into the gaps and bubbles. There is a case. As a result, the remelted solder and the adjacent bump 11 cause an electrical short circuit (short circuit), resulting in a decrease in electrical characteristics and reliability of the semiconductor device. For this reason, in the manufacturing process of the semiconductor device, a technique for forming the underfill 4 in a state in which gaps and bubbles are hardly generated is important. The inventor of the present application has studied a mechanism for generating gaps and bubbles when forming the underfill 4 and has found a countermeasure. Details will be described in detail in the section <Details of sealing process> described later.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the present embodiment will be described. The semiconductor device 1 in the present embodiment is manufactured along the flow shown in FIG. FIG. 9 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device of the present embodiment. In this section, first, the outline of the manufacturing process of the semiconductor device 1 will be described with reference to FIG. 9, and then the details of the sealing process shown in FIG. 9 will be described in detail.

<Board preparation process>
First, in the board preparation step shown in FIG. 9, the wiring board 20 shown in FIGS. 10 and 11 is prepared. FIG. 10 is a plan view showing the entire structure of the wiring board prepared in the board preparation step shown in FIG. 11 is an enlarged plan view of a portion B in FIG. 10, and FIG. 12 is an enlarged sectional view of a part of FIG.

  As shown in FIG. 10, the wiring board 20 prepared in this step includes a plurality of product formation regions 20 a inside a frame portion (frame body) 20 b. Specifically, a plurality (27 in FIG. 10) of product formation regions 20a are arranged in a matrix. The wiring substrate 20 is a so-called multi-cavity substrate having a plurality of product forming regions 20a corresponding to the wiring substrate 3 shown in FIG. 1 and dicing lines (dicing regions) 20c between the product forming regions 20a. Thus, manufacturing efficiency can be improved by using a multi-piece substrate provided with a plurality of product formation regions 20a.

  Further, as shown in FIG. 12, the component members of the wiring board 3 described with reference to FIGS. 1 to 8 are formed in each product formation region 20a. However, the solder balls 5 shown in FIG. 8 are not yet joined. As shown in FIG. 12, a multilayer wiring board in which a plurality of wiring layers 3d are laminated can be formed by, for example, a so-called build-up method.

  Further, as shown in FIG. 11, a chip mounting area CT which is a planned area for mounting a semiconductor chip in the chip mounting process shown in FIG. 9 is provided at the center of the upper surface 3a of the product forming area 20a. In the chip mounting region CT, the plurality of terminals 6 described above are exposed at the opening provided in the solder resist film 3f.

  Each chip mounting area CT has a quadrangular shape in plan view. In other words, the chip mounting area CT includes a side H1, a side H2 that intersects the side H1, a side H3 that intersects the side H1, and that faces the side H2, and a side H4 that faces the side H1. The chip mounting area CT includes a corner K1 that is an intersection of the sides H1 and H2, a corner K2 that is an intersection of the sides H1 and H3, a corner K3 that is an intersection of the sides H2 and H4, and a side H3. And a corner K4 that is an intersection of the side H4.

  Further, the plurality of terminals 6 arranged in the chip mounting area CT are respectively joined to the plurality of bumps 11 of the semiconductor chip 10 described with reference to FIG. That is, in the chip mounting area CT, there is an area NR1 in which the plurality of terminals 6 are regularly arranged at the first arrangement density. In the region NR1, the plurality of terminals 6 are regularly (equally spaced). In the example shown in FIG. 11, in the region NR1, the plurality of terminals 6 are arranged in a staggered pattern, and the distance between the centers of the adjacent terminals 6 is about 280 μm, for example. In the chip mounting area CT, there is an area NR2 in which the plurality of terminals 6 are arranged with a second arrangement density lower than the first arrangement density. In the region NR2, according to the arrangement rule applied to the region NR1, the terminal 6 is not disposed at the place where the terminal 6 is to be disposed. For this reason, in the region NR2, the arrangement density of the plurality of terminals 6 is lower than that in the region NR1, and for example, the distance between the adjacent terminals 6 is 560 to 840 μm.

  Further, the chip mounting region CT includes a region NR3 in which a plurality of terminals 6 are arranged at a third arrangement density lower than the first arrangement density, and a plurality at a fourth arrangement density lower than the first arrangement density. There is a region NR4 in which the terminals 6 are arranged. In each of the regions NR3 and NR4, according to the arrangement rule applied to the region NR1, the terminal 6 is not disposed at a position where the terminal 6 is to be disposed. For this reason, in the regions NR3 and NR4, the arrangement density of the plurality of terminals 6 is lower than that in the region NR1, and for example, the distance between adjacent terminals 6 is 560 to 840 μm. In the example shown in FIG. 11, each of the regions NR2, NR3, NR4, and NR5 shows an example in which a plurality of terminals 6 are arranged with the same arrangement density. However, the semiconductor device manufacturing technique of the present embodiment described below can be applied to an example in which the arrangement densities of the regions NR2, NR3, NR4, and NR5 are different.

  In the example shown in FIG. 11, the regions NR2, NR3, NR4, and NR5 having a lower arrangement density than the region NR1 are arranged as follows. That is, the region NR2 is disposed at a position closest to the corner K3 among the four corners of the chip mounting region CT. Further, the region NR3 is arranged at a position closest to the corner K4 among the four corners of the chip mounting region CT. The region NR4 is arranged at a position closest to the corner portion K1 among the four corner portions of the chip mounting region CT. The region NR5 is disposed at a position closest to the corner portion K2 among the four corner portions of the chip mounting region CT.

  11 and 12 show an example in which a plurality of terminals 6 are exposed. In the chip mounting process shown in FIG. 9, from the viewpoint of improving the bonding property between the terminals 6 and the bumps 11 (see FIG. 8), The following modifications can be applied. That is, a bonding material such as a solder material can be formed in advance on each of the plurality of terminals 6. As a result, the solder wettability of the terminal 6 is improved, so that the terminal 6 and the bump 11 (see FIG. 8) can be easily joined in the chip mounting process shown in FIG.

<Semiconductor chip preparation process>
In the semiconductor chip preparation step shown in FIG. 9, the semiconductor chip 10 shown in FIGS. 5 and 6 is prepared. FIG. 13 is a plan view showing a wafer prepared in the integrated circuit formation step shown in FIG. 14 is an enlarged sectional view showing a part of the wafer shown in FIG. 13 in an enlarged manner, and FIG. 15 is an enlarged sectional view showing a state where the fuse shown in FIG. 14 is cut. FIG. 16 is an enlarged cross-sectional view showing a state in which bumps are bonded on the land portion shown in FIG.

  The semiconductor chip 10 shown in FIGS. 5 and 6 is manufactured as follows, for example. First, in the integrated circuit forming step shown in FIG. 9, a wafer (semiconductor wafer, semiconductor substrate) 25 shown in FIG. 13 is prepared and integrated on the main surface 12a (see FIG. 14) of the semiconductor substrate 12 (see FIG. 14). Form a circuit.

  As shown in FIG. 13, the wafer 25 prepared in this step has a front surface 10a having a substantially circular planar shape and a back surface 10b located on the opposite side of the front surface 10a. The wafer 25 has a plurality of chip regions (device regions) 25a, and each chip region 25a corresponds to the semiconductor chip 10 shown in FIG. A scribe line (scribe region) 25b is formed between adjacent chip regions 25a. The scribe lines 25b are formed in a lattice shape, and divide the surface 10a of the wafer 25 into a plurality of chip regions 25a. The scribe line 25b is formed with a plurality of patterns such as TEG (Test Element Group) and alignment marks for confirming whether or not the semiconductor elements formed in the chip region 25a are correctly formed. .

  In this step, as shown in FIG. 14, a plurality of semiconductor elements (not shown) such as transistors are formed on the main surface (element formation surface) 12a of the semiconductor substrate 12 made of, for example, silicon (Si). Further, the wiring layer 13 is laminated on the main surface 12 a, and the pad PD is formed on the wiring layer 13. At this time, the fuse 15 is formed in the wiring layer 13 or on the wiring layer 13. FIG. 14 shows an example in which the fuse 15 is formed in the same layer as the pad PD. Further, an insulating layer 13d is formed so as to cover the wiring layer 13, and an opening for exposing the pad PD is formed in a part of the insulating layer 13d. In FIG. 14, one pad PD is representatively shown, but a plurality of pads PD are formed on the wiring layer 13 and electrically connected to a plurality of semiconductor elements via a plurality of internal wirings 13a. Has been.

  In the present embodiment, since the WPP type semiconductor chip 10 (see FIG. 6) is obtained as described above, the rewiring layer 14 is further provided on the insulating layer 13d serving as a passivation film for protecting the wiring layer 13. Form.

  The rewiring layer 14 is formed by the following method, for example. An insulating film 14e made of polyimide resin is formed on the insulating layer 13d, and an opening is formed in a part of the insulating film 14e so that a part of the pad PD is exposed. Next, a wiring (rewiring) 14d and a land portion 14c are formed on the insulating film 14e and patterned. Next, an insulating film 14f made of a polyimide film is formed so as to cover the wiring 14d and the land portion 14c. Then, the rewiring layer 14 shown in FIG. 14 is obtained by forming an opening in the insulating film 14f so that a part of the land portion 14c is exposed.

  Next, in the wafer test process shown in FIG. 9, an electrical test of a circuit connected to the land portion 14c is performed by bringing a test terminal (not shown) into contact with the land portion 14c. Further, in the fuse blow process described next to the wafer test process in FIG. 9, the fuse 15 shown in FIG. 14 is cut based on the result of the wafer test process. Thus, when a partial circuit breakage is found in the wafer test process, the broken circuit can be stored.

  In the fuse blow process, as shown in FIG. 15, the laser beam Lz is irradiated from the surface 10 a side of the wafer 25 to cut the fuse 15. Therefore, the land portion 14c is not arranged in the planned area to be irradiated with the laser Lz. Therefore, as described with reference to FIGS. 5 and 6, the surface 10 a of the semiconductor chip 10 has a region NR <b> 1 in which the plurality of bumps 11 are regularly arranged at the first arrangement density. In addition, on the surface 10a of the semiconductor chip 10, there are regions NR2, NR3, and NR4 in which the plurality of bumps 11 are arranged with a lower arrangement density than the first arrangement density.

  Next, in the bump electrode forming step shown in FIG. 9, bumps 11 are formed on the plurality of land portions 14c as shown in FIG. In the present embodiment, since the bump 11 is made of solder, the bump 11 is formed by placing (for example, applying) a solder material on the land portion 14c and heating. Although FIG. 9 shows an example in which the protruding electrode forming process is performed after the wafer test process and the fuse blowing process, as a modified example, after the protruding electrode forming process is performed, the wafer test process and the fuse blowing process are performed. It can be performed. In this case, the shape of the bump 11 may be deformed by bringing a test terminal (not shown) into contact with the bump 11. However, when the bump 11 is formed of solder, it can be easily repaired by heating.

  Next, in the dividing step shown in FIG. 9, the wafer 25 shown in FIG. 16 is divided (divided) into chip regions 25a, and a plurality of semiconductor chips 10 shown in FIGS. 5 and 6 are obtained. In this step, the wafer 25 is cut and divided along the scribe line 25b shown in FIG. Although the cutting method is not particularly limited, a cutting method using a dicing blade (rotating blade) or a cutting method of irradiating a laser can be used.

  Although not shown in FIG. 9, when the thickness of the semiconductor chip 10 is reduced, grinding is performed on the back surface 10b side of the wafer 25 as a back surface grinding step in addition to the steps shown in FIG. Processing may be performed. This back grinding process is performed after the integrated circuit formation process, for example.

<Chip mounting process>
In the chip mounting process shown in FIG. 9, as shown in FIG. 18, the semiconductor chip 10 is arranged on the wiring board 20 so that the surface 10a faces the upper surface 3a of the wiring board 20, and a plurality of terminals 6 and a plurality of terminals are arranged. The bumps 11 are electrically connected. 17 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the chip mounting region shown in FIG. 11, and FIG. 18 is an enlarged cross-sectional view taken along line AA in FIG.

  In this step, first, the semiconductor chip 10 is placed on the wiring substrate 20 so that the surface 10a faces the upper surface 3a of the wiring substrate 20 (semiconductor chip placement step). At this time, as shown in FIGS. 17 and 18, the positions of the plurality of bumps 11 and the positions of the plurality of terminals 6 are arranged so as to overlap in a plan view. Then, the solder material constituting the bump 11 is joined to the terminal 6 by performing a heat treatment to the melting point of the bump 11 or more in a state where the bump 11 and the terminal 6 are in contact with each other. When the solder material is cooled and hardened, the semiconductor chip 10 is fixed on the wiring board 20. At this time, the distance (gap, clearance) G1 between the surface 10a of the semiconductor chip 10 and the upper surface 3a of the wiring substrate 20 is, for example, about 70 μm.

<Sealing process>
Next, in the sealing step shown in FIG. 9, as shown in FIG. 20, the underfill 4 a is supplied between the surface 10 a of the semiconductor chip 10 and the upper surface 3 a of the wiring substrate 20, and the pad PD and the terminal 6 are connected. Seal the joint. FIG. 19 is an enlarged plan view showing a state after an underfill material is supplied between the semiconductor chip and the wiring board shown in FIG. 20 is an enlarged cross-sectional view showing a state in which an underfill material is supplied from a nozzle in the sealing step shown in FIG.

  In this step, for example, a nozzle 31 that is a cylindrical discharge port provided in the supply device 30 for the resin (underfill material) 4a is disposed outside the side surface 10c of the semiconductor chip 10. The nozzle 31 shown in FIG. 20 is a cylindrical body having an inner diameter of, for example, 600 μm, and is arranged next to the side surface 10 c of the semiconductor chip 10. In the example shown in FIG. 20, the distance from the center of the nozzle 31 to the side surface 10c of the semiconductor chip 10 is, for example, 800 μm. Further, since the tip of the nozzle 31 is disposed at a position of, for example, 380 μm from the upper surface 3 a of the wiring substrate 20, it is disposed at a position higher than the surface 10 a of the semiconductor chip 10.

  The resin 4a is, for example, a thermosetting resin, and forms a liquid property when supplied. In the example shown in FIG. 20, the nozzle 31 is connected to the nozzle 31 with a discharge speed adjusting unit (not shown) that discharges the resin 4a at a predetermined constant speed, and the resin 31 is discharged at a predetermined discharge speed. It can be discharged. In the example shown in FIG. 20, for example, the resin 4a is set to be discharged from the nozzle 31 at a discharge rate of 2.2 mg ± 0, 3 mg / second.

  The nozzle 31 is connected to a drive unit (not shown) that moves the position of the nozzle 31 and moves the tip (discharge port) of the nozzle 31 at a preset speed in a preset direction. Can do. In the example shown in FIG. 20, the nozzle 31 is movable at a speed of about 2 mm / second, for example. The moving speed of the nozzle 31 is variable, and the moving speed can be arbitrarily changed in a range of about 1 mm / second to 10 mm / second, for example.

  When the resin 4a is discharged from the nozzle 31, it is sucked into the gap between the semiconductor chip 10 and the wiring board 20, as shown by the arrow JH in FIG. The resin 4a travels through the gap between the semiconductor chip 10 and the wiring board 20 by a so-called capillary phenomenon, and the gap between the semiconductor chip 10 and the wiring board 20 is filled with the resin 4a.

  Thereafter, by curing the resin 4a, as described above, the underfill 4 (see FIG. 19) that functions as a stress relaxation layer that relaxes the stress applied to the bumps 11 is formed. Details of this step will be described later.

<Ball mounting process>
Next, in the ball mounting step shown in FIG. 9, a plurality of solder balls 5 are joined to a plurality of lands 7 formed on the lower surface 3b of the wiring board 20, as shown in FIG. FIG. 21 is an enlarged cross-sectional view showing a state in which solder balls are bonded onto a plurality of lands in the ball mounting step shown in FIG. In this step, as shown in FIG. 21, after the wiring board 20 is inverted, the solder balls 5 are disposed on each of the plurality of lands 7 exposed on the lower surface 3b of the wiring board 20, and then heated to form a plurality of solder balls 5. The solder balls 5 and the lands 7 are joined. Through this step, the plurality of solder balls 5 are electrically connected to the semiconductor chip 10 via the wiring substrate 20. However, the technique described in the present embodiment is not limited to the so-called BGA (Ball Grid Array) type semiconductor device in which the solder balls 5 are joined. For example, as a modification to the present embodiment, the so-called LGA is shipped in which the solder balls 5 are not formed and the lands 7 are exposed, or the lands 7 are coated with a solder paste thinner than the solder balls 5. It can be applied to a (Land Grid Array) type semiconductor device.

<Individualization process>
Next, in the individualization step shown in FIG. 9, the wiring board 20 is divided into the product formation regions 20a shown in FIG. In this step, the wiring board 20 is cut along a dicing line (dicing region) 20c shown in FIG. 10 to obtain a plurality of separated semiconductor devices 1 (see FIG. 1). Although the cutting method is not particularly limited, for example, a method of cutting and cutting the wiring board using a dicing blade (rotating blade) can be used.

  Through the above steps, the semiconductor device 1 described with reference to FIGS. 1 to 8 is obtained. Thereafter, necessary inspections and tests such as an appearance inspection and an electrical test are performed and shipped or mounted on a mounting board (not shown).

<Details of sealing process>
Next, details of the sealing step shown in FIG. 9 will be described.

  As described above, in order to sufficiently exert the stress relaxation function of the underfill 4, it is preferable that the underfill 4 is in close contact with the plurality of bumps 11 so that gaps and bubbles remain in the underfill 4 as much as possible. However, as a result of examination by the inventors of the present application, when the nozzle 31 shown in FIG. 20 is simply moved along one side of the semiconductor chip 10 in the above-described sealing process, bubbles are generated between the semiconductor chip 10 and the wiring substrate 20. I knew it would remain. Therefore, as a result of further investigation by the inventor of the present application, it was found that bubbles are likely to be generated in the regions NR2, NR3, NR4, and NR5 where the arrangement density of the bumps 11 is lower than that in the region NR1, as shown in FIG.

  Hereinafter, the bubble generation mechanism discovered by the present inventor and countermeasures will be described in order. In this section, before explaining the method of supplying the underfill material applied in the embodiment shown in FIG. 19, a description will be given using an embodiment in which the arrangement of the protruding electrodes is simplified. FIG. 22 is a simplified model of the embodiment shown in FIG. 19, and is an explanatory view schematically showing how resin (underfill material) is filled. In FIG. 22, the wiring board 20, the bumps 11, and the terminals 6 shown in FIG. Further, the resin 4a extends to the peripheral region of the semiconductor chip M1 in plan view, but is not shown in FIG. In the following, although a duplicate description is omitted, as in FIG. 22, in the explanatory view schematically showing how the resin (underfill material) is filled, the wiring board 20, bumps 11 and terminals 6 shown in FIG. The illustration is omitted. Similarly, in the explanatory view schematically showing the state in which the resin (underfill material) is filled as in FIG. 22, the illustration of the resin 4a spreading in the peripheral region of the semiconductor chip is omitted.

  In the semiconductor chip M1 shown in FIG. 22, only the region NR1 where the plurality of protruding electrodes are regularly arranged at the first arrangement density and the region NR2 arranged at the second arrangement density lower than the first arrangement density. This is different from the semiconductor chip 10 shown in FIG. An arrow JH1 shown in FIG. 22 indicates the locus of the nozzle 31 that is the supply port of the resin 4a, in other words, the moving direction of the nozzle 31 that supplies the resin 4a. That is, the supply method shown in FIG. 22 shows an example in which the resin 4a is supplied while moving the nozzle 31 along the side H1 from the corner K1 of the semiconductor chip M1 toward the corner K2. Hereinafter, in the explanatory view schematically showing the method of supplying the resin (underfill material) similarly to FIG. 22, the trajectory of the nozzle 31 (supply sequence of the resin 4a) is schematically shown by arrows JH1, JH2, and JH3.

  As shown in FIG. 22, when the resin 4a is supplied while moving the nozzle 31 along the side H1, as shown in FIG. 22 (a), the resin 4a is first drawn from the side H1 side. Proceed while filling the gap toward the side H4. The resin 4a proceeds mainly by capillary action, and generally the penetration rate of the resin 4a tends to increase as the arrangement interval of the protruding electrodes becomes narrower. This is because the permeating resin 4a tries to sneak around the projecting electrode instantly (attempts to wet the projecting electrode instantly) at the moment when the tip contacts the projecting electrode. Goes up. If the spacing between the protruding electrodes is reduced, the number of times the resin 4a contacts the protruding electrodes increases, the entire resin 4a is pulled, and the penetration rate increases. Therefore, in the region NR1 where the protruding electrodes are arranged at a constant interval, the traveling speed of the resin 4a is substantially constant.

  However, as shown in (b) in the middle of FIG. 22, when a part of the resin 4a reaches the region NR2 where the arrangement density of the protruding electrodes is low, the interval between the adjacent protruding electrodes is widened. In NR2, the progress speed of the resin 4a decreases as can be explained by the above-described penetration mechanism. On the other hand, in the region NR1, the resin 4a maintains a constant traveling speed.

  As a result, as shown in (c) described in the lower part of FIG. 22, before the region NR2 is filled with the resin 4a, the periphery of the region NR2 may be surrounded by the resin 4a. In other words, the periphery of the unfilled region KH is surrounded by the resin 4a while the unfilled region KH that is not filled with the resin 4a remains in a part of the region NR2. In this case, since there is no discharge path for discharging the gas in the unfilled region KH to the periphery of the semiconductor chip M1, the unfilled region KH remains as a bubble between the semiconductor chip M1 and the wiring board 20 (see FIG. 19). To do.

  In the mechanism shown in FIG. 22, if the region NR2 where the traveling speed of the resin 4a is slow can be filled with the resin 4a before the region NR1, the generation of bubbles can be prevented or suppressed. Therefore, the inventor of the present application studied a technique for supplying the resin 4a to the region NR2 where the arrangement density of the plurality of protruding electrodes is low before the region NR1 is filled with the resin 4a.

  First, FIG. 23 is an explanatory view schematically showing a state in which resin (underfill material) is filled from a side different from FIG. The supply method shown in FIG. 23 is different from the supply method shown in FIG. 22 in that the nozzle 31 is arranged on the side H4 near the region NR2 and the resin 4a is supplied from the side H4. That is, the supply method shown in FIG. 23 shows an example in which the resin 4a is supplied while moving the nozzle 31 along the side H4 from the corner K3 of the semiconductor chip M1 toward the corner K4. The other points are the same as in FIG.

  As shown in FIG. 23, when the resin 4a is supplied from the side H4 near the region NR2, the unfilled region KH shown in FIG. 22 is hardly formed. This is considered to be due to the following reason. That is, as described above, in the region NR1 where the arrangement interval between the adjacent protruding electrodes is narrow, the influence of the so-called capillary phenomenon is dominant as a factor for determining the traveling speed of the resin 4a. For this reason, in the region NR <b> 2 where the interval between the adjacent protruding electrodes is relatively wide, the traveling speed of the resin 4 a due to the capillary phenomenon decreases as in FIG. 22.

  However, since the spatial volume is wide in the region NR2, the influence of the supply pressure (injection pressure) of the resin 4a becomes large. The influence of the supply pressure on the traveling speed of the resin 4a increases as the distance to the nozzle 31 that is the supply source of the resin 4a is shorter. That is, as shown in FIG. 23A, the region NR2 is disposed near the nozzle 31 that is the supply source of the resin 4a, and therefore the traveling speed of the resin 4a is difficult to decrease in the region NR2.

  As a result, as shown in FIGS. 23B and 23C, the region NR2 is filled with the resin 4a before the region NR1 is filled with the resin 4a. In other words, it is difficult to form the unfilled region (bubble) KH shown in FIG. That is, as shown in FIG. 23, if the resin is supplied from the side H4 near the region NR2, the generation of bubbles can be prevented or suppressed.

  Note that the region NR2 is disposed at a position closest to the corner portion K3, so that the side H4 and the side H2 are the sides closest to the region NR2. Therefore, although illustration is omitted, even when the nozzle 31 is arranged on the side H3 near the region NR2 and the resin 4a is supplied from the side H2 side, the generation of bubbles can be suppressed. That is, the same effect as in FIG. 23 can be obtained also in the case of supplying the resin 4a while moving the nozzle 31 along the side H2 from the corner K3 of the semiconductor chip M1 toward the corner K1. As described above, when the region NR2 is arranged at a position close to any one of the four corners of the semiconductor chip M1, if the resin 4a is supplied along either the side H2 or the side H4, generation of bubbles is generated. Can be suppressed. For this reason, even when there is a factor that the nozzle 31 cannot be arranged on either the side H2 or the side H4, the nozzle 31 may be arranged on the other side.

  Next, a model in the case where there are two regions where the arrangement density of the protruding electrodes is lower than the region NR1 will be described. FIG. 24 is an explanatory view schematically showing a state in which a resin (underfill material) is filled in a semiconductor chip which is a modification to FIG. The semiconductor chip M2 shown in FIG. 24 is different from the semiconductor chip M1 shown in FIG. 23 in that in addition to the regions NR1 and NR2, the region NR3 is arranged at a third arrangement density lower than the first arrangement density. . The other points are the same as the resin 4a supply method described with reference to FIG. 23, including the resin 4a supply method.

  In the embodiment shown in FIG. 24, among the four sides included in the semiconductor chip M2, the side H4 is arranged at a position closest to the region NR2 and the region NR3. When the regions NR2 and NR3 having low bump arrangement density are arranged close to the side H4, the nozzle 31 is arranged on the side H4 and the resin 4a is applied from the side H4 as shown in FIG. By supplying, generation | occurrence | production of a bubble can be suppressed. That is, the resin 4a is supplied while moving the nozzle 31 along the side H4 from the corner K3 of the semiconductor chip M2 toward the corner K4. At this time, as shown in FIG. 24B, the supply of the resin 4a is continued until most of the region NR2 and the region NR3 are filled with the resin 4a. Thereby, even when the resin 4a is injected into the region NR3, a decrease in the traveling speed of the resin 4a can be suppressed due to the influence of the supply pressure of the resin 4a, so that the unfilled region KH as shown in FIG. Occurrence can be suppressed.

  In addition, as shown in FIG. 25, when the region NR2 is disposed at a position closest to the side H2, and the region NR4 is disposed at a position closest to the side H1, the resin is sequentially applied from the side H2 side and the side H1 side. The generation of bubbles can be suppressed by supplying 4a. FIG. 25 is an explanatory view schematically showing a state in which a resin (underfill material) is filled in a semiconductor chip which is another modified example with respect to FIG. The semiconductor chip M3 shown in FIG. 25 is different from the semiconductor chip M1 shown in FIG. 23 in that in addition to the regions NR1 and NR2, the region NR4 is arranged at a fourth arrangement density lower than the first arrangement density. .

  In the model shown in FIG. 25, among the four sides included in the semiconductor chip M2, the side H2 is disposed at a position closest to the region NR2, and the side H1 is disposed at a position closest to the region NR4. In this case, first, as shown in FIG. 25A, the resin 4a is supplied while moving the nozzle 31 along the side H2 from the corner K3 of the semiconductor chip M3 toward the corner K1. Thereby, the resin 4a is filled in the region NR2 as shown in FIG. Subsequently, as indicated by an arrow JH2 in (b), the resin 4a is supplied while moving the nozzle 31 along the side H1 from the corner K1 of the semiconductor chip M3 toward the corner K2. Thereby, as shown in FIG. 25C, the region NR4 is filled with the resin 4a. In FIG. 25, for ease of understanding, the trajectory of the nozzle 31 along the side H2 (arrow JH1) and the trajectory of the nozzle 31 along the side H1 (arrow JH2) are shown separately, but the arrow JH1 It is preferable that the supply of the resin 4a from the nozzle 31 does not stop but continues to be supplied continuously when moving from the arrow to the arrow JH2.

  As described above, there are two regions (region NR2 and region NR3 or region NR2 and region NR4) in which the side where the nozzle 31 is disposed is not limited and the arrangement density of the protruding electrodes is lower than the region NR1. In this case, the resin 4a may be supplied along a side close to a region where the projecting electrode arrangement density is low. However, when the regions NR2, NR3, NR4, and NR5 in which the arrangement density of the bumps 11 is low are arranged near each of the four sides H1, H2, H3, and H4 as in the semiconductor chip 10 shown in FIG. In such a region, an unfilled region is easily formed. FIG. 26 is an explanatory view schematically showing an example of a resin (underfill material) supply method in the embodiment shown in FIG. Moreover, FIG. 27 is explanatory drawing which showed typically the example of the supply method different from FIG.

  In the supply method shown in FIG. 26, first, as shown in FIG. 26A, the resin 4a is moved while moving the nozzle 31 along the side H2 from the corner K3 of the semiconductor chip 10 toward the corner K1. Supply. As a result, as shown in FIG. 26B, the region NR2 and the region NR5 are filled with the resin 4a. Subsequently, as indicated by an arrow JH2 in (b), the resin 4a is supplied while moving the nozzle 31 along the side H1 from the corner K1 of the semiconductor chip 10 toward the corner K2. Thereby, as shown in FIG. 26C, the region NR4 is filled with the resin 4a. Subsequently, as indicated by an arrow JH3 in FIG. 26C, the resin 4a is supplied while moving the nozzle 31 from the corner K2 of the semiconductor chip 10 toward the corner K4 along the side H3. To do.

  However, as shown in FIG. 26B, the resin 4a supplied from the side H2 reaches the region NR3 before the region NR4 is filled with the resin 4a. When the resin 4a reaches the region NR3 (b), the nozzle 31 is disposed at a position along the side H1. Since the distance from the side H1 to the region NR3 is long, in the region NR3, the influence on the traveling speed of the resin 4a is dominated by the capillary phenomenon. As a result, a phenomenon similar to that described with reference to FIG. 22 occurs, and the unfilled region KH tends to occur near the region NR3.

  On the other hand, in the supply method shown in FIG. 27, first, as shown in FIG. 27A, the nozzle 31 is moved along the side H2 from the corner K3 of the semiconductor chip 10 toward the corner K1. 4a is supplied. Thereby, as shown in FIG. 27B, the region NR2 and the region NR5 are filled with the resin 4a. This is the same as the supply method of FIG. Next, the supply of the resin 4a from the nozzle 31 is temporarily stopped, and the nozzle 31 is moved to the side H3 side (near the corner portion K4) as shown in FIG. Then, as indicated by an arrow JH3 in (b), the resin 4a is supplied while moving the nozzle 31 along the side H3 from the corner K4 of the semiconductor chip 10 toward the corner K2. That is, in the supply method shown in FIG. 27, the resin 4a is supplied from two directions on the side H2 side and on the side H3 side facing the side H2.

  As shown in FIG. 27, when the resin 4a is supplied independently from both opposing sides, in the space between the semiconductor chip 10 and the wiring substrate 20 (see FIG. 19), the gas (air) present in the space ) And the flow direction of the resin 4a becomes unstable. For this reason, as shown in FIG. 27C, the resin 4a is united around the space before the partial space in the region NR1 is filled with the resin 4a. As a result, the gas present in the space is surrounded by the resin 4a, and the unfilled region KH is formed.

  Thus, in the case of the supply method shown in FIGS. 26 and 27, even if the resin 4a is filled from the sides close to the regions NR2, NR3, NR4, NR5 where the arrangement density of the protruding electrodes is low, the region NR1, It has been found that the unfilled region KH is easily formed somewhere in NR2, NR3, NR4, and NR5. Therefore, the inventor of the present application examined a supply method for filling each of the regions NR2, NR3, NR4, and NR5 with the resin 4a before the region NR1 was filled with the resin 4a, and found the method shown in FIGS. It was. FIG. 28 is an explanatory diagram showing a detailed flow of the sealing step shown in FIG. Moreover, FIG. 29 is explanatory drawing which showed typically the supply method of resin (underfill material) corresponding to the flow of FIG.

  In the sealing step shown in FIG. 28, first, as the first side supply step (S1), as shown in FIG. 29A, the resin 4a is supplied along the side H1. In this step, the resin 4a is supplied while moving the nozzle 31 of the supply device 30 along the side H1 from the corner K1 side of the semiconductor chip 10 toward the corner K2 side. By this step, the resin 4a sequentially advances to the region NR1 and the region NR4 and is filled with the resin 4a.

  Next, as a discharge stop step (S2) shown in FIG. 28, the discharge of the resin 4a from the nozzle 31 is stopped. Subsequently, as the nozzle moving step (S3) shown in FIG. 28, the nozzle 31 is moved to the side H2 side. In this step, the nozzle 31 is moved while the supply of the resin 4a from the nozzle 31 is stopped.

  Here, in the first side supply step (S1), the resin 4a is on the side H1 side after the discharge of the resin 4a from the nozzle 31 until the nozzle 31 is moved in the nozzle movement step (S3). It progresses toward the side H2 side. For this reason, when the resin 4a is supplied from the side H3 subsequent to the side H1, the resin 4a may reach the region NR2 on the side H2 side.

  Therefore, in the present embodiment, in the first side supply step (S1), the resin 4a is supplied first from the side H2 near the position where the discharge of the resin 4a from the nozzle 31 is started (near the corner K1). For this reason, in the discharge stop step (S2), the discharge of the resin 4a from the nozzle 31 is stopped, and the nozzle 31 is moved in the stopped state.

  In addition, the position at which the supply of the resin 4a from the nozzle 31 is resumed is already filled with the resin 4a supplied from the side H1 in the first side supply step (S1) as shown in FIG. The position P1 is preferable. When the supply of the resin 4a is resumed from the position where the resin 4a is not yet filled, the resin 4a is supplied independently from two directions as described with reference to FIG. 27, and the traveling direction of the resin 4a is unstable. It is easy to become. On the other hand, if the filling is resumed from the position P1 shown in FIG. 29A, the new resin 4a is supplied in the traveling direction of the resin 4a, so that the traveling direction of the resin 4a is stabilized. Therefore, from the viewpoint of suppressing the formation of the unfilled region KH as shown in FIG. 27, in the nozzle moving step (S3), it is preferable to move the nozzle 31 to the position P1 shown in FIG. .

  Further, as shown in FIG. 29A, the position P1 can be set to an arbitrary position within the range between the corner K1 and the tip of the resin 4a. However, from the viewpoint of quickly supplying the resin 4a to the region NR2 in the second side supply step (S4) performed subsequent to this step, the corner K1 and the center of the tip of the resin 4a are set to the tip side. Is preferred.

  Next, as the second side supply step (S4) shown in FIG. 28, the resin 4a is supplied from the side H2 side as shown in FIG. 29 (b). In this step, the resin 4a is supplied while moving the nozzle 31 along the side H2 from the corner K1 side of the semiconductor chip 10 toward the corner K3 side. As a modification of this process, the resin 4a can be supplied in a state where the nozzle 31 is stationary at the position P1 shown in FIG. Even in this case, if the distance between the position P1 and the region NR2 is short, the resin 4a can be injected into the region NR2. In this case, it is possible to reliably prevent the resin 4a supplied from the second side from going around the side H4 and forming an unfilled region. However, from the viewpoint of quickly supplying the resin 4a to the region NR2, as shown in FIG. 29 (b), the nozzle 31 is moved along the side H2 from the corner K1 side toward the corner K3 side. It is preferable to supply the resin 4a. By this step, the resin 4a advances to the region NR2, and the region NR2 is filled with the resin 4a.

  Next, as a discharge stop step (S5) shown in FIG. 28, the discharge of the resin 4a from the nozzle 31 is stopped. Subsequently, as the nozzle moving step (S6) shown in FIG. 28, the nozzle 31 is moved to the side H3 side. In this step, the nozzle 31 is moved while the supply of the resin 4a from the nozzle 31 is stopped.

  As described with reference to FIG. 26, when the influence of the capillary phenomenon is dominant as a factor for determining the traveling speed of the resin 4a, the traveling speed of the resin 4a in a region where the arrangement density of the protruding electrodes is narrow. Decreases. Therefore, as shown in FIG. 29B, it is preferable to supply the resin 4a from the side H3 closest to the region NR3 before the resin 4a reaches the region NR3. For this reason, in the discharge stop step (S5), the discharge of the resin 4a from the nozzle 31 is stopped, and the nozzle 31 is moved to the side H3 in the stopped state.

  The position at which the supply of the resin 4a from the nozzle 31 is resumed is already filled with the resin 4a supplied from the side H1 in the first side supply step (S1) as shown in FIG. The position P2 is preferable. When the supply of the resin 4a is resumed from the position where the resin 4a is not yet filled, the resin 4a is supplied independently from two directions as described with reference to FIG. 27, and the traveling direction of the resin 4a is unstable. It is easy to become. On the other hand, if the filling is resumed from the position P2 shown in FIG. 29B, a new resin 4a is supplied in the direction of travel of the resin 4a, so that the direction of travel of the resin 4a is stabilized. Therefore, from the viewpoint of suppressing the formation of the unfilled region KH as shown in FIG. 27, in the nozzle moving step (S6), it is preferable to move the nozzle 31 to the position P2 shown in FIG. .

  Further, as shown in FIG. 29B, the position P1 can be set to an arbitrary position within the range between the corner K2 and the tip of the resin 4a. However, from the viewpoint of quickly supplying the resin 4a to the region NR3 in the third side supply step (S7) performed following this step, the corner K1 and the center of the tip of the resin 4a are set to the tip side. Is preferred.

  Next, as the third side supply step (S7) shown in FIG. 28, as shown in FIG. 29 (c), the resin 4a is supplied from the side H3 side. As described above, in this step, before the resin 4a reaches the region NR3, the supply of the resin 4a from the side H3 closest to the region NR3 is resumed. Thus, as shown in FIG. 29C, the regions NR2, NR3, NR4, and NR5 can be filled with the resin 4a before the entire region NR1 is filled with the resin 4a.

  In this step, the resin 4a is supplied while moving the nozzle 31 along the side H2 from the corner K2 side of the semiconductor chip 10 toward the corner K4. As a modification of this process, the resin 4a can be supplied in a state where the nozzle 31 is stationary at a position P2 shown in FIG. Even in this case, if the distance between the position P2 and the region NR3 is short, the resin 4a can be injected into the region NR2. In this case, it is possible to reliably prevent the resin 4a supplied from the third side from going around the side H4 and forming an unfilled region. However, from the viewpoint of quickly supplying the resin 4a to the region NR3, as shown in FIG. 29 (c), the nozzle 31 is moved along the side H3 from the corner portion K2 side toward the corner portion K4 side. It is preferable to supply the resin 4a.

  Next, the discharge of the resin 4a from the nozzle 31 is stopped as a discharge stop process (S8) shown in FIG. Then, when the space between the semiconductor chip 10 and the wiring board 20 (see FIG. 19) is filled with the resin 4a, for example, as shown in FIG. The resin 4a (see FIG. 20) may be supplied along the peripheral edge.

  Next, as the resin curing step (S9) shown in FIG. 28, if the resin 4a (see FIG. 29) is cured, the underfill 4 shown in FIG. 19 is obtained. As a method for curing the resin 4a, for example, heat curing by heat treatment can be used.

<Modification>
Next, a preferable aspect including the modification of an above-described embodiment is demonstrated.

  First, the supply amount of the resin 4a when supplying the resin 4a will be described. The supply amount of the resin 4a described in the section <Details of sealing process> can be a constant supply amount in each side (sides H1, H2, and side H3). However, as described with reference to FIG. 29, before the resin 4a reaches the region NR3, from the viewpoint of restarting the supply of the resin 4a from the side H3 closest to the region NR3, different supply amounts from each side It is preferable to supply the resin 4a.

  First, in the first side supply step (S1) shown in FIG. 28, as shown in FIG. 29A, the resin 4a is supplied along the side H1 with a first supply amount. In this step, it is preferable to relatively increase the supply amount from the viewpoint of reliably filling the region NR5 and the region NR4 with the resin 4a. Under the conditions described above, for example, about 9 mg is supplied from the side H1.

  Next, in the second side supply step (S4) shown in FIG. 28, as shown in FIG. 29B, the resin 4a is supplied from the side H2 side. In this step, the resin 4a is supplied from the side H2 in order to quickly fill the region NR2 with the resin 4a as described above. Here, from the viewpoint of suppressing the resin 4a supplied from the side H2 from reaching the region NR3, the supply amount from the side H2 is preferably smaller than the first supply amount. Under the conditions described above, for example, about 4 mg to 7 mg is supplied from the side H1.

  Next, in the third side supply step (S7) shown in FIG. 28, as shown in FIG. 29 (c), the resin 4a is supplied from the side H3 side. In this step, the resin 4a is supplied from the side H3 in order to quickly fill the region NR3 with the resin 4a as described above. However, in the example described with reference to FIG. 29, most of the regions NR4, NR5, and NR2 are filled with the resin 4a at the stage of starting this process. Therefore, it is sufficient that the supply amount (third supply amount) of the resin 4a in this step is sufficient to prevent the formation of the unfilled region in the region NR3. However, from the viewpoint of suppressing the resin 4a from being combined on the side H4 shown in FIG. 29 before the region NR3 is filled with the resin 4a, the supply amount from the side H3 (third supply amount) is changed from the side H1. It is preferable to make it less than the supply amount (first supply amount). Under the conditions described above, for example, about 4 mg to 7 mg is supplied from the side H1.

  As described above, the unfilled region is formed in the region NR3 by making the supply amount from the side H2 (second supply amount) smaller than the supply amount from the side H1 (first supply amount). Can be suppressed. Further, by making the supply amount from the side H3 (third supply amount) smaller than the supply amount from the side H1 (first supply amount), before the region NR3 is filled with the resin 4a, on the side H4 side. It can suppress that resin 4a unites | combines and an unfilled area | region is formed.

  In addition, by increasing the supply amount of the resin 4a from the side H1 that supplies the resin 4a first, the time for the resin 4a shown in FIG. 29 to reach the region NR2 and the vicinity of the region NR1 can be shortened. . For this reason, the time from the start of the first side supply step (S1) shown in FIG. 28 to the start of the second side supply step (S4) can be shortened. That is, the processing time required for the sealing time can be shortened.

  Further, by increasing the supply amount of the resin 4a from the side H1 side, the supply pressure when the resin 4a is embedded in the region NR5 and the region NR4 shown in FIG. 29 can be increased. As a result, it becomes difficult to form unfilled regions in the regions NR5 and NR4.

  The supply amount of the resin 4a is the amount of the resin 4a supplied to the unit region (for example, each side of the semiconductor chip 10), and is defined by (discharge speed of the resin 4a) / (moving speed of the nozzle 31). Is done. For example, when the discharge speed from the nozzle 31 shown in FIG. 20 is constant, the supply amount increases as the movement speed of the nozzle 31 is slower. On the other hand, when the moving speed of the nozzle 31 is constant, the supply amount increases as the discharge speed increases.

  Further, as described above, the position P1 which is the start position of the second side supply step (S4) shown in FIG. 28 is between the corner K1 and the tip of the resin 4a as shown in FIG. It can be set to any position within the range. However, from the viewpoint of quickly supplying the resin 4a to the region NR2 in the second side supply step (S4), it is preferable to set the tip side of the corner K1 and the center of the tip of the resin 4a. Therefore, from the viewpoint of bringing the position P1 which is the start position of the second side supply step (S4) as close as possible to the region NR2, the tip of the resin 4a supplied from the side H1 shown in FIG. 29 exceeds the center of the side H2. It is preferable to start the second side supply step (S4) shown in FIG. Similarly, from the viewpoint of bringing the position P2 that is the start position of the third side supply step (S7) as close to the region NR3 as possible, the tip of the resin 4a supplied from the side H1 shown in FIG. It is preferable to start the third side supply step (S7) shown in FIG.

  Before starting the second side supply step (S4), the time required for the tip of the resin 4a supplied from the side H1 shown in FIG. 29 to exceed the center of the side H2 is the supply pressure of the resin 4a and the resin 4a. A certain degree of reproducibility can be ensured if the distribution of the protruding electrodes in the region to which is supplied is uniform. Therefore, even if the supply amount of the resin 4a from each side (sides H1, H2, and side H3) is the same, the start times of the second side supply step (S4) and the third side supply step (S7) are adjusted. Thus, the positions P1 and P2 can be on the side H4 side from the center of the sides H2 and H3.

  However, depending on the planar dimensions of the semiconductor chip 10, the start times of the second side supply step (S4) and the third side supply step (S7) may have to be strictly managed. Therefore, by making the supply amount of the resin 4a from the side H1 supplying the resin 4a first larger than the supply amount of the resin 4a from the other sides H2 and H3, the positions P1 and P2 are set to the sides H2 and H3. It is preferable to be on the side H4 side than the center.

  In addition, the position at which the supply of the resin 4a from the nozzle 31 is resumed is already filled with the resin 4a supplied from the side H1 in the first side supply step (S1) as shown in FIG. The position P1 is preferable. When the supply of the resin 4a is resumed from the position where the resin 4a is not yet filled, the resin 4a is supplied independently from two directions as described with reference to FIG. 27, and the traveling direction of the resin 4a is unstable. It is easy to become. On the other hand, if the filling is resumed from the position P1 shown in FIG. 29A, the new resin 4a is supplied in the traveling direction of the resin 4a, so that the traveling direction of the resin 4a is stabilized. Therefore, from the viewpoint of suppressing the formation of the unfilled region KH as shown in FIG. 27, in the nozzle moving step (S3), it is preferable to move the nozzle 31 to the position P1 shown in FIG. .

  22 to 29 show examples in which the regions NR2, NR3, NR4, and NR5 each form a circle in plan view. However, as shown in FIG. 30, each of the regions NR2, NR3, NR4, and NR5 However, there is a case where the shape is long and thin. FIG. 30 is an explanatory view schematically showing an example in which the planar shape of the region where the arrangement density of the protruding electrodes is low is long and thin. Moreover, FIG. 31 is explanatory drawing which showed typically the supply method of resin (underfill material) in the example shown in FIG. In the example shown in FIG. 31, the lengths of the regions NR2, NR3, NR4, and NR5 in the direction along the sides H2 and H3 (X direction) are longer than the length in the direction along the side H1 (Y direction). As described above, there may occur a case where the planar shape of the regions NR2, NR3, NR4, and NR5 becomes long and the arrangement density of the protruding electrodes is low. For example, in the example shown in FIG. 19 as well, in the regions NR2, NR3, NR4, and NR5, the length in the direction along the sides H2 and H3 (X direction) is the length in the direction along the side H1 (Y direction). Longer than that.

  As shown in FIG. 30, when the regions NR2, NR3, NR4, and NR5 have an elongated shape in a plan view, it is better to supply the resin 4a from a direction intersecting the longitudinal direction (Y direction in FIG. 30). The effect of the supply pressure of the resin 4a is increased. That is, since the opening area with respect to the supply direction of the resin 4a is widened, the static pressure resistance is lowered and the resin 4a is easily embedded. In particular, as shown in FIG. 31, in a region NR2 that exists at a position far from the side H1, which is the side to which the resin 4a is first supplied, by supplying the resin 4a (see FIG. 30) from the side H2 side, the region NR2 It is difficult to form an unfilled region. Similarly, in the region NR3 that exists at a position far from the side H1 that is the side to which the resin 4a is first supplied, it is difficult to form an unfilled region in the region NR3 by supplying the resin 4a from the side H3 side.

  FIG. 31 shows an example in which the resin 4a (see FIG. 30) is supplied first from the side H1 which is the short side of the four sides of the semiconductor chip 10 having a rectangular shape in plan view. However, as shown in FIG. 32, the resin 4a (see FIG. 30) can be supplied first from the long side. FIG. 32 is an explanatory view schematically showing a resin (underfill material) supply method which is a modification to FIG.

  In the example shown in FIG. 32, the sides H1 and H4 are long sides, and the sides H2 and H3 are short sides. That is, the supply method shown in FIG. 31 is that the resin 4a (see FIG. 30) is supplied first from the side H1 which is the long side of the four sides of the rectangular semiconductor chip 10 in plan view. Is different. When the resin 4a (see FIG. 30) is supplied first from the long side as shown in FIG. 32, the distance between the region NR2 and the region NR3 is longer than that in the example shown in FIG. It is difficult for the resin 4a to reach the region NR3 after the second side supply step (S4) and before the third side supply step (S7). Therefore, for example, even if the supply amount of the resin 4a is increased in the second side supply step (S4), the third side supply step (S7) can be started before the resin 4a reaches the region NR3.

  In addition, in FIGS. 29 to 32, the example in which there are four regions where the arrangement density of the protruding electrodes is low has been described. However, as a modified example, the present invention can be applied to a case where the number of regions where the arrangement density of the protruding electrodes is low. FIG. 33 is an explanatory diagram showing a resin supply method in a modification to the semiconductor chip shown in FIG. FIG. 34 is an explanatory view showing a resin supply method in another modification to the semiconductor chip shown in FIG.

  The semiconductor chip M4 shown in FIG. 33 includes regions NR2 and NR3 where the arrangement density of protruding electrodes is low, and does not have the regions NR4 and NR5 shown in FIG. The region NR2 of the semiconductor chip M4 is disposed at a position closest to the side H2 among the four sides of the semiconductor chip M4, and is disposed at the center of the side H2. The region NR3 of the semiconductor chip M4 is disposed at a position closest to the side H3 among the four sides of the semiconductor chip M4, and is disposed at the center of the side H3. In other words, the region NR2 and the region NR3 are arranged on a line (virtual line) connecting the central part of the side H2 and the central part of the side H3. The semiconductor chip M4 has a rectangular shape in plan view, and the lengths of the sides H2 and H3 are longer than the lengths of the sides H1 and H4. That is, in the semiconductor chip M4, the regions NR2 and NR3 are arranged at positions far from both the sides H1 and H4.

  In the case of the semiconductor chip M4 shown in FIG. 33, as described with reference to FIG. 27, a method of supplying the resin 4a from the side H2 close to the region NR2 and the side H3 close to the region NR3 can be considered. However, in this case, as described with reference to FIG. 27, the resin 4a is supplied independently from both of the two opposing sides. For this reason, in the space between the semiconductor chip M4 and the wiring board 20 (see FIG. 19), the flow direction of the gas (air) and the resin 4a (see FIG. 27) existing in the space becomes unstable. For this reason, as shown in FIG. 27C, the resin 4a is united around the space before the partial space in the region NR1 is filled with the resin 4a. As a result, the gas present in the space is surrounded by the resin 4a, and the unfilled region KH is formed.

  Therefore, as shown in FIG. 33, even if there are only two regions, ie, the region NR2 and the region NR3, where the arrangement density of the protruding electrodes is low, the arrows JH1, JH2, and JH3 are shown in FIG. In addition, it is preferable to sequentially supply the resin 4a (see FIG. 27) in the order of the sides H1, H2, and H3. Thereby, it can prevent or suppress that the unfilled area | region KH as shown in FIG. 27 is formed.

  The semiconductor chip M5 shown in FIG. 34 includes a region NR6 having a sixth arrangement density lower than the first arrangement density in addition to the regions NR2, NR3, NR4, and the region NR5 where the arrangement density of the protruding electrodes is low. This is different from the semiconductor chip 10 shown in FIG. FIG. 34 is an explanatory view showing a resin supply method in another modification to the semiconductor chip shown in FIG. In the semiconductor chip M5 illustrated in FIG. 34, the region NR6 is disposed between the region NR5 and the region NR4. In other words, in the semiconductor chip M5, the regions NR4, NR5, and NR6 having a low placement density of the protruding electrodes are provided at three or more locations along at least one of the four sides (side H1 in FIG. 34). . In such a case, as shown in FIG. 34, it is preferable to first supply the resin 4a along the side H1 where the regions NR4, NR5, and NR6 are arranged.

  In addition to the regions NR2, NR3, NR4, NR5, and the region NR6 where the protruding electrode has a low arrangement density, the semiconductor chip M6 shown in FIG. 35 includes a region NR7 having a seventh arrangement density lower than the first arrangement density. This is different from the semiconductor chip M5 shown in FIG. FIG. 35 is an explanatory diagram showing a resin supply method in a modification to the semiconductor chip shown in FIG. In the semiconductor chip M6 illustrated in FIG. 35, the region NR6 is disposed between the region NR2 and the region NR5 disposed along the side H2. In the semiconductor chip M6, the region NR7 is disposed between the region NR4 and the region NR3 disposed along the side H3. In other words, in the semiconductor chip M6, regions having a low arrangement density of the protruding electrodes are provided at three or more locations along at least two of the four sides facing each other (side H2 and side H3 in FIG. 35). ing. In this case, from the viewpoint of preventing formation of an unfilled region in the region NR6, it is preferable to supply the resin 4a (see FIG. 27) from the side H2. Further, from the viewpoint of preventing an unfilled region from being formed in the region NR7, it is preferable to supply the resin 4a from the side H3 side.

  That is, in the case shown in FIG. 35, it is preferable to supply the resin 4a (see FIG. 27) from the side H2 and the side H3 facing each other. Therefore, as shown with arrows JH1, JH2, and JH3 in FIG. 35, it is preferable to sequentially supply the resin 4a (see FIG. 27) in the order of the sides H1, H2, and H3. Thereby, it can prevent or suppress that the unfilled area | region KH as shown in FIG. 27 is formed.

  Further, as described above, the supply amount of the resin 4a shown in FIG. 20 is the amount of the resin 4a supplied to the unit region (for example, each side of the semiconductor chip 10), and (the discharge speed of the resin 4a) / ( (Moving speed of the nozzle 31). However, as shown in FIG. 36, the supply amount can be further increased by supplying the resin 4a multiple times from the same side. FIG. 36 is an explanatory diagram showing a resin supply method in a modification to the semiconductor chip shown in FIG.

  In the semiconductor chip M7 shown in FIG. 36, the region NR2 is arranged at a position closest to the side H1. 36 differs from the supply method shown in FIG. 23 in that the resin 4a is supplied twice from the side H1. In the example shown in FIG. 36, focusing on the fact that the supply pressure can be increased by increasing the supply amount of the resin 4a, the resin supply is locally performed in the vicinity of the region NR2 where the arrangement density of the protruding electrodes is low. Embodiments with increased amounts.

  In the sealing step shown in FIG. 36, the resin 4a is supplied as follows. First, as a preliminary supply step, as shown in FIG. 36A, the resin 4a is supplied while moving the nozzle 31 along the side H1 of the semiconductor chip M7. Here, as indicated by an arrow JH1 in FIG. 36A, in this step, the resin 4a is not supplied to the entire side H1 from the corner K1 to the corner K2, but a part of the side H1. The resin 4a is supplied to Specifically, the resin 4a is discharged from the nozzle 31 at the portion B1 along the region NR2 in the side H1 of the semiconductor chip M7. In other words, in this step, the resin 4a is supplied while moving the nozzle 31 along the region NR2. Thereby, as shown in FIG. 36A, the resin 4a spreads over the region NR2 and the region closer to the side H1 than the region NR2.

  Next, as a discharge stop process, the discharge of the resin 4a from the nozzle 31 is stopped. This discharge stop process is the same as the discharge stop process (S2) described with reference to FIG. Subsequently, as a nozzle moving step, the nozzle 31 is moved to the next discharge start position. In this step, the nozzle 31 is moved while the supply of the resin 4a from the nozzle 31 is stopped. Here, in the modification shown in FIG. 36, in the first side supply step to be performed next, the discharge is again performed along the side H1, so in the nozzle movement step, one end of the side H1 (in the example shown in FIG. 36) Move to corner K1).

  Next, as a first side supply step, as shown in FIG. 36B, the resin 4a is supplied along the side H1. In this step, the resin 4a is supplied while moving the nozzle 31 of the supply device 30 along the side H1 from the corner K1 side of the semiconductor chip 10 toward the corner K2 side. At this time, since the resin 4a is already supplied to the portion B1 along the region NR2, the supply amount of the resin 4a locally increases in the portion B1. For this reason, the supply pressure of the resin 4a supplied to the region NR2 increases, and as a result, as shown in FIG. 36C, the region NR2 can be more reliably filled with the resin 4a. In other words, the generation of an unfilled region in the vicinity of the region NR2 can be suppressed.

  In FIG. 36, an example in which the region NR2 having a low placement density of the protruding electrodes is provided at one place as an example of a modification of the method of supplying the resin 4a has been described. The present invention can also be applied when a low region is provided at a plurality of locations. That is, the resin 4a supply method described with reference to FIGS. 23 to 35 and the resin 4a supply method described with reference to FIG. 36 can be applied in combination. As an example, an example in the case of being applied in combination with the example shown in FIG. 31 will be described. FIG. 37 is an explanatory view showing a modification of the resin supply method shown in FIG.

  When the method for supplying the resin 4a shown in FIG. 36 is applied to the semiconductor chip 10 shown in FIG. 37, it is particularly effective when applied to the region NR5 and the region NR4 from the side H1 side. In plan view, the shapes of the regions NR4 and NR5 are elongated along the long sides H2 and H3. In this case, when the resin 4a is supplied from the side H1 side, the resin 4a is less likely to be injected into the regions NR4 and NR5 than when the resin 4a is supplied from the side H2 or the side H3 side.

  Therefore, in the embodiment shown in FIG. 37, the resin 4a is supplied a plurality of times from the side H1 side. That is, in the example shown in FIG. 37, first, as the first preliminary supply step, the resin 4a is supplied while moving the nozzle 31 along the side H1 of the semiconductor chip 10. Here, as indicated by an arrow JH1, in this step, the resin 4a is not supplied to the entire side H1 from the corner K1 to the corner K2, but is supplied to a part of the side H1. Specifically, the resin 4a is discharged from the nozzle 31 at the portion B1 along the region NR5 in the side H1 of the semiconductor chip 10. In other words, in this step, the resin 4a is supplied while moving the nozzle 31 along the region NR5. As a result, the resin 4a spreads over the region NR5 and the region closer to the side H1 than the region NR5.

  Next, as a discharge stop process, the discharge of the resin 4a from the nozzle 31 is stopped. This discharge stop process is the same as the discharge stop process (S2) described with reference to FIG. Subsequently, as a nozzle moving step, the nozzle 31 is moved to the next discharge start position. In the example shown in FIG. 37, two regions (regions NR4 and NR5) are provided along the side H1 where the protruding electrode arrangement density is low. For this reason, in this step, the nozzle 31 is moved to the portion B2 along the region NR4 in the side H1 of the semiconductor chip 10.

  Next, as a second preliminary supply step, the resin 4 a is supplied while moving the nozzle 31 along the side H <b> 1 of the semiconductor chip 10. Here, as indicated by the arrow JH2, in this step, the resin 4a is discharged from the nozzle 31 at a part of the side H1, specifically, at the part B1 along the region NR5 in the side H1 of the semiconductor chip 10. Discharge. In other words, in this step, the resin 4a is supplied while moving the nozzle 31 along the region NR3. As a result, the resin 4a spreads over the region NR4 and the region closer to the side H1 than the region NR5.

  Next, as a discharge stop process, the discharge of the resin 4a from the nozzle 31 is stopped. Subsequently, as a nozzle moving step, the nozzle 31 is moved to the next discharge start position. In this step, the nozzle 31 is moved while the supply of the resin 4a from the nozzle 31 is stopped. Here, in the first side supply step to be performed next, the ink is discharged again along the side H1, and therefore, in the nozzle movement step, it is moved to one end of the side H1 (corner portion K1 in the example shown in FIG. 37).

  Next, as a first side supply step, as indicated by the arrow JH3, the resin 4a is supplied along the side H1. In this step, the resin 4a is supplied while moving the nozzle 31 of the supply device 30 along the side H1 from the corner K1 side of the semiconductor chip 10 toward the corner K2 side. At this time, since the resin 4a is already supplied to the portion B1 along the region NR5 and the portion B2 along the region NR4, the supply amount of the resin 4a locally increases in each of the portions B1 and B2. become. For this reason, the supply pressure of the resin 4a supplied to the regions NR5 and NR4 increases, and as a result, the regions NR5 and NR4 can be more reliably filled with the resin 4a even from the side H1 side. In other words, the generation of unfilled regions in the vicinity of the regions NR5 and NR4 can be suppressed.

  In the subsequent steps, as shown with arrows JH4 and JH5 in FIG. 37, the resin 4a is sequentially supplied from the side H2 side and the side H3 side. Details of these steps are the same as the steps after the second side supply step (S4) described with reference to FIGS. Therefore, the overlapping description is omitted.

  As described above, the application of the resin 4a described with reference to FIGS. 23 to 35 and the resin 4a supply method described with reference to FIG. can do.

<Other variations>
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, as described with reference to FIG. 24, for example, the region where the arrangement density of the protruding electrodes is low is arranged on one side (side H4 in FIG. 24) side of the semiconductor chip M2. It is preferable to supply the resin 4a from the side H4 arranged closest to NR2 and NR3. However, depending on the layout on the wiring board, there may be a case where the side supplying the resin 4a cannot be freely selected. For example, in the semiconductor device 40 shown in FIG. 38, since the member 41 is disposed next to the side H4 side of the semiconductor chip 10, it is difficult to supply the resin 4a from the side H4 side. FIG. 38 is a plan view showing the upper surface side of a semiconductor device which is a modification example of FIG. The member 41 shown in FIG. 38 may be, for example, a semiconductor chip or an electronic component other than the semiconductor chip. In FIG. 38, the member 41 is shown as one component, but a plurality of components may be mounted in the region shown as the member 41.

  In the case shown in FIG. 38, it is difficult to supply resin from the side H4 side even if the regions NR2 and NR3 where the arrangement density of the protruding electrodes is low are both arranged at the position closest to the side H4. Therefore, application of the resin supply method described with reference to FIG. 29 can prevent or suppress the formation of an unfilled region.

  Further, for example, in the embodiment, as described with reference to FIGS. 5 and 6, as an example in which a plurality of bumps (projection electrodes) 11 are regularly arranged on the surface 10 a side of the semiconductor chip 10, The WPP type semiconductor chip 10 has been taken up and described. However, in some cases, the pad PD (see FIG. 6) is formed in the peripheral part of the semiconductor chip 10 and the central part inside the peripheral part, and the protruding electrode (bump) is formed immediately above the pad PD. The central portion of the semiconductor chip in plan view is called a core region, and a core circuit such as an arithmetic circuit is formed, for example. The protruding electrode formed on the core region is called an area bump and is formed by bonding a conductor made of, for example, gold (Au) or copper (Cu) to the pad PD. For this reason, when the pad PD and the protruding electrode are formed in the core region, it is necessary to determine the formation position of the pad PD and the protruding electrode in consideration of the positional relationship with the core circuit from the viewpoint of suppressing damage to the core circuit. . Therefore, on the surface of the semiconductor chip, a region with a high area bump arrangement density and a region with a low density are generated. That is, the same problem as the WPP type semiconductor chip 10 exemplarily described in the above embodiment occurs. Therefore, by applying the method for supplying the resin 4a described in the above embodiment, the generation of the unfilled region can be prevented or suppressed.

  Further, in the above-described embodiment, the embodiment using the wiring board 20 which is a so-called multi-piece substrate has been described. However, as a modified example, individual wiring boards corresponding to one product can be prepared in the board preparation step, like the wiring board 3 shown in FIG. In this case, the singulation process can be omitted.

  Moreover, although the said embodiment demonstrated many modified examples, it can apply combining each modified example in the range which does not deviate from the summary.

  The present invention can be used for a semiconductor device in which a semiconductor chip is connected to a substrate by a flip chip connection method.

1 Semiconductor device 3 Wiring board (base material, interposer)
3a Top surface (chip mounting surface, surface)
3b Bottom surface (mounting surface, back surface)
3c Side surface 3d Wiring layer 3f Solder resist film (insulating film, protective film)
3g Solder resist film (insulating film, protective film)
3h Wiring 3z Insulating layer 4 Underfill (underfill resin, resin material, stress relaxation member)
4a Resin (underfill material)
5 Solder ball 6 Terminal (land, bonding lead)
7 Land (external terminal)
10, M1, M2, M3, M4, M5, M6, M7 Semiconductor chip 10a Front surface 10b Back surface 10c Side surface 11 Bump (projection electrode)
12 Semiconductor substrate 12a main surface (semiconductor element formation surface, surface)
12b Main surface (back)
12c Semiconductor element formation region 13 Wiring layer (first wiring layer, chip wiring layer)
13a Internal wiring (wiring)
13b Surface wiring (wiring, uppermost layer wiring)
13c, 13d Insulating layer 14 Rewiring layer (wiring layer, second wiring layer)
14a Upper surface (main surface, surface)
14b Lower surface (main surface, back surface)
14c Land (Bump Land)
14d Wiring (rewiring)
14e Insulating film (organic insulating film)
14f Insulating film (organic insulating film)
15 Fuse 20 Wiring board 20a Product formation area 20b Frame (frame)
20c Dicing line (Dicing area)
25 Wafer (semiconductor wafer, semiconductor substrate)
25a Chip area (device area)
25b Scribe line (scribe area)
30 Supply device 31 Nozzle 40 Semiconductor device 41 Member B1, B2 Partial CT Chip mounting region G1 Distance (gap, clearance)
H1, H2, H3, H4 Side JH Arrow JH1, JH2, JH3, JH4, JH5 Arrow (trajectory)
K1, K2, K3, K4 Corner KH Unfilled area (bubbles)
Lz laser NR1 region (region where the arrangement density of protruding electrodes is high)
NR2, NR3, NR4, NR5, NR6, NR7 regions (regions with low projecting electrode arrangement density)
P1, P2 position (supply restart position)
PD pad (electrode pad)
S1 First side supply step S2 Discharge stop step S3 Nozzle movement step S4 Second side supply step S5 Discharge stop step S6 Nozzle movement step S7 Third side supply step S8 Discharge stop step S9 Resin curing step

Claims (17)

A semiconductor device manufacturing method including the following steps:
(A) preparing a wiring board having a chip mounting surface and a plurality of terminals formed on the chip mounting surface;
(B) a semiconductor chip having a quadrangular surface in plan view, a plurality of projecting electrodes formed on the surface, and a back surface located on the opposite side of the surface, wherein the surface is the chip mounting surface of the wiring board Arranging the plurality of terminals and the plurality of protruding electrodes electrically on the wiring board so as to face each other;
(C) a step of supplying an underfill material between the semiconductor chip and the wiring board after the step (b);
here,
The front surface and the back surface of the semiconductor chip are:
A first side, a second side that intersects with the first side, a third side that intersects with the first side and faces the second side, a fourth side that faces the first side, and the first side And a first corner that is an intersection of the second side, a second corner that is an intersection of the first side and the third side, a third corner that is an intersection of the second side and the fourth side, And a fourth corner that is an intersection of the third side and the fourth side,
On the surface of the semiconductor chip, a first region where the plurality of protruding electrodes are arranged at a first arrangement density, and the plurality of protruding electrodes are arranged at a second arrangement density lower than the first arrangement density. A second region, and a third region in which the plurality of protruding electrodes are arranged at a third arrangement density lower than the first arrangement density,
The second region is disposed at a position closest to the second side among the four sides of the semiconductor chip,
The third region is disposed at a position closest to the third side among the four sides of the semiconductor chip,
The step (c) includes the following steps:
(C1) While moving the discharge port of the supply device for supplying the underfill material along the first side from the first corner portion side to the second corner portion side of the semiconductor chip, Discharging underfill material;
(C2) a step of stopping discharge of the underfill material from the discharge port after the step (c1);
(C3) After the step (c2), the discharge port is already filled with the underfill material that is on the second side and supplied from the first side in the step (c1). Moving to a first position;
(C4) After the step (c3), restarting the discharge of the underfill material from the discharge port and supplying the underfill material from the second side;
(C5) A step of stopping the discharge of the underfill material from the discharge port after the step (c4);
(C6) After the step (c5), the discharge port is already filled with the underfill material that is on the third side and supplied from the first side in the step (c1). Moving to a second position;
(C7) After the step (c3) and before the underfill material reaches the second region on the surface of the semiconductor chip, restart the discharge of the underfill material from the discharge port, Supplying the underfill material from the third side. In claim 1,
The second region is disposed at a position closest to the third corner among the four corners of the semiconductor chip,
The method of manufacturing a semiconductor device, wherein the third region is arranged at a position closest to the fourth corner portion among the four corner portions of the semiconductor chip. In claim 2,
The surface of the semiconductor chip further includes a fourth region in which the plurality of protruding electrodes are arranged at a fourth arrangement density lower than the first arrangement density,
The method of manufacturing a semiconductor device, wherein the fourth region is disposed at a position closest to the first side among the four sides of the semiconductor chip. In claim 1,
In the step (c4), the discharge port is moved along the second side from the first corner side toward the third corner side,
In the step (c7), the discharge port is moved along the third side from the second corner side toward the fourth corner side. In claim 1,
In the step (c1), the underfill material is supplied from the first side with a first supply amount,
In the step (c4), the semiconductor device manufacturing method supplies the underfill material from the second side with a second supply amount smaller than the first supply amount. In claim 1,
In the step (c1), the underfill material is supplied from the first side with a first supply amount,
In the step (c7), the semiconductor device manufacturing method supplies the underfill material from the third side with a third supply amount smaller than the first supply amount. In claim 1,
In the step (c1), the underfill material is supplied from the first side with a first supply amount,
In the step (c4), the underfill material is supplied from the second side with a second supply amount smaller than the first supply amount,
In the step (c7), the semiconductor device manufacturing method supplies the underfill material from the third side with a third supply amount smaller than the first supply amount. In claim 1,
The method of manufacturing a semiconductor device, wherein the third region has a length in the first direction along the third side of the semiconductor chip longer than a length in the second direction along the first side in plan view. In claim 8,
The method of manufacturing a semiconductor device, wherein the second region has a length in a first direction along the second side of the semiconductor chip longer than a length in the second direction along the first side in a plan view. In claim 1,
In plan view, the semiconductor chip has a quadrangular shape, and the lengths of the first side and the fourth side are longer than those of the second side and the third side. In claim 1,
On the surface of the semiconductor chip,
A method of manufacturing a semiconductor device, wherein three or more regions where the plurality of protruding electrodes are arranged at a placement density lower than the first placement density are provided along the second side and the third side, respectively. In claim 1,
In the step (c4), the underfill material is discharged in a state where the discharge port is stationary between the first corner and the third corner,
In the step (c7), the underfill material is discharged in a state where the discharge port is stationary between the second corner portion and the fourth corner portion. In claim 1,
The second region and the third region are disposed on an imaginary line connecting a central portion of the second side and a central portion of the third side,
The semiconductor chip has a rectangular shape in plan view,
The length of the said 2nd side and the said 3rd side is a manufacturing method of the semiconductor device longer than the length of the said 1st side and the said 4th side. A semiconductor device manufacturing method including the following steps:
(A) preparing a wiring board having a chip mounting surface and a plurality of terminals formed on the chip mounting surface;
(B) a semiconductor chip having a quadrangular surface in plan view, a plurality of projecting electrodes formed on the surface, and a back surface located on the opposite side of the surface, wherein the surface is the chip mounting surface of the wiring board Arranging the plurality of terminals and the plurality of protruding electrodes electrically on the wiring board so as to face each other;
(C) a step of supplying an underfill material between the semiconductor chip and the wiring board after the step (b);
here,
The front surface and the back surface of the semiconductor chip are:
A first side, a second side that intersects with the first side, a third side that intersects with the first side and faces the second side, a fourth side that faces the first side, and the first side And a first corner that is an intersection of the second side, a second corner that is an intersection of the first side and the third side, a third corner that is an intersection of the second side and the fourth side, And a fourth corner that is an intersection of the third side and the fourth side,
The surface of the semiconductor chip has a first region where the plurality of protruding electrodes are arranged at a first arrangement density, and the plurality of protruding electrodes arranged at a second arrangement density lower than the first arrangement density. A second region,
The second region is disposed at a position closest to the first side than the other side of the semiconductor chip,
The step (c) includes the following steps:
(C1) A discharge port of a supply device that supplies the underfill material is configured so that a part of the first side is formed along a first part along the second region of the first side of the semiconductor chip. Moving and discharging the underfill material from the discharge port in the first portion;
(C2) a step of stopping discharge of the underfill material from the discharge port after the step (c1);
(C3) After the step (c2), from the discharge port to the underside from the first corner of the semiconductor chip toward the second corner and along the first side of the semiconductor chip. A process of discharging a fill material. In claim 14,
The surface of the semiconductor chip further includes a third region in which the plurality of protruding electrodes are arranged at a third arrangement density lower than the first arrangement density,
The third region is disposed at a position closest to the second corner than the other corner of the semiconductor chip,
The step (c) further includes the following steps between the step (c2) and the step (c3);
(C21) A discharge port of the supply device that supplies the underfill material is arranged so that a part of the first side is formed along a second part along the third region of the first side of the semiconductor chip. Moving and discharging the underfill material from the discharge port in the second portion;
(C22) A step of stopping the discharge of the underfill material from the discharge port after the step (c21). In claim 14,
The surface of the semiconductor chip further includes a third region in which the plurality of protruding electrodes are arranged at a third arrangement density lower than the first arrangement density,
The third region is disposed at a position closest to the second side than the other side of the semiconductor chip,
The step (c) further includes the following steps:
(C4) a step of stopping the discharge of the underfill material from the discharge port after the step (c3);
(C5) After the step (c4), the discharge port is located on the second side and to the first position where the underfill material supplied from the first side is already filled. Moving it;
(C6) A step of restarting the discharge of the underfill material from the discharge port and supplying the underfill material from the second side after the step (c4). In claim 16,
The surface of the semiconductor chip further includes a fourth region in which the plurality of protruding electrodes are arranged at a fourth arrangement density lower than the first arrangement density,
The fourth region is disposed at a position closest to the third side than the other side of the semiconductor chip;
The step (c) further includes the following steps:
(C7) After the step (c6), stopping the discharge of the underfill material from the discharge port;
(C8) After the step (c7), the discharge port is located on the third side and to the second position where the underfill material supplied from the first side is already filled. Moving it;
(C9) After the step (c6) and before the underfill material reaches the fourth region of the surface of the semiconductor chip, restart the discharge of the underfill material from the discharge port, Supplying the underfill material from the third side.

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