JP2014041951A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device which employs TSV technology.SOLUTION: A semiconductor device manufacturing method comprises polishing an insulation film IF2, a liner film IF1 and a barrier metal film BM which covers bottoms of a plurality of through electrodes TE protruding from a rear face of a semiconductor substrate SW in a chemical mechanical polishing (CMP) method to expose bottom faces of the plurality of through electrodes TE from the rear face side of the semiconductor substrate SW. At this time, a slurry which has a polishing rate of the barrier metal film BM more than five times higher than a polishing rate of the insulation film IF2 and a polishing rate of the plurality of through electrodes TE more than twice higher than a polishing rate of the insulation film IF2 is used.

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and can be suitably used for, for example, a through silicon via (TSV) technique required for manufacturing a three-dimensional multifunction device.

  There is TSV technology as an important technology for realizing a three-dimensional multifunction device. The TSV technique is a technique for forming a through electrode that penetrates a semiconductor substrate perpendicularly to the thickness direction.

  For example, by laminating the upper substrate on the lower substrate via the inorganic material post and the organic resin adhesive resin layer filling the periphery of the post, and then forming a via hole penetrating the upper substrate and the post JP, 2010-22260, A (patent documents 1) has indicated the via structure which controlled undercut in the connection part between substrates.

  Further, by using a via first method (TSV is formed before the formation of the semiconductor device) and a via last method (TSV is formed after the formation of the semiconductor device) in combination, a semiconductor device in which the resistance of the connection portion is reduced is provided. It describes in Unexamined-Japanese-Patent No. 2010-219526 (patent document 2).

JP 2010-2226060 A JP 2010-219526 A

  In the TSV technology using the via-middle method (forming TSV in the process of forming a semiconductor device), after projecting the bottoms of the plurality of through electrodes covered with the barrier metal film and the liner film from the back surface of the semiconductor substrate, An insulating film is formed on the back surface of the semiconductor substrate, and the insulating film, liner film, and barrier metal film covering the bottom surfaces of the plurality of through electrodes are removed by a chemical mechanical polishing (CMP) method. However, there is a problem that the reliability of the semiconductor device is lowered due to the exposure of the back surface of the semiconductor substrate or the remaining barrier metal film in the CMP.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the insulating film, liner film, and barrier metal film covering the bottoms of the plurality of through electrodes protruding from the back surface of the semiconductor substrate are polished by CMP to expose the bottom surfaces of the plurality of through electrodes. A slurry in which the polishing rate of the barrier metal film is 5 times or more higher than the polishing rate of the insulating film and the polishing rate of the plurality of through electrodes is 2 times or more higher than the polishing rate of the insulating film is used.

  According to one embodiment, the reliability of a semiconductor device employing TSV technology can be improved.

It is principal part sectional drawing of a semiconductor device provided with TSV by one embodiment. It is a principal part back view of the semiconductor device by one embodiment. FIG. 5 is an essential part cross-sectional view showing an enlarged part of the semiconductor device during the manufacturing process of the semiconductor device according to the embodiment; FIG. 4 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 3; FIG. 5 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 4; FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 5; FIG. 7 is an essential part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 6; FIG. 8 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 7; FIG. 9 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 8; FIG. 10 is an essential part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 9; FIG. 11 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 10; FIG. 12 is an essential part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 11; (A) And (b) is principal part sectional drawing which shows the several penetration electrode in the manufacturing process of a semiconductor device following FIG. FIG. 14 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the semiconductor device, following FIG. 12 and FIG. 13; (A) And (b) is principal part sectional drawing explaining the manufacturing process of the penetration electrode examined by the present inventors. (A) And (b) is principal part sectional drawing explaining the manufacturing process of the other penetration electrode examined by the present inventors.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and apparently indispensable in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., the shape is substantially the same unless otherwise specified or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, the term “wafer” is mainly a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments will be described in detail with reference to the drawings.

(Semiconductor device that the present inventors have compared)
First, since it is considered that the manufacturing method of the semiconductor device adopting the via-middle TSV technology according to the present embodiment will become clearer, the problems in the manufacturing method of the semiconductor device that the present inventors have compared and described will be described. To do.

  15 (a) and 15 (b) and FIGS. 16 (a) and 16 (b) are principal part cross-sectional views for explaining the manufacturing process of the through electrode.

  First, as shown in FIG. 15A, for example, a semiconductor substrate (semiconductor plate having a substantially circular planar shape called a wafer) made of single crystal silicon (Si) is prepared. The thickness of the semiconductor substrate SW is, for example, about 700 μm. Next, although not shown, a plurality of semiconductor elements are formed on the main surface (surface, first main surface) S1 of the semiconductor substrate SW, and the main surface S1 of the semiconductor substrate SW is covered so as to cover the plurality of semiconductor elements. An interlayer insulating film ILD is formed thereon.

Next, by dry etching using the resist pattern as a mask, vias (through holes, connection holes) VI are formed by sequentially processing the interlayer insulating film ILD and the semiconductor substrate SW in a region where a plurality of semiconductor elements are not formed. . Thereafter, a copper (Cu) plating film is embedded in the via VI via a liner film IF1 made of silicon oxide (SiO ₂ ) and a barrier metal film BM made of titanium (Ti) or the like. A through electrode TE made of is formed.

Next, by polishing the back surface (second main surface) S2 opposite to the main surface S1 of the semiconductor substrate SW, the thickness of the semiconductor substrate SW is set to about 50 μm, for example. At this time, since the liner film IF1, the barrier metal film BM, and the through electrode TE are not polished, the bottom of the through electrode TE covered with the liner film IF1 and the barrier metal film BM from the back surface S2 of the semiconductor substrate SW is, for example, 2 Projects about 5 μm. Subsequently, for example, silicon oxide (SiO 2) is formed on the back surface S2 of the semiconductor substrate SW so as to cover the bottom portion of the through electrode TE covered with the liner film IF1 and the barrier metal film BM, which protrudes from the back surface S2 of the semiconductor substrate SW. ₂ ) An insulating film IF2 is formed.

  Next, as shown in FIG. 15B, the insulating film IF2, the liner film IF1, and the barrier metal film BM are polished by CMP using a slurry having no polishing rate selection ratio. As a result, the bottom surface of the through electrode TE is exposed, and at the same time, the back surface S2 of the semiconductor substrate SW on which the through electrode TE is not formed is covered with the insulating film IF2.

  However, the insulating film IF2 in the region where the through electrode TE is not formed is polished in the same manner as the insulating film IF2 in the region where the through electrode TE is formed. Therefore, when the polishing of the insulating film IF2 in the region where the through electrode TE is formed and the barrier metal film BM is further polished, the back surface S2 of the semiconductor substrate SW in the region where the through electrode TE is not formed is exposed. Resulting in. Since the bottom surface of the through electrode TE is also exposed, when the back surface S2 of the semiconductor substrate SW is exposed, copper (Cu) constituting the through electrode TE diffuses from the back surface S2 side of the semiconductor substrate SW into the semiconductor substrate SW. As a result, the operating characteristics of the semiconductor element formed on the main surface S1 side of the semiconductor substrate SW change due to copper (Cu) contamination.

  Therefore, as shown in FIG. 16A, the insulating film IF2 is thicker than the height of the bottom of the through electrode TE protruding from the back surface S2 of the semiconductor substrate SW and covered with the liner film IF1 and the barrier metal film BM. The insulating film IF2, the liner film IF1, and the barrier metal film BM were polished by the CMP method.

  However, since the bottom of the through electrode TE protrudes from the back surface S2 of the semiconductor substrate SW by about 2 to 5 μm, for example, it is difficult to eliminate the step on the surface of the insulating film IF2. For this reason, as shown in FIG. 16B, the barrier metal film BM covering the bottom surface of the through electrode TE cannot be uniformly polished and removed, so that the bottom surface of the through electrode TE cannot be exposed reliably. As a result, there arises a problem of an increase in connection resistance of the through electrode TE.

  It is possible to polish until the barrier metal film BM covering the bottom surface of the through electrode TE is completely removed. However, in this case, since the through electrode TE is scraped and the height of the through electrode TE protruding from the back surface S2 of the semiconductor substrate SW varies, there is a concern about problems such as poor connection of the through electrode TE.

  As described above, in the method of manufacturing a semiconductor device employing the TSV technology using the via / middle method, problems such as fluctuations in the operating characteristics of the semiconductor element due to copper (Cu) contamination and an increase in the connection resistance of the through electrode TE, etc. There is.

  In addition, in Patent Document 1 (Japanese Patent Laid-Open No. 2010-222060), there is a description that a through-substrate via conductor is formed in a via hole by a CMP method, but there is no description or suggestion about a through electrode. In addition, Patent Document 2 (Japanese Patent Laid-Open No. 2010-219526) has no description or suggestion of a problem when exposing the through electrode, and it is considered that the same problem occurs in Patent Document 2. .

(Embodiment)
≪Semiconductor device≫
A semiconductor device including a TSV according to this embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of main parts of a semiconductor device, and FIG. 2 is a rear view of main parts of the semiconductor device.

  In a semiconductor device (semiconductor chip), a region in which various semiconductor elements such as a field effect transistor, a resistance element, and a capacitor element are formed (hereinafter referred to as an element formation region) and a region in which a plurality of through electrodes are formed ( (Hereinafter referred to as TSV formation regions) are provided in different regions. FIG. 1 illustrates an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor among various semiconductor elements formed in the element formation region. In the following description, the n-channel type MISFET is abbreviated as nMISFET.

  First, the configuration of the nMISFET formed in the element formation region will be described with reference to FIG.

As shown in FIG. 1, an isolation portion IR in which an insulating film is embedded in an isolation groove is formed on the main surface (surface, first main surface) S1 of the semiconductor substrate SW in the element formation region. An active region where the nMISFET is formed is defined by the isolation part IR. The thickness of the semiconductor substrate SW is, for example, about 50 μm. A p-type well PW is formed on the main surface S1 of the semiconductor substrate SW, and an nMISFET is formed in the region where the p-type well PW is formed. A gate electrode GE is formed on the main surface S1 of the semiconductor substrate SW via a gate insulating film GI of the nMISFET. The gate insulating film GI is made of, for example, silicon oxide (SiO ₂ ) formed by a thermal oxidation method, and the gate electrode GE is made of, for example, polycrystalline silicon (Si) formed by a CVD (Chemical Vapor Deposition) method.

A sidewall SL is formed on the side surface of the gate electrode GE of the nMISFET. The sidewall SL is made of, for example, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). An n-type semiconductor region SD that functions as a source / drain is formed in the p-type well PW on both sides of the gate electrode GE of the nMISFET with the channel region interposed therebetween.

Further, the nMISFET is covered with a stopper insulating film SIF and an interlayer insulating film ILD1. The stopper insulating film SIF is made of, for example, silicon nitride (Si ₃ N ₄ ). The interlayer insulating film ILD1 is made of, for example, silicon oxide (SiO ₂ ), and the surface thereof is flattened. In the stopper insulating film SIF and the interlayer insulating film ILD1, a connection hole (not shown) reaching the gate electrode GE and a connection hole CN reaching the n-type semiconductor region SD are formed. The connection hole CN has a columnar shape, and the diameter thereof is set to be equal to or smaller than the line width of the first layer wiring M1, and is about 0.06 μm, for example. Inside the connection hole CN, a connection electrode (plug) CE made of metal is formed via a barrier metal film BP.

  On the connection electrode CE, a first layer wiring M1 made of, for example, a copper (Cu) film is connected to the connection electrode CE and formed by a single damascene method. That is, in the first layer wiring M1, a trench TRa for wiring formation is formed in the interlayer insulating film ILD2 deposited on the connection electrode CE and the interlayer insulating film ILD1, and a copper (Cu) film is embedded therein. Is formed by. The line width of the first layer wiring M1 is, for example, about 0.1 μm.

  Further, on the first-layer wiring M1, a second-layer wiring M2 made of, for example, a copper (Cu) film is connected to the first-layer wiring M1 through a connecting member, and dual damascene (Dual Damascene) method. That is, the second-layer wiring M2 forms a wiring-forming groove TA in the interlayer insulating film ILD3 deposited on the first-layer wiring M1 and the interlayer insulating film ILD2, and further, a wiring-forming groove. A connection hole TB is formed in a portion connecting TA and the first layer wiring M1, and a copper (Cu) film is embedded in the connection hole TB. A connection member formed integrally with the second-layer wiring M2 is formed inside the connection hole TB. Note that the second-layer wiring M2 may be formed by a single damascene method in the same manner as the first-layer wiring M1.

  Furthermore, a third-layer wiring M3, a fourth-layer wiring M4, a fifth-layer wiring M5, and a sixth-layer wiring M6 are formed on the second-layer wiring M2. Further, an insulating film IL and a sealing resin RS are formed so as to cover the sixth-layer wiring M6. In the insulating film IL and the sealing resin RS, an opening VO reaching the sixth layer wiring M6 is formed, and a copper layer is connected to the sixth layer wiring M6 inside the opening VO. A (Cu) bump CB is formed, and a hemispherical external terminal (solder ball) SB is formed in connection with the copper (Cu) bump CB.

  In the embodiment, six layers of wiring (wiring M1 to wiring M6) are illustrated, but the present invention is not limited to this. The wiring may be five or less layers or seven or more layers, and the copper (Cu) bump CB and the external terminal SB are formed by connecting to the uppermost layer wiring.

  Next, the structure of the TSV formed in the TSV formation region will be described with reference to FIGS.

As shown in FIG. 1, the semiconductor substrate SW, the stopper insulating film SIF, and the interlayer insulating film ILD1 in the TSV formation region are formed with vias (through holes, connection holes) VI penetrating them. The diameter of the via VI is, for example, about 10 μm, and the depth thereof is, for example, about 50 μm. A liner film (first insulating film) IF1 is formed on the side surface of the via VI. The liner film IF1 is, for example, a silicon oxide (SiO ₂ ) film, a carbon-containing silicon oxide (SiOC) film, or an organic insulating film. Further, a through electrode TE made of a copper (Cu) film or a metal film containing copper (Cu) as a main component is formed inside the via VI via a barrier metal film BM.

  The liner film IF1 functions as a protective film that prevents metal contamination from the through electrode TE. The liner film IF1 also functions to insulate and separate the through electrode TE and the semiconductor substrate SW. The thickness of the liner film IF1 is, for example, about 0.1 to 0.4 μm.

The barrier metal film BM is, for example, a metal film made of titanium (Ti), tantalum (Ta), cobalt (Co), ruthenium (Ru), or nickel (Ni), or titanium (Ti), tantalum (Ta), cobalt (Co ), Ruthenium (Ru) or nickel (Ni) as the main component. In addition, the barrier metal film BM includes, for example, a laminated film made of a plurality of the above metal films with different metal materials, a laminated film made of the above plurality of the alloy films with different metal materials, or the above metal films with different metal materials and the above It is a laminated film made of an alloy film. Here, although the embodiment in the case of using the barrier metal film BM is described, instead of the barrier metal film BM, an insulating film having a copper (Cu) diffusion preventing performance to the liner film IF1 and the semiconductor substrate SW. For example, a silicon nitride (Si ₃ N ₄ ) film or the like may be used.

  The through electrode TE on the main surface S1 side of the semiconductor substrate SW is connected to a connection pad MC that is the same layer as the first layer wiring M1. The connection pad MC is formed by forming a connection pad forming trench TRb in the interlayer insulating film ILD2 and embedding a copper (Cu) film therein.

  An insulating film (second insulating film) IF2 is formed on the back surface (second main surface) S2 of the semiconductor substrate SW. The insulating film IF2 also functions as a protective film that prevents metal contamination from the back surface S2 of the semiconductor substrate SW.

  Furthermore, the bottom of the through electrode TE protrudes from the back surface S2 of the semiconductor substrate SW. The bottom surface of the bottom portion of the through electrode TE is exposed, and its side surface is covered with the barrier metal film BM, the liner film IF1, and the insulating film IF2.

  The size of the region where the plurality of through electrodes TE are formed is determined by a standard in order to maintain connection with a general-purpose product such as a memory. For example, as shown in FIG. 2, in a semiconductor chip (semiconductor device) SC having a size of 6 mm in length × 6 mm in width, 50 through electrodes TE are arranged vertically at a pitch of 40 μm and 6 in the center in the semiconductor chip SC. Four TSV formation areas ATSV thus formed are arranged. That is, the central portion of the semiconductor chip SC is a TSV formation region ATSV where a plurality of through electrodes TE are formed, and the other region is an element formation region where a plurality of semiconductor elements are formed. In FIG. 2, the TSV formation region ATSV is provided in the central portion of the semiconductor chip SC, but the present invention is not limited to the central portion.

≪Semiconductor device manufacturing method≫
Next, a method for manufacturing a semiconductor device employing the TSV technology based on the via / middle method according to the present embodiment will be described in the order of steps with reference to FIGS. 3 to 12 and 14 are cross-sectional views of the main part of the semiconductor device during the manufacturing process of the semiconductor device, showing a part of the element formation region and a part of the TSV formation region. FIGS. 13A and 13B are cross-sectional views of main parts showing a plurality of through electrodes in the manufacturing process of the semiconductor device. Also, nMISFETs are exemplified as semiconductor elements in the element formation regions of FIGS. 3 to 12 and 14. Further, for example, 100 or more through electrodes are formed in the semiconductor device. For convenience, FIGS. 3 to 12 and FIG. 14 show one through electrode and its peripheral portion, and FIG. One through electrode is described.

<Semiconductor element formation process>
First, as shown in FIG. 3, a semiconductor substrate (semiconductor plate having a substantially circular plane called a wafer) SW made of, for example, single crystal silicon (Si) is prepared. The thickness (first thickness) of the semiconductor substrate SW is, for example, about 700 μm. Next, the isolation part IR made of an insulating film is formed in the element isolation region of the main surface (surface, first main surface) of the semiconductor substrate SW. Subsequently, an impurity exhibiting p-type conductivity is ion-implanted into the semiconductor substrate SW in a region where the nMISFET is to be formed, thereby forming a p-type well PW.

  Next, after forming the gate insulating film GI of the nMISFET on the main surface of the semiconductor substrate SW, the gate electrode GE of the nMISFET is formed on the gate insulating film GI. Subsequently, after the sidewall SL is formed on the side surface of the gate electrode GE, an n-type conductivity impurity is ion-implanted into the p-type well PW on both sides of the gate electrode GE to function as a source / drain of the nMISFET. The type semiconductor region SD is formed in a self-aligned manner with respect to the gate electrode GE and the sidewall SL.

Next, a stopper insulating film SIF and an interlayer insulating film ILD1 are sequentially formed on the main surface of the semiconductor substrate SW. The stopper insulating film SIF is a film that serves as an etching stopper when the interlayer insulating film ILD1 is processed, and a material having an etching selectivity with respect to the interlayer insulating film ILD1 is used. The stopper insulating film SIF is, for example, a silicon nitride (Si ₃ N ₄ ) film, and the interlayer insulating film ILD1 is, for example, a silicon oxide (SiO ₂ ) film.

  Next, the interlayer insulating film ILD1 and the stopper insulating film SIF are sequentially processed by dry etching using the resist pattern as a mask to form a connection hole CN in the element formation region. The connection hole CN is formed in a portion that requires voltage application in order to operate the nMISFET such as on the n-type semiconductor region SD and the gate electrode GE.

  Next, a barrier metal film BP is formed on the main surface of the semiconductor substrate SW by, for example, a sputtering method. The barrier metal film BP is, for example, a titanium (Ti) film, a tantalum (Ta) film, a titanium nitride (TiN) film, or a tantalum nitride (TaN) film, and the thickness thereof is, for example, about 0.1 μm. Subsequently, a tungsten (W) film is formed on the barrier metal film BP by, for example, a CVD method or a sputtering method. Subsequently, the tungsten (W) film and the barrier metal film BP in a region other than the inside of the connection hole CN are removed by a CMP method, and a connection electrode (plug) CE made of a tungsten (W) film is formed inside the connection hole CN. Form.

<Penetration electrode formation process>
Next, as shown in FIG. 4, using the resist pattern as a mask, the interlayer insulating film ILD1, the stopper insulating film SIF, and the semiconductor substrate SW in the TSV formation region are sequentially etched to form the interlayer insulating film ILD1, the stopper insulating film SIF, and the semiconductor Vias (through holes, connection holes) VI are formed in the substrate SW. The diameter of the via VI is, for example, about 10 μm, and the depth thereof is, for example, about 50 μm.

Next, as shown in FIG. 5, a liner film (first insulating film) IF1 is formed on the main surface of the semiconductor substrate SW including the bottom and side surfaces of the via VI. The liner film IF1 is, for example, a silicon oxide (SiO ₂ ) film, a carbon-containing silicon oxide (SiOC) film, or an organic insulating film formed by a plasma CVD method, and the thickness thereof is, for example, about 1.0 μm.

  Next, as shown in FIG. 6, after forming a barrier metal film BM on the main surface (on the liner film IF1) of the semiconductor substrate SW, a copper (Cu) seed layer (not shown) is formed on the barrier metal film BM. Further, a copper (Cu) plating film (copper (Cu) film or alloy film containing copper (Cu) as a main component) CP is formed on the seed layer by electrolytic plating.

The barrier metal film BM is, for example, a metal film made of titanium (Ti), tantalum (Ta), cobalt (Co), ruthenium (Ru), or nickel (Ni), or titanium (Ti), tantalum (Ta), cobalt (Co ), Ruthenium (Ru) or nickel (Ni) as the main component. In addition, the barrier metal film BM includes, for example, a laminated film made of a plurality of the above metal films with different metal materials, a laminated film made of the above plurality of the alloy films with different metal materials, or the above metal films with different metal materials and It is a laminated film made of an alloy film. Here, although the embodiment in the case of using the barrier metal film BM is described, instead of the barrier metal film BM, an insulating film having a copper (Cu) diffusion preventing performance to the liner film IF1 and the semiconductor substrate SW. For example, a silicon nitride (Si ₃ N ₄ ) film or the like may be used.

  Next, as shown in FIG. 7, the copper (Cu) plating film CP, the seed layer, the barrier metal film BM, and the liner film IF1 in the region other than the inside of the via VI are removed by the CMP method to be inside the via VI. A through electrode TE made of a copper (Cu) film is formed.

<Process for forming multilayer wiring and external terminals>
Next, as shown in FIG. 8, the first layer wiring M1, the connection pad MC, the second layer wiring M2, the copper (Cu) bump CB, and the external terminals (solder balls) on the main surface side of the semiconductor substrate SW. ) SB is formed sequentially.

  First, the first layer wiring M1 is formed in the element formation region by the single damascene method, and the connection pad MC is formed in the TSV formation region.

An interlayer insulating film ILD2 is formed on the main surface of the semiconductor substrate SW. The interlayer insulating film ILD2 is, for example, a silicon oxide (SiO ₂ ) film or a carbon-containing silicon oxide (SiOC) film formed by a plasma CVD method. Subsequently, using the resist pattern as a mask, the interlayer insulating film ILD2 is dry-etched to penetrate from the upper surface to the lower surface of the interlayer insulating film ILD2 in the region where the first-layer wiring M1 in the element formation region is formed. A trench TRa for wiring formation reaching the electrode CE is formed. At the same time, a trench TRb for forming a connection pad that penetrates from the upper surface to the lower surface of the interlayer insulating film ILD2 and reaches the through electrode TE is formed in a region where the connection pad MC in the TSV formation region is formed.

  Subsequently, a barrier metal film B1 is formed on the main surface of the semiconductor substrate SW. The barrier metal film B1 is a single-layer film such as a titanium (Ti) film, a tantalum (Ta) film, a titanium nitride (TiN) film, or a tantalum nitride (TaN) film, or a laminated film in which several of these films are laminated. is there. Subsequently, a seed layer (not shown) of copper (Cu) is formed on the barrier metal film B1 by CVD or sputtering, and a copper (Cu) plating film (not shown) is further formed on the seed layer by electrolytic plating. Is omitted). The copper (Cu) plating film fills the inside of the wiring formation trench TRa and the inside of the connection pad formation trench TRb.

  Subsequently, the copper (Cu) plating film, the seed layer, and the barrier metal film B1 in regions other than the inside of the wiring formation trench TRa and the inside of the connection pad formation trench TRb are removed by CMP. As a result, the first layer wiring M1 made of a copper (Cu) film is formed inside the wiring formation trench TRa. At the same time, a connection pad MC made of a copper (Cu) film is formed in the trench TRb for forming the connection pad. In the embodiment, the copper (Cu) film constituting the first layer wiring M1 and the connection pad MC is formed by an electrolytic plating method, but may be formed by a CVD method, a sputtering method, a sputter reflow method, or the like. Good.

  Next, a second-layer wiring M2 is formed in the element formation region and the TSV formation region by a dual damascene method.

  An interlayer insulating film ILD3 is formed on the main surface of the semiconductor substrate SW by, for example, a plasma CVD method. The interlayer insulating film ILD3 is formed following the surface shapes of the underlying interlayer insulating film ILD2, the first-layer wiring M1, and the connection pad MC. Since these surfaces are substantially flat, The surface of the insulating film ILD3 is also almost flat. Subsequently, using the resist pattern as a mask, the interlayer insulating film ILD3 is dry-etched to form a wiring formation trench TA in a region where the second-layer wiring M2 is to be formed. Further, a connection hole TB reaching the first layer wiring M1 is formed in a portion connecting the wiring formation trench TA and the first layer wiring M1. At the same time, a connection hole TB reaching the connection pad MC is formed at a portion connecting the trench TA for wiring formation and the connection pad MC.

  Subsequently, after the barrier metal film B2 is formed on the main surface of the semiconductor substrate SW, a copper (Cu) seed layer (not shown) is formed on the barrier metal film B2, and then seeded by electrolytic plating. A copper (Cu) plating film (not shown) is formed on the layer. The barrier metal film B2 is a single-layer film such as a titanium (Ti) film, a tantalum (Ta) film, a titanium nitride (TiN) film, or a tantalum nitride (TaN) film, or a laminated film in which several of these films are laminated. is there.

  Subsequently, the copper (Cu) plating film, the seed layer, and the barrier metal film B2 in a region other than the inside of the wiring forming groove TA and the connection hole TB are removed by CMP to be inside the wiring forming groove TA. A second-layer wiring M2 made of a copper (Cu) film is formed, and a connection member formed integrally with the second-layer wiring M2 is formed inside the connection hole TB.

  Thereafter, an upper layer wiring is formed in the same manner as the first layer wiring M1 or the second layer wiring M2 (see FIG. 1 described above), but the description thereof is omitted here.

  Next, copper (Cu) bumps CB and external terminals (solder balls) SB are formed.

  An insulating film (not shown) and a sealing resin RS are formed on the main surface side of the semiconductor substrate SW so as to cover the uppermost wiring (for example, the sixth wiring M6 shown in FIG. 1). Subsequently, an opening VO reaching the uppermost wiring is formed in the insulating film and the sealing resin RS, and then a copper (Cu) bump CB is formed so as to fill the opening VO using an electrolytic plating method. .

  Subsequently, an external terminal (solder ball) SB is connected to the copper (Cu) bump CB exposed from the opening VO. The external terminal SB is formed, for example, by supplying a ball-shaped soldering agent by a ball supply method and then performing a heat treatment.

<Projection process of through electrode>
Next, as shown in FIG. 9, a glass support GH is attached to the main surface side of the semiconductor substrate SW via an adhesive layer CL. Instead of the glass support GH, a silicon (Si) substrate may be used as the support.

  Next, as shown in FIG. 10, the back surface (second main surface) opposite to the main surface of the semiconductor substrate SW is ground, polished, or etched back, so that the thickness (second thickness) of the semiconductor substrate SW is obtained. Is, for example, 50 μm or less. Accordingly, the bottom of the through electrode TE covered with the liner film IF1 and the barrier metal film BM is projected from the back surface of the semiconductor substrate SW. The height of the bottom portion of the through electrode TE protruding from the back surface of the semiconductor substrate SW is, for example, about 2 to 5 μm.

Next, as shown in FIG. 11, an insulating film (second insulating film) IF2 is formed on the back surface of the semiconductor substrate SW so as to cover the bottom of the protruding through electrode TE. The insulating film IF2 is, for example, a silicon oxide (SiO ₂ ) film or a stacked film of a silicon oxide (SiO ₂ ) film and a silicon nitride (Si ₃ N ₄ ) film. Here, the insulating film IF2 is formed thinner than the height of the bottom portion of the through electrode TE protruding from the back surface of the semiconductor substrate SW. The insulating film IF2 also functions as a protective film that prevents metal contamination from the back surface of the semiconductor substrate SW.

  Next, as shown in FIG. 12, the insulating film IF2, the liner film IF1, and the barrier metal film BM are polished by CMP to expose the bottom surface of the through electrode TE. In the CMP method, the polishing rate of the barrier metal film BM is five times higher than the polishing rate of the insulating film IF2 and the liner film IF1, and the polishing rate of the through electrode TE is higher than the polishing rate of the insulating film IF2 and the liner film IF1. Also use a slurry more than twice as high. In other words, a slurry having a polishing selection ratio of the barrier metal film BM to the insulating film IF2 and the liner film IF1 of 5 times or more and a polishing selection ratio of the through electrode TE to the insulating film IF2 and the liner film IF1 of 2 times or more is used. . The polishing rate of the insulating film IF2 and the liner film IF1 in the element formation region is, for example, 5 nm / min or less.

10 As an example, in the embodiment, the polishing rate of the liner film IF1 polishing rate of the barrier metal film BM formed of titanium (Ti) is made of an insulating film IF2 and the silicon oxide of silicon oxide (SiO ₂₎ (SiO ₂₎ in times, the polishing rate of the through-electrodes TE made of copper (Cu) was used twice the slurry polishing rate of the liner film IF1 made of a silicon oxide insulating film IF2 and silicon oxide consisting of (SiO ₂₎ (SiO ₂₎ . In other words, a slurry in which the polishing selection ratio of the barrier metal film BM to the insulating film IF2 and the liner film IF1 is 10 times and the polishing selection ratio of the through electrode TE to the insulating film IF2 and the liner film IF1 is doubled is used. That is, a slurry having a polishing selection ratio of SiO ₂ : Ti: Cu = 1: 10: 2 was used.

  For the slurry, for example, colloidal silica is used. As for the composition, for example, ph is neutral to acidic (less than ph7), the silica concentration is 13% or less, and contains a Cu anticorrosive (BTA (Benzotriazole) or the like). Moreover, a hard pad (IC1000 polishing pad) is used as the polishing pad, and the pressure during polishing is, for example, 2.5 to 3.5 psi.

  Under the above polishing conditions, the insulating film IF2, the liner film IF1, and the barrier metal film BM are polished.

  At this time, the pressure that the insulating film IF2 on the bottom surface of the protruding through electrode TE is pressed against the polishing pad on the platen provided in the CMP apparatus is increased. Therefore, the polishing rate of the insulating film IF2 in the element forming region is low, but the polishing rate of the insulating film IF2 in the TSV forming region is higher than the polishing rate of the insulating film IF2 in the element forming region. Therefore, as shown in FIGS. 13A and 13B, even if the insulating film IF2 and the liner film IF1 are polished until the barrier metal film BM is exposed, the amount of polishing of the insulating film IF2 in the element formation region is small. The insulating film IF2 in the element formation region maintains a sufficient thickness.

  Further, since the polishing rate of the barrier metal film BM is higher than the polishing rate of the insulating film IF2 and the liner film IF1, the amount of polishing of the insulating film IF2 in the element formation region is reduced as shown in FIG. Thus, the barrier metal film BM can be polished. Further, since the polishing rate of the through electrode TE is lower than the polishing rate of the barrier metal film BM, the through electrode TE is excessively polished after the barrier metal film BM is removed from the bottom surface of the through electrode TE. In addition, the polishing amount of the through electrode TE can be suppressed to 1 μm or less.

  Thereby, the back surface of the semiconductor substrate SW in the element formation region where the through electrode TE is not formed can be reliably covered with the insulating film IF2. In addition, it is possible to suppress variations in the height of the through electrode TE protruding from the back surface of the semiconductor substrate SW and to reliably remove the barrier metal film BM on the bottom surface of the through electrode TE. Therefore, diffusion of copper (Cu) constituting the through electrode TE into the semiconductor substrate SW can be prevented, and fluctuations in operating characteristics of the semiconductor element due to copper (Cu) contamination can be suppressed. In addition, an increase in connection resistance of the through electrode TE can be prevented.

  Next, as shown in FIG. 14, the glass support GH and the adhesive layer CL are removed. Thereafter, the semiconductor substrate SW on which the semiconductor element, the through electrode TE, and the like are formed is diced along dicing lines to divide the semiconductor device individually. The semiconductor device is substantially completed through the above steps.

  Thus, according to the embodiment, diffusion of copper (Cu) constituting the through electrode TE into the semiconductor substrate SW can be prevented, and fluctuations in operating characteristics of the semiconductor element due to copper (Cu) contamination. Can be suppressed. In addition, an increase in connection resistance of the through electrode TE can be prevented. As a result, it is possible to avoid a decrease in the reliability of the semiconductor device.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

ATSV TSV formation region B1, B2, BM, BP Barrier metal film CB Copper bump CE Connection electrode (plug)
CL adhesive layer CN connection hole CP copper plating film GE gate electrode GH glass support GI gate insulating film IF1 liner film (first insulating film)
IF2 insulating film (second insulating film)
IR isolation part IL Insulating film ILD, ILD1, ILD2, ILD3 Interlayer insulating film M1, M2, M3, M4, M5, M6 Wiring MC Connection pad PW p-type well RS Sealing resin S1 Main surface (surface, first main surface)
S2 Back side (second main surface)
SB External terminal (solder ball)
SC semiconductor chip (semiconductor substrate)
SD n-type semiconductor region SIF Stopper insulating film SL Side wall SW Semiconductor substrate TA Groove TB Connection hole TE Through electrode TRa Wiring formation groove TRb Connection pad formation groove VI Via (through hole, connection hole)
VO opening

Claims (6)

A semiconductor device manufacturing method including the following steps:
(A) forming a plurality of vias on a first main surface of a semiconductor substrate having a first thickness;
(B) forming a plurality of through electrodes in the plurality of vias via a first insulating film and a barrier film;
(C) processing the semiconductor substrate from a second main surface opposite to the first main surface to make the first thickness of the semiconductor substrate a second thickness smaller than the first thickness; Projecting bottom portions of the plurality of through electrodes covered with an insulating film and the barrier film from the second main surface of the semiconductor substrate;
(D) a step of forming a second insulating film on the second main surface of the semiconductor substrate after the step (c);
(E) After the step (d), polishing the second insulating film, the first insulating film, and the barrier film by a CMP method to expose bottom surfaces of the plurality of through electrodes,
Here, in the CMP method in the step (e), the polishing rate of the barrier film is five times higher than the polishing rate of the second insulating film, and the polishing rate of the plurality of through electrodes is the second insulating film. Use a slurry that is at least twice as high as the polishing rate. In the manufacturing method of the semiconductor device according to claim 1,
The second insulating film formed in the step (d) is a laminated film of a silicon oxide film and a silicon nitride film. In the manufacturing method of the semiconductor device according to claim 1,
The thickness of the second insulating film formed in the step (d) is smaller than the height of the plurality of through electrodes protruding from the second main surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 1,
A height of the plurality of through electrodes protruding from the second main surface of the semiconductor substrate is 2 to 5 μm. In the manufacturing method of the semiconductor device according to claim 1,
The polishing rate of the second insulating film in the region where the plurality of through electrodes are not formed is 5 nm / min or less. In the manufacturing method of the semiconductor device according to claim 1,
The plurality of through electrodes are copper or an alloy film containing copper as a main component,
The barrier film includes a metal film made of titanium, tantalum, cobalt, ruthenium or nickel, an alloy film containing titanium, tantalum, cobalt, ruthenium or nickel as a main component, and a laminated film made of a plurality of the metal films having different metal materials. A laminated film made of a plurality of the alloy films having different metal materials, or a laminated film made of the metal film and the alloy film having different metal materials,
The first insulating film is a silicon oxide film, a carbon-containing silicon oxide film, or an organic insulating film.

Images