JP2014041422A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect data dependency between instructions even when instructions being exerted have access to the same register.SOLUTION: A processor comprises: registers in which data are stored; at least one flag table having, for each register, a flag group including the number of flags assignable to corresponding instructions being exerted; a flag set section configured to set a flag assigned to an instruction in the flag group corresponding to a register to which an instruction has access according to the issue of the instruction that has access to the register; a flag reset section configured such that in response to the termination of access to the register by the instruction, the flag set in accordance with the issue of the instruction is reset; and a determination section configured to determine whether to have access to the register on the basis of the state of the flag group corresponding to the register being accessed.

Description

  The present invention relates to a processor.

  The processor executes the instructions while keeping the dependency between the instructions. Data dependence between instructions includes, for example, RAW (Read After Write) dependence, WAW (Write After Write) dependence, and WAR (Write After Read) dependence. In RAW dependence, the first instruction does not read data from the register until the instruction preceding the first instruction writes data to the register. In the WAW dependency, the first instruction does not write data to the register until the instruction preceding the first instruction writes data to the register. In WAR dependence, the first instruction does not write data to the register until the instruction preceding the first instruction reads data from the register.

  Scoreboard control has been proposed as a technique for protecting RAW dependence and the like (see, for example, Patent Documents 1 and 2). For example, in scoreboard control related to RAW dependence, when a second instruction preceding a first instruction is issued, the processor first corresponds to a register to which data is written by the second instruction (hereinafter also referred to as a target register). A flag (hereinafter also referred to as a target flag) is set. Then, the processor resets the target flag when the second instruction writes data to the target register.

  The first instruction refers to the target flag when reading data from the target register. When the target flag is reset, the processor reads data from the target register. When the target flag is set, the processor waits for the first instruction until the target flag is reset. Thereby, RAW dependence is protected.

Japanese Patent Laid-Open No. 5-2482 JP 2001-209537 A

  When a plurality of instructions being executed write data to the same register, it is not known which instruction of the plurality of instructions indicates the execution state. For this reason, the processor cannot appropriately determine whether or not the writing of data to the register by the instruction preceding the instruction to be processed is completed even if the flag is referred to. In this case, it is difficult to keep RAW dependency and WAW dependency. Similarly, when a plurality of instructions being executed read data from the same register, it is difficult to maintain WAR dependency.

  In one aspect, an object of the present invention is to protect data dependency between instructions even when multiple executing instructions access the same register.

  In one form of the present invention, the processor includes at least one flag table having, for each register, a register in which data is stored and a flag group including a number of flags that can be assigned to each of the plurality of instructions being executed. A flag set unit for setting a flag assigned to an instruction in a flag group corresponding to a register accessed by the instruction according to the issue of the instruction for accessing the register, and a flag set according to the issue of the instruction. And a flag reset unit that resets upon completion of access to the register by the instruction, and a determination unit that determines whether to access the register based on the state of the flag group corresponding to the register to be accessed. .

  Even when a plurality of instructions being executed access the same register, data dependency between instructions can be protected.

2 illustrates an example of a processor in one embodiment. An example of the flag table shown in FIG. 1 is shown. 3 illustrates an example of a logical sum unit illustrated in FIG. 2. 2 shows an example of the operation of the processor shown in FIG. 6 shows another example of the operation of the processor shown in FIG. An example of a relationship between an instruction pattern and access to a flag table is shown. 3 illustrates an example of a processor in another embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 illustrates an example of a processor 10 in one embodiment. The processor 10 processes a plurality of instructions in parallel. For example, the processor 10 performs pipeline processing. The processor 10 may execute a plurality of instructions in parallel by a plurality of arithmetic units. Further, the processor 10 may execute a plurality of pipeline processes in parallel by a plurality of arithmetic units.

  The processor 10 includes, for example, a register file 20, a flag table 30, a flag set unit 40, a flag reset unit 50, and a determination unit 60. The register file 20 includes registers R (R0 to R15) that store data. The number of bits of the register R is, for example, 32 bits or more. Note that the number of bits of the register R may be less than 32 bits. Further, the number of registers R is not limited to 16.

  The flag table 30 has a flag group FG (FG0 to FG15) for each register R. The number at the end of the sign of the flag group FG corresponds to the number at the end of the sign of the register R. For example, the flag group FG0 corresponds to the register R0. Each flag group FG has a plurality (n + 1) of flags F indicating the usage state of the corresponding register R.

  For example, the flag group FG0 has n + 1 flags F (F000-F00n) indicating the usage state of the register R0. Note that the left two digits of the last three digits of the flag F code correspond to the last digits of the flag group FG code. For example, as many flags F of each flag group FG are prepared as can be assigned to each of a plurality of instructions being executed. For example, when the maximum number of instructions that can be executed simultaneously (the maximum number of in-flight instructions) is 8, each flag group FG has 8 flags F.

  The flag setting unit 40 sets the flag F assigned to the instruction in the flag group FG corresponding to the register R accessed by the instruction in response to the issuance of the instruction for accessing the register R. For example, the flag setting unit 40 sets the flag F to be set to “1” using the set signal SETC. For example, the flag setting unit 40 may be included in a decoding unit that decodes an instruction.

  The flag reset unit 50 resets the flag F set according to the issuance of an instruction when the access to the register R by the instruction ends. For example, the flag reset unit 50 resets the reset target flag F to “0” using the reset signal RSTC. For example, the flag reset unit 50 may be included in a register read unit that reads data from the register R, a register write unit that writes data to the register, or the like.

  The determination unit 60 determines whether to access the register R based on the state of the flag group FG corresponding to the register R to be accessed. For example, the determination unit 60 outputs a signal CHK indicating the tail pointer (tail pointer TP shown in FIG. 2) in the flag table 30 when the instruction to be determined is issued to the flag table 30. Then, the determination unit 60 receives from the flag table 30 a signal REP indicating the usage state of the register R of the instruction preceding the instruction to be determined. The determination unit 60 determines whether to access the register R based on the signal REP.

  For example, the determination unit 60 may be included in a register read unit, a register write unit, or the like. When the determination unit 60 is included in the register read unit, for example, the determination unit 60 determines whether data can be read from the register R based on the state of the flag group FG corresponding to the register R to be read. . Thereby, the processor 10 can execute the instruction while keeping RAW (Read After Write) dependence. In the RAW dependence, the first instruction does not read data from the register until an instruction preceding the first instruction (hereinafter also referred to as a preceding instruction) writes data to the register.

  When the determination unit 60 is included in the register write unit, for example, the determination unit 60 determines whether or not data can be written to the register R based on the state of the flag group FG corresponding to the register R to be written. judge. As a result, the processor 10 can execute the instruction while keeping WAW (Write After Write) dependency, WAR (Write After Read) dependency, and the like. Note that in the WAW dependency, the first instruction does not write data to the register until the instruction preceding the first instruction writes data to the register. In the WAR dependency, the first instruction does not write data to the register until the instruction preceding the first instruction reads data from the register.

  Here, in the case of dealing with all of the RAW dependency, the WAW dependency, and the WAR dependency, the processor 10 has two types of a RAW / WAW flag table 30 and a WAR flag table 30. The RAW / WAW flag table 30 includes a flag F indicating whether or not writing to the register R has been completed. The WAR flag table 30 includes a flag F indicating whether or not reading to the register R is completed.

  The processor 10 has one or both of the RAW / WAW flag table 30 and the WAR flag table 30 according to the dependency relationship to be confirmed using the flag table 30.

  FIG. 2 shows an example of the flag table 30 shown in FIG. FIG. 2 shows an example of the flag table 30 when the number of flags F in each flag group FG is eight. The shaded area in FIG. 2 indicates the range of valid flags F (data) at a certain time. For example, the flag table 30 holds information indicating the usage state of the register R for each instruction even when a plurality of instructions being executed access the same register R. A column Q (Q0 to Q7) in FIG. 2 indicates the position of the flag F in the flag group FG. For example, the flag F in the same column Q indicates the usage state of the register R by the same instruction.

  The flag table 30 includes flag groups FG0 to FG15, a pointer control unit PCNT, and a logical sum unit ORU (ORU0 to ORU15). The flag F of the flag group FG is set, for example, in the order in which instructions are issued. The one-digit number at the end of the sign of the flag F corresponds to the number at the end of the sign of the column Q. In other words, the last digit of the flag F sign indicates the position of the flag F in the flag group FG. Therefore, for example, flags F having the same one-digit number at the end of the sign of the flag F indicate the use state of the register R by the same instruction. For example, the same control as the FIFO is executed on the flag group FG.

  The head pointer HP is a pointer indicating the head position (column Q) of the valid flag F. The tail pointer TP is a pointer indicating the position (column Q) next to the last position (column Q) of the valid flag F. That is, the tail pointer TP is a pointer indicating the column Q of the flag F set by a new instruction. Therefore, in the range of the valid flag F (the shaded portion in FIG. 2), the instruction that sets the flag F on the head pointer HP side is an instruction that precedes the instruction that sets the flag F on the tail pointer TP side.

  The pointer control unit PCNT controls the head pointer HP and the tail pointer TP. For example, when all the flags F of the column Q indicated by the head pointer HP (in FIG. 2, the flag F of the column Q1) are reset, the pointer control unit PCNT heads up to the column Q where the set flag F exists. The pointer HP is moved to the end side (right side in FIG. 2) of the flag group FG. When the head pointer HP indicates the column Q7, the head pointer HP moves to the column Q0, for example.

  The pointer control unit PCNT moves the tail pointer TP to the end side (right side in FIG. 2) of the flag group FG every time an instruction to access the register R is issued, for example. For example, in the RAW / WAW flag table 30, the pointer control unit PCNT moves the tail pointer TP to the end of the flag group FG (the right side in FIG. 2) every time an instruction to write data to the register R is issued. . Alternatively, in the WAR flag table 30, the pointer control unit PCNT moves the tail pointer TP to the tail side (right side in FIG. 2) of the flag group FG every time an instruction to read data from the register R is issued. When the tail pointer TP indicates the column Q7, the tail pointer TP moves to the column Q0, for example.

  Each OR unit ORU (ORU0-ORU15) receives a signal indicating the state of the flag F of each flag group FG (FG0-FG15), the head pointer HP, the tail pointer TP, and the signal CHK, and uses the corresponding register R. A signal REP (REP0-REP15) is output. The numbers at the end of the signs of the logical sum ORU and the signal REP correspond to the numbers at the end of the signs of the flag group FG. That is, the numbers at the end of the signs of the logical sum ORU and the signal REP correspond to the numbers at the end of the signs of the register R.

  The signal CHK is, for example, a signal indicating the tail pointer TP when a determination target instruction is issued. That is, the instruction assigned to the flag F on the head pointer HP side from the position indicated by the signal CHK is an instruction preceding the instruction to be determined. For example, the logical sum unit ORU selects the flag F on the head pointer HP side from the position indicated by the signal CHK as the target of the logical sum from the range of the valid flag F. Then, the logical sum unit ORU outputs the logical sum result of the selected flag F as a signal REP indicating the use state of the register R.

  That is, the OR unit ORU selects the flag F corresponding to the instruction preceding the instruction to be determined from the flag group FG corresponding to the register R to be accessed. Then, the logical sum unit ORU outputs the logical sum result REP of the selected flag F to the determination unit 60. Thereby, the determination unit 60 can appropriately determine the usage state of the register R by the instruction preceding the instruction to be determined.

  FIG. 3 shows an example of the logical sum unit ORU shown in FIG. FIG. 3 shows an example of the logical sum unit ORU0 corresponding to the flag group FG0. In FIG. 3, the same reference numerals as those of the flags F (F000-F007) are used as signals indicating the states of the flags F (F000-F007) of the flag group FG0. The configuration of the logical sum unit ORU other than the logical sum unit ORU0 is the same as that of the logical sum unit ORU0. For example, the configuration of the logical sum units ORU1 to ORU15 is the same as that of the logical sum unit ORU0.

  The logical sum unit ORU0 includes a selection unit SELU (SELU0-SELU7) corresponding to the flag F (F000-F007) of the flag group FG0 and a logical sum circuit OR1. The number at the end of the code of the selection unit SELU corresponds to the number of the last digit of the code of the flag F. For example, the selection unit SELU0 corresponds to the flag F000. The configurations of the selection units SELU0 to SELU7 are the same as each other. For example, the configuration of the selection units SELU1 to SELU7 is the same as that of the selection unit SELU0. Therefore, in FIG. 3, the selection unit SELU0 will be described in detail.

  Based on the signal CHK and the head pointer HP, the selection unit SELU0 outputs either the value of the flag F000 or the signal of the logic value “0” to the OR circuit OR1. For example, the selection unit SELU0 includes comparison units COMP1 and COMP2, and AND circuits AND1 and AND2.

  The comparison unit COMP1 compares the position (value) indicated by the signal CHK with the position “0” of the flag F000, and outputs the comparison result to the AND circuit AND1. For example, when the position “0” of the flag F000 is smaller than the position (value) indicated by the signal CHK, the comparison unit COMP1 outputs a signal having a logical value “1” to the AND circuit AND1. Further, the comparison unit COMP1 outputs a signal having a logic value “0” to the AND circuit AND1 when the position “0” of the flag F000 is equal to or greater than the position (value) indicated by the signal CHK.

  The comparison unit COMP2 compares the position (value) indicated by the head pointer HP with the position “0” of the flag F000, and outputs the comparison result to the AND circuit AND1. For example, when the position “0” of the flag F000 is greater than or equal to the position (value) indicated by the head pointer HP, the comparison unit COMP2 outputs a signal having a logical value “1” to the AND circuit AND1. Further, when the position “0” of the flag F000 is smaller than the position (value) indicated by the head pointer HP, the comparison unit COMP1 outputs a signal having a logical value “0” to the AND circuit AND1.

  The AND circuit AND1 outputs a logical product result of the comparison result received from the comparison unit COMP1 and the comparison result received from the comparison unit COMP2 to the AND circuit AND2. That is, in the block including the comparison units COMP1 and COMP2 and the AND circuit AND1, the position “0” of the flag F000 is equal to or larger than the position (value) indicated by the head pointer HP and smaller than the position (value) indicated by the signal CHK. At this time, a signal of logical value “1” is output to the AND circuit AND2.

  In other words, the block including the comparison units COMP1 and COMP2 and the logical product circuit AND1 outputs a signal having the logical value “1” to the logical product circuit AND2 when the position “0” of the flag F000 is the logical sum target range. . Therefore, the block including the comparison units COMP1 and COMP2 and the logical product circuit AND1 outputs a signal having a logical value “0” to the logical product circuit AND2 when the position “0” of the flag F000 is outside the logical OR target range.

  The AND circuit AND2 receives the flag F000 and the output signal of the AND circuit AND1. Then, the logical product circuit AND2 outputs the logical product result OUT0 of the flag F000 and the output signal of the logical product circuit AND1 to the logical sum circuit OR1. That is, the AND circuit AND2 outputs the value of the flag F000 as the signal OUT0 to the OR circuit OR1 when the position “0” of the flag F000 is in the range of the logical sum. Further, when the position “0” of the flag F000 is outside the range of the logical sum, the logical product circuit AND2 outputs the signal OUT0 having the logical value “0” to the logical sum circuit OR1 regardless of the value of the flag F000.

  As described above, the selection unit SELU0 outputs the value of the flag F000 to the logical sum circuit OR1 as the signal OUT0 when the position “0” of the flag F000 is the logical sum target range. The selection unit SELU0 outputs a signal OUT0 having a logical value “0” to the logical sum circuit OR1 when the position “0” of the flag F000 is outside the logical sum target range.

  Similar to the selection unit SELU0, each of the selection units SELU1 to SELU7 uses the value of the flag F as a signal OUT (OUT1 to OUT7) when the position of the flag F corresponding to each selection unit SELU1 to SELU7 is within the logical OR target range. Output to the OR circuit OR1. Each of the selection units SELU1 to SELU7 outputs a signal OUT (OUT1 to OUT7) having a logical value “0” when the position of the flag F corresponding to each selection unit SELU1 to SELU7 is outside the logical sum target range. Output to OR1.

  For example, the selection unit SELU1 outputs the value of the flag F001 as the signal OUT1 to the logical sum circuit OR1 when the position “1” of the flag F001 is the logical sum target range. The selection unit SELU1 outputs a signal OUT1 having a logical value “0” to the logical sum circuit OR1 when the position “1” of the flag F001 is outside the logical sum target range.

  For example, in FIG. 2, when the head pointer HP is positioned on the right side of the tail pointer TP, the comparison unit COMP1 of each selection unit SELU indicates the position of the flag F below the position (value) indicated by the tail pointer TP. Correct and compare. That is, in FIG. 2, when the position indicated by the head pointer HP (the last digit of the code of the column Q) is larger than the position indicated by the tail pointer TP (the last digit of the code of the column Q), the comparison unit of each selection unit SELU. COMP1 or the like corrects and compares the position of the flag F below the position indicated by the tail pointer TP.

  For example, in FIG. 2, when the position indicated by the head pointer HP is larger than the position indicated by the tail pointer TP, the position of the flag F below the position indicated by the tail pointer TP is 8 in the last digit of the sign of the flag F. It is converted into a value obtained by adding and compared. Similarly, when the position indicated by the head pointer HP is larger than the position indicated by the tail pointer TP, for example, the signal CHK indicating a position corresponding to the position indicated by the tail pointer TP or less indicates 8 at the position (value) indicated by the signal CHK. It is converted into the added value and compared.

  The OR circuit OR1 outputs a logical sum result REP0 of the signals OUT0 to OUT7 received from the selection units SELU0 to SELU7. As a result, the signal REP0 indicating the usage state of the register R0 by the instruction preceding the instruction corresponding to the position indicated by the signal CHK (the instruction to be determined) is output to the determination unit 60 illustrated in FIG.

  The configuration of the logical sum unit ORU is not limited to this example. Further, the configuration of the processor 10 is not limited to the example described with reference to FIGS. For example, the determination unit 60 may include the logical sum unit ORU illustrated in FIGS. In this case, the logical sum unit ORU is omitted from the flag table 30.

  FIG. 4 shows an example of the operation of the processor 10 shown in FIG. FIG. 4 shows an example of the operation of the processor 10 that uses the flag table 30 as the RAW / WAW flag table 30. For example, the processor 10 uses the RAW / WAW flag table 30 to execute control similar to scoreboard control. In the example of FIG. 4, the processor 10 executes pipeline processing having an instruction issue stage IS, a register read stage RR, an execution stage EX, and a register write stage WB. In FIG. 4, in order to make the drawing easy to see, signals between the instructions IS1 and IS3 and the flag groups FG0 and FG15 are extracted and described.

  The instruction IS1 is an instruction that reads data from a register R other than the registers R0 and R15 and writes an execution result (data) to the register R0. The instruction IS2 is an instruction that reads data from a register R other than the registers R0 and R15 and writes an execution result (data) to a register R other than the registers R0 and R15. The instruction IS3 is an instruction that reads data from the register R0 and writes an execution result (data) to the register R15.

  For example, in the instruction issue stage ID of the instruction IS1, the processor 10 reads the instruction IS1 from the instruction memory. Then, the processor 10 decodes the instruction IS1 read from the instruction memory and issues the instruction IS1. Furthermore, the flag setting unit 40 of the processor 10 sets the flag F003 of the flag group FG0 corresponding to the register R0 into which the execution result of the instruction IS1 is written to “1” using the set signal SETC. That is, the flag F003 is set when the instruction IS1 is issued.

  In the register read stage RR of the instruction IS1, the processor 10 reads data used in the instruction IS1 from the register R specified by the operand. In the execution stage EX of the instruction IS1, processing (calculation or the like) based on the instruction IS1 is executed using the data read in the register read stage RR.

  In the register write stage WB of the instruction IS1, the determination unit 60 of the processor 10 determines the use state of the register R0 by the preceding instruction of the instruction IS1. For example, the determination unit 60 outputs a signal CHK indicating the position “3” of the flag F003 corresponding to the instruction IS1 to the flag table 30. Then, the determination unit 60 receives the signal REP0 indicating the usage state of the register R0 by the instruction preceding the instruction IS1 from the flag table 30. Based on signal REP0 received from flag table 30, determination unit 60 determines whether or not the writing of data to register R0 by the preceding instruction of instruction IS1 is completed.

  For example, when the head point HP indicates the position “0” of the flag F000, when all of the flags F000-F002 are reset to “0”, data is written to the register R0 by the preceding instruction of the instruction IS1. Have finished. Further, for example, when the head point HP indicates the position “0” of the flag F000, when at least one of the flags F000-F002 is set to “1”, data to the register R0 by the preceding instruction of the instruction IS1 Writing has not been completed.

  When the writing of data to the register R0 by the preceding instruction of the instruction IS1 is completed, the processor 10 writes the execution result to the register R0. Further, the flag reset unit 50 of the processor 10 resets the flag F003 of the flag group FG0 set at the instruction issue stage ID to “0” using the reset signal RSTC. That is, the flag F003 is reset when data is written to the register R0 by the instruction IS1.

  Note that when the writing of data to the register R0 by the preceding instruction of the instruction IS1 is not completed, the processor 10 performs processing of the register writing stage WB and the stages upstream of the register writing stage WB (stage ID, RR, EX). Stall. For example, the processor 10 stalls the processing of the instruction issue stage ID, the register read stage RR, the execution stage EX, and the register write stage WB until the writing of data to the register R0 by the instruction preceding the instruction IS1 is completed.

  In this way, the determination unit 60 determines whether or not the writing of data to the register R0 by the preceding instruction of the instruction IS1 is completed even when a plurality of currently executed instructions IS writes data to the same register R0. A determination can be made based on the signal REP0. As a result, the processor 10 can execute the instruction IS1 while keeping the WAW dependence, even when a plurality of instructions IS being executed writes data to the same register R0. In addition, for example, the processor 10 can protect WAW dependence when executing the issuance of instructions out of order.

  Each stage ID, RR, EX, and WB of the instruction IS2 is executed after each stage ID, RR, EX, and WB of the instruction IS1 is completed. For example, the instruction issue stage ID of the instruction IS2 is executed after the instruction issue stage ID of the instruction IS1 is completed. The processing of each stage ID, RR, EX, and WB of the instruction IS2 is the same as the processing of each stage ID, RR, EX, and WB of the instruction IS1, except for the register R and flag F to be accessed.

  Each stage ID, RR, EX, and WB of the instruction IS3 is executed after each stage ID, RR, EX, and WB of the instruction IS2 is completed. For example, the instruction issue stage ID of the instruction IS3 is executed after the instruction issue stage ID of the instruction IS2 is completed. The processing of each stage ID, RR, EX, and WB of the instruction IS3 is the same as the processing of each stage ID, RR, EX, and WB of the instruction IS1, except for the register R and flag F to be accessed.

  For example, in the instruction issue stage ID of the instruction IS3, the processor 10 decodes the instruction IS3 read from the instruction memory and issues the instruction IS3. Further, the flag setting unit 40 of the processor 10 sets the flag F155 of the flag group FG15 corresponding to the register R15 to which the execution result of the instruction IS3 is written to “1” using the set signal SETC. That is, the flag F155 is set when the instruction IS3 is issued.

  In the register read stage RR of the instruction IS3, the determination unit 60 of the processor 10 determines the usage state of the register R0 by the preceding instruction of the instruction IS3. For example, the determination unit 60 outputs a signal CHK indicating the position “5” of the flag F corresponding to the instruction IS3 to the flag table 30. Then, the determination unit 60 receives the signal REP0 indicating the usage state of the register R0 by the preceding instruction of the instruction IS3 from the flag table 30. Based on signal REP0 received from flag table 30, determination unit 60 determines whether or not the writing of data to register R0 by the preceding instruction of instruction IS3 is completed.

  For example, when the head point HP indicates the position “3” of the flag F003, when all of the flags F003 and F004 are reset to “0”, data is written to the register R0 by the preceding instruction of the instruction IS3. Have finished. Further, for example, when the head point HP indicates the position “3” of the flag F003, when at least one of the flags F003 and F004 is set to “1”, data to the register R0 by the preceding instruction of the instruction IS3 Writing has not been completed.

  For example, in FIG. 4, since the instruction IS2 does not write data to the register R0, the flag F004 is reset to “0”. Therefore, for example, when the flag F003 is reset to “0”, the determination unit 60 receives the signal REP0 having a logical value “0”. That is, in the example of FIG. 4, when the head point HP indicates the position “3” of the flag F003, when the writing of data to the register R0 by the instruction IS1 is completed, the determination unit 60 determines the logical value “0”. Signal REP0. As a result, the determination unit 60 determines that the writing of data to the register R0 by the preceding instruction of the instruction IS3 is completed.

  In FIG. 4, for example, when the instruction IS2 is an instruction to write data to the register R0, the flag F004 corresponding to the instruction IS2 is set to “1”. Therefore, even if the flag F003 is reset to “0”, the determination unit 60 receives the signal REP0 having the logical value “1” during the period in which the flag F004 is set to “1”. For this reason, the determination unit 60 determines that the writing of data to the register R0 by the preceding instruction of the instruction IS3 is not completed. In this way, the determination unit 60 indicates whether or not the writing of data to the register R0 by the preceding instruction of the instruction IS3 is completed even when a plurality of currently executed instructions IS writes data to the same register R0. The determination can be made based on REP0.

  When the writing of data to the register R0 by the instruction preceding the instruction IS3 has been completed, the processor 10 reads data used by the instruction IS3 from the register R0. Note that when the writing of data to the register R0 by the preceding instruction of the instruction IS3 is not completed, the processor 10 stalls the processing of the register reading stage RR and the instruction issuing stage IS upstream from the register reading stage RR. For example, the processor 10 stalls the processing of the instruction issue stage IS and the register read stage RR until the writing of data to the register R0 by the instruction preceding the instruction IS3 is completed.

  In this way, the processor 10 indicates whether or not the writing of data to the register R0 by the preceding instruction of the instruction IS3 is completed even when a plurality of instructions IS being written writes data to the same register R0. The determination can be made based on REP0. As a result, the processor 10 can execute the instruction IS3 while keeping the RAW dependence even when a plurality of instructions IS being executed writes data to the same register R0. In addition, for example, the processor 10 can protect the RAW dependency even when the instruction issuance is executed out of order.

  In the execution stage EX of the instruction IS3, processing (calculation or the like) based on the instruction IS3 is executed using the data read in the register read stage RR. In the register write stage WB of the instruction IS3, the processor 10 writes the execution result in the register R15. Further, the flag reset unit 50 of the processor 10 resets the flag F155 of the flag group FG15 set at the instruction issue stage ID to “0” using the reset signal RSTC. That is, the flag F155 is reset when data is written to the register R15 by the instruction IS3.

  Thus, in both the RAW-dependent confirmation process and the WAW-dependent confirmation process, the flag F is set in the instruction issue stage ID, and the flag F is reset in the register write stage WB. For this reason, in this embodiment, both the RAW dependency and the WAW dependency can be confirmed using the common flag table 30. Note that the timing for referencing the flag F (the stage of pipeline processing) differs between the RAW-dependent confirmation processing and the WAW-dependent confirmation processing.

  For example, when confirming both RAW dependency and WAW dependency in the processing for one instruction, the processor 10 determines the state of the flag group FG (more specifically, the flag F corresponding to the preceding instruction of the instruction to be determined) This is confirmed when data is read from the register R and when data is written to the register R. That is, when confirming both RAW dependency and WAW dependency in the processing for one instruction, the processor 10 confirms the state of the flag group FG twice.

  When the RAW / WAW flag table 30 receives the signal CHK transmitted at the register read stage RR and the signal CHK transmitted at the register write stage WB almost simultaneously, for example, it corresponds to the previously issued instruction. The processing based on the signal CHK to be performed is executed first.

  FIG. 5 shows another example of the operation of the processor 10 shown in FIG. FIG. 5 shows an example of the operation of the processor 10 that uses the flag table 30 as the WAR flag table 30. For example, the processor 10 uses the WAR flag table 30 to execute the same control as the scoreboard control. In the example of FIG. 5, the processor 10 executes pipeline processing having an instruction issue stage IS, a register read stage RR, an execution stage EX, and a register write stage WB.

  The processing of each stage ID, RR, EX, and WB is the same as the processing of each stage ID, RR, EX, and WB described with reference to FIG. 4 except for the operation related to the flag F and the register to be accessed. Detailed description of the processing described in FIG. 4 is omitted. In FIG. 5, signals between the instructions IS4 and IS6 and the flag groups FG0 and FG15 are extracted and described for easy understanding of the drawing.

  The instruction IS4 is an instruction that reads data from the register R0 and writes an execution result (data) to a register R other than the registers R0 and R15. The instruction IS5 is an instruction that reads data from a register R other than the registers R0 and R15 and writes an execution result (data) to a register R other than the registers R0 and R15. The instruction IS6 is an instruction that reads data from the register R15 and writes an execution result (data) to the register R0.

  For example, in the instruction issue stage ID of the instruction IS4, the processor 10 decodes the instruction IS4 read from the instruction memory and issues the instruction IS4. Further, the flag setting unit 40 of the processor 10 sets the flag F003 of the flag group FG0 corresponding to the register R0 from which data used by the instruction IS4 is read to “1” using the set signal SETC. That is, the flag F003 is set when the instruction IS4 is issued.

  In the register read stage RR of the instruction IS4, the processor 10 reads data used in the instruction IS4 from the register R0. Further, the flag reset unit 50 of the processor 10 resets the flag F003 of the flag group FG0 set at the instruction issue stage ID to “0” using the reset signal RSTC. That is, the flag F003 is reset when data is read from the register R0 by the instruction IS4.

  In the execution stage EX of the instruction IS4, processing (calculation or the like) based on the instruction IS4 is executed using the data read in the register read stage RR. In the register write stage WB of the instruction IS4, for example, the processor 10 writes the execution result in the register R specified by the operand. Note that the execution result is written to the register R after confirming the use state of the register R to which the execution result is written, as shown in the instruction IS6.

  Each stage ID, RR, EX, and WB of the instruction IS5 is executed after each stage ID, RR, EX, and WB of the instruction IS4 is completed. For example, the instruction issue stage ID of the instruction IS5 is executed after the instruction issue stage ID of the instruction IS4 is completed. The processing of each stage ID, RR, EX, and WB of the instruction IS5 is the same as the processing of each stage ID, RR, EX, and WB of the instruction IS4, except for the register R and flag F to be accessed.

  The stage ID, RR, EX, and WB of the instruction IS6 are executed after the stage ID, RR, EX, and WB of the instruction IS5 are completed. For example, the instruction issue stage ID of the instruction IS6 is executed after the instruction issue stage ID of the instruction IS5 is completed. The processing of each stage ID, RR, EX, and WB of the instruction IS6 is the same as the processing of each stage ID, RR, EX, and WB of the instruction IS4, except for the register R and the flag F that are accessed.

  For example, in the instruction issue stage ID of the instruction IS6, the processor 10 decodes the instruction IS6 read from the instruction memory and issues the instruction IS6. Further, the flag setting unit 40 of the processor 10 sets the flag F155 of the flag group FG15 corresponding to the register R15 from which data used by the instruction IS6 is read to “1” using the set signal SETC. That is, the flag F155 is set when the instruction IS6 is issued.

  In the register read stage RR of the instruction IS6, the processor 10 reads data used in the instruction IS6 from the register R15. Further, the flag reset unit 50 of the processor 10 resets the flag F115 of the flag group FG15 set by the instruction issue stage ID to “0” using the reset signal RSTC. That is, the flag F115 is reset when data is read from the register R15 by the instruction IS6. In the execution stage EX of the instruction IS6, the instruction IS6 is executed using the data read in the register read stage RR.

  In the register write stage WB of the instruction IS6, the determination unit 60 of the processor 10 determines the use state of the register R0 by the preceding instruction of the instruction IS6. For example, the determination unit 60 outputs a signal CHK indicating the position “5” of the flag F corresponding to the instruction IS6 to the flag table 30. Then, the determination unit 60 receives the signal REP0 indicating the usage state of the register R0 by the preceding instruction of the instruction IS6 from the flag table 30. Based on signal REP0 received from flag table 30, determination unit 60 determines whether or not reading of data from register R0 by the preceding instruction of instruction IS6 has been completed.

  For example, when the head point HP indicates the position “3” of the flag F003, when all of the flags F003 and F004 are reset to “0”, reading of data from the register R0 by the preceding instruction of the instruction IS6 is performed. Have finished. Further, for example, when the head point HP indicates the position “3” of the flag F003, when at least one of the flags F003 and F004 is set to “1”, the data from the register R0 by the preceding instruction of the instruction IS6 The reading of is not completed.

  For example, in FIG. 5, since the instruction IS5 does not read data from the register R0, the flag F004 is reset to “0”. Therefore, for example, when the flag F003 is reset to “0”, the determination unit 60 receives the signal REP0 having a logical value “0”. In other words, in the example of FIG. 5, when the head point HP indicates the position “3” of the flag F003, when the reading of data from the register R0 by the instruction IS4 is completed, the determination unit 60 sets the logical value “0”. Signal REP0. Thereby, the determination unit 60 determines that reading of data from the register R0 by the preceding instruction of the instruction IS6 is completed.

  In FIG. 5, for example, when the instruction IS5 is an instruction for reading data from the register R0, the flag F004 corresponding to the instruction IS5 is set to “1”. Therefore, even if the flag F003 is reset to “0”, the determination unit 60 receives the signal REP0 having the logical value “1” during the period in which the flag F004 is set to “1”. For this reason, the determination unit 60 determines that reading of data from the register R0 by the preceding instruction of the instruction IS6 has not been completed. In this way, the determination unit 60 indicates whether or not the reading of data from the register R0 by the preceding instruction of the instruction IS6 is completed even when a plurality of currently executed instructions IS read data from the same register R0. The determination can be made based on REP0.

  When the reading of data from the register R0 by the preceding instruction of the instruction IS6 is completed, the processor 10 writes the execution result in the register R0. Note that when the reading of data from the register R0 by the preceding instruction of the instruction IS6 has not been completed, the processor 10 performs processing of the register write stage WB and the stages upstream of the register write stage WB (stage ID, RR, EX). Stall. For example, the processor 10 stalls the processing of the instruction issue stage ID, the register read stage RR, the execution stage EX, and the register write stage WB until the reading of data from the register R0 by the preceding instruction of the instruction IS6 is completed.

  In this way, the processor 10 determines whether or not the reading of data from the register R0 by the preceding instruction of the instruction IS6 is completed even when a plurality of instructions IS being executed read data from the same register R0. Can be determined based on As a result, the processor 10 can execute the instruction IS6 while maintaining the WAR dependence even when a plurality of instructions IS being executed read data from the same register R0. In addition, for example, the processor 10 can protect the WAR dependence when executing the issuance of an instruction out of order.

  In the WAR-dependent confirmation process, the flag F that is set is different from the flag F that is set in the RAW-dependent and WAW-dependent confirmation processes. For this reason, in this embodiment, when confirming all of RAW dependence, WAW dependence, and WAR dependence, the processor 10 has two types of the RAW / WAW flag table 30 and the WAR flag table 30. That is, when confirming all of the RAW dependency, WAW dependency, and WAR dependency, the processor 10 sets, for each register R, the number of flags F that is twice the maximum number of instructions that can be executed simultaneously (maximum number of in-flight instructions). Have.

  Note that an increase in the number of flags F is suppressed in a processor (for example, a vector processor) in which the number of instructions (in-flight instructions) existing in the processor is small. For example, in a vector processor that handles a large amount of data with a single instruction, the disadvantages due to the increase in the number of flags F (disadvantages such as an increase in circuit scale) are compared to the configuration in which the number of registers R is increased for register renaming. Small.

  FIG. 6 shows an example of the relationship between the instruction pattern PT and access to the flag table 30. The circles in FIG. 6 indicate that the processing of each item for the flag table 30 is executed.

  The instruction of the pattern PT1 is an instruction that executes both register read (reading data from the register R) and register write (writing data to the register R). In the instruction pattern PT1, the flag F in the WAR flag table 30 is set / reset, the flag F in the WAR flag table 30 is referenced, the flag F in the RAW / WAW flag table 30 is set / reset, and the RAW / WAW. The flag F in the use flag table 30 is referred to.

  The instruction of pattern PT2 is an instruction that executes only register read out of register read and register write. In the instruction pattern PT2, setting / resetting of the flag F of the WAR flag table 30 and reference of the flag F of the RAW / WAW flag table 30 are executed.

  The instruction of pattern PT3 is an instruction that executes only register write out of register read and register write. In the instruction pattern PT3, the flag F in the WAR flag table 30 is referred to, the flag F in the RAW / WAW flag table 30 is set / reset, and the flag F in the RAW / WAW flag table 30 is referred to. .

  The instruction of pattern PT4 is an instruction in which neither register read nor register write is executed. Therefore, in the instruction pattern PT4, neither the WAR flag table 30 nor the RAW / WAW flag table 30 is accessed. As described above, in the instruction for accessing the register R (instructions of the patterns PT1 to PT3), at least one flag F of the WAR flag table 30 and the RAW / WAW flag table 30 is set.

  When the processor 10 has both the WAR flag table 30 and the RAW / WAW flag table 30, the common head pointer HP and tail pointer TP are used in the WAR flag table 30 and the RAW / WAW flag table 30. Is done. That is, the processor 10 has a pointer control unit PCNT common to the WAR flag table 30 and the RAW / WAW flag table 30. In this case, the pointer control unit PCNT, for example, sets the tail pointer TP to the tail side of the flag group FG (the right side in FIG. 2) every time an instruction to access the register R (any one of the patterns PT1 to PT3) is issued. ).

  For example, the pointer control unit PCNT updates the head pointer HP when the flag F at the position indicated by the head pointer HP is all reset in both the WAR flag table 30 and the RAW / WAW flag table 30. . For example, the pointer control unit PCNT moves the head pointer HP to the end side (right side in FIG. 2) of the flag group FG to the position where the set flag F exists.

  As described above, in this embodiment, the processor 10 has, for each register R, a flag group FG including a number of flags F that can be assigned to each of the plurality of instructions being executed. For example, the processor 10 uses the flag F of the flag group FG as a flag indicating whether or not reading to the register R is completed, so that a plurality of instructions IS being executed can read data from the same register R. WAR dependency can be protected. For example, the determination unit 60 of the processor 10 determines whether or not reading of data from the register R by an instruction preceding the instruction to be determined is completed even when a plurality of currently executed instructions IS read data from the same register R. Can be determined based on the signal REP.

  Further, the processor 10 uses, for example, the flag F of the flag group FG as a flag indicating whether or not the writing to the register R is completed, so that a plurality of instructions IS being executed writes data to the same register R. In addition, RAW dependency and WAW dependency can be protected. For example, the determination unit 60 of the processor 10 determines whether or not the writing of data to the register R by the instruction preceding the instruction to be determined is completed even when a plurality of currently executed instructions IS writes data to the same register R. Can be determined based on the signal REP.

  Further, in this embodiment, by using both the WAR flag table 30 and the RAW / WAW flag table 30, even when a plurality of executing instructions access the same register R, the WAR dependency and the RAW dependency And WAW dependency can be protected. Thus, in this embodiment, even when a plurality of instructions being executed access the same register R, data dependence between instructions can be protected.

  In this embodiment, since the flag table 30 includes a flag group FG including a plurality of flags F for each register R, the setting of the flag F and the resetting of the flag F are performed at different stages in the pipeline processing. It can be executed with. Thereby, in this embodiment, the number of pipeline processing stages (the number of stages) can be appropriately designed.

  FIG. 7 shows an example of the processor 12 in another embodiment. Elements similar to those described in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. The processor 12 processes a plurality of instructions in parallel. For example, the processor 12 executes two pipeline processes in parallel by two processing systems. The register read unit RGR1, the arithmetic unit ALU1, and the register write unit RGW1 are included in one of the two processing systems. Further, the register read unit RGR2, the arithmetic unit ALU2, and the register write unit RGW2 are included in the other processing system of the two processing systems. The processor 12 may be designed to execute three or more pipeline processes in parallel, or may be designed to execute one pipeline process.

  Pipeline processing executed by the processor 12 is divided into, for example, an instruction issue stage, a register read stage, an execution stage, and a register write stage by the pipeline register PRG. The processing of the instruction issue stage, the register read stage, the execution stage, and the register write stage is the same as the process of the instruction issue stage ID, register read stage RR, execution stage EX, and register write stage WB described with reference to FIGS. .

  The processor 12 includes, for example, a register file 20, a RAW / WAW flag table 30A, a WAR flag table 30B, an instruction memory MEM, a decode unit DEC, register read units RGR1, RGR2, arithmetic units ALU1, ALU2, register write units RGW1, RGW2 and pipeline registers PRG11, PRG12, PRG21, PRG22, PRG31, and PRG32 are included.

  The register file 20 is the same as the register file 20 of the embodiment described with reference to FIGS. The RAW / WAW flag table 30A and the WAR flag table 30B are the same as the flag table 30 of the embodiment described with reference to FIGS. For example, each flag table 30A, 30B has a flag group FG including a number of flags F that can be assigned to each of a plurality of instructions being executed for each register R. The pointer controller PCNT shown in FIG. 2 is included in one of the RAW / WAW flag table 30A and the WAR flag table 30B. Each flag table 30A, 30B has, for example, a logical sum unit ORU corresponding to each of two processing systems.

  The instruction memory MEM stores an instruction to be executed by the processor 12, for example. The instruction stored in the instruction memory MEM is read by the decoding unit DEC, for example, at the instruction issue stage.

  For example, at the instruction issue stage, the decode unit DEC decodes the instruction read from the instruction memory MEM and issues the instruction. The decoding unit DEC has a flag setting unit 40. The flag setting unit 40 of the decoding unit DEC is the same as the flag setting unit 40 of the embodiment described with reference to FIGS. For example, the flag set unit 40 assigns an entry (flag F at the position indicated by the tail point TP shown in FIG. 2) in each flag table 30A, 30B to the instruction read from the instruction memory MEM in the order in which the instructions are issued. Then, the flag setting unit 40 sets a specific flag F (flag F corresponding to the register R accessed by the instruction) on the assigned entry using the signal SETC.

  Thereby, in the RAW / WAW flag table 30A, for example, the flag F corresponding to the register R into which data is written by the instruction is set out of the flags F at the position indicated by the tail point TP. In the WAR flag table 30B, for example, the flag F corresponding to the register R from which data is read by an instruction is set out of the flags F at the position indicated by the tail point TP.

  Output data (decoding result of the instruction, etc.) from the decoding unit DEC is held in the pipeline register PRG1 (PRG11, PRG12). The data held in the pipeline register PRG1 (PRG11, PRG12) is transferred to the register read unit RGR (RGR1, RGR2) at the register read stage, for example.

  In the register read stage, the register read unit RGR (RGR1, RGR2) reads data from the register R designated by the instruction operand. The register read unit RGR includes a flag reset unit 50 and a determination unit 60. The flag reset unit 50 and the determination unit 60 of the register read unit RGR are the same as the flag reset unit 50 and the determination unit 60 of the embodiment described with reference to FIGS. Therefore, the register read unit RGR can keep RAW dependence when reading data from the register R.

  For example, before reading data from the register file 20, the determination unit 60 of the register read unit RGR refers to the RAW / WAW flag table 30A and checks the flag F corresponding to the register R from which data is read by an instruction. The RAW / WAW flag table 30 </ b> A outputs a signal REP indicating the state of the flag F in a range based on the signal CHK received from the determination unit 60 to the determination unit 60. Based on the signal REP, the determination unit 60 determines whether the writing of data to the register R by the instruction preceding the instruction to be determined has been completed.

  When the flag F in the range based on the signal CHK is set (when writing of data to the register R by an instruction preceding the instruction to be processed has not been completed), the register read unit RGR receives data from the register R. Wait for reading. That is, the processor 12 stalls the processing of the register read stage when the data writing to the register R by the instruction preceding the instruction to be processed has not been completed. Furthermore, the processor 12 stalls the processing of the stage upstream from the register read stage.

  When the flag F in the range based on the signal CHK is reset (when writing of data to the register R by the instruction preceding the instruction to be processed has been completed), the register read unit RGR receives data from the register R. While reading, the WAR flag table 30B is updated. For example, the flag reset unit 50 of the register read unit RGR uses the flag F of the WAR flag table 30B corresponding to the register R from which data is read by the instruction among the flags F of the entry to which the instruction is assigned, using the signal RSTC. To reset.

  Data read by the register read unit RGR (RGR1, RGR2) is held in the pipeline register PRG2 (PRG21, PRG22). The data held in the pipeline register PRG2 (PRG21, PRG22) is transferred to the arithmetic unit ALU (ALU1, ALU2) in the execution stage, for example.

  In the execution stage, the arithmetic units ALU (ALU1, ALU2) execute an operation based on the instruction decoded by the decoding unit DEC. For example, the arithmetic unit ALU performs an operation using the data read by the register read unit RGR. Output data (calculation results, etc.) from the arithmetic units ALU (ALU1, ALU2) is held in the pipeline register PRG3 (PRG31, PRG32). The data held in the pipeline register PRG3 (PRG31, PRG32) is transferred to the register write unit RGW (RGW1, RGW2) at the register write stage, for example.

  In the register write stage, the register write unit RGW (RGW1, RGW2) writes the execution result (operation result, etc.) of the instruction to the register R specified by the instruction operand. The register write unit RGW includes a flag reset unit 50 and a determination unit 60. The flag reset unit 50 and the determination unit 60 of the register write unit RGW are the same as the flag reset unit 50 and the determination unit 60 of the embodiment described with reference to FIGS. Therefore, the register write unit RGW can protect WAR dependency and WAW dependency when writing data to the register R.

  For example, before writing data to the register file 20, the determination unit 60 of the register write unit RGW refers to the RAW / WAW flag table 30A and checks the flag F corresponding to the register R into which data is written by an instruction. The RAW / WAW flag table 30 </ b> A outputs a signal REP indicating the state of the flag F in a range based on the signal CHK received from the determination unit 60 to the determination unit 60. Based on the signal REP, the determination unit 60 determines whether the writing of data to the register R by the instruction preceding the instruction to be determined has been completed.

  When the flag F in the range based on the signal CHK is set (when writing of data to the register R by the instruction preceding the instruction to be processed has not been completed), the register write unit RGW performs data transfer to the register R. Wait for writing. That is, the processor 12 stalls the processing of the register writing stage when the data writing to the register R by the instruction preceding the instruction to be processed has not been completed. Furthermore, the processor 12 stalls the processing of the stage upstream from the register write stage.

  Further, before writing data into the register file 20, the determination unit 60 of the register write unit RGW refers to the WAR flag table 30B and checks the flag F corresponding to the register R into which data is written by an instruction. The WAR flag table 30 </ b> B outputs a signal REP indicating the state of the flag F in the range based on the signal CHK received from the determination unit 60 to the determination unit 60. Based on the signal REP, the determination unit 60 determines whether reading of data from the register R by the instruction preceding the instruction to be determined has been completed.

  When the flag F in the range based on the signal CHK is set (when reading of data from the register R by an instruction preceding the instruction to be processed has not been completed), the register write unit RGW performs data transfer to the register R. Wait for writing. That is, the processor 12 stalls the processing of the register write stage when the reading of data from the register R by the instruction preceding the instruction to be processed has not been completed. Furthermore, the processor 12 stalls the processing of the stage upstream from the register write stage.

  When the flag F in the range based on the signal CHK is reset in both the RAW / WAW flag table 30A and the WAR flag table 30B, the register write unit RGW writes data into the register R and also for the RAW / WAW Update the flag table 30A. For example, the flag reset unit 50 of the register write unit RGW uses the flag F of the RAW / WAW flag table 30A corresponding to the register R to which data is written by the instruction, among the flags F of the entry to which the instruction is assigned, as a signal RSTC. Use to reset.

  In this way, the register write unit RGW finishes writing data to the register R by the instruction preceding the instruction to be processed, and ends reading data from the register R by the instruction preceding the instruction to be processed. If so, write data to register R. As a result, the processor 12 can correctly execute the program while keeping the dependency relationship between the instructions, even if a plurality of instructions for updating the same register R are allowed to exist in the processor 12 at the same time.

  The configuration and operation of the processor 12 are not limited to this example. For example, each of the flag tables 30A and 30B may include a logical sum unit ORU that is commonly used in two processing systems. In this case, each of the flag tables 30A and 30B may include an arbitration circuit that selects one of the signals CHK received from the two processing systems and transfers the selected signal to the OR unit ORU. For example, the arbitration circuit selects the signal CHK corresponding to the previously issued command from the signals CHK received from the two processing systems. Further, the arbitration circuit transfers the signal REP to, for example, the determination unit 60 that has transmitted the selected signal CHK.

  As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 6 can be obtained. For example, in this embodiment, the processor 12 includes a RAW / WAW flag table 30A and a WAR flag table 30B. Each flag table 30A, 30B has, for each register R, a flag group FG including a number of flags F that can be assigned to each of the plurality of instructions being executed. For this reason, in this embodiment, even when a plurality of instructions being executed access the same register R, WAR dependency, RAW dependency, and WAW dependency can be protected. That is, in this embodiment, even when a plurality of instructions being executed access the same register R, data dependence between instructions can be protected.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  10, 12 ... Processor; 20 ... Register file; 30, 30A, 30B ... Flag table; 40 ... Flag set part; 50 ... Flag reset part; 60 ... Judgment part; AND1, AND2 ... AND circuit; Unit: DEC: decode unit; F, F000-F157: flag; FG, FG0-FG15: flag group; MEM: instruction memory; OR1: logical OR circuit; ORU0-ORU15: logical sum unit; , PRG12, PRG21, PRG22, PRG31, PRG32 Pipeline register; R, R0-R15, register; RGR1, RGR2, Register read section; RGW1, RGW2, Register write section;

Claims (4)

A register in which data is stored;
At least one flag table having, for each register, a flag group including a number of flags that can be assigned to each of a plurality of instructions being executed;
A flag set unit for setting a flag assigned to the instruction in the flag group corresponding to the register accessed by the instruction in response to the issuance of an instruction to access the register;
A flag reset unit that resets the flag set in response to the issuance of the instruction in response to the end of access to the register by the instruction;
And a determination unit that determines whether to access the register based on a state of the flag group corresponding to the register to be accessed. The flag table is at least two,
The flag of one of the flag tables indicates whether writing to the register is complete,
The processor according to claim 1, wherein the flag of the remaining one flag table of the flag table indicates whether or not reading from the register is completed. The processor according to claim 1 or 2, wherein the setting of the flag and the resetting of the flag are executed at different stages of pipeline processing. The flag corresponding to the instruction preceding the instruction to be determined by the determination unit is selected from the flag group corresponding to the register to be accessed, and the logical sum result of the selected flag is output to the determination unit A logical sum part,
4. The determination unit according to claim 1, wherein the determination unit determines whether to access the register based on the logical sum result received from the logical sum unit. 5. Processor.

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