JP2014038986A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that floating of minority carriers, which is possible to cause interference between adjacent diffusion layers and deteriorate performance of a depletion MOS transistor.SOLUTION: A semiconductor device comprises: a semiconductor having an active region; an insulator arranged under or lateral to the semiconductor; an electrode layer which is embedded in the insulator and arranged so as not to contact the semiconductor; and a contact which pierces a part of the insulator arranged on the electrode and supplies potential to the electrode layer.

Description

  The present invention relates to a semiconductor device having a depletion type transistor.

  Conventionally, SOI (Silicon On Insulator) technology and depletion type transistors having a three-dimensional structure such as Fin (fin) in the body (silicon substrate) have been put into practical use for improving the performance of MOS transistors. There are a fully depleted transistor in which the body of each transistor is divided, and a partially depleted transistor in which the body is shared by a plurality of transistors as shown in FIG.

JP 2004-207271 A JP 2005-116623 A Japanese Patent Laid-Open No. 11-40811 JP 2002-118264 A

  The following analysis is given by the inventor.

  In a partially depleted transistor, since the body is floating, minority carriers (electrons in the NMOS) in the body diffuse within a range where they can move with a lifetime (see FIG. 10). In a partially depleted transistor, the influence of the gate electrode during operation increases due to element miniaturization, and when the distance to the adjacent transistor is reduced, minority carriers may reach the diffusion layer of the adjacent transistor and cause malfunction. There is a problem.

  In order to solve such problems, for example, in Patent Documents 1 and 2, a semiconductor region (diffusion layer) is provided on a support substrate (first semiconductor substrate), and an insulating film (diffusion layer) is formed on the semiconductor region (diffusion layer). In an SOI substrate (semiconductor device) in which a semiconductor layer (second semiconductor substrate) is provided via a first insulating film and a depletion transistor is formed on the semiconductor layer (second semiconductor substrate), a floating body and A semiconductor layer (second semiconductor substrate) is disclosed in which an electric field can be applied from a semiconductor region (diffusion layer) on the substrate side. However, in the SOI substrates (semiconductor devices) described in Patent Documents 1 and 2, when the insulating film (first insulating film) is thin, a fully depleted transistor or a partially depleted transistor cannot be realized. The film thickness of the insulating film (first insulating film) must be changed.

  In Patent Document 3, a single-crystal Si layer that is a minority carrier path is secured between the source and drain of the SOI / MOS transistor and the buried oxide film, and the recombination center is provided below the opening for connecting the source and drain. A semiconductor device in which a region is provided and minority carriers in this portion can be eliminated is disclosed. However, the semiconductor device described in Patent Document 3 does not have means for collecting minority carriers in contact with the provided recombination center region.

  Further, in Patent Document 4, a single crystal Si layer is formed on a support substrate via an insulating film 3, a gate electrode is formed on the surface of the single crystal Si layer via a gate oxide film, and a single crystal under the gate electrode 7 is formed. Diffusion layers serving as source / drain regions are formed on both sides of the crystalline Si layer, pinholes are formed below the gate electrode in the insulating film, and holes due to impact ionization generated in the single crystal Si layer are removed from the pinholes. A semiconductor device that can be pulled out to the support substrate side is disclosed. However, in the semiconductor device described in Patent Document 4, since a potential is applied to the support substrate while being a depletion type transistor (depletion type MOS transistor), the MOS performance cannot be improved.

  In one aspect of the present invention, in a semiconductor device, a semiconductor having an active region, an insulator disposed adjacently below or beside the semiconductor, and embedded in the insulator so as not to contact the semiconductor An electrode layer disposed on the electrode layer; and a contact penetrating through the portion of the insulator disposed on the electrode layer and supplying a potential to the electrode layer.

  According to the present invention, by applying a potential (a positive potential for NMOS) to the electrode layer embedded in the insulator, it attracts minority carriers in the range of the depletion layer extending into the semiconductor, and reduces the diffusion distance. By extending or recombining at the interface between the semiconductor and the insulator, a depletion transistor that can eliminate excess minority carriers can be realized. In other words, the floating of minority carriers that may interfere between adjacent diffusion layers can be eliminated without degrading the performance of the depletion type MOS transistor. Further, it is not necessary to change the film thickness of the insulator in realizing the depletion type transistor.

1A is a plan view schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2B is a cross-sectional view between XX ′ and YY ′. It is the figure which showed typically the energy band of the semiconductor device which concerns on Embodiment 1 of this invention. It is the circuit diagram which showed typically the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is the top view which showed typically the structure of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 5 is a cross-sectional view taken along the line XX ′ and the line YY ′ in FIG. 4 schematically illustrating the configuration of the semiconductor device according to the second embodiment of the present invention. It is the top view which showed typically the structure of the semiconductor device which concerns on Embodiment 3 of this invention. 6A is a cross-sectional view taken along the line XX ′ in FIG. 6 and FIG. 6B is a cross-sectional view taken along the line Y-Y ′ schematically illustrating the configuration of the semiconductor device according to the third embodiment of the present invention. It is the (A) top view which showed typically the structure of the semiconductor device which concerns on Embodiment 4 of this invention, (B) It is sectional drawing between XX 'and between YY'. It is sectional drawing which showed typically the structure of the semiconductor device which concerns on a prior art example. It is the figure which showed typically the energy band of the semiconductor device which concerns on a prior art example.

(Embodiment 1)
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1A is a plan view schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 1B is a cross-sectional view between XX ′ and YY ′. FIG. 2 is a diagram schematically showing an energy band of the semiconductor device according to the first embodiment of the present invention.

  Referring to FIG. 1, in a semiconductor device 1A, a semiconductor layer 5 (for example, a single crystal silicon body) serving as an active region is formed on a support substrate 2 (for example, silicon) through an insulating layer 3 (for example, silicon oxide film). This is a semiconductor device using the formed SOI substrate. The semiconductor device 1A includes a partially depleted transistor that shares a semiconductor layer 5 with a plurality of MOS transistors (semiconductor elements). The semiconductor layer 5 is partitioned by an element isolation region 6 (for example, a silicon oxide film) that electrically isolates elements. The element isolation region 6 is formed between the insulating layer 3 and the interlayer insulating film 10. On the semiconductor layer 5, a gate electrode 8 (for example, polysilicon) is disposed in a predetermined region via a gate insulating film 7 (for example, a silicon oxide film). Two gate electrodes 8 are arranged on one semiconductor layer 5 surrounded by the element isolation region 6 and are separated from each other. A diffusion region 9 in which impurities (for example, boron and phosphorus) are diffused is provided on both sides of a channel (portion of the semiconductor layer 5) under the gate insulating film 7. The diffusion region 9 arranged in the region between the gate electrodes 8 becomes a common diffusion region for adjacent MOS transistors. An interlayer insulating film 10 is formed on the element isolation region 6 including the MOS transistor. In the interlayer insulating film 10, a contact 11 is formed in a pilot hole that communicates with the gate electrode 8, and a contact 12 is formed in a pilot hole that communicates with the diffusion region 9. The contact 11 is electrically connected to, for example, a word line (not shown). The contact 12 is electrically connected to a bit line (not shown), a capacitor (not shown), etc., for example.

  The insulating layer 3 has a configuration in which an electrode layer 4 (for example, copper) is embedded between a lower insulating layer 3a (for example, a silicon oxide film) and an upper insulating layer 3b (for example, a silicon oxide film). The lower insulating layer 3 a is disposed between the support substrate 2 and the electrode layer 4. The upper insulating layer 3 b is disposed between the electrode layer 4 and the semiconductor layer 5. The electrode layer 4 is connected to a contact 13 formed in a pilot hole penetrating the interlayer insulating film 10, the element isolation region 6, and the upper insulating layer 3b. The contact 13 is electrically connected to a controller (not shown) through wiring (not shown).

  A positive potential is applied to the electrode layer 4 if the MOS transistor is NMOS. As long as the influence of this potential does not affect the NMOS channel, minority carriers that cause noise in the semiconductor layer 5 can be excluded from the channel (attracted to the electrode layer 4 side) (see FIG. 2). The impurity profile (impurity concentration distribution) is adjusted.

  In the semiconductor device manufacturing method according to the first embodiment, when the insulating layer 3 is formed on the support substrate 2, the lower insulating layer 3a, the electrode layer 4, and the upper insulating layer 3b are formed in this order, and A conventional manufacturing method can be used except for the step of forming a pilot hole communicating with the electrode layer 4 in the interlayer insulating film 10, the element isolation region 6 and the upper insulating layer 3b and forming the contact 13 in the pilot hole. Further, the electrode layer 4 may be formed not only on the entire surface of the substrate but also in a part of the region.

  According to the first embodiment, the electrode layer 4 is embedded in the insulating layer 3 in the SOI substrate in which the semiconductor layer 5 is formed on the support substrate 2 via the insulating layer 3, and the electrode layer 4 has a potential (positive in the case of NMOS). By applying (potential), it is possible to realize a depletion type transistor that affects other than the channel of the semiconductor layer 5 and can eliminate excess minority carriers. Further, it is not necessary to change the film thickness of the insulating layer 3 to realize a depletion type transistor. Further, it is possible to eliminate the floating of minority carriers that may interfere between the adjacent diffusion regions 9 without degrading the performance of the depletion type transistor. In other words, minority carriers within the range of the depletion layer extending into the semiconductor layer 5 are attracted to the electrode layer 4 side, and the diffusion distance is extended or recombination at the interface with the insulating film so as not to affect the adjacent transistor. can do.

(Embodiment 2)
A semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 4 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line XX ′ and the line YY ′ in FIG. 4 schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention.

  A semiconductor device 1B according to the second embodiment is obtained by applying the semiconductor device according to the first embodiment (1A in FIG. 1) to an adjacent 2-bit memory cell array of a DRAM (Dynamic Random Access Memory). The configuration of region A in the circuit diagram of FIG. 3 corresponds to the configuration of region A in the plan view of FIG. The cross-sectional configuration in FIG. 5 corresponding to the section between XX ′ and YY ′ in FIG. 4 is the same as that in the first embodiment. Note that the common diffusion region 9 of adjacent transistors Tr in the memory cell is electrically connected to the bit line BL via the contact 12, and the non-common diffusion region 9 is common source line CS via the contact 12 and the capacitor C. The gate electrode 8 is a part of the word line WL, and the electrode layer 4 is connected to a controller (not shown) via a contact.

  Note that the manufacturing method of the semiconductor device according to the second embodiment is the same as that of the first embodiment.

  According to the second embodiment, the same effect as that of the first embodiment is obtained, and a potential is positively applied to the electrode layer 4 between the two affecting transistors Tr so that minority carriers are recombined and disappeared at the interface. Thus, malfunction due to interference between the two transistors Tr can be prevented.

  A minority carrier becomes a problem in recent devices when a floating body is shared by partial depletion between adjacent devices close to the diffusion distance (adjacent two bits of DRAM). In addition, a dynamic acceleration event due to a potential change of a word line or the like is usually accompanied. However, as in Patent Document 3, no countermeasure is taken in a recombination center region that is a carrier capture region that is statically waiting.

(Embodiment 3)
A semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a plan view schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention. 7A and 7B schematically show the configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 7A is a cross-sectional view taken along the line XX ′ in FIG. 6 and FIG. 7B is a cross-sectional view taken along the line Y-Y ′. .

  The semiconductor device 1C according to the third embodiment is a modification of the first embodiment, and is applied to an inverter using a CMOS (Complementary Metal Oxide Semiconductor). In the CMOS configuration, in order to be able to apply different potentials to the electrode layer 4a in the PMOS region and the electrode layer 4b in the NMOS region, an electrode isolation region 21 for electrically separating the electrode layers 4a and 4b is provided. Yes.

  6 and 7, in the semiconductor device 1C, an N well 5a and a P well 5b serving as an active region are formed on a support substrate 2 (eg, silicon) via an insulating layer 3 (eg, silicon oxide film). This is a semiconductor device using the manufactured SOI substrate. The semiconductor device 1C has a fully depleted transistor in which the body of each transistor is separated. The N well 5a and the P well 5b are partitioned by an element isolation region 6 (for example, a silicon oxide film) that electrically isolates elements. The element isolation region 6 is formed between the insulating layer 3 and the interlayer insulating film 10. On the N well 5a serving as a PMOS region, a gate electrode 8a (for example, polysilicon) is disposed in a predetermined region via a gate insulating film 7 (for example, a silicon oxide film). On the P well 5b serving as the NMOS region, a gate electrode 8b (for example, polysilicon) is arranged in a predetermined region via a gate insulating film 7 (for example, a silicon oxide film). One gate electrode 8 a is arranged on one N well 5 a surrounded by the element isolation region 6. One gate electrode 8 b is arranged on one P well 5 b surrounded by the element isolation region 6. Diffusion regions 9a and 9b in which impurities (for example, phosphorus) are diffused are provided on both sides of a channel (portion of the N well 5a) under the gate insulating film 7 in the PMOS region. Diffusion regions 9c and 9d in which impurities (for example, boron) are diffused are provided on both sides of a channel (part of the P well 5b) under the gate insulating film 7 in the NMOS region.

  An interlayer insulating film 10 is formed on the element isolation region 6 including the PMOS transistor and the NMOS transistor. In the interlayer insulating film 10, a contact 11a is formed in a pilot hole that communicates with the gate electrode 8a and a contact 12a is formed in a pilot hole that communicates with the diffusion region 9a. A contact 12b is formed. In the interlayer insulating film 10, a contact 11b is formed in a pilot hole that communicates with the gate electrode 8b, and a contact 12c is formed in a pilot hole that communicates with the diffusion region 9c. A contact 12d is formed. On the interlayer insulating film 10, a wiring 17 that is electrically connected to the contact 11a and the contact 11b, a wiring 18 that is electrically connected to the contact 12b and the contact 12d, and a contact 12a are electrically connected. A wiring 19 and a wiring 20 electrically connected to the contact 12c are arranged.

  In the insulating layer 3, an electrode layer 4a (for example, copper) is embedded in the PMOS region between the lower insulating layer 3a (for example, silicon oxide film) and the upper insulating layer 3b (for example, silicon oxide film), and the NMOS region The electrode layer 4b (for example, copper) is embedded in the structure. The lower insulating layer 3a is disposed between the support substrate 2 and the electrode layers 4a and 4b. The upper insulating layer 3 b is disposed between the electrode layers 4 a and 4 b and the semiconductor layer 5. The electrode layer 4a and the electrode layer 4b are electrically separated by an electrode separation region 21 (for example, a silicon oxide film). The electrode isolation region 21 is a region between the N well 5a and the P well 5b, and is a groove that passes through the element isolation region 6, the upper insulating layer 3b, the electrode layers 4a and 4b, and the lower insulating layer 3a and communicates with the support substrate 2. Is formed. The electrode layer 4a is connected to a contact 13a formed in a pilot hole penetrating the interlayer insulating film 10, the element isolation region 6, and the upper insulating layer 3b. The contact 13a is electrically connected to a controller (not shown) via the wiring 19. The wiring 19 is electrically connected to the contacts 12a and 14 in addition to the contact 13a. The contact 14 is formed in a pilot hole that passes through the interlayer insulating film 10 and the electrode isolation region 21 and communicates with the support substrate 2, and is electrically connected to the support substrate 2. The electrode layer 4b is connected to a contact 13b formed in a pilot hole penetrating the interlayer insulating film 10, the element isolation region 6, and the upper insulating layer 3b. The contact 13b is electrically connected to a controller (not shown) via the wiring 20. The wiring 20 is electrically connected to the contact 12c in addition to the contact 13b.

  A negative potential is applied to the electrode layer 4b in the PMOS region, and a positive potential is applied to the electrode layer 4b in the NMOS region. Minority carriers (holes in the case of PMOS, electrons in the case of NMOS) that are noises in the N well 5a and the P well 5b can be excluded from the channel within the range in which the influence of this potential does not affect the channel of the MOS transistor (electrode) The impurity profile (impurity concentration distribution) in the N well 5a and the P well 5b is adjusted so as to be attracted to the layer 4 side.

  In the semiconductor device manufacturing method according to the third embodiment, when the insulating layer 3 is formed on the support substrate 2, the lower insulating layer 3a, the electrode layers 4a and 4b, and the upper insulating layer 3b are formed in this order. A step of forming a pilot hole communicating with the electrode layers 4a and 4b in the interlayer insulating film 10, the element isolation region 6 and the upper insulating layer 3b and forming contacts 13a and 13b in the pilot hole, the element isolation region 6 and the upper insulating layer 3b Forming a groove communicating with the support substrate 2 in the electrode layers 4a and 4b and the lower insulating layer 3a and forming the electrode isolation region 21 in the groove; communicating with the support substrate 2 in the interlayer insulating film 10 and the electrode isolation region 21 Except for the step of forming a pilot hole and forming the contact 14 in the pilot hole, a conventional manufacturing method can be used.

  According to the third embodiment, as in the first embodiment, the electrode separation region 21 is separated in the insulating layer 3 in the SOI substrate in which the N well 5a and the P well 5b are formed on the support substrate 2 via the insulating layer 3. By embedding the formed electrode layers 4a and 4b, different potentials can be applied to the electrode layers 4a and 4b, and by applying a potential (positive potential on the NMOS side and negative potential on the PMOS side) to the electrode layers 4a and 4b. Thus, it is possible to realize a depletion type transistor that affects other than the channels of the N well 5a and the P well 5b and can eliminate excess minority carriers. Further, it is not necessary to change the film thickness of the insulating layer 3 to realize a depletion type transistor. Furthermore, by applying different potentials to the electrode layers 4a and 4b, leakage current to the support substrate 2 can be suppressed, and standby current can be suppressed.

  In the CMOS configuration, it is necessary to apply different potentials to the floating body of NMOS (negative channel metal oxide semiconductor) and PMOS (positive channel metal oxide semiconductor). In the semiconductor device, there is a leakage current from the semiconductor region (diffusion layer) to the support substrate (first semiconductor substrate), and the standby current cannot be suppressed.

(Embodiment 4)
A semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 8A is a plan view schematically showing a configuration of a semiconductor device according to Embodiment 4 of the present invention, and FIG. 8B is a cross-sectional view between XX ′ and YY ′.

  A semiconductor device 1D according to the fourth embodiment is a modification of the first embodiment, and is applied to a semiconductor device having a fin portion 2a on a support substrate 2 and a fully depleted transistor.

  The support substrate 2 (for example, silicon) has a fin portion 2a serving as an active region protruding upward. The fin portion 2a is partitioned by an element isolation region 15 (for example, a silicon oxide film) that electrically isolates elements. The element isolation region 15 is formed between the support substrate 2 (portion excluding the fin portion 2 a) and the interlayer insulating film 10. On the fin portion 2a, a gate electrode 8 (for example, polysilicon) is disposed in a predetermined region via a gate insulating film 7 (for example, a silicon oxide film). One gate electrode 8 is arranged on one semiconductor layer 5 surrounded by the element isolation region 15. A diffusion region 9 in which impurities (for example, boron and phosphorus) are diffused is provided on both sides of a channel (portion of the semiconductor layer 5) under the gate insulating film 7. An interlayer insulating film 10 is formed on the element isolation region 15 including the MOS transistor. In the interlayer insulating film 10, a contact 11 is formed in a pilot hole that communicates with the gate electrode 8, and a contact 12 is formed in a pilot hole that communicates with the diffusion region 9. The contact 11 is electrically connected to, for example, a word line (not shown). The contact 12 is electrically connected to a bit line (not shown), a capacitor (not shown), etc., for example.

  An electrode layer 16 (for example, copper) is embedded in the element isolation region 15. The electrode layer 16 is embedded between the lower insulating layer 15a (for example, silicon oxide film) and the upper insulating layer 15b (for example, silicon oxide film). The end portion of the electrode layer 16 (the end portion facing the fin portion 2a) is not in contact with the fin portion 2a and is covered with an insulator (either the upper insulating layer 15b or the lower insulating layer 15a is acceptable). The lower insulating layer 15 a is disposed between the support substrate 2 and the electrode layer 16. The upper insulating layer 15 b is disposed between the electrode layer 16 and the interlayer insulating film 10. The electrode layer 16 is connected to a contact 13 formed in a pilot hole penetrating the interlayer insulating film 10 and the upper insulating layer 15b. The contact 13 is electrically connected to a controller (not shown) through wiring (not shown).

  A positive potential is applied to the electrode layer 16 if the MOS transistor is NMOS. As a result, the impurity profile (impurity concentration distribution) in the fin portion 2a beside the element isolation region 15 can be optimized, and the depletion layer can be set to extend within a range that does not affect the channel.

  For the method of manufacturing the semiconductor device according to the fourth embodiment, when forming the insulating layer 3 on the support substrate 2, except for the step of forming the lower insulating layer 15a, the electrode layer 16, and the upper insulating layer 15b in this order, Conventional manufacturing methods can be used.

  According to the fourth embodiment, as in the first embodiment, the electrode layer 16 is embedded in the element isolation region 15, and a potential (positive potential in the case of NMOS) is applied to the electrode layer 16, so that the channel of the fin portion 2 a In addition, it is possible to realize a depletion type transistor that affects other than that and can eliminate excess minority carriers. Further, it is not necessary to change the film thickness of the element isolation region 15 in realizing a depletion type transistor.

  Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments.

  Note that, within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. . That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

1A, 1B, 1C, 1D, 101 Semiconductor device 2, 102 Support substrate 2a Fin portion (semiconductor)
3, 103 Insulating layer (insulator)
3a Lower insulation layer (insulator)
3b Upper insulating layer (insulator)
4 Electrode layer 4a Electrode layer (first electrode layer)
4b Electrode layer (second electrode layer)
5, 105 Semiconductor layer (semiconductor)
5a N well (semiconductor)
5b P-well (semiconductor)
6, 106 Element isolation region 7, 107 Gate insulating film 8, 8a, 8b, 108 Gate electrode 9, 9a, 9b, 9c, 9d, 109 Diffusion region 10, 110 Interlayer insulating film 11, 11a, 11b, Contact 12, 12a , 12b, 12c, 12d, 112 contact 13, 14 contact 13a contact (first contact)
13b Contact (second contact)
15 Element isolation region (insulator)
15a Lower insulating layer 15b Upper insulating layer 16 Electrode layer 17, 18, 19, 20 Wiring 21 Electrode separation region BL Bit line WL Word line Tr Transistor C Capacitor CS Common source

Claims (6)

A semiconductor having an active region;
An insulator disposed adjacently under or beside the semiconductor;
An electrode layer embedded in the insulator and arranged not to contact the semiconductor;
A contact for passing through the portion of the insulator disposed on the electrode layer and supplying a potential to the electrode layer;
A semiconductor device comprising: The insulator is disposed adjacent to and under the semiconductor;
A support substrate made of a semiconductor under the insulator;
An element isolation region for partitioning the semiconductor on the insulator;
The contact penetrates the element isolation region and a part of the insulator,
The semiconductor device according to claim 1, wherein the upper surface of the electrode layer has a portion facing the bottom surface of the semiconductor.   The semiconductor device according to claim 2, wherein the insulator is also disposed between the electrode layer and the support substrate.   The semiconductor device according to claim 1, wherein a plurality of semiconductor elements are formed in the active region. Of the adjacent semiconductor elements, one is a PMOS transistor, the other is an NMOS transistor,
Having the element isolation region in a region between the NMOS transistor and the PMOS transistor;
In the region between the PMOS transistor and the NMOS transistor, the device isolation region, the insulator, and the groove penetrating the electrode layer are embedded, and the electrode layer is connected to the first electrode layer under the PMOS transistor and the An electrode isolation region that separates the second electrode layer under the NMOS transistor;
5. The contact according to claim 4, wherein the contact includes a first contact for supplying a potential to the first electrode layer and a second contact for supplying a potential to the second electrode layer. Semiconductor device. The insulator is disposed adjacent to the side of the semiconductor;
A support substrate integrated with the semiconductor under the semiconductor and the insulator;
The semiconductor device according to claim 1, wherein an end portion of the electrode layer has a portion facing a side surface of the semiconductor.

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