JP2014038908A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of a high-speed operation achieved by reduction of a signal delay time difference.SOLUTION: A semiconductor device comprises: a wiring board on which solder balls as data input/output terminals corresponding to a high order byte and a low order byte; and a first chip and a second chip on each of which a plurality of DQ pads as data input/output terminals are formed on one surface. The first chip and the second chip respectively include DQ pads for the high order byte and DQ pads for the low order byte. For example, in the first chip, the DQ pads for the low order byte are arranged so as to make a distance with the solder balls for the low order byte be closer, and in the second chip, the DQ pads for the high order byte are arranged so as to make a distance with the solder balls for the high order byte be closer.

Description

  The present invention relates to a DDP (Dual Die Package) type semiconductor device.

  In recent years, in portable electronic devices such as mobile phones, demands for miniaturization and higher functionality have increased, and in order to increase the density of semiconductor devices mounted on circuit boards, semiconductors mounted with a plurality of semiconductor chips Equipment has been developed. As an example, there is a DDP type semiconductor device in which two semiconductor chips are stacked on a package substrate (wiring substrate).

  For example, a DRAM (Dynamic Random Access Memory) has a configuration in which a DDP type × 16 DRAM is realized by stacking two × 8 chips on a wiring board. “× 8” and “× 16” indicate the number of bits of data input / output in one DRAM. For DRAMs, products such as “× 8”, “× 16”, and “× 32” are provided by various manufacturers corresponding to various electronic devices. A semiconductor (DRAM) chip that can handle any of “× 8”, “× 16”, and “× 32” is described in Patent Document 1, for example.

  In the above-described DDP type semiconductor device, for example, a x16 DRAM, 16-bit data is obtained by stacking the lower semiconductor chip (semiconductor chip on the wiring board side) and the upper semiconductor chip (semiconductor chip far from the wiring board). One byte (8 bits) is divided and stored. For example, the lower byte is stored in the lower semiconductor chip (hereinafter referred to as the first chip), and the upper byte is stored in the upper semiconductor chip (hereinafter referred to as the second chip).

  Solder balls serving as data input / output (DQ) terminals corresponding to the lower byte and the upper byte are respectively provided on the wiring board. On the other hand, when two semiconductor chips (the first chip and the second chip) mounted on the wiring board have the same common configuration, the data input / output (DQ) terminals of the first chip and the second chip The positions of the pads (hereinafter referred to as DQ pads) are the same. In this case, depending on the positional relationship between the DQ pads of the first chip and the second chip and the solder balls for the lower byte and the upper byte, from the DQ pad of the first chip to the solder ball for the lower byte The wiring length may be greatly different from the wiring length from the DQ pad of the second chip to the solder ball for the upper byte.

For example, FIGS. 5A and 5B show a plurality of pads arranged in a row (one row) near the center of one surface of the first chip 52 and the second chip 53, and one end of the pad row. A configuration example in which eight DQ pads 55 ₁ (55 ₂ ) are arranged on the side is shown. The first chip 52 and the second chip 53 shown in FIGS. 5A and 5B are, for example, x8 DRAM chips.

In the semiconductor device shown in FIGS. 5A and 5B, an opening 54 is provided at the center of the wiring substrate 51. As shown in FIG. 5A, the first chip 52 has a pad forming surface. mounted in a face-down to face the wiring board 51, a DQ pad 55 _1, the bond fingers 56 ₁ provided in a row along the opening 54 the edge of the circuit board 51, passes through the opening 54 They are connected by bonding wires 57. 5B, the second chip 53 is mounted face-up on the first chip 52 so that the pad formation surface faces in the opposite direction with respect to the wiring substrate 51. and DQ pads 55 _2, and the bond fingers 56 ₂ provided in a row along the wiring substrate 51 ends, are connected by a bonding wire 57 ₂ formed so as to straddle the second chip 53 (JP 2).

In the configuration shown in FIGS. 5A and 5B, the lower byte solder balls (hereinafter referred to as “DQ pad 55 _1” and the DQ pad 55 ₂ of the second chip 53) are arranged. A lower bite ball (referred to as a lower bite ball) 58 is arranged nearby, and a solder ball for an upper bite (hereinafter referred to as an upper bite ball) 59 is arranged apart. Therefore, as shown by the dotted arrows in FIGS. 5A and 5B, the bonding wire 57 ₂ connecting the DQ pad 55 ₂ for the upper byte and the bond finger 56 ₂ , and the upper bit ball 59 and the bond finger 56 wiring in the wiring board 51 for connecting the _2, DQ pad 55 ₁ and the bond fingers 56 bonding wire 57 ₁ connected _1, and lower byte balls 58 and the wiring board 51 for connecting the bonding fingers 56 ₁ for lower byte It becomes longer than the inner wiring. Specifically, the wiring length from the DQ pads 55 ₂ to the upper byte balls 59 of the second chip 53, the wiring length from the DQ pads 55 ₁ of the first chip 52 to the lower byte ball 58 , About 3 times.

6A and 6B, two rows of pads are arranged near the center of one surface of the first chip 62 and the second chip 63, and a DQ pad 65 ₁ (65 ₂ ) shows an example of the arrangement. The first chip 62 and the second chip 63 shown in FIGS. 6A and 6B are, for example, x8 DRAM chips.

In the semiconductor device shown in FIGS. 6A and 6B, both the first chip 62 and the second chip 63 are mounted face-up so that the pad forming surface faces the opposite direction with respect to the wiring substrate 61. The As shown in FIG. 6 (a), the DQ pad 65 ₁ of the first chip 62 and the bonding finger 66 ₁ provided in a row along the wiring board 61 end, cross the first chip 62 It is connected by a bonding wire 67 ₁ formed as. Further, as shown in FIG. 6B, the DQ pad 65 ₂ of the second chip 63 and the bond fingers 66 ₂ provided in a row along the end of the wiring board 61 connect the second chip 63 to each other. _They are connected by bonding wires 672 formed so as to straddle (refer to Patent Document 3 as related technology).

FIG 6 (a), in the configuration shown in (b), provided close to the lower byte ball 68 relative to the position of the DQ pad 65 ₂ DQ pads 65 ₁ and the second chip 63 of the first chip 62 The upper bite ball 69 is provided separately. Therefore, as shown by the dotted arrows in FIGS. 6A and 6B, the wiring in the wiring board connecting the upper bite ball 69 and the bond finger 66 ₁ is connected to the lower bite ball 68 and the bond finger 66 ₂ . It becomes longer than the wiring in the wiring board 61 to be connected.

JP 2010-287733 A JP 2011-249582 A JP 2006-40983 A

  As described above, in the semiconductor device shown in FIGS. 5A and 5B, the wiring length from the DQ pad of the second chip to the upper byte ball is lower than the DQ pad of the first chip. The wiring length up to the ball is about three times as long.

  For this reason, the signal delay time difference between the data strobe signal DQS and the data DQ with respect to the clock CK becomes large between the lower byte and the upper byte, which becomes a factor that hinders the high-speed operation of the semiconductor device.

  In the semiconductor device shown in FIGS. 6A and 6B, the wiring in the wiring board that connects the upper bite ball and the bond finger is also the wiring in the wiring board that connects the lower biting ball and the bond finger. Therefore, the difference in the signal delay time between the data strobe signal DQS and the data DQ with respect to the clock CK becomes large between the lower byte and the upper byte, which is a factor that hinders the high-speed operation of the semiconductor device.

The semiconductor device of the present invention includes a wiring board provided with solder balls as data input / output terminals corresponding to the upper byte and the lower byte,
A plurality of DQ pads that are data input / output terminals are formed on one surface, and a first chip and a second chip that are semiconductor chips stacked on the wiring board;
Have
The first chip and the second chip have a DQ pad for the upper byte and a DQ pad for the lower byte, respectively.
Corresponding to the positional relationship between the solder ball for the lower byte and the solder ball for the upper byte provided on the wiring board, the first chip includes the first byte and the lower byte. The DQ pad for the one bite is arranged so that the distance from the solder ball for one bite used in the chip is close,
The DQ pad for the other bit is arranged on the second chip so as to be close to the solder ball for the other bit used in the second chip.

  In the semiconductor device having the above configuration, for example, the wiring length from the DQ pad of the first chip to the solder ball for the lower byte and the upper byte from the DQ pad of the second chip are compared with the semiconductor device of the background art. The wiring length to the solder ball can be made closer.

In addition, another semiconductor device of the present invention includes a wiring board provided with solder balls as data input / output terminals corresponding to the upper byte and the lower byte,
A plurality of DQ pads that are data input / output terminals are formed on one surface, and a first chip and a second chip that are semiconductor chips stacked on the wiring board;
Have
The first chip and the second chip are:
A rewiring layer that connects the DQ pad and a chip pad provided at a chip end, each having a wiring length different between the first chip and the second chip, is provided.

  In the semiconductor device configured as described above, the lengths of the wirings in the rewiring layer provided on the first chip and the second chip are made different. That is, by adjusting the length of the wiring in the rewiring layer provided on the first chip and the second chip, for example, the wiring length from the DQ pad of the first chip to the solder ball for the lower byte, The wiring length from the DQ pad of the second chip to the solder ball for the upper byte can be made equal.

  According to the present invention, the difference in signal delay time between the upper byte and the lower byte is reduced, and the semiconductor device can be operated at higher speed.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the example of 1 structure of the semiconductor device of 1st Embodiment, The figure (a) is a top view which shows the example of a connection of a 1st chip and a wiring board, The figure (b) is a 2nd chip. It is a top view which shows the example of a connection of a wiring board. It is a figure which shows the other structural example of the semiconductor device of 1st Embodiment, The figure (a) is a top view which shows the example of a connection of a 1st chip | tip and a wiring board, The figure (b) is a 2nd figure. It is a top view which shows the example of a connection of a chip | tip and a wiring board. It is a figure which shows the example of 1 structure of the semiconductor device of 2nd Embodiment, The figure (a) is a top view which shows the example of a connection of a 1st chip | tip and a wiring board, The figure (b) is a 2nd chip | tip. It is a top view which shows the example of a connection of a wiring board. It is a figure which shows the other structural example of the semiconductor device of 2nd Embodiment, The figure (a) is a top view which shows the example of a connection of a 1st chip | tip and a wiring board, The figure (b) is a 2nd figure. It is a top view which shows the example of a connection of a chip | tip and a wiring board. It is a figure which shows one structural example of the semiconductor device of background art, The figure (a) is a top view which shows the example of a connection of a 1st chip | tip and a wiring board, The figure (b) is a 2nd chip | tip and a wiring board. It is a top view which shows the example of a connection. It is a figure which shows the other structural example of the semiconductor device of background art, The figure (a) is a top view which shows the example of a connection of a 1st chip | tip and a wiring board, The figure (b) is a 2nd chip | tip and a wiring board. It is a top view which shows the example of a connection.

Next, the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of the semiconductor device according to the first embodiment. FIG. 1A is a plan view illustrating a connection example of a first chip and a wiring board, and FIG. It is a top view which shows the example of a connection of a 2nd chip | tip and a wiring board. The semiconductor device shown in FIGS. 1A and 1B has a configuration having a wiring board 11 and a first chip 12 and a second chip 13 mounted on the wiring board 11. 1A and 1B, a plurality of pads are arranged in a row (one row) near the center of one surface of the first chip 12 and the second chip 13, and one end side of the pad row. ₁ shows a configuration example in which DQ pads 15 ₁ (15 ₂ ) are arranged.

The first chip 12 and the second chip 13 included in the semiconductor device shown in FIGS. 1A and 1B are DRAM chips that can handle, for example, “× 16” and “× 8”, respectively. In the form, they are used as “× 8”. That is, the first chip 12 and the second chip 13 mounted on the wiring board 11 are each provided with at least a lower byte DQ pad 15 ₁ and an upper byte DQ pad 15 ₂ .

As shown in FIG. 1 (a) and (b), the second chip 13, for example using eight pads of pad row end side as DQ pads 15 _2, the first chip 12, the second chip The eight pads adjacent to the DQ pad 15 ₂ used at 13 on the center side of the pad row are used as the DQ pad 15 ₁ . DQ pads 15 ₂ used in DQ pads 15 ₁ and a second chip 13 used in the first chip 12, corresponds to the positional relationship between the lower byte balls 18 provided on the wiring substrate 11 and the upper byte balls 19 to, for example, the distance is close between the DQ pad 15 ₁ and the lower byte balls 18 used in the first chip 12, the distance between the DQ pad 15 ₂ and the upper byte balls 19 used in the second chip 13 What is necessary is just to arrange | position so that it may become close. The lower bite ball 18 and the upper bite ball 19 are respectively provided with a DQ ball corresponding to the DQ pads 15 ₁ and 15 ₂ , a DQS ball supplied with a DQ strobe signal, and an inverted signal of the DQ strobe signal. DQSB balls, DQs supplied to the input circuit corresponding to DQS, DQSB, VDDQ balls for supplying VDD voltage to the input circuits, VSSQ balls for supplying VSS voltage to the input circuits, DQ at the input circuit It is assumed that a Vref ball for supplying a Vref voltage serving as a reference voltage at the time of capture, a DM ball for supplying a data mask signal, and the like are included. FIGS. 1A and 1B show an example in which the first chip 12 is used in the lower byte and the second chip 13 is used in the upper byte. However, the first chip 12 is used in the upper byte. And the second chip 13 may be used in the lower byte.

In the semiconductor device shown in FIGS. 1A and 1B, an opening 14 is provided in the central portion of the wiring substrate 11, and the pad formation surface of the first chip 12 has a pad forming surface as shown in FIG. Bonding wires that are mounted so as to face the wiring board 11, and each DQ pad 15 ₁ and each bond finger 16 ₁ provided in a row along the opening 14 end of the wiring board 11 pass through the opening 14. 17 ₁ are connected to each other. Further, as shown in FIG. 1 (b), the second chip 13, the pad forming surface is mounted so as to face the opposite direction to the wiring substrate 11, and the DQ pads 15 _2, the wiring substrate 11 edge each bond fingers 16 ₂ provided in a row along the are connected by bonding wires 17 ₂ formed so as to straddle the second chip 13.

In such a configuration, FIG. 1 (a), a dotted line as indicated by an arrow, the wiring length in the wiring board 11 for connecting the lower byte ball 18 and the bond fingers 16 _1, the upper byte balls 19 (b) And the wiring length in the wiring substrate 11 to which the bond fingers 16 ₂ are connected are substantially equal. Therefore, FIG. 5 (a), compared with the semiconductor device of the background art shown (b), the wiring length from the DQ pads 15 ₁ of the first chip 12 to the lower byte ball 18, the second chip 13 The wiring length from the DQ pad 15 ₂ to the upper bite ball 19 can be made closer.

  Therefore, the signal delay time difference between the data strobe signal DQS and the data DQ with respect to the clock CK is reduced between the lower byte and the upper byte, and the semiconductor device can be operated at higher speed.

FIG. 2 is a diagram illustrating another configuration example of the semiconductor device according to the first embodiment. FIG. 2A is a plan view illustrating a connection example between the first chip and the wiring board, and FIG. These are top views which show the example of a connection of a 2nd chip | tip and a wiring board. The semiconductor device shown in FIGS. 2A and 2B includes a wiring board 21, and a first chip 22 and a second chip 23 that are stacked on the wiring board 21. 2A and 2B, two rows of pads are arranged near the center of one surface of the first chip 22 and the second chip 23, and a DQ pad 25 ₁ (on the one end side of the pad row). 25 ₂ ) shows an example of the arrangement.

The first chip 22 and the second chip 23 included in the semiconductor device shown in FIGS. 2A and 2B are also DRAM chips that can handle, for example, “× 16” and “× 8”, respectively. In the form, they are used as “× 8”. That is, the first chip 22 and the second chip 23 mounted on the wiring board 21 are each provided with at least a lower byte DQ pad 25 ₁ and an upper byte DQ pad 25 ₂ .

As shown in FIGS. 2A and 2B, the second chip 23 uses, for example, eight pads on one end side of the pad row as the DQ pad 25 ₁ , and the first chip 22 is the second chip. The eight pads adjacent to the DQ pad 25 ₁ used at 23 on the center side of the pad row are used as the DQ pad 25 ₂ . The DQ pad 25 ₁ used in the first chip 22 and the DQ pad 25 ₂ used in the second chip 23 correspond to the positional relationship between the lower byte 28 and the upper byte 29 provided on the wiring board 21. For example, the distance between the DQ pad 25 ₁ used in the first chip 22 and the lower bite ball 28 is short, and the distance between the DQ pad 25 ₂ used in the second chip 23 and the upper bite ball 29 is short. What is necessary is just to arrange | position so that it may become close. 2A and 2B show an example in which the first chip 22 is used in the lower byte and the second chip 23 is used in the upper byte. However, the first chip 22 is used in the upper byte. And the second chip 23 may be used in the lower byte.

In the semiconductor device shown in FIGS. 2A and 2B, both the first chip 22 and the second chip 23 are mounted such that the pad formation surface faces in the opposite direction with respect to the wiring board. As shown in FIG. 2A, the DQ pad 25 ₁ of the first chip 22 and the bond fingers 26 ₁ provided in a row along the end of the wiring substrate 21 straddle the first chip 22. They are connected by bonding wires 27 ₁ formed as described above. Further, as shown in FIG. 2B, the DQ pad 25 ₂ of the second chip 23 and the bond fingers 26 ₂ provided in a row along the end of the wiring substrate 21 connect the second chip 23 to each other. _They are connected by bonding wires 272 formed so as to straddle.

In such a configuration, FIG. 2 (a), the dotted line as shown by an arrow, and the wiring length of the wiring board 21 to connect the lower byte ball 28 and the bond fingers 26 _1, the upper byte ball 29 (b) And the wiring length in the wiring substrate 21 to which the bond finger 26 ₂ is connected are substantially equal, the length of the bonding wire 27 ₁ that connects the DQ pad 25 ₁ of the first chip 22 and the bond finger 26 ₁ , and the second The length of the bonding wire 27 ₂ connecting the DQ pad 25 ₂ of the chip 23 and the bond finger 26 ₂ is substantially equal. Therefore, FIG. 5 (a), (b) and 6 (a), as compared with the semiconductor device of the background art shown (b), the from the DQ pads 25 ₁ to lower byte ball 28 of the first chip 22 And the wiring length from the DQ pad 25 ₂ of the second chip 23 to the upper bite ball 29 can be made closer to each other.

  Therefore, the signal delay time difference between the data strobe signal DQS and the data DQ with respect to the clock CK is reduced between the lower byte and the upper byte, and the semiconductor device can be operated at higher speed.

  When DRAM chips that can handle “× 16” and “× 8” are used as the first chip 12 (22) and the second chip 13 (23), the first chip 12 (22) and A circuit connected to an unnecessary DQ pad included in the second chip 13 (23) is preferably set so as not to operate. In that case, excessive power consumption of the semiconductor device is suppressed. An example of the circuit connected to the DQ pad is an input / output buffer circuit.

In addition, when DRAM chips that can respectively correspond to “× 16” and “× 8” are used as “× 8”, the DRAM chip is usually as shown in FIG. 1A or FIG. 2A. The eight pads on the center side of the pad row are used as the DQ pads 15 ₁ (25 ₁ ). Therefore, as shown in FIG. 1B or FIG. 2B, in order to use the eight pads on one end side of the pad row as DQ pads, it is necessary to change the wiring of the semiconductor chip (second chip). become. The wiring of the second chip 13 (23) may be changed, for example, by exchanging an exposure mask used in the chip manufacturing process, or may be changed using a known fuse element or antifuse element.
(Second Embodiment)
FIG. 3 is a diagram illustrating a configuration example of the semiconductor device according to the second embodiment. FIG. 3A is a plan view illustrating a connection example between the first chip and the wiring board, and FIG. It is a top view which shows the example of a connection of a 2nd chip | tip and a wiring board. The semiconductor device shown in FIGS. 3A and 3B includes a wiring board 31 and a first chip 32 and a second chip 33 stacked on the wiring board 31. 3A and 3B, a plurality of pads are arranged in a row (one row) near the center of one surface of the first chip 32 and the second chip 33, and one end side of the pad row. ₁ shows a configuration example in which DQ pads 35 ₁ (35 ₂ ) are arranged.

  For the first chip 32 and the second chip 33 shown in FIGS. 3A and 3B, for example, x8 DRAM chips are used. The first chip 32 and the second chip 33 are mounted on the wiring board 31 such that the pad forming surfaces thereof face in opposite directions with respect to the wiring board 31.

In the semiconductor device of this embodiment, an RDL (Redistribution Layer) is provided on each of the first chip 32 and the second chip 33, and is provided near the center of the first chip 32 by wiring in the RDL. The connected DQ pad 35 ₁ and the chip pad 34 ₁ provided in a row along the end of the first chip 32 are connected, and the DQ pad 35 ₂ provided near the center of the second chip 33 and the second a structure for connecting the chip pads 34 ₂ provided in a row along the chip 33 ends. In FIGS. 3A and 3B, dotted lines in the first chip 32 and the second chip 33 indicate wirings in the RDL, respectively.

The chip pads 34 ₁ provided in a row along the end of the first chip 32 and the bond fingers 36 ₁ provided in a row along the end of the wiring substrate 31 are connected by bonding wires 37 ₁ , respectively. the bond fingers 36 ₂ provided in a row along the chip pads 34 ₂ and the wiring board 31 end mounted in rows along the second chip 33 ends, are connected by bonding wires 37 _2, respectively. Chip pads 34 _1, for example as bonding wires 37 ₁ is the length of the required minimum, is disposed in the vicinity of the corresponding bond fingers 36 ₁ on the wiring board 31, chip pads 34 _2, for example, bonding wires It is arranged in the vicinity of the corresponding bond finger 36 ₂ on the wiring board 31 so that 37 ₂ has the minimum necessary length.

  FIGS. 3A and 3B show an example in which the first chip 32 is used as the lower byte and the second chip 33 is used as the upper byte. However, the first chip 32 is used as the upper byte. And the second chip 33 may be used in the lower byte.

In the semiconductor device of this embodiment, as shown in FIG. 3 (a), (b) , the wiring length from the DQ pads 35 ₁ of the first chip 32 to the lower byte ball 38, the second chip 33 DQ from the pad 35 ₂ as the wiring length to the upper byte balls 39 are equal, setting the wiring length of the RDL on the first chip 32 and second chip 33. That is, the wiring length in the RDL provided on the first chip 32 is different from the wiring length in the RDL provided on the second chip 33.

The wiring in the RDL provided on the first chip 32 is made longer than the wiring in the RDL provided on the second chip 33. A wiring length difference is the first chip 32 and bond fingers 36 bonding wire 37 ₁ length and lower byte ball 38 and the bond fingers 36 ₁ and the value obtained by adding the wiring length of the wiring board 31 for connection that connects ₁ And the value obtained by adding the length of the bonding wire 37 ₂ connecting the second chip 33 and the bond finger 36 ₂ and the wiring length in the wiring board 31 connecting the upper bite ball 39 and the bond finger 36 ₂ to each other. It only has to be equal.

FIG. 4 is a diagram illustrating another configuration example of the semiconductor device according to the second embodiment. FIG. 4A is a plan view illustrating a connection example between the first chip and the wiring board, and FIG. These are top views which show the example of a connection of a 2nd chip | tip and a wiring board. The semiconductor device shown in FIGS. 4A and 4B includes a wiring board 41 and a first chip 42 and a second chip 43 that are stacked on the wiring board 41. 4A and 4B, two rows of pads are arranged near the center of one surface of the first chip 42 and the second chip 43, and a DQ pad 45 ₁ (on the one end side of the pad row). 45 ₂ ) shows an example of the arrangement.

  For the first chip 42 and the second chip 43 shown in FIGS. 4A and 4B, for example, x8 DRAM chips are used. The first chip 42 and the second chip 43 are mounted on the wiring board 41 so that the pad formation surface faces in the opposite direction to the wiring board 41.

The semiconductor devices shown in FIGS. 4A and 4B are also provided with RDLs (Redistribution Layers) on the first chip 42 and the second chip 43, respectively, and the first DL is provided by wiring in the RDL. The DQ pad 45 ₁ provided near the center of the chip 42 and the chip pad 44 ₁ provided in a row along the end of the first chip 42 are connected, and provided near the center of the second chip 43. In this configuration, the DQ pad 45 ₂ is connected to the chip pad 44 ₂ provided in a row along the end of the second chip 43.

  Also in FIGS. 4A and 4B, dotted lines in the first chip 42 and the second chip 43 indicate wirings in the RDL.

Chip pads 44 ₁ provided in a row along the end of the first chip 42 and bond fingers 46 ₁ provided in a row along the end of the wiring substrate 41 are connected by bonding wires 47 ₁ , respectively. The chip pads 44 ₂ provided in a row along the ends of the two chips 43 and the bond fingers 46 ₂ provided in a row along the ends of the wiring substrate 41 are connected by bonding wires 47 ₂ . The chip pad 44 ₁ is disposed in the vicinity of the corresponding bond finger 46 ₁ on the wiring board 41 so that each bonding wire 47 ₁ has a minimum necessary length, for example, and the chip pad 44 ₂ is, for example, each bonding wire. It is arranged in the vicinity of the corresponding bond finger 46 ₂ on the wiring board 41 so that 47 ₂ has the minimum necessary length.

Further, FIG. 4 (a), the even arrangement shown in (b), as in the configuration shown in FIG. 3 (a), (b) , the DQ pads 45 ₁ to lower byte ball 48 of the first chip 42 of the wiring length, so that the wiring length from the DQ pad 45 ₂ of the second chip 43 to the upper byte balls 49 are equal, the wiring length within RDL on the first chip 42 and second chip 43 Set. That is, the wiring length in the RDL provided on the first chip 42 is different from the wiring length in the RDL provided on the second chip 43.

  4A and 4B show an example in which the first chip 42 is used in the lower byte and the second chip 43 is used in the upper byte. However, the first chip 42 is used in the upper byte. And the second chip 43 may be used in the lower byte.

Note that the first chip 42 and the second chip 43 shown in FIGS. 4A and 4B are used as a single unit (in the case of realizing a × 8 DRAM), the pad formation surface of which is the wiring substrate 41. Mounted to face. Therefore, if the pad formation surface is mounted so as to face the opposite direction with respect to the wiring substrate 41 as in the present embodiment, the arrangement relationship of the left and right pad rows is reversed. Therefore, in FIGS. 4A and 4B, the left DQ pad 45 ₁ (45 ₂ ) provided on the first chip 42 and the second chip 43 is arranged in a row at the right end of the chip by wiring in the RDL. Chip pad 46 ₁ (46 ₂ ) provided on the chip, and right DQ pad 45 ₁ (45 ₂ ) and chip pad 46 ₁ (46 ₂ ) provided in a row at the left end of the chip are connected. .

According to the semiconductor device of the second embodiment, the wiring length from the DQ pad 35 ₁ (45 ₁ ) of the first chip 32 (42) to the lower byte 38 (48), and the second chip 33 On the first chip 32 (42) and the second chip 33 (43), the wiring length from the DQ pad 35 ₂ (45 ₂ ) of (43) to the upper bite ball 39 (49) is equal. It adjusts with the length of the wiring in RDL provided.

  Therefore, the signal delay time difference between the data strobe signal DQS and the data DQ with respect to the clock CK is reduced between the lower byte and the upper byte, and the semiconductor device can be operated at higher speed.

Further, depending on the wiring length in the RDL, the wiring length from the DQ pad 35 ₁ (45 ₁ ) of the first chip 32 (42) to the lower byte 38 (48) and the second chip 33 (43) In order to adjust the wiring length from the DQ pad 35 ₂ (45 ₂ ) to the upper byte 39 (49) to be equal to each other, the lower byte DQ is provided in each semiconductor chip as in the first embodiment. There is no need to provide a pad and a DQ pad for the upper byte. Therefore, compared with the structure of 1st Embodiment, the increase in the circuit area of the 1st chip | tip 32 (42) and the 2nd chip | tip 33 (43) can be suppressed.

11, 21, 31, 41 Wiring board 12, 22, 32, 42 First chip 13, 23, 33, 43 Second chip 14 Opening 15 ₁ , 15 ₂ , 25 ₁ , 25 ₂ , 35 ₁ , 35 ₂ , 45 _1, 45 ₂ DQ pads 16 _1, 16 _2, 26 _1, 26 _2, 36 _1, 36 _2, 46 _1, 46 ₂ bond fingers 17 _1, 17 _2, 27 _1, 27 _2, 37 _1, 37 ₂ , 47 _1, 47 ₂ bonding wires 18,28,38,48 ball lower byte ball 19,29,39,49 upper byte 34 _1, 34 _2, 44 _1, 44 ₂ chip pad

Claims (5)

A wiring board provided with solder balls as data input / output terminals corresponding to the upper byte and the lower byte,
A plurality of DQ pads that are data input / output terminals are formed on one surface, and a first chip and a second chip that are semiconductor chips stacked on the wiring board;
Have
The first chip and the second chip have a DQ pad for the upper byte and a DQ pad for the lower byte, respectively.
Corresponding to the positional relationship between the solder ball for the lower byte and the solder ball for the upper byte provided on the wiring board, the first chip includes the first byte and the lower byte. The DQ pad for the one bite is arranged so that the distance from the solder ball for one bite used in the chip is close,
A semiconductor device characterized in that a DQ pad for the other bit is disposed on the second chip so that the distance from the solder ball for the other bit used in the second chip is reduced. .   2. The semiconductor device according to claim 1, wherein the first chip and the second chip are DRAM chips capable of supporting “× 16” and “× 8”, and are used as “× 8”, respectively. A wiring board provided with solder balls as data input / output terminals corresponding to the upper byte and the lower byte,
A plurality of DQ pads that are data input / output terminals are formed on one surface, and a first chip and a second chip that are semiconductor chips stacked on the wiring board;
Have
The first chip and the second chip are:
A semiconductor device comprising: a rewiring layer that connects the DQ pad and a chip pad provided at a chip end, the wiring lengths of which are different between the first chip and the second chip.   The wiring length in the rewiring layer provided in the first chip and the wiring length in the rewiring layer provided in the second chip are determined from the upper byte and the lower byte from the DQ pad of the first chip. The wiring length to the solder ball for one byte is set to be equal to the wiring length from the DQ pad of the second chip to the solder ball for the other byte of the upper byte and the lower byte. The semiconductor device according to claim 3.   5. The semiconductor device according to claim 3, wherein the first chip and the second chip are “× 8” DRAM chips.

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