JP2014033396A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of reducing noise in a pixel signal without accelerating AD conversion processing.SOLUTION: A multi-level conversion circuit 8 converts a level of a pixel signal VSIG read from a pixel PC into a plurality of levels, and a column ADC circuit 4A detects the pixel signal VSIG on the basis of a result of comparison of the plurality of levels of the pixel signal VSIG output from the multi-level conversion circuit 8 with a reference signal VREF.

Description

  Embodiments described herein relate generally to a solid-state imaging device.

  In order to reduce thermal noise and 1 / f noise generated in the pixels of the solid-state imaging device, there is a method of multi-sampling pixel signals read from the solid-state imaging device. In this multi-sample, AD conversion is performed a plurality of times on the same pixel signal read from the solid-state imaging device, and then the plurality of signals are averaged.

JP 2011-142443 A

  An object of one embodiment of the present invention is to provide a solid-state imaging device capable of reducing noise of a pixel signal without increasing the speed of AD conversion processing.

  According to one embodiment of the present invention, a pixel array section, a multi-level conversion circuit, and a column ADC circuit are provided. In the pixel array portion, pixels that accumulate photoelectrically converted charges are arranged in a matrix. The multi-level conversion circuit converts the level of the pixel signal read from the pixel into a plurality of levels. The column ADC circuit detects the pixel signal based on a comparison result between a plurality of levels of the pixel signal and a reference signal.

FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG. FIG. 3 is a timing chart showing voltage waveforms at various parts during the read operation of the solid-state imaging device of FIG. FIG. 4 is a block diagram showing a configuration example of a multi-level conversion circuit and a column ADC circuit for one column of the solid-state imaging device of FIG. FIG. 5A is a timing chart showing sample timings of signal levels and reset levels read from the solid-state imaging device of FIG. 1, and FIGS. 5B and 5C are diagrams of FIG. 6 is a timing chart showing output waveforms of comparators CP1 and CP2 corresponding to sample timing. FIG. 6 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the second embodiment. FIG. 7 is a timing chart showing voltage waveforms at various parts during the read operation of the solid-state imaging device of FIG. FIG. 8 is a block diagram illustrating a configuration example of a multi-level conversion circuit and a column ADC circuit for one column of the solid-state imaging device of FIG. FIG. 9A is a timing chart showing sample timings of the signal level and the reset level read from the solid-state imaging device of FIG. 6, and the comparator CP1 corresponding to the sample timings of FIGS. 9B to 9E. It is a timing chart which shows the output waveform of -CP4. FIG. 10 is a diagram showing the relationship between the ADC resolution and random noise when the number of signal level samples is changed. FIG. 11 is a diagram illustrating the relationship between the ADC resolution and the dynamic range when the number of signal level samples is changed.

  Exemplary embodiments of a solid-state imaging device will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment.
In FIG. 1, a pixel array unit 1 is provided in the solid-state imaging device. In the pixel array section 1, pixels PC that accumulate photoelectrically converted charges are arranged in a matrix in the row direction RD and the column direction CD. Further, in the pixel array unit 1, a horizontal control line Hlin that performs read control of the pixel PC is provided in the row direction RD, and a vertical signal line Vlin that transmits a signal read from the pixel PC is provided in the column direction CD. It has been.

  Further, in the solid-state imaging device, a source follower operation is performed between the pixel PC to be read out and the vertical scanning circuit 2 that scans the pixel PC in the vertical direction and the pixel PC, so that the vertical signal line Vlin from the pixel PC to each column. The load circuit 3 for reading signals, the column ADC circuit 4A for detecting the signal component of each pixel PC for each column by the CDS, the horizontal scanning circuit 5 for horizontally scanning the pixel PC to be read, and the column ADC circuit 4A A reference voltage generation circuit 6 that outputs a voltage VREF, a timing control circuit 7 that controls the timing of reading and accumulation of each pixel PC, and a multi-level conversion that converts the level of the pixel signal VSIG read from the pixel PC into a plurality of levels A circuit 8 is provided. Here, the column ADC circuit 4A can detect the pixel signal VSIG based on the comparison result between the plurality of levels of the pixel signal VSIG output from the multi-level conversion circuit 8 and the reference signal VREF. Note that a ramp wave can be used as the reference voltage VREF.

  Then, the pixel PC is selected in the row direction RD by the vertical scanning circuit 2 scanning the pixel PC in the vertical direction. Then, in the load circuit 3, a source follower operation is performed between the pixel PC and the pixel signal VSIG read from the pixel PC is transmitted via the vertical signal line Vlin to the multi-level conversion circuit 8. Sent. In the multi-level conversion circuit 8, the level of the pixel signal VSIG read from the pixel PC is converted into a plurality of levels and sent to the column ADC circuit 4A. In the reference voltage generation circuit 6, a ramp wave is set as the reference voltage VREF and sent to the column ADC circuit 4A. In the column ADC circuit 4A, a clock counting operation is performed until the signal level and reset level of the plurality of pixel signals VSIG output from the multilevel conversion circuit 8 match the level of the reference voltage VREF. The signal component of each pixel PC is detected by taking the difference average between the plurality of signal levels and the reset level, and is output as the output signal Vout.

  Here, the level of the pixel signal VSIG read from the same pixel PC is converted into a plurality of levels, and the plurality of levels of the pixel signal VSIG are compared with the reference voltage VREF, thereby parallelizing the comparison processing. The pixel signal VSIG can be multisampled. For this reason, it becomes possible to reduce thermal noise and 1 / f noise, to suppress an increase in time required for the comparison process, and to suppress a decrease in frame rate.

FIG. 2 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG.
In FIG. 2, the pixel PC is provided with a photodiode PD, an amplification transistor Tb, a reset transistor Tc, and a readout transistor Td. In addition, a floating diffusion FD is formed as a detection node at a connection point between the amplification transistor Tb, the reset transistor Tc, and the read transistor Td.

  The source of the read transistor Td is connected to the photodiode PD, and the read signal READ is input to the gate of the read transistor Td. The source of the reset transistor Tc is connected to the drain of the read transistor Td, the reset signal RSG is input to the gate of the reset transistor Tc, and the drain of the reset transistor Tc is connected to the power supply potential RSD. The source of the amplification transistor Tb is connected to the vertical signal line Vlin, the gate of the amplification transistor Tb is connected to the drain of the read transistor Td, and the drain of the amplification transistor Tb is connected to the power supply potential VDD.

  The load circuit 3 is provided with a current source G for each column. The current source G is connected to the vertical signal line Vlin for each column. Note that the horizontal control line Hlin in FIG. 2 can transmit the read signal READ and the reset signal RSG to the pixel PC for each row.

FIG. 3 is a timing chart showing voltage waveforms at various parts during the read operation of the solid-state imaging device of FIG. In the example of FIG. 3, the method of converting one level of the pixel signal VSIG into two levels is shown.
In FIG. 3, with the power supply potential RSD rising (t1), when the reset signal RSG rises (t2), the reset transistor Tc is turned on, and excess charge generated due to leakage current or the like is reset to the floating diffusion FD. . A voltage corresponding to the reset level of the floating diffusion FD is applied to the gate of the amplification transistor Tb. Here, since the amplification transistor Tb and the current source G form a source follower, the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb, and the output voltage VSIG at the reset level is vertical. The signal is sent to the multilevel conversion circuit 8 via the signal line Vlin. Then, in the multi-level conversion circuit 8, the reset level of the pixel signal VSIG read from the pixel PC is converted into two reset levels VRP and VRN and sent to the column ADC circuit 4A.

  In the column ADC circuit 4A, when the output voltage VSIG of the two reset levels VRP and VRN is input and a ramp wave is applied as the reference voltage VREF, the output voltage VSIG of the two reset levels VRP and VRN and the ramp are supplied. The wave is compared.

  The output voltage VSIG of the two reset levels VRP and VRN is down-counted until they match the ramp wave level (t3 and t4), so that the output voltage VSIG of the two reset levels VRP and VRN becomes a digital value. Each is converted and held.

  Next, when the read signal READ rises (t5), the read transistor Td is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD, and a voltage corresponding to the signal level of the floating diffusion FD is amplified. Apply to the gate of Tb. Here, since the amplification transistor Tb and the current source G constitute a source follower, the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb, and the output voltage VSIG at the signal level is vertical. The signal is sent to the multilevel conversion circuit 8 via the signal line Vlin. In the multi-level conversion circuit 8, the signal level of the pixel signal VSIG read from the pixel PC is converted into two signal levels VSP and VSN, and sent to the column ADC circuit 4A.

  In the column ADC circuit 4A, when the output voltage VSIG of the two signal levels VSP and VSN is input and a ramp wave is applied as the reference voltage VREF, the output voltage VSIG of the two signal levels VSP and VSN and the ramp are supplied. The wave is compared.

  The output voltages VSIG of the two signal levels VSP and VSN are then up-counted until they match the ramp wave level (t6, t7), so that the output voltage VSIG of the signal levels VSP and VSN and the reset level VRP are obtained. , The difference between VRN and output voltage VSIG is converted into a digital value. Then, after the difference between the output voltage VSIG of the signal levels VSP and VSN and the output voltage VSIG of the reset levels VRP and VRN is averaged, it is output as the output signal S1.

  Next, when the reset signal RSG rises with the power supply potential RSD falling (t8), the reset transistor Tc is turned on, and the potential of the floating diffusion FD is set to a low level. For this reason, the amplification transistor Tb is turned off, and the voltage of the direct signal line Vlin does not follow the potential of the floating diffusion FD.

FIG. 4 is a block diagram showing a configuration example of a multi-level conversion circuit and a column ADC circuit for one column of the solid-state imaging device of FIG.
In FIG. 4, the multi-level conversion circuit 8 is provided with a differential amplifier DA for each column. The column ADC circuit 4A is provided with comparators CP1 and CP2, an arithmetic unit 11, a counter 12, a latch circuit 13, a multiplier 14 and an adder 15.

The differential amplifier DA can convert one level of the pixel signal VSIG into two levels by differentiating the pixel signal VSIG. The comparators CP1 and CP2 can compare the two levels of the pixel signal VSIG with the reference voltage VREF in parallel. The computing unit 11 can compute the current carry CA and the remainder B {0, 1} based on the outputs of the current comparators CP1 and CP2 and the remainder B {0, 1} from the previous computing unit 11. it can. The computing unit 11 may be an adder or a lookup table. Further, since the carry CA and the remainder B {0, 1} are each 1 bit, the arithmetic unit 11 can take a 3-bit input and a 2-bit output. The counter 12 can count the carry CA according to the counter clock CK. The latch circuit 13 can latch the remainder B {0, 1} according to the counter clock CK. The multiplier 14 can multiply the count result of the counter 12 by 2 ¹ = 2. The adder 15 can add the output of the multiplier 14 and the remainder B {0, 1}.

  FIG. 5A is a timing chart showing sample timings of signal levels and reset levels read from the solid-state imaging device of FIG. 1, and FIGS. 5B and 5C are diagrams of FIG. 6 is a timing chart showing output waveforms of comparators CP1 and CP2 corresponding to sample timing.

  5A to 5C, when the reset signal RSG rises in the state where the power supply potential RSD of FIG. 3 has risen, the output voltage VSIG at the reset level is changed to the differential amplifier DA via the vertical signal line Vlin. Sent to. In the differential amplifier DA, the output voltage VSIG at the reset level is differentiated, so that the set level of the output voltage VSIG is converted into two reset levels VRP and VRN, which are input to the comparators CP1 and CP2, respectively. . The reference voltage VREF is input from the reference voltage generation circuit 6 to the comparators CP1 and CP2.

  Then, the comparators CP1 and CP2 compare the two reset levels VRP and VRN of the output voltage VSIG with the reference voltage VREF. When the reset level VRP matches the reference voltage VREF, the output of the comparator CP1 is inverted, and the inverted result is input to the calculator 11 (t3). When the reset level VRN coincides with the reference voltage VREF, the output of the comparator CP2 is inverted, and the inverted result is input to the calculator 11 (t4). The previous remainder B from the calculator 11 is held in the latch circuit 13 and input to the calculator 11. Then, the arithmetic unit 11 adds the outputs of the comparators CP1 and CP2 and the previous remainder B {0, 1} to calculate the carry CA and the current remainder B {0, 1}, and the carry CA. Is output to the counter 12 and the remainder B {0, 1} of this time is held in the latch circuit 13. Then, the counter 12 counts the carry CA according to the counter clock CK, and outputs the count result to the multiplier 14. The multiplier 14 doubles the count result, and the adder 15 adds the remainder B {0, 1}.

  Next, when the read signal READ rises (t5), the signal level output voltage VSIG is sent to the differential amplifier DA via the vertical signal line Vlin. Then, in the differential amplifier DA, the signal level output voltage VSIG is differentiated, whereby the signal level of the output voltage VSIG is converted into two signal levels VSP and VSN, which are input to the comparators CP1 and CP2, respectively. . The reference voltage VREF is input from the reference voltage generation circuit 6 to the comparators CP1 and CP2.

  Then, the comparators CP1 and CP2 compare the two signal levels VSP and VSN of the output voltage VSIG with the reference voltage VREF. When the signal level VSN matches the reference voltage VREF, the output of the comparator CP1 is inverted, and the inverted result is input to the calculator 11 (t6). When the signal level VSP matches the reference voltage VREF, the output of the comparator CP2 is inverted, and the inverted result is input to the calculator 11 (t7). The previous remainder B {0, 1} from the computing unit 11 is held in the latch circuit 13 and input to the computing unit 11. Then, the arithmetic unit 11 adds the outputs of the comparators CP1 and CP2 and the previous remainder B {0, 1} to calculate the carry CA and the current remainder B {0, 1}, and the carry CA. Is output to the counter 12 and the remainder B {0, 1} of this time is held in the latch circuit 13. Then, the counter 12 counts the carry CA according to the counter clock CK, and outputs the count result to the multiplier 14. Then, after the count value is doubled in the multiplier 14, the remainder B {0, 1} is added in the adder 15.

  For example, it is assumed that the output of the comparator CP1 becomes 11111100 and the output of the comparator CP2 becomes 11100000 according to the clocks k1 to k8. In this case, since the count value of the output of the comparator CP1 is 6 and the count value of the output of the comparator CP2 is 3, the sum of these count values is 9.

  On the other hand, when the outputs of the comparators CP1 and CP2 are input to the arithmetic unit 11, the carry CA becomes 11101000 and the remainder B {0, 1} becomes 00001111 according to the clocks k1 to k8. Therefore, the count value of the counter 12 is 4, and the remainder B {0,1} is 1. When the count value of the counter 12 is doubled and the remainder B {0,1} = 1 is added, the value 9 is obtained. Is obtained. For this reason, even when one counter 12 is shared by the comparators CP1 and CP2, the same value as that obtained when a separate counter is provided for each of the comparators CP1 and CP2 is obtained. For this reason, even when multi-sampling of the pixel signal VSIG is performed, an increase in the number of counters can be suppressed, and the circuit scale of the counters can be reduced.

Here, if the signal component by CDS of the column ADC circuit 4A is ΔVCDS, the reset level of the pixel signal VSIG is VR, and the signal level of the pixel signal VSIG is VS, ΔVCDS = VR−VS.
On the other hand, if the signal component when the pixel signal VSIG is differentiated is VDIF, VDIF = 2 × ΔVCDS. For this reason, the effect of doubling the gain can be obtained, and the quantization noise can be reduced to ½.

  Also, if the count time corresponding to the signal component of the pixel signal VSIG is ΔTCDS and the count time corresponding to the signal component when the pixel signal VSIG is differentiated is ΔTCDP and ΔTCDN, respectively, ΔTCDS = (ΔTCDP + ΔTCDN) / 2 is given. And thermal noise can be reduced to 1 / √2. If the count times at the reset levels VRP and VRN are TRP and TRN, and the count times at the signal levels VSP and VSN are TSP and TSN, respectively, ΔTCDP = TSP-TRP and ΔTCDN = TSN-TRN can be given.

  In the first embodiment described above, the method of converting one level of the pixel signal VSIG into two levels has been described. However, one level of the pixel signal VSIG may be converted into three or more levels. .

  In the first embodiment described above, the method of sharing one counter 12 for the two comparators CP1 and CP2 has been described. However, a counter is separately prepared for each of the comparators CP1 and CP2, and the counters from those counters are prepared. The output may be averaged.

(Second Embodiment)
FIG. 6 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the second embodiment.
In FIG. 6, this solid-state imaging device is provided with a column ADC circuit 4B and reference voltage generating circuits 6A and 6B instead of the column ADC circuit 4A and the reference voltage generating circuit 6 of the solid-state imaging device of FIG. The reference voltage generation circuit 6 can output the reference voltages VREF1 and VREF2 to the column ADC circuit 4B. The reference voltages VREF1 and VREF2 can use ramp waves. The reference voltages VREF1 and VREF2 can have the same waveform, and the reference voltage VREF2 can be generated by shifting the reference voltage VREF1 with time. The column ADC circuit 4B can detect the pixel signal VSIG based on the comparison result between the plurality of levels of the pixel signal VSIG output from the multilevel conversion circuit 8 and the reference signals VREF1 and VREF2.

  Then, the pixel PC is selected in the row direction RD by the vertical scanning circuit 2 scanning the pixel PC in the vertical direction. Then, in the load circuit 3, a source follower operation is performed between the pixel PC and the pixel signal VSIG read from the pixel PC is transmitted via the vertical signal line Vlin to the multi-level conversion circuit 8. Sent. Then, in the multi-level conversion circuit 8, the level of the pixel signal VSIG read from the pixel PC is converted into a plurality of levels and sent to the column ADC circuit 4B. In the reference voltage generation circuits 6A and 6B, ramp waves are set as the reference voltages VREF1 and VREF2 and sent to the column ADC circuit 4B. In the column ADC circuit 4B, the clock count operation is performed until the signal level and the reset level of the plurality of pixel signals VSIG output from the multi-level conversion circuit 8 coincide with the levels of the reference voltages VREF1 and VREF2, respectively. After the difference between the plurality of signal levels and the reset level for the signal VSIG is taken for each of the reference voltages VREF1 and VREF2, the signal components of each pixel PC are detected by averaging them and output as the output signal Vout Is done.

  Here, the level of the pixel signal VSIG read from the same pixel PC is converted into a plurality of levels, and the plurality of levels of the pixel signal VSIG are compared with a plurality of reference voltages VREF1 and VREF2, thereby performing the comparison process. It is possible to multisample the pixel signal VSIG while parallelizing. For this reason, it becomes possible to reduce thermal noise and 1 / f noise, to suppress an increase in time required for the comparison process, and to suppress a decrease in frame rate.

FIG. 7 is a timing chart showing voltage waveforms at various parts during the read operation of the solid-state imaging device of FIG. In the example of FIG. 7, the method of comparing the two levels of the pixel signal VSIG with the two reference signals VREF1 and VREF2 is shown.
In FIG. 7, when the power supply potential RSD rises (t1) and the reset signal RSG rises (t2), the reset transistor Tc is turned on, and excess charge generated due to leakage current or the like is reset to the floating diffusion FD. . A voltage corresponding to the reset level of the floating diffusion FD is applied to the gate of the amplification transistor Tb. Here, since the amplification transistor Tb and the current source G form a source follower, the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb, and the output voltage VSIG at the reset level is vertical. The signal is sent to the multilevel conversion circuit 8 via the signal line Vlin. Then, in the multi-level conversion circuit 8, the reset level of the pixel signal VSIG read from the pixel PC is converted into two reset levels VRP and VRN and sent to the column ADC circuit 4B.

  In the column ADC circuit 4B, when the output voltage VSIG of the two reset levels VRP and VRN is input and a ramp wave is applied as the reference voltages VREF1 and VREF2, the output voltage VSIG of the two reset levels VRP and VRN. Are compared with the reference voltages VREF1 and VREF2.

  The output voltage VSIG at the reset level VRP is down-counted until it matches the levels of the reference voltages VREF1 and VREF2 (t3, t4), so that the output voltage VSIG at the reset level VRP is converted into a digital value and held. The Further, the output voltage VSIG at the reset level VRN is down-counted until it matches the levels of the reference voltages VREF1 and VREF2 (t5, t6), so that the output voltage VSIG at the reset level VRN is converted into a digital value and held. The

  Next, when the read signal READ rises (t7), the read transistor Td is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD, and a voltage corresponding to the signal level of the floating diffusion FD is amplified. Apply to the gate of Tb. Here, since the amplification transistor Tb and the current source G constitute a source follower, the voltage of the vertical signal line Vlin follows the voltage applied to the gate of the amplification transistor Tb, and the output voltage VSIG at the signal level is vertical. The signal is sent to the multilevel conversion circuit 8 via the signal line Vlin. In the multi-level conversion circuit 8, the signal level of the pixel signal VSIG read from the pixel PC is converted into two signal levels VSP and VSN, and sent to the column ADC circuit 4B.

  In the column ADC circuit 4B, when the output voltage VSIG of the two signal levels VSP and VSN is input and a ramp wave is applied as the reference voltages VREF1 and VREF2, the output voltage VSIG of the two signal levels VSP and VSN. Are compared with the reference voltages VREF1 and VREF2.

  Then, the output voltage VSIG of the signal level VSN is up-counted until the level of the reference voltages VREF1 and VREF2 coincides with each other (t8, t9), thereby outputting the output voltage VSIG of the signal level VSN and the reset level VRN. A difference from the voltage VSIG is converted into a digital value for each of the reference voltages VREF1 and VREF2. Further, the output voltage VSIG of the signal level VSP is now up-counted until it matches the level of each of the reference voltages VREF1 and VREF2 (t10, t11), thereby outputting the output voltage VSIG of the signal level VSP and the reset level VRP. A difference from the voltage VSIG is converted into a digital value for each of the reference voltages VREF1 and VREF2. Then, the difference between the output voltage VSIG of the signal levels VSP and VSN and the output voltage VSIG of the reset levels VRP and VRN at the reference voltages VREF1 and VREF2 is averaged, and then output as the output signal S1.

  Next, when the reset signal RSG rises with the power supply potential RSD falling (t12), the reset transistor Tc is turned on and the potential of the floating diffusion FD is set to a low level. For this reason, the amplification transistor Tb is turned off, and the voltage of the direct signal line Vlin does not follow the potential of the floating diffusion FD.

FIG. 8 is a block diagram illustrating a configuration example of a multi-level conversion circuit and a column ADC circuit for one column of the solid-state imaging device of FIG.
In FIG. 8, the column ADC circuit 4B is provided with comparators CP1 to CP4, an arithmetic unit 21, a counter 22, a latch circuit 23, a multiplier 24, and an adder 25.

The comparators CP1 to CP4 can compare two levels of the pixel signal VSIG with the two reference voltages VREF1 and VREF2, respectively, in parallel. The computing unit 21 can compute the current carry CA and the remainder B {0, 2} based on the outputs of the current comparators CP1 to CP4 and the remainder B {0, 2} from the previous computing unit 21. it can. The calculator 21 may be an adder or a lookup table. Since the carry CA is 1 bit and the remainder B {0, 2} is 2 bits, the arithmetic unit 21 can make a 6-bit input and a 3-bit output. The counter 22 can count the carry CA according to the counter clock CK. The latch circuit 23 can latch the remainder B {0, 2} according to the counter clock CK. The multiplier 24 can multiply the count result of the counter 22 by 2 ² = 4. The adder 25 can add the output of the multiplier 24 and the remainder B {0, 2}.

FIG. 9A is a timing chart showing sample timings of the signal level and the reset level read from the solid-state imaging device of FIG. 6, and the comparator CP1 corresponding to the sample timings of FIGS. 9B to 9E. It is a timing chart which shows the output waveform of -CP4.
9A to 9E, when the reset signal RSG rises in the state where the power supply potential RSD of FIG. 7 has risen, the output voltage VSIG at the reset level is changed to the differential amplifier DA via the vertical signal line Vlin. Sent to. In the differential amplifier DA, the output voltage VSIG at the reset level is differentiated, so that the set level of the output voltage VSIG is converted into two reset levels VRP and VRN. The reset level VRP is input to the comparators CP1 and CP3, and the reset level VRN is input to the comparators CP2 and CP4. The reference voltage VREF1 is input to the comparators CP1 and CP2 from the reference voltage generation circuit 6A, and the reference voltage VREF2 is input to the comparators CP3 and CP4 from the reference voltage generation circuit 6B.

  Then, the comparators CP1 to CP4 compare the two reset levels VRP and VRN of the output voltage VSIG with the reference voltages VREF1 and VREF2. When the reset level VRP matches the reference voltage VREF1, the output of the comparator CP1 is inverted, and the inverted result is input to the calculator 21 (t3). When the reset level VRN coincides with the reference voltage VREF1, the output of the comparator CP2 is inverted, and the inverted result is input to the calculator 21 (t4). When the reset level VRP matches the reference voltage VREF2, the output of the comparator CP3 is inverted, and the inverted result is input to the calculator 21 (t5). When the reset level VRN coincides with the reference voltage VREF2, the output of the comparator CP4 is inverted, and the inverted result is input to the calculator 21 (t6). The previous remainder B {0, 2} from the arithmetic unit 21 is held in the latch circuit 23 and input to the arithmetic unit 21. Then, the arithmetic unit 21 adds the outputs of the comparators CP1 to CP4 and the previous remainder B {0, 2}, thereby calculating the carry CA and the current remainder B {0, 2}. Is output to the counter 22, and the remainder B {0, 2} of this time is held in the latch circuit 23. Then, the counter 22 counts the carry CA according to the counter clock CK and outputs the count result to the multiplier 24. Then, after the count result is multiplied by 4 in the multiplier 24, the remainder B {0, 2} is added in the adder 25.

  Next, when the read signal READ rises (t7), the signal level output voltage VSIG is sent to the differential amplifier DA via the vertical signal line Vlin. In the differential amplifier DA, the signal level of the output voltage VSIG is differentiated, whereby the signal level of the output voltage VSIG is converted into two signal levels VSP and VSN. The signal level VSP is input to the comparators CP1 and CP3, and the signal level VSN is input to the comparators CP2 and CP4. The reference voltage VREF1 is input to the comparators CP1 and CP2 from the reference voltage generation circuit 6A, and the reference voltage VREF2 is input to the comparators CP3 and CP4 from the reference voltage generation circuit 6B.

  Then, the comparators CP1 to CP4 compare the two signal levels VSP and VSN of the output voltage VSIG with the reference voltages VREF1 and VREF2. When the signal level VSN matches the reference voltage VREF1, the output of the comparator CP2 is inverted, and the inverted result is input to the calculator 21 (t8). When the signal level VSN matches the reference voltage VREF2, the output of the comparator CP4 is inverted, and the inverted result is input to the calculator 21 (t9). When the signal level VSP matches the reference voltage VREF1, the output of the comparator CP1 is inverted, and the inverted result is input to the calculator 21 (t10). When the signal level VSP matches the reference voltage VREF2, the output of the comparator CP3 is inverted, and the inverted result is input to the calculator 21 (t11). The previous remainder B {0, 2} from the arithmetic unit 21 is held in the latch circuit 23 and input to the arithmetic unit 21. Then, the arithmetic unit 21 adds the outputs of the comparators CP1 to CP4 and the previous remainder B {0, 2}, thereby calculating the carry CA and the current remainder B {0, 2}. Is output to the counter 22, and the remainder B {0, 2} of this time is held in the latch circuit 23. Then, the counter 22 counts the carry CA according to the counter clock CK and outputs the count result to the multiplier 24. Then, after the count value is multiplied by 4 in the multiplier 24, the remainder B {0, 2} is added in the adder 25.

  Here, the count time according to the signal component of the pixel signal VSIG is ΔTCDS, and the count time according to the signal component when the pixel signal VSIG is differentiated at the reference voltage VREF1 is the pixel signal at ΔTCDP1, ΔTCDN1, and the reference voltage VREF2, respectively. If the count times corresponding to the signal components when VSIG is differentiated are ΔTCDP2 and ΔTCDN2, respectively, ΔTCDS = (ΔTCDP1 + ΔTCDN1 + ΔTCDP2 + ΔTCDN2) / 4 can be given, and the thermal noise can be reduced to 1 / √4.

  In the second embodiment described above, the method of comparing the plurality of levels of the pixel signal VSIG with the plurality of reference signals VREF1 and VREF2 has been described. However, one level of the pixel signal VSIG and the plurality of reference signals VREF1, The number of samples of the pixel signal VSIG read from the same pixel PC may be increased by performing a comparison with VREF2.

  In the second embodiment described above, the method of converting one level of the pixel signal VSIG into two levels has been described. However, one level of the pixel signal VSIG may be converted into three or more levels. . In the second embodiment described above, the method using the two time-shifted reference signals VREF1 and VREF2 has been described. However, three or more time-shifted reference signals may be used.

  Further, in the second embodiment described above, the method of sharing one counter 22 for the four comparators CP1 to CP4 has been described. However, a counter is separately prepared for each of the comparators CP1 to CP4, and the counters from those counters are prepared. The output may be averaged.

FIG. 10 is a diagram illustrating a relationship between ADC (AD converter) resolution and random noise when the number of signal level samples is changed.
In FIG. 10, when the number of samples at the signal level is increased, random noise can be reduced even when the AD converter resolution is constant. For example, when the number of samples is doubled, the random noise becomes 1 / √2.

FIG. 11 is a diagram illustrating the relationship between the ADC resolution and the dynamic range when the number of signal level samples is changed.
In FIG. 11, when the number of signal level samples is increased, the dynamic range can be increased even when the AD converter resolution is constant. For example, doubling the number of samples increases the dynamic range by 3 dB.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  PC pixel, Tb amplification transistor, Tc reset transistor, Td readout transistor, PD photodiode, FD floating diffusion, Vlin vertical signal line, Hlin horizontal control line, 1 pixel array unit, 2 vertical scanning circuit, 3 load circuit, 4A, 4B Column ADC circuit, 5 horizontal scanning circuit, 6, 6A, 6B reference voltage generation circuit, 7 timing control circuit, 8 multi-level conversion circuit, DA differential amplifier, CP1 to CP4 comparator, 11, 21 calculator, 12, 22 counter , 13, 23 Latch circuit, 14, 24 Multiplier, 15, 25 Adder

Claims (5)

A pixel array unit in which pixels for accumulating photoelectrically converted charges are arranged in a matrix;
A multi-level conversion circuit for converting the level of the pixel signal read from the pixel into a plurality of levels;
A reference signal generation circuit for generating a plurality of reference signals to be compared with pixel signals read from the pixels;
A column ADC circuit that detects the pixel signal based on a comparison result between the plurality of levels of the pixel signal and the plurality of reference signals;
The column ADC circuit includes:
A plurality of comparators for comparing the plurality of levels of the pixel signal with the plurality of reference signals;
An arithmetic unit that outputs an addition result of the outputs of the plurality of comparators;
A solid-state imaging device comprising: a counter that counts a carry of the addition result. A pixel array unit in which pixels for accumulating photoelectrically converted charges are arranged in a matrix;
A multi-level conversion circuit for converting the level of the pixel signal read from the pixel into a plurality of levels;
A solid-state imaging device comprising: a column ADC circuit that detects the pixel signal based on a comparison result between a plurality of levels of the pixel signal and a reference signal.   The solid-state imaging device according to claim 2, wherein the multi-level conversion circuit converts the level of the pixel signal into a plurality of levels by differentiating the pixel signal. A pixel array unit in which pixels for accumulating photoelectrically converted charges are arranged in a matrix;
A reference signal generation circuit for generating a plurality of reference signals to be compared with pixel signals read from the pixels;
A solid-state imaging device comprising: a column ADC circuit that detects the pixel signal based on a comparison result between the level of the pixel signal and the plurality of reference signals.   The solid-state imaging device according to claim 4, wherein the reference signal generation circuit generates a plurality of reference signals by shifting one reference signal in terms of time.

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