JP2014032726A - Semiconductor device and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique, which allows manufacturers who package SiP (System in Package) products to repair defects of a memory chip that have occurred in its packaging process or after the process without using a defect repair technique of the memory chip, for the SiP products that have the memory chip and a logic chip packaged in an identical package.SOLUTION: The logic chip includes: a comparison circuit that compares an address of a defective memory cell of the memory chip, which is detected beforehand, with an address that is generated for the logic chip to access the memory chip; a storage circuit; and a selection circuit. If the address for the access matches the address of the defective memory cell, the selection circuit makes a change so as to cause the storage circuit provided in the logic chip to be accessed instead of the access target memory chip.

Description

  The present invention relates to a semiconductor integrated circuit that accesses a memory chip and a semiconductor device in which the memory chip and the memory chip are mounted in the same package. It can be done.

  With the spread of small portable devices, the importance of SiP (System in Package) products, in which large-capacity memory and SoC (System on Chip) chips are mounted in the same package, is increasing. If a large-capacity memory and an SoC chip are mounted in the same package to manufacture a SiP product, a defect may occur in the memory cells in the memory in the process.

  For example, as disclosed in Patent Document 1, a large-capacity memory is provided with a spare memory cell in advance, and the defective memory cell generated in the manufacturing process is replaced with a spare memory cell to repair the defect. Technology is widely adopted. Such a defect repair technique is a technique for repairing defects generated in the memory manufacturing stage before shipping the memory, and the repair method has been developed and implemented by the memory manufacturer itself. Is something that others cannot know and do. Therefore, a manufacturer who purchases a large-capacity memory and manufactures a SiP product usually cannot use a defect repair method for the memory.

  Patent Document 2 discloses a stacked memory chip in which a fuse portion and a relief control circuit are formed on a fuse chip different from a memory core chip and these are stacked. Since complicated control related to relief is performed with a fuse chip and stacked as a separate chip, the mounting area can be reduced, and defective memory cells generated after the stacking process can also be trimmed to the fuse chip after the stacking process This can be remedied.

  Patent Document 3 discloses a repair technique for a defective cell generated after a memory IC chip and a logic IC chip are joined in a SiP product including a memory IC chip and a logic IC chip. A switching element for switching a defective cell to a spare memory cell in the memory IC chip is separately mounted in a region other than the region where the memory IC chip is bonded on the logic IC chip, thereby relieving the defective cell.

  Patent Document 4 describes a semiconductor memory device that uses information stored in a nonvolatile memory for defect repair of a volatile memory different from the nonvolatile memory. In order to relieve the defect of the volatile memory, the connection of the circuit in the volatile memory is changed using the storage information of the nonvolatile memory.

JP-A-5-225796 JP 2009-206218 A JP 2007-53126 A JP 2000-149588 A

  Patent Document 4 does not disclose or suggest a method to be applied to a SiP product, but if the relief technique described in Patent Documents 2 and 3 is used, a defect in a memory generated in the process of manufacturing the SiP product will also be disclosed. Can be rescued. However, all of Patent Documents 2, 3 and 4 are based on the premise that spare memory cells for relief are prepared in the memory in advance, and the memory cells are produced in the memory process for relief. The same repair method as that for defect repair is applied. Therefore, a maker who manufactures a SiP product by purchasing and mounting a memory cannot use the remedy method unless the remedy method is disclosed by the maker of the memory. Even if disclosed, the technique described in Patent Document 2 needs to include a separate switching element in order to use the laser trimming apparatus and the technique described in Patent Document 3. As described above, it is practically difficult for a manufacturer who purchases a memory and manufactures a SiP product to carry out defect relief according to the conventional technology.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, in a semiconductor device in which a memory chip and a logic chip are mounted in the same package, the logic chip includes a comparison circuit and a storage circuit that compare an address of a defective memory cell of the memory chip with an address for accessing the memory chip. And a data selection circuit that switches the access target from the memory chip to the storage circuit when they match.

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, defect repair can be performed for a defect in a memory chip that occurs at the manufacturing stage of the SiP product or thereafter, without using a defect repair method for a memory chip mounted on the SiP product.

FIG. 1 is a block diagram of the SiP product according to the first embodiment. FIG. 2 is a block diagram of the SiP product according to the second embodiment. FIG. 3 is a detailed block diagram of the relief block according to the second embodiment. FIG. 4 is a block diagram of the SiP product according to the third embodiment. FIG. 5 is a block diagram of the SiP product according to the fourth embodiment. FIG. 6 is a timing chart of defect relief in burst read. FIG. 7 is a timing chart of defect relief when a wide I / O DRAM is connected.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Repairing memory defects with memory circuits in SoC chips (SiP products)>
The semiconductor device (1) in which the memory chip (2) and the logic chip (3) are mounted in the same package is configured as follows. The logic chip compares a repair address (24) of a defective memory cell of the memory chip with an access address (22) for accessing the memory chip, and outputs a comparison result of matching or mismatching (13 ), A storage circuit (14), and a data selection circuit (15) for switching the access target to the storage circuit when the comparison results match.

  Thus, defect repair can be performed for a defect of a memory chip that occurs at the manufacturing stage of the SiP product or thereafter, without using a defect repair method for a memory chip mounted on the SiP product.

[2] <Burst read>
In item 1, the memory chip is a burst accessible memory (2), and the logic chip includes a memory interface circuit (16, 17) and a processor (4) connected to each other via a bus (8). It is prepared as follows.

  The processor can issue a burst read command to the memory interface circuit via the bus. The memory interface circuit can read and temporarily store a plurality of data from the memory chip in a burst mode based on the burst read command. The processor can output, to the bus after issuing the burst read command, a read command that involves outputting an address in the memory chip of a part or all of the plurality of data to the bus. is there. The memory interface circuit can output data corresponding to an address designated by the read command among the plurality of data to the data selection circuit.

  The comparison circuit is configured to be able to compare the address in the read command with the relief address.

  Thus, when a burst accessible memory (for example, DRAM) is connected, when some or all of a plurality of burst accessed data is defective, the data including the defect is stored in the storage circuit 14. By replacing the data with no defect, defect relief can be performed.

[3] <Wide IO-DRAM>
In item 1, the logic chip includes a memory interface circuit (16, 17) and a processor (4) connected to each other via a bus (7) having a first data width, and is configured as follows.

  The memory chip is connected to the memory interface circuit via an external data bus (31) having a second data width wider than the first data width.

  The processor can issue a wide IO read command to the memory interface circuit via the bus. The memory interface circuit can read and temporarily store data of the second data width from the memory chip based on the wide IO read command. The processor outputs a read command accompanied by outputting an address for reading data of the first data width corresponding to a part or all of the data of the second data width to the bus. It can be output to the bus after it is issued. The memory interface circuit can output data corresponding to an address specified by the read command among the data having the second data width to the data selection circuit.

  The comparison circuit is configured to be able to compare the address in the read command with the relief address.

  Thus, when a wide IO-DRAM having a data width (second data width) larger than the data width (first data width) of the internal bus is connected, a part or all of the data having the second data width is connected. When there is a defect, defect repair can be performed by replacing the data including the defect with data having no defect stored in the storage circuit 14 in the unit of the first data width which is the access unit of the processor.

[4] <Relief Address Register>
In item 1, item 2 or item 3, the logic chip further includes a relief address register (12) for holding the relief address and outputting a value to be held in the comparison circuit.

  Thereby, the speed at which the relief address is read out can be increased.

[5] <Non-volatile memory on SoC>
In item 4, the logic chip further includes a nonvolatile memory (5), and has a circuit for transferring the relief address from the nonvolatile memory to the relief address register.

  As a result, the number of components integrated in the SiP product can be reduced, and the mounting area can be reduced.

[6] <Memory + SoC + nonvolatile memory SiP product>
Item 4 further includes a nonvolatile memory (9) mounted in the same package, and the logic chip has a circuit for transferring the relief address from the nonvolatile memory to the relief address register.

  Thereby, the manufacturing cost of the SoC chip can be reduced as compared with the SoC chip in Item 3.

[7] <Relief address transferred at power-on>
In item 4, item 5 or item 6, the logic chip further includes a transfer circuit (10) for transferring the relief address from the nonvolatile memory to the relief address register when power is turned on.

  As a result, the SiP product can autonomously start a memory defect repair operation.

[8] <Relief address conversion circuit>
In the first, second, or third aspect, the logic chip receives the access address instead of the comparison circuit, outputs the comparison result, and stores the access address when the comparison result is coincident with the storage circuit. An address conversion circuit (19) for converting and outputting the address is provided.

  As a result, it is not necessary to have the nonvolatile memory 5 or 9 connected inside or outside the SoC, and a defect relief operation can be performed without an operation such as transferring and setting a relief address.

[9] <ROM table>
In item 8, the address conversion circuit includes a ROM (19).

  Thereby, it is not necessary to have the nonvolatile memory 5 or 9 connected inside or outside the SoC, and the manufacturing process can be simplified.

[10] <SoC that repairs memory defects by replacing the memory circuit in the chip>
A semiconductor integrated circuit device (3) having a terminal for accessing the memory chip (2) is configured as follows. A comparison circuit (13) for comparing a relief address (24) of a defective memory cell of the memory chip and an access address (22) for accessing the memory chip and outputting a comparison result of matching or mismatching; and a storage circuit (14) and a data selection circuit (15) for switching the access target to the storage circuit when the comparison result is coincident.

  As a result, SoC chips can be used to repair defects in memory chips that occur during or after the manufacture of the SiP product without using a defect repair method for the memory chip mounted on the SiP product. Can be provided.

[11] <Burst read>
In item 10, the memory chip is a burst accessible memory (2), and the semiconductor integrated circuit device includes a memory interface circuit (16, 17) and a processor (4) connected to each other via a bus (8). And is configured as follows.

  The processor can issue a burst read command to the memory interface circuit via the bus. The memory interface circuit can read and temporarily store a plurality of data from the memory in a burst mode based on the burst read command. The processor can output, to the bus after the burst read command is issued, a read command that involves outputting an address of a part of the plurality of data in the memory chip to the bus. The memory interface circuit can output data corresponding to an address designated by the read command among the plurality of data to the data selection circuit.

  The comparison circuit is configured to be able to compare the address in the read command with the relief address.

  Thus, when a burst accessible memory (for example, DRAM) is connected, when some or all of a plurality of burst accessed data is defective, the data including the defect is stored in the storage circuit 14. By replacing the data with no defect, defect relief can be performed.

[12] <Wide IO-DRAM>
In item 10, the semiconductor integrated circuit device includes a memory interface circuit (16, 17) and a processor (4) connected to each other via a bus (7) having a first data width, and is configured as follows. The

  The memory chip can be connected to the memory interface circuit via an external data bus (31) having a second data width wider than the first data width.

  The processor can issue a wide IO read command to the memory interface circuit via the bus. The memory interface circuit can read and temporarily store data of the second data width from the memory chip based on the wide IO read command. The processor outputs a read command accompanied by outputting an address for reading data of the first data width corresponding to a part or all of the data of the second data width to the bus. It can be output to the bus after it is issued. The memory interface circuit can output data corresponding to an address specified by the read command among the data having the second data width to the data selection circuit.

  The comparison circuit is configured to be able to compare the address in the read command with the relief address.

  Thus, when a wide IO-DRAM having a data width (second data width) larger than the data width (first data width) of the internal bus is connected, a part or all of the data having the second data width is connected. When there is a defect, defect repair can be performed by replacing the data including the defect with data having no defect stored in the storage circuit 14 in the unit of the first data width which is the access unit of the processor.

[13] <Relief Address Register>
The repair address register (12) further includes a repair address register (12) that stores the repair address and outputs a value stored in the comparison circuit.

  Thereby, the speed at which the relief address is read out can be increased.

[14] <On-chip flash>
Item 13 further includes a nonvolatile memory (5) that can store the relief address, and further includes a circuit that transfers the relief address from the nonvolatile memory to the relief address register.

  As a result, the integration density of the SoC can be improved, and the number of peripheral parts and the mounting area can be reduced.

[15] <SoC with external nonvolatile memory>
Item 13 further includes a terminal for connecting a nonvolatile memory (9), and further includes a circuit for transferring the relief address from the nonvolatile memory to the relief address register.

  Thereby, the manufacturing cost can be reduced as compared with the SoC chip in Item 10.

[16] <Relief address transferred at power-on (DMAC)>
In Item 13, 14, or 15, further comprising a transfer circuit (10) for transferring the relief address from the nonvolatile memory to the relief address register when power is turned on.

  As a result, the SoC can autonomously start a memory defect repair operation.

[17] <Relief Address Conversion Circuit>
Item 10, Item 11, or Item 12, instead of the comparison circuit, the access address is input, the comparison result is output, and the access address is converted into an address of the storage circuit when the comparison result is coincident And an address conversion circuit (19) for outputting.

  As a result, it is not necessary to have the nonvolatile memory 5 or 9 connected inside or outside the SoC, and a defect relief operation can be performed without an operation such as transferring and setting a relief address.

[18] <ROM table>
In item 17, the address conversion circuit comprises a ROM (19).

  Thereby, it is not necessary to have the nonvolatile memory 5 or 9 connected inside or outside the SoC, and the manufacturing process can be simplified.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1] <SiP = Mem + SoC with Memory Defect Relief Function>
FIG. 1 is a block diagram of a SiP product according to a representative embodiment.

  In the SiP product 1, an SoC 3 equipped with a CPU 4 and a DRAM 2 are integrated. The CPU 4 is connected to the DRAM 2 via a DRAM controller 16 and a DRAM interface 17 mounted on the same SoC 3. The DRAM controller 16 receives an address 22 from the CPU 4 via the bus 8, and fetches data 23 from the bus 8 and outputs it to the DRAM 2 via the DRAM interface 17 when the access to the DRAM 2 is writing. When the access to the DRAM 2 is read, the data 31 is fetched from the DRAM 2 via the DRAM interface 17.

  In this embodiment, a repair block 11 is provided between the bus 8 and the DRAM controller 16 to repair a defect that has occurred in the DRAM 2. The CPU 4 may be various processors such as a microcontroller, and can access the external DRAM 2 by designating an address 30 and write or read data 31. DRAM 2 is another memory, for example, an SRAM or an electrically rewritable nonvolatile memory such as a flash memory, a ferroelectric memory, a phase change memory, or a non-writable nonvolatile memory such as a mask ROM. There may be.

  The configuration of the relief block 11 will be described. A relief address storage register 12 and a relief data storage register 14 are provided, and an address comparison conversion circuit 13 and a data selection circuit 15 are further provided. The relief address storage register 12 stores the relief address of the DRAM 2, that is, the address of the defective memory cell to be repaired. The address comparison / conversion circuit 13 compares the address value 22 to be accessed by the CPU 4 with the relief address 24 stored in the relief address storage register 12, and if they match, converts it to the address 25 of the relief data storage register 14. And a match flag 26 indicating that they match is set. Based on the converted address 25, the data value 23 to be accessed by the CPU 4 is written into the repair data storage register 14, or the data value 27 stored in the repair data storage register 14 is output to the data selection circuit 15. Based on the match flag 26, the data selection circuit 15 selects either the data value 27 output from the relief data storage register 14 or the data value 28 read from the DRAM 2, and sends the selected data 29 to the bus 8. Output.

  The operation flow will be described. After completing the SiP product 1 on which the DRAM 2 and the SoC 3 are mounted, the DRAM 2 is tested to detect a relief address (address of a defective memory cell). A test may be performed by accessing the DRAM 2 from the CPU 4 without operating the relief block 11. A dedicated test circuit may be built in the SoC 3 or externally attached for testing. The detected relief address (address of the defective memory cell) is stored in the relief address storage register 12.

  A data write operation to the DRAM 2 will be described. The CPU 4 outputs an address 20 and data 21 to the bus 8 and a bus command (not shown) indicating a data write operation, and requests data write to the DRAM 2. In the relief block 11, the address 22 at this time is fetched from the bus 8, and the address to which the CPU 4 intends to write data using the address comparison / conversion circuit 13 is the relief address stored in the relief address register 12. Compare for a match. If they match, the address is converted to the address 25 in the relief data storage register 14 corresponding to the relief address, and the data to be written into the DRAM 2 is written into the relief data storage register 14. If there is no particular problem in writing data to the defective address in maintaining the reliability of the DRAM 2, the write operation to the DRAM 2 may be executed as it is. On the other hand, the write operation to the DRAM 2 may be omitted.

  A data read operation from the DRAM 2 will be described. The CPU 4 outputs a bus command (not shown) indicating the address 20 and data read operation to the bus 8 and requests a data read to the DRAM 2. In the relief block 11, the address 22 at this time is fetched from the bus 8, and the address from which the CPU 4 is reading data using the address comparison / conversion circuit 13 is the relief address stored in the relief address register 12. Compare whether or not. If they do not match, the data selection circuit 15 outputs the value read from the DRAM 2 to the CPU 4 via the bus 8. On the other hand, if they match, the address 25 in the repair data storage register 14 corresponding to the repair address is converted and output, and the match flag 26 is set and output. The data 27 stored in the converted address 25 is read out from the relief data storage register 14, and the CPU 4 is connected via the bus 8 instead of the data 28 to be read out from the DRAM 2 by the data selection circuit 15 based on the match flag 26. Output to.

  Accordingly, defect repair can be performed for a defect of a memory chip that occurs at the manufacturing stage of the SiP product or thereafter, without using a defect repair method for a memory chip mounted on the SiP product. Further, even after shipment, the DRAM 2 is tested at any time to detect the address of the defective memory cell, and when a new defective memory cell is detected, the address is added to the relief address storage register 12 and registered. By doing so, it is possible to perform defect relief even for a defective memory chip that occurs after shipment.

  The operation when the DRAM 2 is burst read will be described in detail. FIG. 6 is a timing chart of defect relief in burst read. At time t1, the CPU 4 issues a burst read command for the DRAM 2 to the DRAM controller 16 via the bus 8. The DRAM controller 16 issues an address to the DRAM 2 from the time t2 via the DRAM interface 17, and sequentially reads data D0, D1, X, D3 stored at the address specified by the burst read instruction. Here, the address may be composed of a row address and a column address. If the data X is not defective, the data D2 is read. If there is a defect, an incorrect value X is read due to the defect, and the address A2 where the data D2 is to be stored is stored in the relief storage address register 12 in advance. In the following description, it is assumed that the data D2 is stored in advance in the repair data storage register 14. Data D0, D1, X, and D3 read from the DRAM 2 from time t4 to t8 are temporarily held in the DRAM controller 16.

  The CPU 4 issues a normal read instruction to the addresses A0, A1, A2, A3 storing the data D0, D1, D2, D3 to be burst read after a period corresponding to the number of cycles for burst reading the DRAM 2. Issue sequentially.

  At time t9, a read command specifying address A0 is issued. Since the address A0 is not a relief address, the coincidence flag 26 is not raised, and the data selection circuit 15 outputs the data D0 held in the DRAM controller 16 to the data bus 7 of the bus 8, so that the CPU 4 has the data of the address A0. Read D0. The relief block 11 analyzes the bus command, detects that a normal read command has been issued, and compares the value of the address bus 6 at that time with the relief address 24 stored in the relief address storage register 12. Next, at time t10, the CPU 4 reads the data D1 by a read command designating the address A1. Since the address A1 is not a relief address, the data D1 held in the DRAM controller 16 is read. At time t11, the CPU 4 issues a read command specifying the address A2. Since the address A2 is a value stored in the relief address register 12, the coincidence flag 26 is set. FIG. 6 shows a waveform when the match flag is designed with negative logic, and transitions to low at time t11. The address comparison / conversion circuit 13 outputs the coincidence flag 26 and also outputs the address 25 in the relief data storage register 14 where the data D2 corresponding to the address A2 is stored. The relief data storage register 14 reads the data D2 into the relief read data 27. The data selection circuit 15 selects the data on the rescue read data 27 side based on the match flag 26 and outputs it to the data bus 7 of the bus 8. Thereby, the defect data X read from the DRAM 2 can be replaced with normal data D2 and read by the CPU 4, and the defect is relieved. At the next time t12, a read command designating the normal address A3 is issued, so the match flag 26 returns to high, and the data selection circuit 15 reads the data D3 read from the DRAM 2 and held in the DRAM controller 16 Is output to the data bus 7 of the bus 8.

  As a result, even when defective data is included in some of the plurality of burst-read data, the defective data can be relieved. Here, a DRAM having a burst mode has been described as an example, but the same effect can be obtained even when another memory having a similar burst mode is connected.

  The operation when the DRAM 2 is a so-called wide I / O DRAM having a data width wider than that of the internal bus will be described in detail. Wide I / O DRAM is effective for eliminating a bottleneck between the CPU and DRAM, and usually has a data width that is an integral multiple of the CPU bus. FIG. 7 is a timing chart of defect relief when the DRAM 2 is a wide I / O DRAM. It is a timing chart based on the following example (assuming), and will be described along with it. However, numerical values and the like are merely examples and are not limited thereto. The data width of the data 31 of the DRAM 2 is 512 bits, which is 8 times the data width of the CPU bus 8 64 bits, and the eight data D00 to D07 corresponding to the addresses A00 to A07 are collectively designated as data W0. It can be written and read. Assume that the memory cell of the DRAM 2 that stores the data D21 corresponding to the address A21 is defective, and the 512-bit data W2 includes a defect at the position where the data D21 is stored. The data W2 is 512 bits, and is associated with addresses A20, A21, A22, and A27 every 64 bits in order from the beginning. Since it is assumed that the memory cell of the DRAM 2 to store the data D21 corresponding to A21 is defective, a defective bit is included between the 65th bit and the 128th bit from the top.

  Since the memory cell of the DRAM 2 in which the data D21 corresponding to the address A21 is to be stored is defective, the address A21 is stored in advance in the relief address storage register 12, and the address is changed by the write operation before the read operation shown in FIG. Data D21 corresponding to A21 is stored in the relief data storage register 14. At time t1, the CPU 4 issues a read command for the wide I / O DRAM 2. In response to this, the DRAM controller 16 outputs an address 30 to the DRAM 2 via the DRAM interface 17, and sequentially fetches 512-bit data W 0, W 1, W 2 to the DRAM controller 16 via the DRAM interface 17. At this time, each of the 512-bit data W0, W1, and W2 is temporarily stored in the DRAM controller 16 for every 64 bits that is the data width of the CPU bus 8. 512-bit data W0 is stored as 8 64-bit data D00 to D07, data W1 is stored as data D10 to D17, and data W2 is stored as data D20, X, D22 to D27. As described above, since the defective bit is included between the 65th bit and the 128th bit from the head, the next 64 bits of the data D20 include the defective bit and are stored as the data X.

  The CPU 4 sequentially issues a read command designating the addresses A00 to A07, A10 to A17, and A20 to A27 from time t4 after a period corresponding to the number of cycles for reading the DRAM 2. In response to this, the DRAM controller sequentially outputs data D00 to D07, D10 to D17, D20, X, D22 to D27 as DRAM read data 28 to the data selection circuit 15. Here, X is defect data for a defect. The addresses A00 to A07, A10 to A17, and A20 to A27 issued by the CPU 4 are sequentially compared with the contents of the relief address storage register 12 by the address comparison / conversion circuit 13, and when they match, the match flag 26 is set (because it is negative logic). Transition to low). Since the address A21 is stored in the relief address storage register 12, the coincidence flag 26 becomes low at time t21 when the address 22 input from the address bus 6 becomes A21. At this time, the address 25 in which the data D21 corresponding to the address A21 in the relief data storage register 14 is stored is output. The relief data storage register 14 reads the data D21 into the relief read data 27. The data selection circuit 15 selects the data on the rescue read data 27 side based on the match flag 26 and outputs it to the data bus 7 of the bus 8. Thereby, the defect data X read from the DRAM 2 can be replaced with normal data D21 and read by the CPU 4, and the defect is relieved. At the next time t22, since a read command designating a normal address A22 is issued, the match flag 26 returns to high, and the data selection circuit 15 reads the data D22 read from the DRAM 2 and held in the DRAM controller 16. Is output to the data bus 7 of the bus 8.

  Thus, even when defective data is included in a part of multi-bit width data read in batch by the wide I / O DRAM, a part of the defective data can be relieved. Here, a DRAM having a wide I / O has been described as an example, but the same effect can be achieved even when another memory having a similar wide I / O is connected.

[Embodiment 2] <SiP = Mem + SoC with flash>
FIG. 2 is a block diagram of the SiP product according to the second embodiment, and FIG. 3 is a detailed block diagram of the address comparison / conversion circuit according to the second embodiment.

  Compared to the SiP product 1 (FIG. 1) according to the first embodiment, in the SoC chip 3, the bus 8 is hierarchized into a CPU bus 8_1 and an internal bus 8_2, and a nonvolatile memory 5 and a direct memory access controller (DMAC) ) 10 is connected to the CPU bus 8_1 and is integrated on the same chip as the CPU 4. The CPU bus 8_1 is a bus that is faster than the internal bus 8_2 and transfers programs and data related to processing to be executed at high speed. The nonvolatile memory 5 stores a program and data for the CPU 4. The DMAC 10 is a functional block that transfers data between memories based on parameters set in advance by the CPU 4. By mounting the DMAC 10, the DMAC 10 takes the bus right and becomes a bus master during a period when the processing of the CPU 4 does not use the bus 8 (bus cycle), and can autonomously transfer data. As a result, data can be transferred in a so-called background without imposing a burden on the processing of the CPU 4. The CPU 4 itself can directly read data from the transfer source memory and write it to the transfer destination memory without mounting the DMAC 10.

  In the nonvolatile memory 5, in addition to the program and data of the CPU 4, a relief address can be stored. In a reset sequence including a power-on reset immediately after power-on, the CPU 4 executes an initialization routine for setting initial parameters for various functional blocks. At this time, the relief address is also read from the nonvolatile memory 5 and transferred to the relief address storage register 12. As a result, it is possible to increase the reading speed of the relief address input to the address comparator 13 as compared to reading it directly from the nonvolatile memory 5 every time the DRAM 2 is accessed. The transfer of the relief address from the nonvolatile memory 5 to the relief address storage register 12 may be performed using the DMAC 10.

  By integrating the nonvolatile memory 5 storing the relief address on the same SoC chip 3 as the CPU 4 and the relief block 11, the number of components integrated in the SiP product can be reduced and the mounting area can be reduced. Furthermore, by transferring the relief address from the nonvolatile memory 5 to the relief address storage register 12 in the initialization routine, the SiP product according to the present embodiment can autonomously start the memory defect relief operation.

  By using the nonvolatile memory 5 for storing the program and data of the CPU 4 to store the relief address, the transfer of the relief address can be positioned as a part of the initialization routine of the entire SoC chip. Is consistent with On the other hand, if there is another non-volatile memory for storing the initialization parameters collectively and only storing the initialization parameters such as the relief address, it is accessed only by the initialization routine, so the internal bus, not the CPU bus 8_1. You may connect to 8_2.

  FIG. 3 is a detailed block diagram of the relief block 11 according to the second embodiment. The present invention can also be applied to relief blocks in other embodiments such as the first, third, and fourth embodiments.

  The relief address storage register 12 includes a storage element capable of storing a plurality of relief addresses. The relief address is sequentially transferred to the relief address storage register 12 by designating the address 32 and the data 33 from the CPU bus 8_1. And stored. The plurality of relief addresses 24 are read out in parallel and input to the plurality of comparators 51 and compared with the address 22 that the CPU 4 is trying to access. If a result indicating a match is output as any one of the comparison results 54, the NOR gate 52 generates and outputs a negative logic match flag 26, and the address conversion circuit 53 outputs the corresponding relief data. It is converted into the address 25 of the storage register 14 and output. The relief data storage register 14 can be constituted by a two-port memory, for example, as shown in FIG. Based on the address 25, in the case of a write operation, the data value 23 is fetched and stored in the relief data storage register 14. In the case of a read operation, if the address 22 accessed by the CPU 4 matches one of the relief addresses stored in the relief address storage register 12, the match flag 26 is set, so that the data selection circuit 15 is read from the DRAM 2. Instead of the DRAM read data 28, the repair read data 27 read from the repair data storage register 14 is selected as data 29 and output to the internal bus 8_2. Although FIG. 3 shows a negative logic circuit (outputs low when the comparison result is “match”) as an example of a circuit that outputs the match flag 26, it may be positive logic.

  In the write operation, an operation of writing the data 23 into the DRAM 2 may be performed regardless of whether the address 22 matches one of the relief addresses. If memory cells in only some columns of the same row are defective, the defective memory cells are also subjected to the same burst write sequence as accesses to normal memory cells in other columns. Write all at once. Since it is not necessary to break the burst access sequence, the number of access cycles from the CPU 4 to the DRAM 2 is maintained. On the other hand, writing to normal columns other than some defective memory cells can be broken down into writing for each byte so that writing to defective memory cells does not occur. This is effective when the write operation to the defective memory cell may cause a through current to flow through the DRAM 2 and should be prohibited.

  In the read operation, when the coincidence flag 26 is set, the data stored in the repair data storage register 14 is read instead of the DRAM 2.

  In this embodiment, the storage area of the relief address storage register 12 and the number of the address comparators 51 corresponding to the assumed number of relief addresses are provided, and the address comparison operation can be executed in parallel. However, in general, access to the external DRAM 2 often requires a plurality of cycles. Therefore, sequential address comparison can be employed within a range that can be realized with the same number of cycles. Thereby, the circuit scale of the comparison circuit can be suppressed.

[Embodiment 3] <SiP = Mem + SoC + flash>
FIG. 4 is a block diagram of the SiP product according to the third embodiment.

  The difference between the SiP product according to the second embodiment and the first embodiment shown in FIG. 2 is that a non-volatile memory chip 9 such as a flash memory different from the SoC chip is used as a non-volatile memory for storing a relief address in the same package. It is a point accumulated in the inside. Connection is made via the external memory interface 18. Even if it is externally attached to another chip, the relief address stored in the flash memory 9 may be read by the initialization routine and transferred to the relief address storage register 12 as in the case of on-chip.

  When the flash memory 9 stores the program and data of the CPU 4, it is preferable to connect to the CPU bus 8_1 as shown in FIG. On the other hand, if it is not necessary to read out the program or data of the CPU 4 or the CPU 4 has a cache memory even if it is stored, it is connected to the internal bus 8_2 like the DRAM 2. May be. Further, the interface circuits 16, 17 and 18 of the DRAM 2 and the flash memory 9 may be shared, and the terminals may be shared. Thereby, the number of terminals of the SoC chip 3 can be suppressed to substantially the same number as the SoC chip 3 of the second embodiment in which the flash memory is formed on-chip.

  When the nonvolatile memory such as the flash memory 5 is formed on the SoC 3 like the SiP product 1 according to the second embodiment, the number of parts required for the SiP product 1 is reduced. On the other hand, by making the non-volatile memory 9 such as flash memory a chip different from the SoC 3, the SoC chip 3 is a manufacturing process of only a pure CMOS logic circuit, for example, and the flash memory 9 is a manufacturing process dedicated thereto. Each can be manufactured. Since each semiconductor manufacturing process is simplified and the yield is improved, each manufacturing cost can be kept low.

[Embodiment 4] <SiP = Mem + SoC with fuse>
FIG. 5 is a block diagram of the SiP product according to the fourth embodiment.

  Instead of the relief address storage register 12 and the address comparison / conversion circuit 13 in the relief block 11 described in the first embodiment (FIG. 1), a fuse 19 for performing address conversion is provided. The address 22 may be input, and the address 25 and the match flag 26 converted based on the address 22 may be output. This can be realized by comparing the address 22 previously associated with the address 25 with the fuse information. For example, by using an element that can be rewritten only once, such as a one-time ROM or an electric fuse, it can be inexpensive and highly integrated. You may comprise as a lookup table by ROM. Furthermore, for example, by using an electrically rewritable ROM by accessing from the bus 8, defective memory cells detected after product shipment can be remedied by adding the addresses to the ROM.

  This eliminates the need to have the nonvolatile memory 5 or 9 connected inside or outside the SoC, simplifies the manufacturing process, and enables defect relief operation without the operation of transferring and setting the relief address. It can be carried out.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, a technique for relieving access to a defective memory cell in the DRAM 2 among accesses from the CPU 4 to the DRAM 2 has been described. However, any memory, and a circuit accessing the memory may be a circuit other than the CPU, such as a DMAC. What is necessary is just to be what is called a bus master which accesses a memory not only by CPU but by specifying an address. Furthermore, even if the SoC does not have the common bus disclosed above, if it has the function to access the memory by specifying the address, it monitors that address and detects access to the defective memory cell. Alternatively, the memory area in the SoC may be accessed.

  In addition, a memory defect can be relieved according to the present embodiment, for example, without remedying a defect in the memory chip before the memory chip is mounted on the SiP.

1 SiP product 2 Memory chip (DRAM)
3 SoC chip 4 CPU
5 Nonvolatile Memory 6 Address Bus 7 Data Bus 8 Bus 8_1 CPU Bus 8_2 Internal Bus 9 Nonvolatile Memory Chip 10 Data Transfer Circuit (DMAC)
DESCRIPTION OF SYMBOLS 11 Relief block 12 Relief address storage register 13 Address comparison conversion circuit 14 Relief data storage register 15 Data selection circuit 16 DRAM controller 17 DRAM interface 18 External memory interface 19 ROM (address conversion)

Claims (18)

In a semiconductor device in which a memory chip and a logic chip are mounted in the same package,
The logic chip compares a relief address of a defective memory cell of the memory chip with an access address for accessing the memory chip, and outputs a match or mismatch result, a storage circuit, and the comparison circuit A semiconductor device comprising: a data selection circuit that switches the access target to the storage circuit when the results match. The memory chip according to claim 1, wherein the memory chip is a burst accessible memory.
The logic chip includes a memory interface circuit and a processor connected to each other via a bus,
The processor can issue a burst read command to the memory interface circuit via the bus, and the memory interface circuit reads a plurality of data from the memory chip in a burst mode based on the burst read command. The processor is capable of temporarily storing, and after the burst read command is issued, the processor outputs a read command that involves outputting addresses in the memory chip of some or all of the plurality of data to the bus. The memory interface circuit can output data corresponding to an address specified by the read command among the plurality of data to the data selection circuit;
The semiconductor device is configured such that the comparison circuit can compare the address in the read command with the relief address. In claim 1,
The logic chip includes a memory interface circuit and a processor connected to each other via a bus having a first data width,
The memory chip is connected to the memory interface circuit via an external data bus having a second data width wider than the first data width.
The processor can issue a wide IO read command to the memory interface circuit via the bus, and the memory interface circuit receives data of the second data width from the memory chip based on the wide IO read command. Can be temporarily stored and the processor outputs an address for reading the data having the first data width corresponding to a part or all of the data having the second data width to the bus. Can be output to the bus after issuing the wide IO read command, and the memory interface circuit corresponds to the address specified by the read command in the data of the second data width. Can be output to the data selection circuit. It is in,
The semiconductor device is configured such that the comparison circuit can compare the address in the read command with the relief address.   2. The semiconductor device according to claim 1, wherein the logic chip further includes a relief address register that holds the relief address and outputs a value held in the comparison circuit.   5. The semiconductor device according to claim 4, wherein the logic chip further includes a nonvolatile memory that can store the relief address, and includes a circuit that transfers the relief address from the nonvolatile memory to the relief address register.   5. The semiconductor device according to claim 4, further comprising a nonvolatile memory mounted in the same package, wherein the logic chip includes a circuit that transfers the relief address from the nonvolatile memory to the relief address register.   5. The semiconductor device according to claim 4, wherein the logic chip further includes a transfer circuit that transfers the relief address from the nonvolatile memory to the relief address register when power is turned on.   2. The logic chip according to claim 1, wherein the logic chip receives the access address instead of the comparison circuit, outputs the comparison result, and converts the access address to an address of the storage circuit when the comparison result is coincident. A semiconductor device including an address conversion circuit that outputs the output of   9. The semiconductor device according to claim 8, wherein the address conversion circuit includes a ROM.   A semiconductor integrated circuit device having a terminal for accessing a memory chip, wherein a repair address of a defective memory cell of the memory chip and an access address for accessing the memory chip are compared, and a comparison result of matching or mismatching is output A semiconductor integrated circuit device comprising: a comparison circuit that performs a storage circuit; and a data selection circuit that switches the access target to the storage circuit when the comparison results match. The memory chip according to claim 10, wherein the memory chip is a burst accessible memory.
The semiconductor integrated circuit device includes a memory interface circuit and a processor connected to each other via a bus,
The processor can issue a burst read command to the memory interface circuit via the bus, and the memory interface circuit reads a plurality of data from the memory chip in a burst mode based on the burst read command. The processor is capable of temporarily storing, and after the burst read command is issued, the processor outputs a read command that involves outputting addresses in the memory chip of some or all of the plurality of data to the bus. The memory interface circuit can output data corresponding to an address specified by the read command among the plurality of data to the data selection circuit;
The semiconductor integrated circuit device, wherein the comparison circuit is configured to be able to compare the address in the read command with the relief address. In claim 10,
The semiconductor integrated circuit device includes a memory interface circuit and a processor connected to each other via a bus having a first data width,
The memory chip can be connected to the memory interface circuit via an external data bus having a second data width wider than the first data width.
The processor can issue a wide IO read command to the memory interface circuit via the bus, and the memory interface circuit receives data of the second data width from the memory chip based on the wide IO read command. Can be temporarily stored and the processor outputs an address for reading the data having the first data width corresponding to a part or all of the data having the second data width to the bus. Can be output to the bus after issuing the wide IO read command, and the memory interface circuit corresponds to the address specified by the read command in the data of the second data width. Can be output to the data selection circuit. It is in,
The semiconductor integrated circuit device, wherein the comparison circuit is configured to be able to compare the address in the read command with the relief address.   11. The semiconductor integrated circuit device according to claim 10, further comprising a relief address register that holds the relief address and outputs a value held in the comparison circuit.   14. The semiconductor integrated circuit device according to claim 13, further comprising a nonvolatile memory capable of storing the relief address, and further comprising a circuit that transfers the relief address from the nonvolatile memory to the relief address register.   14. The semiconductor integrated circuit device according to claim 13, further comprising a terminal for connecting a nonvolatile memory, and a circuit for transferring the relief address from the nonvolatile memory to the relief address register.   14. The semiconductor integrated circuit device according to claim 13, further comprising a transfer circuit that transfers the relief address from the nonvolatile memory to the relief address register when power is turned on.   14. The address according to claim 13, wherein the access address is input instead of the comparison circuit, the comparison result is output, and the access address is converted into an address of the storage circuit when the comparison result is coincident. A semiconductor integrated circuit device comprising a conversion circuit.   18. The semiconductor integrated circuit device according to claim 17, wherein the address conversion circuit is configured by a ROM.

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