JP2014027465A - Flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the rate of reading out data from a balloon latch in repowering a master latch and a slave latch.SOLUTION: A flip-flop circuit includes: a master latch ML for capturing data DA on the basis of a clock signal CLK; a slave latch SL for holding the data DA captured by the master latch ML on the basis of the clock signal CLK; a balloon latch BL for holding the data DA captured by the master latch ML on the basis of a save signal SAVE; and a bypass circuit BP1 for outputting the data DA captured by the master latch ML as bypassing the slave latch SL and the balloon latch BL. The master latch ML and the slave latch SL are driven by a different power supply from the balloon latch BL and the bypass circuit BP1.

Description

  Embodiments described herein relate generally to a flip-flop circuit.

  In the flip-flop circuit, there is a method of reducing power consumption by providing a balloon latch in addition to the master latch and the slave latch, and holding the data in the balloon latch when the power source of the master latch and the slave latch is turned off.

JP 2007-110728 A

  An object of one embodiment of the present invention is to provide a flip-flop circuit capable of increasing the data reading speed from the balloon latch when the master latch and the slave latch are powered back.

  According to one embodiment of the present invention, a master latch, a slave latch, a balloon latch, and a bypass circuit are provided. The master latch captures data based on the clock signal. The slave latch holds the data fetched into the master latch based on the clock signal. The balloon latch holds the data fetched into the master latch based on the save signal. The bypass circuit bypasses the slave latch and the balloon latch and outputs the data fetched by the master latch. The master latch and the slave latch are driven by a separate power source from the balloon latch and the bypass circuit.

FIG. 1 is a circuit diagram showing a schematic configuration of a flip-flop circuit according to the first embodiment. FIG. 2 is a timing chart showing voltage waveforms at various parts during operation of the master latch and slave latch of FIG. FIG. 3 is a timing chart showing voltage waveforms at various parts during the operation of the balloon latch of FIG. FIG. 4 is a circuit diagram showing the flow of data from the balloon latch when the master latch and slave latch of FIG. 1 return to power. FIG. 5 is a circuit diagram showing a schematic configuration of a flip-flop circuit according to the second embodiment.

  Hereinafter, a flip-flop circuit according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a circuit diagram showing a schematic configuration of a flip-flop circuit according to the first embodiment.
In FIG. 1, the flip-flop circuit is provided with a master latch ML, a slave latch SL, a balloon latch BL, and a bypass circuit BP1. The master latch ML can take in the data DA based on the clock signal CLK. The slave latch SL can hold the data fetched into the master latch ML based on the clock signal CLK. The balloon latch BL can hold the data fetched into the master latch ML based on the save signal SAVE. The bypass circuit BP1 can bypass the slave latch SL and the balloon latch BL and output the data fetched by the master latch ML.

  Here, the master latch ML is provided with inverters V1 and V2, a clocked inverter V3, and a transfer gate T1. The output terminal of the inverter V1 is connected to the input terminal of the inverter V2 via the transfer gate T1. The output terminal of the inverter V2 is connected to the input terminal of the clocked inverter V3, and the output terminal of the clocked inverter V3 is connected to the input terminal of the inverter V2.

  In the slave latch SL, inverters V4 and V6, a clocked inverter V5, and a transfer gate T4 are provided. The output terminal of the inverter V4 is connected to the input terminal of the clocked inverter V5, and the output terminal of the clocked inverter V5 is connected to the input terminal of the inverter V4 via the transfer gate T4. The output terminal of the inverter V4 is connected to the input terminal of the inverter V6.

  The balloon latch BL is provided with an inverter V7, a clocked inverter V8, and a transfer gate T3. The output terminal of the transfer gate T3 is connected to the input terminal of the inverter V7. The output terminal of the inverter V7 is connected to the input terminal of the clocked inverter V8, and the output terminal of the clocked inverter V8 is connected to the input terminal of the inverter V7.

  The bypass circuit BP1 is provided with a clocked inverter V9. The output terminal of the clocked inverter V9 is connected to the input terminal of the inverter V11. The input terminal of the clocked inverter V9 is connected to the output terminal of the inverter V2.

  The output terminal of the inverter V2 is connected to the input terminal of the inverter V4, the input terminal of the transfer gate T3, and the input terminal of the transfer gate T4 via the transfer gate T2. The output terminal of the inverter V6 is connected to the input terminal of the inverter V11 via the clocked inverter V10.

  The flip-flop circuit is provided with inverters V12 to V16. The inverters V12 and V13 are connected in series with each other, and the inverters V14 and V15 are connected in series with each other. A clock signal CLK is input to the inverter V12, a clock inverted signal CN is output from the inverter V12, and a clock non-inverted signal CP is output from the inverter V13. A transfer signal RSTR is input to the inverter V14, a transfer inverted signal STRN is output from the inverter V14, and a transfer non-inverted signal STR is output from the inverter V15. A save signal SAVE is input to the inverter V16, and a save inversion signal SAVE is output from the inverter V16.

  The clock inversion signal CN is input to the clock terminals of the clocked inverters V3 and V9 and the clock terminal of the transfer gate T2. The clock non-inverted signal CP is input to the clock terminals of the clocked inverters V5 and V10 and the clock terminal of the transfer gate T1. The transfer inversion signal STRN is input to the clock terminal of the transfer gate T3. The transfer non-inverted signal STR is input to the clock terminal of the transfer gate T4. The save inversion signal SAVEN is input to the clock terminal of the clocked inverter V8.

  Here, the master latch ML, the slave latch SL, the clocked inverter V10, and the inverters V12 and V13 are formed in the well WL1. The balloon latch BL, the bypass circuit BP1, the transfer gate T2, and the inverters V11 and V14 to V16 are formed in the well WL2. The wells WL1 and WL2 can be provided on the same semiconductor chip. Master latch ML, slave latch SL, clocked inverter V10 and inverters V12, V13 are driven by power supply voltage VD1, and balloon latch BL, bypass circuit BP1, transfer gate T2, and inverters V11, V14-V16 are supplied with power supply voltage VD2. It is driven by. The power supply voltages VD1 and VD2 can be supplied from different power sources.

  Then, the clock signal CLK is inverted by the inverter V12 to generate the clock inverted signal CN, which is input to the clocked inverters V3 and V9 and the transfer gate T2. Further, the clock inversion signal CN is inverted by the inverter V13 to generate the clock non-inversion signal CP, which is input to the clocked inverters V5 and V10 and the transfer gate T1.

  Further, the transfer signal RSTR is inverted by the inverter V14 to generate the transfer inverted signal STRN and input to the transfer gate T3. Further, the transfer inversion signal STRN is inverted by the inverter V15, whereby the transfer non-inversion signal STR is generated and input to the transfer gate T4. Further, the save inversion signal SAVE is generated by inverting the save signal SAVE by the inverter V16, and is input to the clocked inverter V8.

  Data DA is input to transfer gate T1 via inverter V1. When the clock signal CLK falls, the data DA is input to the inverter V2 via the transfer gate T1, and is input to the transfer gate T2 and the clocked inverters V3 and V9 via the inverter V2.

  Next, when the clock signal CLK rises, the data DA is returned to the input terminal of the inverter V2 via the clocked inverter V3 and held in the master latch ML. Data DA is output as data Z through clocked inverter V9 and inverter V11. Further, the data DA is input to the inverter V4 and the transfer gates T3 and T4 via the transfer gate T2. At this time, the data DA input to the inverter V4 is input to the clocked inverter V5 and also to the clocked inverter V10 via the inverter V6.

  Here, when the data DA is held in the master latch ML, the data DA is output as the data Z through the clocked inverter V9 and the inverter V11, thereby eliminating the need to pass the node IQ2. For this reason, since the balloon latch BL is connected to the node IQ2 in addition to the slave latch SL, even when the load capacity of the node IQ2 is large, it is possible to suppress the slow rise of the voltage accompanying the transition of the data DA. Thus, the speed of the flip-flop circuit can be increased.

  Next, when the clock signal CLK falls and the transfer signal RSTR falls, the data DA is returned to the input terminal of the inverter V4 via the clocked inverter V5 and the transfer gate T4, and held in the slave latch SL. Data Z is output via clocked inverter V10 and inverter V11.

  On the other hand, when the save signal SAVE rises and the transfer signal RSTR rises, the data DA is input to the inverter V7 via the transfer gate T3, and is returned to the input terminal of the inverter V7 via the clocked inverter V8. Held in BL. At this time, even when the power supply voltage VD1 is cut off in the power saving mode, the power supply voltage VD2 can be supplied to the balloon latch BL, and the data DA held in the balloon latch BL can be prevented from being destroyed. Can do.

  Next, when the clock signal CLK rises and the transfer signal RSTR rises when the power is restored, the data DA held in the balloon latch BL is input to the inverter V11 via the transfer gate T2 and the clocked inverter V9. Output as Z. Here, when the power is restored, the data DA held in the balloon latch BL is output via the transfer gate T2 and the clocked inverter V9, so that it is not necessary to output the data DA via the slave latch SL. It becomes possible to increase the data reading speed from the.

FIG. 2 is a timing chart showing voltage waveforms at various parts during operation of the master latch and slave latch of FIG.
In FIG. 2, when the potential of the data DA rises before the clock signal CLK rises, the potential of the data DA is sequentially transmitted through the inverter V1, the transfer gate T1, and the inverter V2, and the potential of the node IQ1 rises.

  Next, when the clock signal CLK rises, the potential of the data DA is transmitted via the transfer gate T2, and the potential of the node IQ2 rises. The potential of the node IQ2 is transmitted through the inverters V2 and V3, and the output Q of the clocked inverter V3 rises. At this time, since the balloon latch BL is connected to the node IQ2 in addition to the slave latch SL, the load capacity of the node IQ2 increases and the rise of the output Q of the inverter V3 is delayed.

  When the clock signal CLK rises, the potential of the data DA is transmitted via the clocked inverter V9 and the inverter V11 and output as data Z. When the potential of the data DA is transmitted through the clocked inverter V9 and the inverter V11, the node IQ2 is bypassed, so that it is not affected by the load capacity of the node IQ2, and the data is compared with the rise of the output Q of the inverter V3. The rise of the potential of Z can be made faster.

FIG. 3 is a timing chart showing voltage waveforms at various parts during the operation of the balloon latch of FIG.
In FIG. 3, when the save signal SAVE rises and the transfer signal RSTR rises, the data DA is input to the inverter V7 via the transfer gate T3, and the potential of the node IQ3 rises, whereby the data DA is taken into the balloon latch BL. .

  Then, when the potential of the node IQ3 is returned to the input terminal of the inverter V7 via the clocked inverter V8, the transfer signal RSTR falls, whereby the data DA is held in the balloon latch BL. At this time, even when the power supply voltage VD1 is cut off in the power saving mode, the power supply voltage VD2 is supplied to the balloon latch BL, and the data DA is held in the balloon latch BL.

  Next, when the clock signal CLK rises and the transfer signal RSTR rises when the power is restored, the data DA held in the balloon latch BL is input to the inverter V11 via the transfer gate T2 and the clocked inverter V9. Output as Z.

FIG. 4 is a circuit diagram showing the flow of data from the balloon latch when the master latch and slave latch of FIG. 1 return to power.
In FIG. 4, by making the balloon latch BL and bypass circuit BP1 separate from the master latch ML and slave latch SL, the data DA held in the balloon latch BL is changed from node IQ3 → transfer gate T3 → transfer gate T2 → clock. It is possible to output via the route of the inverter V9 → the inverter V11. For this reason, it is not necessary to output the data DA held in the balloon latch BL via the slave latch SL when the power is restored, and the data reading speed from the balloon latch BL can be increased.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a schematic configuration of a flip-flop circuit according to the second embodiment.
5, in this flip-flop circuit, a bypass circuit BP2 and a transfer gate T6 are provided instead of the bypass circuit BP1, the clocked inverter V10, and the inverter V11 of the flip-flop circuit of FIG. The bypass circuit BP2 is provided with a transfer gate T5.

  The output terminals of the transfer gates T5 and T6 are connected to each other. The input terminal of the transfer gate T5 is connected to the output terminal of the inverter V2. The input terminal of the transfer gate T6 is connected to the output terminal of the inverter V6. A clock inversion signal CN is input to the clock terminal of the transfer gate T5, and a clock non-inversion signal CP is input to the clock terminal of the transfer gate T6.

  Here, the master latch ML, the slave latch SL, the transfer gate T6, and the inverters V12 and V13 are formed in the well WL1. The balloon latch BL, the bypass circuit BP2, the transfer gate T2, and the inverters V14 to V16 are formed in the well WL2. Master latch ML, slave latch SL, transfer gate T6 and inverters V12, V13 are driven by power supply voltage VD1, and balloon latch BL, bypass circuit BP2, transfer gate T2, and inverters V14-V16 are driven by power supply voltage VD2. Is done.

  Then, the clock signal CLK is inverted by the inverter V12 to generate the clock inverted signal CN, which is input to the clocked inverter V3 and the transfer gates T2 and T5. Further, the clock inversion signal CN is inverted by the inverter V13 to generate the clock non-inversion signal CP, which is input to the clocked inverter V5 and the transfer gates T1 and T6.

  Further, the transfer signal RSTR is inverted by the inverter V14 to generate the transfer inverted signal STRN and input to the transfer gate T3. Further, the transfer inversion signal STRN is inverted by the inverter V15, whereby the transfer non-inversion signal STR is generated and input to the transfer gate T4. Further, the save inversion signal SAVE is generated by inverting the save signal SAVE by the inverter V16, and is input to the clocked inverter V8.

  Data DA is input to transfer gate T1 via inverter V1. When the clock signal CLK falls, the data DA is input to the inverter V2 via the transfer gate T1, and is input to the transfer gates T2 and T5 and the clocked inverter V3 via the inverter V2.

  Next, when the clock signal CLK rises, the data DA is returned to the input terminal of the inverter V2 via the clocked inverter V3 and held in the master latch ML. Data DA is output as data Z through transfer gate T5. Further, the data DA is input to the inverter V4 and the transfer gates T3 and T4 via the transfer gate T2. At this time, the data DA input to the inverter V4 is input to the clocked inverter V5 and to the transfer gate T6 via the inverter V6.

  Here, when the data DA is held in the master latch ML, the data DA is output as the data Z through the transfer gate T5, so that it is not necessary to pass through the node IQ2. For this reason, since the balloon latch BL is connected to the node IQ2 in addition to the slave latch SL, even when the load capacity of the node IQ2 is large, it is possible to suppress the slow rise of the voltage accompanying the transition of the data DA. Thus, the speed of the flip-flop circuit can be increased.

  Next, when the clock signal CLK falls and the transfer signal RSTR falls, the data DA is returned to the input terminal of the inverter V4 via the clocked inverter V5 and the transfer gate T4, and held in the slave latch SL. Data Z is output via the transfer gate T6.

  On the other hand, when the save signal SAVE rises and the transfer signal RSTR rises, the data DA is input to the inverter V7 via the transfer gate T3, and is returned to the input terminal of the inverter V7 via the clocked inverter V8. Held in BL. At this time, even when the power supply voltage VD1 is cut off in the power saving mode, the power supply voltage VD2 can be supplied to the balloon latch BL, and the data DA held in the balloon latch BL can be prevented from being destroyed. Can do.

  Next, at the time of power recovery, when the clock signal CLK rises and the transfer signal RSTR rises, the data DA held in the balloon latch BL is output as data Z through the transfer gates T2 and T5. Here, when the power is restored, the data DA held in the balloon latch BL is output via the transfer gates T2 and T5, so that it is not necessary to output the data DA via the slave latch SL. It is possible to increase the reading speed.

  Further, by using transfer gates T5 and T6 instead of clocked inverters V9 and V10 in FIG. 1, the number of elements can be reduced, and the circuit scale can be reduced.

  In the above-described embodiment, the positive edge shift type in which data transitions at the rising edge of the clock pulse is taken as an example. However, it is applied to the negative edge shift type in which data transitions at the falling edge of the clock pulse. Also good. Although the delay type retention flip-flop is taken as an example of the flip-flop configuration, the flip-flop may be applied to a flip-flop having a test enable terminal, a clear terminal, a scan terminal, or the like.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  ML master latch, SL slave latch, BL balloon latch, BP1, BP2 bypass circuit, WL1, WL2 well, V1, V2, V4, V6, V7, V11 to V16 inverter, V3, V5, V8 to V10 clocked inverter, T1 ~ T6 Transfer Gate

Claims (6)

A master latch that captures data based on a clock signal;
A slave latch that holds data captured in the master latch based on the clock signal;
A balloon latch that holds data captured in the master latch based on a save signal;
A bypass circuit that bypasses the slave latch and the balloon latch and outputs the data captured in the master latch;
The master latch and the slave latch are formed in a first well;
The balloon latch and the bypass circuit are formed in a second well;
The master latch and the slave latch are driven by a separate power source from the balloon latch and the bypass circuit,
The data latched in the master latch while the power supply of the master latch and the slave latch is cut off is held in the balloon latch,
A flip-flop circuit wherein data held in the balloon latch is output via the bypass circuit when the master latch and the slave latch are powered back on. A master latch that captures data based on a clock signal;
A slave latch that holds data captured in the master latch based on the clock signal;
A balloon latch that holds data captured in the master latch based on a save signal;
A bypass circuit that bypasses the slave latch and the balloon latch and outputs the data captured in the master latch;
The flip-flop circuit, wherein the master latch and the slave latch are driven by a separate power source from the balloon latch and the bypass circuit. The master latch and the slave latch are formed in a first well;
The flip-flop circuit according to claim 2, wherein the balloon latch and the bypass circuit are formed in a second well. The data latched in the master latch while the power supply of the master latch and the slave latch is cut off is held in the balloon latch,
3. The flip-flop circuit according to claim 2, wherein the data held in the balloon latch is output via the bypass circuit when the power supply of the master latch and the slave latch is restored.   5. The flip-flop circuit according to claim 1, wherein the bypass circuit is a clocked inverter that operates based on the clock signal. 6.   5. The flip-flop circuit according to claim 1, wherein the bypass circuit is a transfer gate that operates based on the clock signal. 6.

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