JP2014022423A - Method and device for extracting parasitic resistance in field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of extracting parasitic resistance in a field effect transistor.SOLUTION: A parasitic resistance extraction device comprises: an S parameter measurement unit 100 which, while changing a gate-source voltage Vunder drain-source voltage V=0 conditions, measures the S parameter of a HEMT or MOSFET which is the field effect transistor of concern; an impedance matrix conversion unit 101 for converting the S parameter into an impedance matrix [Z] to find the real part of impedance, Re{Z}; and an arithmetic unit 102 which, when gate resistance, source resistance, and fitting parameters are defined as R, R, and G, V respectively, determines the gate resistance R, the source resistance R, and the fitting parameters G, V by a least square method so that Re{Z} obtained from a prescribed relational expression and Re{Z} found by the impedance matrix conversion unit 101 will match.

Description

  The present invention relates to a technique for obtaining device parameters of a field effect transistor, and more particularly to a parasitic resistance extraction method and apparatus for extracting a parasitic resistance of a field effect transistor.

  Various methods have been proposed for extracting device parameters of field effect transistors. The discussion focuses on parasitic resistance extraction and describes conventional technology. The cold FET method is widely used for parasitic resistance extraction of MESFET (Metal-Semiconductor Field Effect Transistor) and HEMT (High Electron Mobility Transistor), and is considered to be the most excellent method (Non-Patent Document 1, Non-Patent Document 1). Reference 2).

FIG. 5 is a diagram showing an equivalent circuit of the field effect transistor. Here, the case where the gate-source voltage V _gs = 0 V and the drain-source voltage V _ds = 0 V is shown. In FIG. 5, 1 is a gate terminal, 2 is a drain terminal, 3 is a source terminal, 15 is an intrinsic region, R _g is a gate resistance, R _d is a drain resistance, R _s is a source resistance, R _c1 is a channel resistance, L _g Is a gate inductance, L _d is a drain inductance, L _s is a source inductance, C _gs is a gate capacitance, and I _g is a gate current.

The cold FET method is a method of extracting device parameters by limiting the drain-source voltage V _ds to zero or a very small voltage and greatly changing the gate-source voltage V _gs . In the cold FET method, the measured S parameter is converted into an impedance matrix [Z] and used for analysis. The conversion to the impedance matrix [Z] is disclosed in Non-Patent Document 3, for example.

In the cold FET method, since the drain-source voltage V _ds is zero or extremely small, the measurement is performed in a so-called resistance operation region in which the transistor does not have an amplifying action. Therefore, it can be replaced with a simpler equivalent circuit than a transistor in a normal operation state, and device parameters can be easily extracted. An impedance matrix [Z] is shown when the field effect transistor is grounded to the source, the gate terminal 1 is defined as port 1, and the drain terminal 2 is defined as port 2.

The relational expression between each matrix element of the matrix [Z] used in the cold FET method and the device parameters of the field effect transistor is shown in the following expressions [2]-[9]. In the cold FET method, the parasitic resistance value is extracted by solving these simultaneous equations. When the drain-source voltage V _ds = 0 and the gate-source voltage V _gs = 0, the relationship of Expression [2] -Expression [5] is established in the equivalent circuit of FIG.

In Formula [2] -Formula [4], ω is an angular frequency. FIG. 6 shows an equivalent circuit of the field effect transistor when the drain-source voltage V _ds = 0 and the gate-source voltage V _gs << the threshold voltage V _t of the field effect transistor. In FIG. 6, C _b is a gate capacitance, the C _gd gate-drain capacitance, the C _ds is the capacitance between the drain and the source. In the case of the drain-source voltage V _ds = 0 and the gate-source voltage V _gs << threshold voltage V _t , the relationship of Expression [6] is established in the equivalent circuit of FIG.

In Equation [6], Re {Z ₁₁ } is the real part of the input impedance Z ₁₁ of the field effect transistor. FIG. 7 shows an equivalent circuit of the field effect transistor in the case of the drain-source voltage V _ds = 0, the gate-source voltage V _gs >> the diffusion potential V _f of the gate Schottky junction. In FIG. 7, R _c2 is the channel resistance, and R _dy is the differential resistance of the gate Schottky junction. When the drain-source voltage V _ds = 0 and the gate-source voltage V _gs >> the diffusion potential V _f , the relationship of Expression [7] -Expression [9] is established in the equivalent circuit of FIG.

In Equation [7]-[9], n is an ideal factor of a Schottky junction, k is a Boltzmann constant, T is an absolute temperature of the junction, and q is an elementary charge.
The imaginary part of impedance Z ₁₁ includes gate capacitance C _b , gate-drain capacitance C _gd , drain-source capacitance C _ds , gate inductance L _g , source inductance L _s, etc., but the real part of impedance Z ₁₁ Therefore, the influences of these reactances are removed in the equations [6] and [7].

We will examine the above equation in more detail. Since the number of device parameters to be extracted is large, the cold FET method is not _{limited to} the conditions of drain-source voltage V _ds = 0 and gate-source voltage V _gs = 0 (formula [2] _-formula [5]). Source-to-source voltage V _ds = 0, gate-to-source voltage V _gs << threshold voltage V _t condition (formula [6]) or drain-to-source voltage V _ds = 0, gate-to-source voltage V _{gs >>>} diffusion potential V _f It is necessary to use the measurement result of the impedance matrix [Z] under the conditions (formula [7] -formula [9]). In other words, in the conventional cold FET method, it is essential to extract a plurality of greatly different gate-source voltages V _gs in order to extract parasitic resistance. In the conventional cold FET method, it is assumed that the resistance and inductance outside the intrinsic region 15 are always unchanged.

The first problem of the conventional cold FET method is that the state of the depletion layer around the gate electrode is considerably different between the state where the gate-source voltage V _gs = 0 and the state between the gate-source voltage V _gs << threshold voltage V _t. Regardless, it is assumed that the state of the depletion layer is the same. For example, under the condition of gate-source voltage V _gs << threshold voltage V _t , the gate depletion layer greatly spreads in the lateral direction in the wafer surface, so that a region beside the gate where the source resistance R _s and the drain resistance R _d are generated. The depletion layer is eroding. Therefore, the values of the source resistance R _s and the drain resistance R _d in the equivalent circuit of FIG. 6 are slightly different from the values of the source resistance R _s and the drain resistance R _d in the equivalent circuit of FIG. In addition, the phenomenon that the depletion layer erodes the region beside the gate becomes more pronounced with a short-channel field effect transistor, and therefore, a field effect transistor with higher high-frequency characteristics tends to be more difficult to extract parasitic resistance more accurately.

On the other hand, under the condition of the gate-source voltage V _gs >> diffusion potential V _f is large gate current I _g to the gate electrode flows, the resulting gate capacitance C _gs is negligible sufficiently large at the same time, local due to the gate current I _g There is a problem that the resistance value of the source resistance R _s , the drain resistance R _d , the channel resistance R _c , and the differential resistance R _dy of the gate Schottky junction increases due to the self-heating.

However, in the cold FET method, an increase in resistance value due to heat generation is not corrected, and there is no good method for correcting it. Further, in the cold FET method, differential resistance R _dy gate Schottky junction is expected to become sufficiently reduced by the gate current I _g. This is because when the differential resistance R _dy of the gate Schottky junction is sufficiently small, the real part Re {Z ₁₁ } of the impedance Z _{11 in} Equation [7] becomes a term in which R _s + R _g dominates. _{This is because} the value of R _s + R _g can be accurately extracted from ₁₁ }.

In an ideal Schottky junction, the gate current _Ig can be arbitrarily increased, and as a result, the differential resistance _Rdy can be reduced to near zero. However, in the actual Schottky junction, since the increase in resistance and heat damage caused by heat at a certain gate current I _g starting, not flowed is very large currents. As a result, the differential resistance R _dy (formula [9]) of the gate Schottky junction has a large value equal to or greater than the gate resistance R _g and the source resistance R _s, and does not become as low as expected. . In addition, the cold FET method has a problem that the measurement result tends to be unstable because the current is increased just before thermal breakdown. Because of these problems, it is inherently undesirable to use the condition of gate-source voltage V _gs >> diffusion potential V _f for parasitic resistance extraction. As described above, it is a cause of various problems of the cold FET method to confuse and use the measurement results with greatly different bias conditions for analysis.

G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A New Method for Determining the FET Small-Signal Equivalent Circuit”, IEEE Transaction on Microwave Theory and Techniques, Vol. 36, No. 7, July 1988 , Pp.1151-1159 R.Tayrani, J.E.Gerber, T.Daniel, R.S.Pengelly, and U.L.Rohde, “A New and Reliable Direct Parasitic Extraction Method for MESFETs and HEMTs”, Microwave Conference 23rd European, Sept. 1993, pp. 451-453 Yoshihiro Konishi, “Configuration Method of High-Frequency Microwave Circuits”, General Electronic Publishing Company, ISBN 4-915449-69-6, 1993, pp. 30

In the conventional cold FET method, there is a limit to the extraction accuracy of the parasitic resistance of the field effect transistor. The first reason that the extraction accuracy of the parasitic resistance is limited is that the state of the depletion layer around the gate electrode is in the state where the gate-source voltage V _gs = 0 and the gate-source voltage V _gs << threshold voltage V _t. The reason is that the state of the depletion layer is assumed to be the same although it is quite different. The second reason that the extraction accuracy of the parasitic resistance is limited is that a large gate current _Ig flows in the gate electrode under the condition of the gate-source voltage _Vgs >> the diffusion potential _Vf , and as a result, the gate capacitance _Cgs is reduced. At the same time, it can be ignored sufficiently, and at the same time, local self-heating causes an increase in resistance values of the source resistance R _s , drain resistance R _d , channel resistance R _c , and differential resistance R _dy of the gate Schottky junction. The third reason that the extraction accuracy of the parasitic resistance is limited is that the differential resistance R _dy that is preferably small is not as small as expected due to the heat generation of the gate Schottky junction.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a parasitic resistance extraction method and apparatus capable of improving the extraction accuracy of the parasitic resistance of a field effect transistor.

の関係式から得られるＲｅ｛Ｚ₁₁｝と前記インピーダンス行列変換ステップで求めたＲｅ｛Ｚ₁₁｝とが一致するように、ゲート抵抗Ｒ_g、ソース抵抗Ｒ_sとフィッティングパラメータＧ，Ｖの組み合わせを最小二乗法により決定する演算ステップとを備えることを特徴とするものである。 The parasitic resistance extraction method for a field effect transistor according to the present invention is performed by changing the gate-source voltage V _gs under the condition of the drain-source voltage V _ds = 0, and the S parameter of the HEMT or MOSFET as the target field effect transistor. An S-parameter measurement step for measuring V _gs , an impedance matrix conversion step for converting the S-parameter measured in this S-parameter measurement step into an impedance matrix [Z], and obtaining the real part Re {Z ₁₁ } of the impedance, When the gate resistance is defined as R _g , the source resistance as R _s , and the fitting parameters as G and V,

As the Re obtained from the equation {Z _11} and Re {Z _11} has been determined by the impedance matrix transformation step is matched, gate resistor R _g, source resistance R _s and fitting parameters G, a combination of V And a calculation step determined by a least square method.

の関係式から得られるＲｅ｛Ｚ₁₁｝と前記インピーダンス行列変換ステップで求めたＲｅ｛Ｚ₁₁｝とが一致するように、ゲート抵抗Ｒ_g、ソース抵抗Ｒ_sとフィッティングパラメータＧ，Ｖ_B，Ｖ_pの組み合わせを最小二乗法により決定する演算ステップとを備えることを特徴とするものである。 The parasitic resistance extraction method for a field effect transistor according to the present invention is based on the S parameter of the MESFET that is the target field effect transistor while changing the gate-source voltage V _gs under the condition of the drain-source voltage V _ds = 0. An S-parameter measurement step for measuring V _gs , an impedance matrix conversion step for converting the S-parameter measured in this S-parameter measurement step into an impedance matrix [Z], and obtaining the real part Re {Z ₁₁ } of the impedance, When the gate resistance is defined as R _g , the source resistance is defined as R _s , and the fitting parameters are defined as G, V _B , and V _p ,

As the Re {Z _11} obtained from the relational expression and Re {Z _11} has been determined by the impedance matrix transformation step is matched, gate resistor R _g, source resistance R _s and fitting parameters G, V _B, V and a calculation step of determining a combination of _p by a least square method.

の関係式から得られるＲｅ｛Ｚ₁₁｝と前記インピーダンス行列変換手段が求めたＲｅ｛Ｚ₁₁｝とが一致するように、ゲート抵抗Ｒ_g、ソース抵抗Ｒ_sとフィッティングパラメータＧ，Ｖの組み合わせを最小二乗法により決定する演算手段とを備えることを特徴とするものである。 In addition, the parasitic resistance extraction device for a field effect transistor according to the present invention changes the gate-source voltage V _gs under the condition of the drain-source voltage V _ds = 0, while the HEMT or MOSFET as the target field effect transistor is changed. S parameter measuring means for measuring S parameter for each V _gs, and impedance matrix conversion for converting S parameter measured by the S parameter measuring means into an impedance matrix [Z] to obtain a real part Re {Z ₁₁ } of the impedance When the means, gate resistance is defined as R _g , source resistance is defined as R _s , and fitting parameters are defined as G and V,

Such that the Re {Z _11} obtained from equation the impedance matrix transformation means Re {Z _11} and matches found, the gate resistor R _g, source resistance R _s and fitting parameters G, a combination of V And an arithmetic means for determining by the least square method.

の関係式から得られるＲｅ｛Ｚ₁₁｝と前記インピーダンス行列変換手段が求めたＲｅ｛Ｚ₁₁｝とが一致するように、ゲート抵抗Ｒ_g、ソース抵抗Ｒ_sとフィッティングパラメータＧ，Ｖ_B，Ｖ_pの組み合わせを最小二乗法により決定する演算手段とを備えることを特徴とするものである。 The parasitic resistance extraction apparatus for a field effect transistor according to the present invention changes the S parameter of the MESFET which is the target field effect transistor while changing the gate-source voltage V _gs under the condition of the drain-source voltage V _ds = 0. S parameter measuring means for measuring V _gs , and impedance matrix converting means for converting the S parameter measured by the S parameter measuring means into an impedance matrix [Z] to obtain the real part Re {Z ₁₁ } of the impedance; When the gate resistance is defined as R _g , the source resistance is defined as R _s , and the fitting parameters are defined as G, V _B , and V _p ,

Such that the Re {Z _11} obtained from equation the impedance matrix conversion means and Re {Z _11} matches found, the gate resistor R _g, source resistance R _s and fitting parameters G, V _B, V and an arithmetic means for determining a combination of _p by the least square method.

  According to the present invention, it is possible to extract a resistance of a field effect transistor with higher accuracy than in the prior art, and to improve design accuracy of a high frequency circuit including the field effect transistor.

It is a figure which shows the fitting result of impedance matrix [Z] by the 1st Embodiment of this invention. It is a figure which shows the fitting result of impedance matrix [Z] by the 1st Embodiment of this invention. It is a figure which shows the fitting result of impedance matrix [Z] by the 1st Embodiment of this invention. It is a block diagram which shows the structure of the parasitic resistance extraction apparatus which concerns on the 1st Embodiment of this invention. V _gs = 0V, which is a diagram showing an equivalent circuit of the field effect transistor in the case of V _ds = 0V. V _gs << V _t, is a diagram showing an equivalent circuit of the field effect transistor in the case of V _ds = 0V. It is a figure which shows the equivalent circuit of the field effect transistor in the case of _Vgs >> _Vf and _Vds = 0V.

[First Embodiment]
The parasitic resistance extraction method according to the first embodiment of the present invention will be described using the equivalent circuit of FIG. The target device is a HEMT field effect transistor having a two-dimensional electron gas layer. As described above, the equivalent circuit of FIG. 5 is an equivalent circuit corresponding to the conditions (formula [2] _−formula [5]) of the drain-source voltage V _ds = 0 and the gate-source voltage V _gs = 0. Since the real part and the imaginary part of the element of the impedance matrix [Z] can be calculated separately, the following four expressions are obtained by writing out only the real part of Expression [2] -Expression [5].

Among the above four formulas, the three formulas [10]-[12] are independent, and since there are four unknowns, a solution cannot usually be obtained. Therefore, a method of obtaining another independent expression from the result using the impedance matrix [Z] when the gate-source voltage V _gs is _slightly increased or decreased near zero is considered. The gate-source voltage V _gs given here is near zero in order to keep the change in the gate depletion layer small, and is in the range of threshold voltage V _t << gate-source voltage V _gs << diffusion potential V _f. It is hoped that. Since the rate of change of the channel resistance R _c with respect to the gate-source voltage V _gs is large, a new equation independent of the equations [10] to [12] is obtained. However, if a relational expression other than the equations [10]-[12] is not introduced, the channel resistance R _c changes depending on the gate-source voltage V _gs, and therefore the number of independent equations increases and the unknown ( The increase in R _c ) with different values proceeds at the same rate and again no solution is obtained. Therefore, a method for stopping the increase of the unknown R _c will be considered next.

Here, the case of a HEMT structure having a two-dimensional electron gas layer will be specifically considered. The theoretical formula of the channel resistance R _c is given as follows.

Equations [14]-[16] are described in the literature “K. Lee, MSShur, TJDrummond, and H. Morkoc,“ Parasitic MESFET in (Al, Ga) As / GaAs Modulation Doped FET's and MODFET Characterization ”, IEEE Transaction on Electron Devices. , Vol.ED-31, No.1, January 1984, pp.29-35 ". Here, G ₀ is the drain conductance, V ₀ is the voltage, μ is the electron mobility, ε _r is the dielectric constant of the spacer layer, Z _g is the gate width, L _g is the gate length, d ₂ is the gate metal and two-dimensional electrons. It is the effective distance of the gas layer.

G ₀ and V ₀ are device-specific constants that can be calculated using Equation [15] and Equation [16]. However, since there are various error factors in an actual HEMT, the equations [15] and [16] are not necessarily accurate. Therefore, G ₀ and V ₀ will be treated as fitting parameters in the future. Of course, if G ₀ and V ₀ show values that deviate significantly from the equations [15] and [16], some troubles are predicted in the measurement and calculation, which is one benchmark.

The above equations [14]-[16] are for the HEMT, but are described in the literature “Masayoshi Kishino, Mitsumasa Koyanagi,“ Physics of VLSI Devices ”, Maruzen Publishing, ISBN 4-621-03094-9, 1986, pp. 90 ”, the N-type MOS field-effect transistor can obtain almost the same expression as Expressions [14] to [16] when the drain-source voltage V _ds is near zero, and parasitic resistance can be extracted as in the HEMT. I can easily imagine something.

The specific fitting procedure will be described. First, Expression [14] is substituted into Expression [10]-[13], and Re {Z ₁₁ }, Re {Z ₁₂ }, Re {Z ₂₂ } obtained from S parameter measurement of the field effect transistor are minimized. Fitting is performed so as to match the squares, and parameters G ₀ and V ₀ and resistances R _g , R _s and R _d are determined. At this time, it is preferable to perform fitting with the entire threshold voltage V _t << gate-source voltage V _gs << diffusion potential V _f . For example, a Z matrix measured at V _gs = −0.2V, −0.1V, 0V, 0.1V, 0.2V is used.

Here, if the range of the gate-source voltage V _gs is too narrow, the independence of each measurement condition is weakened and the fitting result is not stable. Thus, initially starting from a narrow range of gate-source voltage V _gs, the result needs to go to a wide scanning range of the gate-source voltage V _gs to stabilize. However, when the gate-source voltage V _gs increases and approaches the threshold voltage V _t , the field effect transistor is pinched off, so that equation [14] does not hold and the square error of fitting increases. Further, when the gate-source voltage V _gs approaches the diffusion potential V _f , the gate forward current I _g increases, so that equation [14] does not hold and the square error of fitting increases. Therefore, the range of the gate-source voltage V _gs is determined while observing the tendency of the square error.

Here, the number of unknowns and the extraction accuracy are considered. As long as the expression [14] is used, even if the gate-source voltage V _gs is changed variously, only two new unknowns, G ₀ and V ₀ , increase. Therefore, when two or more gate-source voltages V _gs are selected and evaluated, simultaneous equations with high independence from which all resistance values R _g , R _s and R _d can be extracted are obtained. Further, if the number of equations is increased to 3, 4, more accurate results can be obtained. This is because the function representing the square error of the fitting is a functional of the equation [14], so that a stable and accurate fitting result can be obtained even if there are some errors in individual measured values. .

1 to 3 are diagrams showing the fitting result of the impedance matrix [Z] according to the present embodiment. The gate-source voltage V _gs is fitted in the range of −0.2V to + 0.2V. FIG. 1 shows the fitting result when the measurement frequency is 1 GHz, FIG. 2 shows the fitting result when the measurement frequency is 10 GHz, and FIG. 3 shows the fitting result when the measurement frequency is 20 GHz. 1 to 3, Meas. Re {Z ₁₁ }, Meas. Re {Z ₁₂ }, Meas. Re {Z ₂₂ } is the real part of the impedances Z ₁₁ , Z ₁₂ , and Z ₂₂ obtained from the S parameter measurement, respectively. Sim Re {Z ₁₁ }, Sim Re {Z ₁₂ }, and Sim Re {Z ₂₂ } are obtained from the relational expressions after completion of fitting (formulas obtained by substituting formula [14] into formulas [10] to [13]), respectively. The real parts of the impedances Z ₁₁ , Z ₁₂ , and Z _{22 obtained} .

As a result of the fitting shown in FIG. 1 to FIG. 3, R _g = 4.1Ω, R _s = 5.9Ω, R _d = 7.8Ω, G ₀ = 0.42 S / V, V ₀ = −0.5 V The value of was obtained. It can be seen from the equations [2]-[4] that there is basically no frequency dependence in the real part of the Z parameter. Therefore, the same result should be obtained no matter which measurement frequency Z matrix is used, and FIGS. 1 to 3 show this. However, due to a technical problem of S-parameter measurement, the measurement error of the real part of the Z matrix becomes large at a very low frequency, and the resistance value extraction accuracy deteriorates. Further, at low frequencies, the influence of frequency dispersion of the field effect transistor appears and the measurement error increases. On the other hand, when the frequency is too high, the measurement error of the S parameter increases due to other measurement error factors such as calibration accuracy and interprobe interference. Because of the above circumstances, there is an optimum measurement frequency range unique to each field effect transistor, and it is necessary to evaluate the frequency dependence of the Z parameter and reject data whose values on the low frequency side and high frequency side are not stable. . For a normal field effect transistor, a measurement frequency of 1 GHz to 20 GHz is a guide.

  FIG. 4 is a block diagram showing the configuration of the parasitic resistance extraction apparatus according to the present embodiment. The parasitic resistance extraction apparatus includes an S parameter measurement unit 100, an impedance matrix conversion unit 101, a calculation unit 102, and an output unit 103.

The S parameter measuring unit 100 measures the S parameter of the target field effect transistor for each V _gs while changing the gate-source voltage V _gs near 0 under the condition of the drain-source voltage V _ds = 0.
The impedance matrix conversion unit 101 converts the S parameter for each V _gs measured by the S parameter measurement unit 100 into an impedance matrix [Z], and the real part of impedance Re {Z ₁₁ }, Re {Z ₁₂ }, Re {Z ₂₂ } is obtained for each V _gs . As described above, Non-Patent Document 3 discloses a method for converting an S parameter into an impedance matrix [Z].

Operation section 102, and Re {Z _11} impedance matrix transformation unit 101 is calculated relation (Equation [14] Equation [10] - Formula equation obtained by substituting the [13]) to be obtained from Re {Z _11} And Re {Z ₁₂ } obtained by the impedance matrix conversion unit 101 and Re {Z ₁₂ } obtained from the relational expression match, and Re {Z ₂₂ } obtained by the impedance matrix conversion unit 101 and the relational expression The gate resistance R _g , the source resistance R _s , the drain resistance R _d, and the fitting parameters G ₀ and V ₀ are determined by the least square method so that the obtained Re {Z ₂₂ } matches.
The output unit 103 displays the gate resistance R _g , source resistance R _s , drain resistance R _d, and fitting parameters G ₀ and V ₀ calculated by the calculation unit 102.

As described above, in the method according to the present embodiment, it can be seen that the gate-source voltage V _gs used in the resistance extraction process is only near zero. That is, the extreme bias condition of the conventional cold FET method, that is, without using the gate-source voltage V _gs «threshold voltage V _t , gate-source voltage V _{gs >>>>} diffusion potential V _f is highly accurate. Resistance extraction is possible. At the same time, in this embodiment, a large gate current I _g to break down the gate Schottky junction is performing conditions resistor extraction without flow. Therefore, measurement can be stably continued without damaging the HEMT.

  Note that the following three equations may be used instead of the equation in which the equation [14] is substituted into the equations [10]-[13].

Equation [17] -Equation [19] corresponds to an equation obtained by substituting Equation [14] into Equation [10] -Equation [13], but fitting parameters G, V instead of G ₀ , V _0. Is used. G ₀ and V ₀ are inherently device-specific constants. However, since there are various error factors, the parameters G ₀ and V ₀ obtained as a result of fitting do not completely match the device-specific constants. Therefore, G and V are used as fitting parameters including an error.

[Second Embodiment]
A parasitic resistance extraction method according to the second embodiment of the present invention will be described using the equivalent circuit of FIG. In this embodiment, the target device is a MESFET. As described above, the equivalent circuit of FIG. 5 is an equivalent circuit corresponding to the conditions (formula [2] _−formula [5]) of the drain-source voltage V _ds = 0 and the gate-source voltage V _gs = 0. Since the difference from the case of the HEMT shown in the first embodiment is only the equation [14], only that portion will be described.

The channel of the MESFET is a conductive layer remaining under the gate depletion layer, and its thickness varies depending on the gate-source voltage V _gs . On the other hand, the HEMT does not change because the channel is always at a certain distance from the gate. Therefore, the dependence of the channel resistance R _{c on} the gate-source voltage V _gs differs between the MESFET and the HEMT. The channel resistance R _{c of the} MESFET is given by the following equation.

Equations [20]-[22] are described in the literature “PLHower and NGBechtel,“ Current Saturation and Small-Signal Charactoristics of GaAs Field-Effect Transistors ”, IEEE Transaction on electron devices, Vol. ED-20, No. 3, March 1973. , Pp.213-220 ”. Here, G ₁ is an open channel drain conductance, V _p is a pinch-off voltage, μ is an electron mobility, Z _g is a gate width, L _g is a gate length, a is a channel junction depth, and N ₀ is a channel carrier concentration. , V _B is a built-in potential of the Schottky junction, and q is an elementary charge.

G ₁ is a device-specific constant that can be calculated using Equation [21]. V _B , N ₀ and a are also constants specific to the structure of the Schottky junction. However, since there are various error factors in an actual MESFET, equations [21] and [22] are not necessarily accurate. Therefore, G ₁ , V _p , and V _B will be treated as fitting parameters in the future. Of course, if G ₁ shows a value that deviates significantly from the equation [21], some trouble is expected in measurement and calculation. Also, V _p should not be significantly different from the value predicted from the subthreshold characteristics.

In the present embodiment, Expression [20] is substituted into Expression [10] −Expression [13], and Re {Z ₁₁ }, Re {Z ₁₂ }, Re {obtained from S parameter measurement of the field effect transistor. Fitting is performed so that it matches the least squares with Z ₂₂ }, and parameters G ₁ , V _p , V _B and resistances R _g , R _s , R _d may be determined.

Also in the present embodiment, the configuration of the parasitic resistance extraction device is the same as that of the first embodiment, and therefore will be described using the reference numerals in FIG.
The operations of the S parameter measurement unit 100 and the impedance matrix conversion unit 101 are the same as those in the first embodiment.

The calculation unit 102 according to the present embodiment obtains Re {Z ₁₁ } obtained by the impedance matrix conversion unit 101 and a relational expression (an expression obtained by substituting Expression [20] into Expression [10] −Expression [13]). {Z ₁₁ } matches, Re {Z ₁₂ } obtained by the impedance matrix converter 101 matches Re {Z ₁₂ } obtained from the relational expression, and Re {Z ₂₂ obtained by the impedance matrix converter 101 } And Re {Z ₂₂ } obtained from the relational expression are matched by the least square method to determine the gate resistance R _g , source resistance R _s , drain resistance R _d, and fitting parameters G ₁ , V _p , V _B. To do.
The output unit 103 displays the gate resistance R _g , source resistance R _s , drain resistance R _d, and fitting parameters G ₁ , V _p , and V _B calculated by the calculation unit 102.

Thus, in the present embodiment, the same effect as that of the first embodiment can be obtained with respect to the MESFET.
Note that the following three equations may be used instead of the equation in which the equation [20] is substituted into the equations [10]-[13].

Expression [23] -expression [25] corresponds to an expression obtained by substituting expression [20] into expression [10] -expression [13], but uses a fitting parameter G instead of G ₁ . G ₁ is inherently a device-specific constant. However, since there are various error factors, the parameter G ₁ obtained as a result of fitting does not completely match the device-specific constant. Therefore, G is used as a fitting parameter including an error.

  Of the parasitic resistance extraction devices described in the first and second embodiments, at least the impedance matrix conversion unit 101 and the calculation unit 102 control a computer including a CPU, a storage device, and an interface, and hardware resources thereof. It can be realized by a program to do. The CPU executes the processing described in the first and second embodiments in accordance with a program stored in the storage device.

  The present invention can be applied to a technique for obtaining device parameters of a field effect transistor.

DESCRIPTION OF SYMBOLS 1 ... Gate terminal, 2 ... Drain terminal, 3 ... Source terminal, 15 ... Intrinsic region, 100 ... S parameter measurement part, 101 ... Impedance matrix conversion part, 102 ... Operation part, 103 ... Output part, _Vgs ... Between gate sources Voltage, V _ds ... Drain-source voltage, R _g ... Gate resistance, R _s ... Source resistance, R _d ... Drain resistance, R _c , R _c1 , R _c2 ... Channel resistance, R _dy ... Differential resistance of gate Schottky junction , L _g ... gate inductance, L _s ... source inductance, L _d ... drain inductance, C _gs , C _b ... gate capacitance, C _gd ... gate-drain capacitance, C _ds ... drain-source capacitance.

Claims (8)

An S parameter measurement step of measuring the S parameter of the HEMT or MOSFET as the target field effect transistor for each V _gs while changing the gate source voltage V _gs under the condition of the drain-source voltage V _ds = 0;
An impedance matrix conversion step of converting the S parameter measured in the S parameter measurement step into an impedance matrix [Z] to obtain a real part Re {Z ₁₁ } of the impedance;
When the gate resistance is defined as R _g , the source resistance as R _s , and the fitting parameters as G and V,

As the Re obtained from the equation {Z _11} and Re {Z _11} has been determined by the impedance matrix transformation step is matched, gate resistor R _g, source resistance R _s and fitting parameters G, a combination of V And a parasitic resistance extraction method for a field effect transistor, comprising: an arithmetic step determined by a least square method. The parasitic effect extraction method for a field effect transistor according to claim 1,
The impedance matrix conversion step further obtains real parts Re {Z ₁₂ }, Re {Z ₂₂ } of the impedance,
In the calculation step, when the drain resistance is defined as R _d ,

Re {Z _11} obtained from the relational _{expression, Re {Z 12}, Re} {Z 22} and the impedance matrix conversion Re {Z _11} calculated in step, Re {Z _12}, and Re {Z _22} A parasitic resistance extraction method for a field effect transistor, wherein a combination of a gate resistance R _g , a source resistance R _s , a drain resistance R _d, and fitting parameters G and V is determined by a least square method so that the two match. An S parameter measurement step of measuring the S parameter of the MESFET, which is a target field effect transistor, for each V _gs while changing the gate source voltage V _gs under the condition of the drain-source voltage V _ds = 0;
An impedance matrix conversion step of converting the S parameter measured in the S parameter measurement step into an impedance matrix [Z] to obtain a real part Re {Z ₁₁ } of the impedance;
When the gate resistance is defined as R _g , the source resistance is defined as R _s , and the fitting parameters are defined as G, V _B , and V _p ,

As the Re {Z _11} obtained from the relational expression and Re {Z _11} has been determined by the impedance matrix transformation step is matched, gate resistor R _g, source resistance R _s and fitting parameters G, V _B, V and a parasitic resistance extraction method for a field effect transistor, comprising: an operation step of determining a combination of _p by a least square method. The parasitic effect extraction method for a field effect transistor according to claim 3,
The impedance matrix conversion step further obtains real parts Re {Z ₁₂ }, Re {Z ₂₂ } of the impedance,
In the calculation step, when the drain resistance is defined as R _d ,

Re {Z _11} obtained from the relational _{expression, Re {Z 12}, Re} {Z 22} and the impedance matrix conversion Re {Z _11} calculated in step, Re {Z _12}, and Re {Z _22} The parasitic resistance of the field effect transistor is characterized in that the combination of the gate resistance R _g , the source resistance R _s , the drain resistance R _d and the fitting parameters G, V _B , V _p is determined by the least square method so that Extraction method. S parameter measuring means for measuring the S parameter of the HEMT or MOSFET as the target field effect transistor for each V _gs while changing the gate source voltage V _gs under the condition of the drain-source voltage V _ds = 0;
Impedance matrix conversion means for converting the S parameter measured by the S parameter measurement means into an impedance matrix [Z] to obtain a real part Re {Z ₁₁ } of the impedance;
When the gate resistance is defined as R _g , the source resistance as R _s , and the fitting parameters as G and V,

Such that the Re {Z _11} obtained from equation the impedance matrix transformation means Re {Z _11} and matches found, the gate resistor R _g, source resistance R _s and fitting parameters G, a combination of V An apparatus for extracting parasitic resistance of a field effect transistor, comprising: an arithmetic means for determining by a least square method. The parasitic resistance extraction device for a field effect transistor according to claim 5,
The impedance matrix conversion means further obtains real parts Re {Z ₁₂ }, Re {Z ₂₂ } of the impedance,
When the drain means defines the drain resistance as R _d ,

Of Re obtained from equation _{{Z 11}, Re {Z} 12}, Re {Z 22} and the impedance matrix conversion means is determined _{Re {Z 11}, Re {} Z 12}, and Re {Z _22} A parasitic resistance extraction device for a field effect transistor, wherein a combination of a gate resistance R _g , a source resistance R _s , a drain resistance R _d, and fitting parameters G and V is determined by a least square method so that S parameter measuring means for measuring the S parameter of MESFET, which is a target field effect transistor, for each V _gs while changing the gate source voltage V _gs under the condition of drain-source voltage V _ds = 0;
Impedance matrix conversion means for converting the S parameter measured by the S parameter measurement means into an impedance matrix [Z] to obtain a real part Re {Z ₁₁ } of the impedance;
When the gate resistance is defined as R _g , the source resistance is defined as R _s , and the fitting parameters are defined as G, V _B , and V _p ,

Such that the Re {Z _11} obtained from equation the impedance matrix conversion means and Re {Z _11} matches found, the gate resistor R _g, source resistance R _s and fitting parameters G, V _B, V _An apparatus for extracting parasitic resistance of a field effect transistor, comprising: an arithmetic means for determining a combination of _p by a least square method. The parasitic resistance extraction device for a field effect transistor according to claim 7,
The impedance matrix conversion means further obtains real parts Re {Z ₁₂ }, Re {Z ₂₂ } of the impedance,
When the drain means defines the drain resistance as R _d ,

Of Re obtained from equation _{{Z 11}, Re {Z} 12}, Re {Z 22} and the impedance matrix conversion means is determined _{Re {Z 11}, Re {} Z 12}, and Re {Z _22} The parasitic resistance of the field effect transistor is characterized in that the combination of the gate resistance R _g , the source resistance R _s , the drain resistance R _d and the fitting parameters G, V _B , V _p is determined by the least square method so that Extraction device.

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